TWI426365B - Method of electrical adjustment pogramming for record,store and implementation - Google Patents

Method of electrical adjustment pogramming for record,store and implementation Download PDF

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TWI426365B
TWI426365B TW097121360A TW97121360A TWI426365B TW I426365 B TWI426365 B TW I426365B TW 097121360 A TW097121360 A TW 097121360A TW 97121360 A TW97121360 A TW 97121360A TW I426365 B TWI426365 B TW I426365B
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wafer
implementation method
electrically adjustable
record storage
parameter
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TW200951655A (en
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Actron Technology Corp
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Description

電性調整可程式化記錄儲存實施方法 Electrical adjustment programmable record storage implementation method

本發明係提出一種方法，用來解決半導體晶片在生產製程過程，因環境溫度變動而產生電性漂移現象。該方法係將半導體晶片生產製造時，透過操作介面進入參數記錄儲存位置存取儲存所需之參數值，並將參數載入修整(trim)之半導體晶片，來提高半導體晶片製造時程與降低半導體晶片過去因電性漂移修整修整(trim)時程。 The present invention proposes a method for solving the electrical drift phenomenon of a semiconductor wafer during a manufacturing process due to fluctuations in ambient temperature. The method is to increase the semiconductor wafer manufacturing time and reduce the semiconductor by manufacturing the semiconductor wafer through the operation interface, entering the parameter record storage location, and storing the parameter values required for storage, and loading the parameters into the trimmed semiconductor wafer. The wafer used to trim the trim time course due to electrical drift.

請參考圖1，圖1係半導體晶圓之製程，晶圓其材質是矽亦是積體電路在生產製作所用之矽晶片，晶圓製程共有九項主要程序步驟，晶圓(Wafer)其形狀因為圓形所以亦稱之為晶圓，透過將電路建構於矽晶圓上的方式，每片晶圓可包含數百個甚至數千個晶粒，其製造方式是採逐層建構的方式來進行，每一層的製程為一種循環，除了光罩上的圖案及植入的離子不同之外其他部份也幾乎相同只是程序的變化。 Please refer to FIG. 1. FIG. 1 is a process of a semiconductor wafer. The material of the wafer is 矽 is also used in the production and fabrication of the wafer. The wafer process has nine main program steps, the shape of the wafer (Wafer). Because of the circular shape, it is also called a wafer. Each wafer can contain hundreds or even thousands of grains by constructing the circuit on a silicon wafer. The manufacturing method is to build the layer by layer. The process of each layer is a cycle, except that the pattern on the mask and the implanted ions are almost identical except for the program changes.

晶圓製造程序步驟上均會經過氧化、薄膜沉積、擴散、離子值入、微影、蝕刻、金屬化、檢測等製程，每一程序描述如下： The wafer fabrication process steps are subjected to oxidation, thin film deposition, diffusion, ion implantation, lithography, etching, metallization, and inspection. Each program is described as follows:

1.氧化(Dxidation)：當矽晶圓曝露於含氧的環境時，在晶圓表面長出一層的二氧化矽，作為絕緣體(如步驟S101)。 1. Dxidation: When the germanium wafer is exposed to an oxygen-containing environment, a layer of germanium dioxide is grown on the surface of the wafer as an insulator (step S101).

2.薄膜沉積(Deposition)：利用物理現象或化學反應的方式，在晶圓表面上產生一層薄膜(如步驟S102)。 2. Deposition: A film is formed on the surface of the wafer by physical phenomena or chemical reaction (step S102).

3.擴散(Diffusion)：將雜質原子滲透到矽內，然後利用高溫來作為雜質擴散以得到所需雜質濃度(如步驟S103)。 3. Diffusion: Impurity atoms are infiltrated into the crucible, and then high temperature is used as an impurity to diffuse to obtain a desired impurity concentration (step S103).

4.離子植入(Ion Implantation)：利用離子植入器將雜質注入矽中，掺雜濃度能由離子束電流大小加以控制(如步驟S104)。 4. Ion Implantation: Impurity is implanted into the crucible using an ion implanter, and the doping concentration can be controlled by the magnitude of the ion beam current (step S104).

5.微影(Lithography)：將各種積體電路元件的表面結構利用照相技術，將光罩的圖案移至晶圓表面(如步驟S105)。 5. Lithography: The surface structure of various integrated circuit components is transferred to the wafer surface by a photographic technique (step S105).

6.蝕刻(Etching)：把微影製程沒有被光阻鋪蓋的薄膜部份，以化學反應或物理現象的方式加以去除，以達到整個圖案移轉到薄膜的目的(如步驟S106)。 6. Etching: The film portion of the lithography process that is not covered by the photoresist is removed by chemical reaction or physical phenomenon to achieve the purpose of transferring the entire pattern to the film (step S106).

7.金屬化(Metallization)：當矽基上的元件製造完成後，必需將其連接，以達到電路連接的功能(如步驟S107)。 7. Metallization: When the components on the bismuth base are manufactured, they must be connected to achieve the function of circuit connection (step S107).

8.平坦化(Flatness Process)：將晶圓表面起伏的介電層外觀，加以平坦化的一種半導體製程技術(如步驟S108)。 8. Flatness Process: A semiconductor process technology that planarizes the appearance of a wavy dielectric layer on a wafer surface (step S108).

9.晶圓檢查(Wafer inspection)：晶圓製造完成後，按照晶圓的品質給予分類(如步驟S109)，不合格者報廢(如步驟S110)。 9. Wafer inspection: After the wafer fabrication is completed, the classification is given according to the quality of the wafer (step S109), and the unqualified person is scrapped (step S110).

每片晶圓(Wafer)因材質、生產製程特有之電性關係，在晶圓內部會產生電性漂移，致使每批晶圓出廠時，其內部之每一單晶片內部電性記錄值均會呈現不同參數。 Each wafer (Wafer) has an electrical drift inside the wafer due to the material and manufacturing-specific electrical relationship, so that each batch of wafers will have an internal electrical record value for each internal wafer. Present different parameters.

在半導體IC晶片生產初始，需對每片晶圓進行檢測，檢測每片晶圓良率及內部晶粒電性，當半導體IC晶片進入生產後，將晶圓載入晶圓測試機(wafer probe)由測試機內檢測探針針對晶圓上的每顆晶片進行量測及記錄；量測記錄完成後再依晶片個別電性漂移狀況，載入製程所需 程式及參數後，再由燒錄機進行電性修整(trim)，每片晶圓上晶粒電性漂宜記錄的值均不一樣，在修整時載入晶圓上每顆晶粒的參數就會不同，每片晶圓在進行電性修整時，其需使用20分鐘。 At the beginning of semiconductor IC wafer production, each wafer needs to be inspected to test each wafer yield and internal die electrical properties. When the semiconductor IC wafer enters production, the wafer is loaded into the wafer tester (wafer probe). Test and record for each wafer on the wafer by the test probe in the test machine; after the measurement record is completed, according to the individual electrical drift of the wafer, the process required for loading After the program and parameters, the trimming machine is electrically trimmed, and the values of the grain electric drift on each wafer are different. The parameters of each die loaded on the wafer during trimming are changed. It will be different, each wafer will take 20 minutes when it is electrically trimmed.

請參照圖2所示，圖2為目前半導體晶圓修整(Trim)製程，在圖2所示係晶圓測試機讀取晶圓參數後進行記錄(Record)，圖2如步驟S204至S206為將晶圓載入晶圓燒錄機輸入需求參數後進行修整(Laser trim)，以及將晶圓載入後進行燒錄(trim)，如步驟S207為修整完之電性測試，若因修整錯誤該片晶片即報廢，修整完之晶片其中設置有電路包含一線性電路單元及一數位邏輯控制單元，晶片電路可載入程式，即是電路因電流導通使電路發生運作，並產生電性與電壓及載入控制程式使電路產生電壓值控制，再利用電路之數位邏輯控制單元來對電流導通所生成之電壓進行編碼/解碼執行。其結果產出參數，提供予數位/類比轉換邏輯單元，並經適當運算後輸出一參考電壓，並由線性電路單元依據該參考電壓，據以設定電壓控制值或溫度值，因此若對晶片數位邏輯控制單元執行編碼/解碼，即可利用此方式針對相同屬性的晶片實施相同的電壓值或溫度值作業。 Please refer to FIG. 2 . FIG. 2 is a current semiconductor wafer trimming process. Recording is performed after the wafer tester is read by the wafer testing machine shown in FIG. 2 , and FIG. 2 is as shown in steps S204 to S206 . After the wafer is loaded into the wafer writer, the input parameters are trimmed (Laser trim), and the wafer is loaded and then trimmed, as in step S207, the trimmed electrical test is performed, if the trimming error occurs. The chip is scrapped, and the trimmed chip is provided with a circuit including a linear circuit unit and a digital logic control unit. The chip circuit can be loaded into the program, that is, the circuit is operated by current conduction, and the electrical and voltage are generated. And the load control program causes the circuit to generate voltage value control, and then uses the digital logic control unit of the circuit to encode/decode the voltage generated by the current conduction. The resulting output parameter is provided to the digital/analog conversion logic unit, and a suitable reference voltage is outputted by the linear circuit unit according to the reference voltage, thereby setting the voltage control value or the temperature value, so if the wafer is digitally The logic control unit performs encoding/decoding, which can be used to perform the same voltage value or temperature value operation for wafers of the same property.

現行方法是以雷射修整(Laser Trim)方式對半導體晶片電路進行修整(trim)，在半導體晶片中設定有數位邏輯單元與線性電路單元，其中線性電路單元主要包含有運算放大器(Operational Amplifiers)，而數位邏輯控制單元包括有功能參數編碼邏輯單元、功能參數解碼邏輯單元及數位/類比轉換邏輯單元(D/AConverter)等，半導體晶片是利用數 位邏輯控制單元來執行編碼/解碼，其產生的結果用來提供數位/類比轉換邏輯單元用以輸出一參考電壓，而線性電路單元則依據參考電壓產生一控制電壓值，此一電壓值可用以做為半導體晶片功能設定之參數值。 The current method is to trim a semiconductor chip circuit by a laser trimming method, and a digital logic unit and a linear circuit unit are set in the semiconductor chip, wherein the linear circuit unit mainly includes an operational amplifier (Operational Amplifiers). The digital logic control unit includes a function parameter coding logic unit, a function parameter decoding logic unit, and a digital/analog conversion logic unit (D/AConverter), etc., and the semiconductor wafer is utilized. The bit logic control unit performs encoding/decoding, and the result thereof is used to provide a digital/analog conversion logic unit for outputting a reference voltage, and the linear circuit unit generates a control voltage value according to the reference voltage, and the voltage value can be used. As a parameter value set for the semiconductor wafer function.

但是在半導體晶圓(wafer)在生產製程中會產生電性漂移，致使原設定之電位準、參數值產生非預期的變動，為確保半導體製程時能維持一致性，需以修整(trim)來對晶圓內部進行檢測及進行修整。習知做法是對晶片進行選擇性修整，亦即是以雷射或電流燒針對晶圓做參數載入，晶圓依不同面積可分割成數量不等的晶片，且高容量的數位邏輯匣僅占有限面積，因此可燒錄4bit、8bit、16bit、32bit、64bit等數位邏輯匣。 However, in the semiconductor wafer (wafer) in the production process will produce electrical drift, resulting in the original set potential, the parameter values produce unexpected changes, in order to ensure consistency in the semiconductor process, the need to trim (trim) The inside of the wafer is inspected and trimmed. The conventional method is to selectively trim the wafer, that is, to load the wafer by laser or current burning, the wafer can be divided into a number of different wafers according to different areas, and the high-capacity digital logic is only It occupies a limited area, so it can burn 4bit, 8bit, 16bit, 32bit, 64bit and other digital logic.

習知可程式化晶片因製程及電氣特性會產生電性規格漂移現象因此目前晶片在參數匹配對應方式上係採用單一載入方式，將對應參數逐一載入晶片匹配採用逐一修整方式實施調配，當量產製作時，採用逐一對應匹配方式將需求參數以修整方式載入晶片並逐一進行修整，而晶片須依規格需求電壓、頻率將參數逐一寫入設定，若參數有數種參數質時，需逐一比對、載入及檢測，使參數能匹配對應，若有溫度需求產生時，亦需將溫度參數載入修整，若此，當晶片大量生產製造時，不僅耗時亦增加生產與庫存作業成本，無法快速回應生產所需與滿足市場需求，且晶片逐一進行參數設定時，其環境變數與人員操作均會因變動使整體時程與可靠度存在不可知的變動。 Conventional programmable wafers can cause electrical drift due to process and electrical characteristics. Therefore, the current wafer is loaded in a single loading mode in the parameter matching method. The corresponding parameters are loaded into the wafer one by one, and the matching is performed one by one. In mass production, the demand parameters are loaded into the wafer in a trimming manner and trimmed one by one. The wafers must be written one by one according to the required voltage and frequency. If the parameters have several parameters, one by one. Alignment, loading and inspection, so that the parameters can be matched. If temperature requirements are generated, the temperature parameters should be loaded and trimmed. If the wafer is mass-produced, it will not only take time and increase the cost of production and inventory operations. When it is unable to respond quickly to the production needs and meet the market demand, and the parameters are set one by one, the environmental variables and personnel operations will have an agnostic change in the overall time and reliability.

本發明是一種方法來簡化半導體晶片修整製程及 提高半導體晶片修整(trim)效能之方法，實施程序將半導體晶圓由測試機(Wafer Probe)晶圓承載盤載入，承載盤載入晶圓後檢測頭上探針會對晶圓內部晶片串列電氣特性進行電氣良率載測，被載測之晶片將被檢測晶片電性良率是否完整，損壞之晶片將會被註記，電性功能正常的晶片將依電壓、頻率高低位階逐項修整(trim)並被註記形成一個記錄(Record)或資料(data)並施予編碼分類(code Calibration)存記。存記之記錄將依類別、屬性、位置儲存於特定儲存欄位或資料庫；另部份晶片則會進行溫度修整(Temperature trim)，即是將晶片依高低溫特性進行逐項修整及記錄，並將晶片之溫度修整參數記錄儲存，即是將溫度參數儲存(store)於特定儲存欄位(Table)或資料庫(database)，特定儲存欄位或資料庫即以分類方式載錄半導體晶片生產製程中有關溫度參數、電壓值、電頻等相關參數。 The present invention is a method for simplifying semiconductor wafer trimming process and A method for improving the trim performance of a semiconductor wafer, the program is used to load a semiconductor wafer from a Wafer Probe wafer carrier, and the probe is loaded onto the wafer and the probe is placed on the wafer internal wafer. Electrical characteristics are measured by electrical yield. The wafer to be tested will be tested for completeness of the wafer's electrical yield. The damaged wafer will be noted. The electrically functional wafer will be trimmed by voltage and frequency. Trim) and be noted to form a record or data and apply a code calibration. The record of the record will be stored in a specific storage field or database according to the category, attribute, location; the other part will be temperature trimmed (Temperature trim), that is, the wafer will be trimmed and recorded according to the high and low temperature characteristics. The temperature reading parameters of the wafer are recorded and stored, that is, the temperature parameters are stored in a specific storage field (Table) or a database, and the specific storage field or the database is used to record the semiconductor wafer production in a classified manner. Relevant parameters related to temperature parameters, voltage values, and frequency in the process.

當生產需求產生時，晶圓電性在良率檢測及電性漂移狀態已經實施量測，並對晶圓內部晶片狀態及良率不佳的晶片予以標註(Mark)，因此在生產製造時不需經過修整(trim)，可直接將已測試之晶圓依客戶需求規格自記載區或資料夾取出相關參數進行修整，修整完成之晶圓即可以進行後續貼片(Wafer mount)、切割(Die saw)、黏晶(Die Bond)、銲線(Wire Bond)、封膠(mold)、打印(mark)…等一係列半導體製程。 When production requirements arise, wafer conductivity has been measured in yield and electrical drift states, and wafers with poor wafer state and yield are marked (Mark), so they are not manufactured at the time of manufacture. It needs to be trimmed, and the tested wafer can be directly trimmed according to the customer's requirements, and the relevant parameters can be removed from the recorded area or folder. The finished wafer can be used for subsequent patching (Wafer mount) and cutting (Die). Saw), Die Bond, Wire Bond, mold, mark, etc. A series of semiconductor processes.

本方法可提高半導體晶片製程效能及簡化半導體晶圓修整步驟，該方法可適用於任一款半導體晶片製程。 The method can improve the process performance of the semiconductor wafer and simplify the semiconductor wafer trimming step, and the method can be applied to any semiconductor wafer process.

請參照圖5所示，本發明係使用一種方法來簡化半導體晶片製程，圖5為該方法較佳實施例之流程示意圖。此方式係將晶圓片由晶圓匣(Carriers)取出，以平置方式放置於晶圓檢測機(Wafer Probe)台上之托盤，由晶圓檢測機台托盤將晶圓以平行引導或吸入方式將晶圓載入檢測機之檢測室，載入之晶圓由晶圓檢測機內探針(Probe)對載入托盤內之晶圓有效面積上之每一片晶片均進行電性測試，電性測試在進行電性判斷則會產生晶圓良率判斷，良率判斷會將晶圓電性檢測良好之晶片予以註記，並進行電壓值校對，校對校對完成之晶片，電壓值資料記錄將存入資料夾予以保存。另良率判斷，晶圓電性檢測不佳之晶片予以損壞註記，並將損壞註記記錄存入資料夾予以保存。部份晶圓電性檢測良好之晶片另進行溫度之測試，將溫度測試記錄，存入資料夾予以保存。當需求產生時，將晶圓置放於托盤載入晶圓進入雷射修整機，另參數(電壓、頻率、溫度)導入雷射修整機使雷射修整機讀取導入之參數，雷射修整機將電流或雷射光，以高溫方式將參數載入晶圓特定位置，將參數載入完成之晶片再進行檢測，燒錄檢測完成之晶圓，由托盤載出，載出之晶圓置放於特定位置進行貼片等一連串製程。 Referring to FIG. 5, the present invention uses a method to simplify the semiconductor wafer process. FIG. 5 is a schematic flow chart of a preferred embodiment of the method. In this way, the wafer is taken out from the wafers and placed on the wafer on the wafer inspection machine (Wafer Probe) in a flat manner, and the wafer is guided or in parallel by the wafer inspection machine tray. The method is to load the wafer into the detection chamber of the inspection machine, and the loaded wafer is electrically tested by a probe in the wafer inspection machine for each wafer on the effective area of the wafer loaded in the tray. In the case of electrical test, the wafer yield is judged. The yield judgment will record the wafer with good wafer electrical detection, and the voltage value will be proofed. The proofreading completed wafer and the voltage value data record will be stored. Enter the folder to save. According to another yield judgment, the wafer with poor wafer electrical detection is damaged and the damage annotation record is stored in the folder for storage. Some wafers with good electrical conductivity are tested for temperature, and the temperature test records are stored in a folder for storage. When the demand arises, the wafer is placed on the tray to load the wafer into the laser finisher, and the parameters (voltage, frequency, temperature) are imported into the laser trimmer to make the laser trimmer read and import the parameters, and the laser is trimmed. The machine applies current or laser light to the specific position of the wafer at a high temperature, loads the parameters into the completed wafer, and then tests the completed wafer, which is loaded by the tray, and the loaded wafer is placed. A series of processes such as patching at a specific location.

綜上所述，本發明係應用於半導體晶片之生產製程，其綜效顯著，不但可縮短整體半導體晶片規格修整時程，亦能提高匹配良率，亦能於生產實施時快速導入生產流程，且晶片電性、溫度特性經測試、驗證並加以儲 存。當生產實施時，即能將客戶不同規格需求之相關電性溫度、參數載入，具有可立即明顯的提升生產量，因此具有新穎性、進步性及產業利用性，符合發明之要件，爰依法提出申請，祈請 貴審查委員准予核定，至感德便。 In summary, the present invention is applied to a semiconductor wafer production process, and the comprehensive effect thereof is remarkable, which not only shortens the overall semiconductor wafer specification repairing time course, but also improves the matching yield, and can also quickly introduce the production process during production implementation. And the electrical and temperature characteristics of the wafer are tested, verified and stored. Save. When the production is implemented, it can load the relevant electrical temperature and parameters of different specifications of customers, and it can immediately increase the production volume obviously. Therefore, it has novelty, progress and industrial utilization, which meets the requirements of the invention. Make an application and ask your review board to approve the approval.

[習知] [知知]

S101~S110‧‧‧流程圖步驟說明 S101~S110‧‧‧ Flowchart Step Description

S201~S215‧‧‧流程圖步驟說明 S201~S215‧‧‧ Flowchart Step Description

[本發明] [this invention]

S301~S323‧‧‧流程圖步驟說明 S301~S323‧‧‧ Flowchart Step Description

S401~S406‧‧‧各個步驟流程說明 S401~S406‧‧‧ Description of each step process

S501~S503‧‧‧各個步驟流程說明 S501~S503‧‧‧ Description of each step process

圖1 半導體晶圓生產製作流程圖。 Figure 1 Flow chart of semiconductor wafer production.

圖2 習知半導體晶片修整流程圖。 Figure 2 shows a conventional semiconductor wafer trimming flow chart.

圖3 本發明半導體晶片修整改善流程圖(框線為改善區域)。 Figure 3 is a flow chart showing the improvement of the semiconductor wafer trimming of the present invention (the frame line is an improved region).

圖4 本發明半導體晶片修整改善描述方塊圖一。 Figure 4 is a block diagram of the semiconductor wafer trimming improvement of the present invention.

圖5 本發明半導體晶片修整改善描述方塊圖二。 Figure 5 is a block diagram of the semiconductor wafer trimming improvement of the present invention.

S501~S503‧‧‧各個步驟流程說明 S501~S503‧‧‧ Description of each step process

Claims (26)

一種電性調整可程式化記錄儲存實施方法，其特徵為：該方法係將半導體IC晶片電性修整(trim)參數儲存於特定位置，當製造需求產生時，可將儲存參數自儲存特定位置取出，並傳輸至具有參數載入功能之設備，該設備可將預儲之修整參數，依製造規格需求，快速載入生產指定位置實施。 An electrically adjustable programmable record storage implementation method is characterized in that: the method is to store the semiconductor trim chip electrical trim parameters in a specific position, and when the manufacturing requirements are generated, the storage parameters can be taken out from the storage specific location. And transferred to the device with parameter loading function, the device can quickly load the pre-stored trimming parameters into the production specified position according to the manufacturing specification requirements. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中參數包含有電壓、頻率、溫度單元(cell)參數。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the parameter comprises a voltage, a frequency, and a temperature cell parameter. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中修整(trim)方法可使用雷射、電流方式實施。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the trim method can be implemented using a laser or a current method. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中修整參數可以記錄、儲存、分類、寫入。 An electrical adjustment programmable record storage implementation method according to claim 1, wherein the trimming parameters can be recorded, stored, classified, and written. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置可包含一屬性檔(Property file)，可用以儲存該電性資料之參數。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein storing the specific location may include a property file, which may be used to store parameters of the electrical data. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存參數包含電壓、溫度、頻率參數、時間參數。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storage parameter comprises a voltage, a temperature, a frequency parameter, and a time parameter. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置為具有磁軌儲存功能之設備。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storage of the specific location is a device having a magnetic track storage function. 如申請專利範圍第1項所述之一種電性調整可程式化 記錄儲存實施方法，其中儲存特定位置為具有光儲存功能設備。 An electrical adjustment as described in item 1 of the patent application can be programmed A record storage implementation method in which a specific location is stored as a device having an optical storage function. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置為具有記錄讀寫功能之儲存設備。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storage location is a storage device having a record reading and writing function. 如申請專利範圍第5項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置記錄功能包含有一載入(Load)功能。 An electrically adjustable programmable record storage implementation method according to claim 5, wherein the storing the specific location recording function comprises a load function. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置記錄功能包含有一***(Insert)功能。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storing the specific location recording function includes an Insert function. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置記錄功能包含有一修改(Update)功能。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storing the specific location recording function includes an update function. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置記錄功能包含有一刪除(Delete)功能。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the storing the specific location recording function includes a delete function. 如申請專利範圍第3項所述之一種電性調整可程式化記錄儲存實施方法，其中溫度參數修整(trim)為對半導體晶圓面積上之晶粒電性進行修整(trim)。 An electrically adjustable programmable record storage implementation method according to claim 3, wherein the temperature parameter trim is to trim the die electrical properties on the semiconductor wafer area. 如申請專利範圍第3項所述之一種電性調整可程式化記錄儲存實施方法，其中電壓參數修整(trim)，為對半導體晶圓面積上之晶粒電性進行修整(trim)。 An electrically adjustable programmable record storage implementation method according to claim 3, wherein the voltage parameter trimming is to trim the grain electrical properties on the semiconductor wafer area. 如申請專利範圍第3項所述之一種電性調整可程式化記錄儲存實施方法，其中頻率參數修整(trim)，係對半導體晶圓面積上之晶粒電性進行修整(trim)。 An electrically adjustable programmable record storage implementation method according to claim 3, wherein the frequency parameter trimming trims the grain electrical properties on the semiconductor wafer area. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置記錄功能包含有記錄異動開始/異動結束功能。 An electrical adjustment programmable record storage implementation method according to claim 1, wherein the storage specific location recording function includes a recording transaction start/transaction end function. 如申請專利範圍第1項所述之一種電性調整可程式化記錄儲存實施方法，其中儲存特定位置之參數具有排序之功能。 An electrically adjustable programmable record storage implementation method according to claim 1, wherein the parameter storing the specific location has a sorting function. 一種電性調整可程式化記錄儲存實施方法，其方法包括下列之步驟：將晶圓置入晶圓檢測機(Wafer probe)，由晶圓檢測機以探針(probe)量測晶圓內部電性及良率，並將量測及測試之各種參數予以分類、記錄、註記，再將參數分類儲存於特定儲存位置；製程作業實施時，將晶圓取出後載入具修整(trim)功能之機台，依製程功能需求自特定儲存位置存取所需參數，並將需求參數按設定修整方式載入半導體晶片。 An electrically adjustable programmable record storage implementation method includes the steps of: placing a wafer into a wafer inspection machine (Wafer probe), and measuring a wafer internal power by a wafer inspection machine with a probe Sex and yield, and classify, record, and record various parameters of measurement and test, and then store the parameters in a specific storage location; when the process is implemented, the wafer is taken out and loaded into a trim function. The machine accesses the required parameters from a specific storage location according to the process function requirements, and loads the demand parameters into the semiconductor wafer according to the set trimming mode. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測晶圓所得之溫度、電壓、頻率之電性參數，其電壓參數具有儲存、標記、修改功能。 An electrically adjustable programmable record storage implementation method according to claim 19, wherein a wafer detector measures the temperature, voltage, and frequency electrical parameters obtained by the wafer, and the voltage parameter thereof. With storage, marking, modification. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測晶圓所得之溫度、電壓、頻率之電性參數，其溫度參數具有儲存、標記、修改功能。 An electrically adjustable programmable record storage and storage method according to claim 19, wherein a wafer detector measures a temperature parameter of a temperature, a voltage, and a frequency obtained by the wafer, and a temperature parameter thereof. With storage, marking, modification. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測晶圓所得之溫度、電壓、頻率之電性參數，其頻率參數具有儲存、標記、修改功能。 An electrically adjustable programmable record storage implementation method according to claim 19, wherein a wafer detector measures a temperature parameter of a temperature, a voltage, and a frequency obtained by the wafer, and a frequency parameter thereof. With storage, marking, modification. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測包含為對半導體晶圓上之晶粒進行電壓(Voltage)測試。 An electrically adjustable programmable record storage implementation method according to claim 19, wherein the wafer inspection (Wafer probe) measurement comprises performing a voltage test on the die on the semiconductor wafer. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測，包含對半導體晶圓面積上之晶粒，進行溫度(temperature)測試。 An electrically adjustable programmable record storage implementation method according to claim 19, wherein the wafer detector measures the temperature of the crystal grains on the semiconductor wafer area. test. 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)量測，包含對半導體晶圓面積上之晶粒進行頻率(Frequency)測試。 An electrically adjustable programmable record storage implementation method according to claim 19, wherein the wafer inspection (Wafer probe) measurement comprises performing frequency testing on the die on the semiconductor wafer area. . 如申請專利範圍第19項所述之一種電性調整可程式化記錄儲存實施方法，其中晶圓檢測機(Wafer probe)檢測之半導體晶圓，若晶圓面積上之晶粒電性發生損毀，該損毀位置會予以註記並記錄於儲存特定位置。 The method for implementing an electrically adjustable programmable record storage method according to claim 19, wherein the semiconductor wafer detected by the wafer detector is damaged if the crystal quality of the wafer area is damaged. The location of the damage is noted and recorded in a specific location.
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