TWI425898B - Method for fabricating wiring structure of circuit board - Google Patents
Method for fabricating wiring structure of circuit board Download PDFInfo
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- TWI425898B TWI425898B TW96144304A TW96144304A TWI425898B TW I425898 B TWI425898 B TW I425898B TW 96144304 A TW96144304 A TW 96144304A TW 96144304 A TW96144304 A TW 96144304A TW I425898 B TWI425898 B TW I425898B
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Description
本發明是有關於一種線路板(Circuit Board)的製程，且特別是有關於一種線路板的線路結構的製造方法。The present invention relates to a circuit board process, and more particularly to a method of fabricating a circuit board circuit structure.
現今的線路板科技已發展出內埋式線路板(embedded circuit board)，而這種線路板在其表面的線路是埋入於介電層中，並非突出於介電層的表面。Today's circuit board technology has developed an embedded circuit board in which the lines on the surface are buried in the dielectric layer, not protruding from the surface of the dielectric layer.
圖1A至圖1E是根據習知一種內埋式線路板的製造方法所繪示的流程示意圖。請先參閱圖1A，習知的內埋式線路板的製造方法包括以下步驟。首先，在一承載基板112a上依序形成一銅金屬層114a以及一銅線路層116a，以形成一線路承載基板110a。1A to FIG. 1E are schematic flow diagrams illustrating a method of manufacturing a buried circuit board according to a conventional method. Referring first to FIG. 1A, a conventional method of manufacturing a buried wiring board includes the following steps. First, a copper metal layer 114a and a copper wiring layer 116a are sequentially formed on a carrier substrate 112a to form a wiring carrier substrate 110a.
請參閱圖1B，接著，藉由一膠片(prepreg)，將線路承載基板110a壓合於另一個線路承載基板110b上，其中線路承載基板110b的結構與線路承載基板110a相同。詳言之，線路承載基板110b同樣也包括一承載基板112b、一銅線路層116b以及一位於銅線路層116b與承載基板112b之間的銅金屬層114b。在線路承載基板110a壓合於線路承載基板110b上之後，膠片會固化而形成一介電層120。Referring to FIG. 1B, the line carrier substrate 110a is then pressed onto the other line carrier substrate 110b by a prepreg, wherein the line carrier substrate 110b has the same structure as the line carrier substrate 110a. In detail, the line carrier substrate 110b also includes a carrier substrate 112b, a copper wiring layer 116b, and a copper metal layer 114b between the copper wiring layer 116b and the carrier substrate 112b. After the line carrier substrate 110a is pressed onto the line carrier substrate 110b, the film is cured to form a dielectric layer 120.
請參閱圖1B與圖1C，接著，移除承載基板112a與承載基板112b，並留下銅金屬層114a、114b以及銅線路層116a、116b。之後，依序進行機械鑽孔與通孔電鍍(Plating Through Hole,PTH)，以形成導電通孔結構(conductive through hole structure)T1。當形成導電通孔結構T1時，在銅金屬層114a與銅金屬層114b上會分別形成一銅電鍍層130a與一銅電鍍層130b。Referring to FIG. 1B and FIG. 1C, the carrier substrate 112a and the carrier substrate 112b are removed, and the copper metal layers 114a, 114b and the copper wiring layers 116a, 116b are left. Thereafter, mechanical drilling and through-hole plating (PTH) are sequentially performed to form a conductive through hole structure T1. When the conductive via structure T1 is formed, a copper plating layer 130a and a copper plating layer 130b are formed on the copper metal layer 114a and the copper metal layer 114b, respectively.
請參閱圖1C與圖1D，接著，進行蝕刻製程，以移除銅電鍍層130a、130b以及銅金屬層114a、114b。之後，填充油墨材料140於導電通孔結構T1內。Referring to FIG. 1C and FIG. 1D, an etching process is then performed to remove the copper plating layers 130a, 130b and the copper metal layers 114a, 114b. Thereafter, the ink material 140 is filled in the conductive via structure T1.
請參閱圖1D與圖1E，在填充油墨材料140之後，形成一防焊層150a於銅線路層116a上，形成一防焊層150b於銅線路層116b上。如此，一種內埋式線路板100已經製造完成。Referring to FIG. 1D and FIG. 1E, after filling the ink material 140, a solder resist layer 150a is formed on the copper wiring layer 116a to form a solder resist layer 150b on the copper wiring layer 116b. As such, an embedded circuit board 100 has been manufactured.
然而，在移除銅電鍍層130a、130b以及銅金屬層114a、114b的過程中，由於此移除的方法是採用蝕刻製程，因此銅線路層116a與116b的表面會變的很粗糙(如圖1D與圖1E所示)，以致於銅線路層116a與116b二者的厚度變的不均勻。這樣會嚴重降低內埋式線路板100在電性方面的品質，並造成良率降低。However, in the process of removing the copper plating layers 130a, 130b and the copper metal layers 114a, 114b, since the removal method is an etching process, the surfaces of the copper wiring layers 116a and 116b become rough (see figure). 1D and FIG. 1E), so that the thickness of both of the copper wiring layers 116a and 116b becomes uneven. This will seriously degrade the electrical quality of the buried wiring board 100 and cause a decrease in yield.
本發明是提供一種線路板的線路製造方法，以提高線路板的良率。The present invention provides a circuit manufacturing method for a circuit board to improve the yield of the circuit board.
本發明提出一種線路板的線路結構的製造方法。首先，形成一線路承載基板，其包括一承載基板、一第一線路層以及一位於承載基板與第一線路層之間的防蝕阻礙層。接著壓合該線路承載基板於一絕緣層上，其中絕緣層配置於一第二線路層上，且第一線路層與第二線路層分別位於絕緣層的相對二側。在壓合線路承載基板之後，形成一導電連接結構於絕緣層中以及移除承載基板。導電連接結構連接於第一線路層與第二線路層之間。The invention provides a method of manufacturing a circuit structure of a circuit board. First, a line carrier substrate is formed, which includes a carrier substrate, a first circuit layer, and an anti-corrosion barrier layer between the carrier substrate and the first circuit layer. Then, the circuit carrier substrate is pressed onto an insulating layer, wherein the insulating layer is disposed on a second circuit layer, and the first circuit layer and the second circuit layer are respectively located on opposite sides of the insulating layer. After the bonding line carries the substrate, a conductive connection structure is formed in the insulating layer and the carrier substrate is removed. The conductive connection structure is connected between the first circuit layer and the second circuit layer.
在本發明之一實施例中，上述線路板的線路結構的製造方法更包括移除防蝕阻礙層。In an embodiment of the invention, the method of fabricating the wiring structure of the circuit board further includes removing the anti-corrosion barrier layer.
在本發明之一實施例中，上述移除防蝕阻礙層的方法包括部分移除防蝕阻礙層。In an embodiment of the invention, the method of removing the anti-corrosion barrier layer includes partially removing the anti-corrosion barrier layer.
在本發明之一實施例中，上述承載基板是由單一材料所製成。In an embodiment of the invention, the carrier substrate is made of a single material.
在本發明之一實施例中，上述承載基板包括一第一材料層與一第二材料層，而第一材料層位於第二材料層與防蝕阻礙層之間。移除承載基板的方法包括：在形成導電連接結構以前，移除第二材料層。在形成導電連接結構以後，蝕刻第一材料層。In an embodiment of the invention, the carrier substrate comprises a first material layer and a second material layer, and the first material layer is located between the second material layer and the corrosion inhibiting layer. The method of removing the carrier substrate includes removing the second material layer prior to forming the conductive connection structure. After forming the conductive connection structure, the first material layer is etched.
在本發明之一實施例中，上述形成導電連接結構的方法包括：對第一線路層進行一鑽孔製程，以形成一盲孔，其中盲孔從第一線路層延伸至第二線路層。接著，形成一導電盲孔結構於盲孔內，其中導電盲孔結構電性連接於第一線路層與第二線路層之間。In an embodiment of the invention, the method of forming the conductive connection structure includes: performing a drilling process on the first circuit layer to form a blind via, wherein the blind via extends from the first circuit layer to the second circuit layer. Then, a conductive blind via structure is formed in the blind via, wherein the conductive blind via structure is electrically connected between the first wiring layer and the second wiring layer.
在本發明之一實施例中，上述鑽孔製程為雷射鑽孔製程(laser drilling)。In an embodiment of the invention, the drilling process is a laser drilling process.
在本發明之一實施例中，上述第一線路層包括至少一環形導電圖案，而盲孔從環形導電圖案延伸至第二線路層。In an embodiment of the invention, the first circuit layer includes at least one annular conductive pattern, and the blind via extends from the annular conductive pattern to the second wiring layer.
在本發明之一實施例中，上述防蝕阻礙層的材質是選自於由鎳、錫、金、鉻以及鈦所組成的族群。In an embodiment of the invention, the material of the corrosion inhibiting layer is selected from the group consisting of nickel, tin, gold, chromium, and titanium.
在本發明之一實施例中，上述防蝕阻礙層的厚度介於0.1微米至10微米之間。In an embodiment of the invention, the anti-corrosion barrier layer has a thickness of between 0.1 micrometers and 10 micrometers.
在本發明之一實施例中，上述形成線路承載基板的方法包括：在承載基板上形成一圖案化感光層，其局部暴露承載基板的表面。之後，形成防蝕阻礙層於承載基板上，其中防蝕阻礙層覆蓋圖案化感光層所局部暴露的承載基板的表面。接著，形成第一線路層，其中第一線路層覆蓋防蝕阻礙層。之後，移除圖案化感光層。In one embodiment of the invention, the method of forming a line carrier substrate includes forming a patterned photosensitive layer on the carrier substrate that partially exposes a surface of the carrier substrate. Thereafter, an anti-corrosion barrier layer is formed on the carrier substrate, wherein the anti-corrosion barrier layer covers the surface of the carrier substrate partially exposed by the patterned photosensitive layer. Next, a first wiring layer is formed, wherein the first wiring layer covers the anti-corrosion barrier layer. Thereafter, the patterned photosensitive layer is removed.
在本發明之一實施例中，上述形成線路承載基板的方法包括：在承載基板上形成一防蝕阻礙層，其中防蝕阻礙層全面性地覆蓋承載基板。接著，形成第一線路層於防蝕阻礙層上。In an embodiment of the invention, the method for forming a line carrier substrate includes: forming an anti-corrosion barrier layer on the carrier substrate, wherein the anti-corrosion barrier layer comprehensively covers the carrier substrate. Next, a first wiring layer is formed on the anti-corrosion barrier layer.
藉由上述防蝕阻礙層，第一線路層得以受到保護，以避免第一線路層的表面變的粗糙。相較於習知技術而言，本發明能使第一線路層的厚度均勻，並且提高線路板在電性方面的品質，以提高線路板的良率。With the above-described anti-corrosion barrier layer, the first wiring layer is protected from being roughened by the surface of the first wiring layer. Compared with the prior art, the present invention can make the thickness of the first circuit layer uniform, and improve the electrical quality of the circuit board to improve the yield of the circuit board.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉一些實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features, and advantages of the present invention will become more apparent and understood.
圖2A至圖2J是根據本發明第一實施例的線路板的線路結構的製造方法所繪示的流程示意圖。請先參閱圖2D，首先，形成一線路承載基板200。線路承載基板200包括一承載基板210、一防蝕阻礙層220以及一第一線路層230，而防蝕阻礙層220位於承載基板210與第一線路層230之間。2A to 2J are schematic flow charts showing a method of manufacturing a circuit structure of a circuit board according to a first embodiment of the present invention. Referring first to FIG. 2D, first, a line carrier substrate 200 is formed. The circuit carrier substrate 200 includes a carrier substrate 210, an anti-corrosion barrier layer 220, and a first wiring layer 230, and the anti-corrosion barrier layer 220 is located between the carrier substrate 210 and the first wiring layer 230.
承載基板210可以是僅由單一材料所製成，例如承載基板210可以是單一材質的金屬板、陶瓷板或塑膠板。當然，承載基板210亦可以是由二種或二種以上的材料所製成的複合板。The carrier substrate 210 may be made of only a single material. For example, the carrier substrate 210 may be a single material metal plate, ceramic plate or plastic plate. Of course, the carrier substrate 210 may also be a composite board made of two or more materials.
在本實施例中，承載基板210為一種雙層材料的複合板，且包括一第一材料層212a以及一第二材料層212b，其中第一材料層212a位於防蝕阻礙層220與第二材料層212b之間。第一材料層212a的材質可以是金屬，例如銅、鋁或其他適當的金屬材料，且第一材料層212a的材質與防蝕阻礙層220不同。In this embodiment, the carrier substrate 210 is a composite material of a two-layer material, and includes a first material layer 212a and a second material layer 212b, wherein the first material layer 212a is located in the corrosion inhibiting layer 220 and the second material layer. Between 212b. The material of the first material layer 212a may be a metal such as copper, aluminum or other suitable metal material, and the material of the first material layer 212a is different from the corrosion inhibiting layer 220.
第二材料層212b可以是金屬，或者是陶瓷、高分子材料或其他適當的非金屬材料。當第二材料層212b為高分子材料時，第二材料層212b可以是聚醯亞胺(polyimide,PI)。The second material layer 212b can be a metal, or a ceramic, polymeric material, or other suitable non-metallic material. When the second material layer 212b is a polymer material, the second material layer 212b may be polyimide (PI).
雖然圖2D所示的承載基板210僅包括第一材料層212a與第二材料層212b，但是在其他未繪的實施例中，承載基板210更可以包括一第三材料層，其配置於第一材料層212a與第二材料層212b之間，而且第三材料層的材質可以是高分子材料，例如聚醯亞胺。因此，圖2A至圖2J所示的承載基板210僅為舉例說明，在此強調非限定本發明。Although the carrier substrate 210 shown in FIG. 2D includes only the first material layer 212a and the second material layer 212b, in other unillustrated embodiments, the carrier substrate 210 may further include a third material layer disposed on the first The material layer 212a and the second material layer 212b, and the material of the third material layer may be a polymer material such as polyimide. Therefore, the carrier substrate 210 shown in FIGS. 2A to 2J is merely illustrative, and the present invention is not limited thereto.
防蝕阻礙層220的材質可以是金屬，且與第一線路層230的材質不同。詳言之，第一線路層230的材質可以是銅、鋁或其他適當的導電材料，而防蝕阻礙層220可以是鎳、錫、金、鉻、鈦或其他低化學活性的金屬材料，或者也可以是這些金屬材料的任意組合。此外，防蝕阻礙層220的厚度可以介於0.1微米至10微米之間。當然，端視產品的需求，防蝕阻礙層220的厚度也可以超過10微米。The material of the anti-corrosion barrier layer 220 may be metal and different from the material of the first circuit layer 230. In detail, the material of the first circuit layer 230 may be copper, aluminum or other suitable conductive material, and the anti-corrosion barrier layer 220 may be nickel, tin, gold, chromium, titanium or other low-chemically active metal materials, or It can be any combination of these metallic materials. Further, the thickness of the anti-corrosion barrier layer 220 may be between 0.1 micrometers and 10 micrometers. Of course, the thickness of the anti-corrosion barrier layer 220 may also exceed 10 microns depending on the requirements of the product.
有關線路承載基板200，其形成方法有多種，而以下將配合圖2A至圖2D以詳細說明其中一種線路承載基板200的形成方法。There are various methods for forming the line carrier substrate 200, and a method of forming one of the line carrier substrates 200 will be described in detail below with reference to FIGS. 2A to 2D.
請參閱圖2A，首先，在承載基板210上形成一圖案化感光層240，其局部暴露承載基板210的表面210a。在本實施例中，圖案化感光層240局部暴露位於第二材料層212b上的第一材料層212a，而圖案化感光層240可經由微影製程而形成，且可以是濕膜(liquid film)或乾膜(dry film)。Referring to FIG. 2A, first, a patterned photosensitive layer 240 is formed on the carrier substrate 210, which partially exposes the surface 210a of the carrier substrate 210. In this embodiment, the patterned photosensitive layer 240 partially exposes the first material layer 212a on the second material layer 212b, and the patterned photosensitive layer 240 may be formed through a lithography process, and may be a liquid film. Or dry film.
請參閱圖2B，接著，形成防蝕阻礙層220於承載基板210上，其中防蝕阻礙層220覆蓋圖案化感光層240所局部暴露的承載基板210的表面210a。防蝕阻礙層220可以採用電鍍法、無電電鍍法(electroless plating)或化學氣相沉積法(Chemical Vapor Deposition,CVD)來形成，或者也可以採用蒸鍍法、濺鍍法或其他物理氣相沉積法(Physical Vapor Deposition,PVD)來形成。Referring to FIG. 2B, an anti-corrosion barrier layer 220 is formed on the carrier substrate 210, wherein the anti-corrosion barrier layer 220 covers the surface 210a of the carrier substrate 210 partially exposed by the patterned photosensitive layer 240. The anti-corrosion barrier layer 220 may be formed by electroplating, electroless plating, or chemical vapor deposition (CVD), or may be vapor deposition, sputtering, or other physical vapor deposition. (Physical Vapor Deposition, PVD) to form.
請參閱圖2C，接著，形成第一線路層230。第一線路層230覆蓋防蝕阻礙層220，而形成第一線路層230的方法可以與形成防蝕阻礙層220的方法相同。請參閱圖2C與圖2D，在第一線路層230形成之後，移除圖案化感光層240。如此，線路承載基板200得以形成。Referring to FIG. 2C, next, a first wiring layer 230 is formed. The first wiring layer 230 covers the anti-corrosion barrier layer 220, and the method of forming the first wiring layer 230 may be the same as the method of forming the anti-corrosion barrier layer 220. Referring to FIG. 2C and FIG. 2D, after the first wiring layer 230 is formed, the patterned photosensitive layer 240 is removed. As such, the line carrier substrate 200 is formed.
請參閱圖2E，在形成線路承載基板200之後，壓合線路承載基板200於一絕緣層310上，其中絕緣層310配置於一第二線路層320上，且第一線路層230與第二線路層320分別位於絕緣層310的相對二側。Referring to FIG. 2E, after the line carrier substrate 200 is formed, the bonding line carrier substrate 200 is disposed on an insulating layer 310, wherein the insulating layer 310 is disposed on a second wiring layer 320, and the first circuit layer 230 and the second line are disposed. The layers 320 are respectively located on opposite sides of the insulating layer 310.
圖2E所示的第二線路層320可以是線路板的內層線路(inner circuit layer)。不過，在其他未繪示實施例中，第二線路層320也可以是線路板的外層線路，而第一線路層230與第二線路層320可以是雙面線路板(double sided circuit board)所具有的二層線路。因此，圖2A至圖2J所示的第二線路層320僅為舉例說明，並非限定本發明。The second circuit layer 320 shown in FIG. 2E may be an inner circuit layer of the wiring board. However, in other embodiments not shown, the second circuit layer 320 may also be an outer layer of the circuit board, and the first circuit layer 230 and the second circuit layer 320 may be double sided circuit boards. Has a two-layer line. Therefore, the second circuit layer 320 shown in FIGS. 2A to 2J is merely illustrative and does not limit the present invention.
絕緣層310可以根據不同的產品設計，而具有不同的厚度。當絕緣層310必需要具有較薄的厚度時，例如在10密爾(mil)以下，絕緣層310可以是由半固化的膠片所形成。反之，當絕緣層310必需要具有較厚的厚度時，例如超過10密爾，絕緣層310可以包括半固化的膠片以及空白核心層(blank core)。The insulating layer 310 can be designed to have different thicknesses depending on different products. When the insulating layer 310 necessarily needs to have a relatively thin thickness, for example, 10 mils or less, the insulating layer 310 may be formed of a semi-cured film. Conversely, when the insulating layer 310 necessarily needs to have a relatively thick thickness, such as more than 10 mils, the insulating layer 310 may include a semi-cured film and a blank core.
請參閱圖2E與圖2F，接著，可移除承載基板210。詳細而言，可移除承載基板210的一部分，例如移除第二材料層212b。舉例而言，由於第二材料層212b可以是金屬，因此第二材料層212b可以採用蝕刻製程來移除。此外，第二材料層212b還可以是塑膠或高分子材料，所以第二材料層212b也可以採用剝離或其他方式來移除。Referring to FIG. 2E and FIG. 2F, the carrier substrate 210 can then be removed. In detail, a portion of the carrier substrate 210 can be removed, such as removing the second material layer 212b. For example, since the second material layer 212b may be metal, the second material layer 212b may be removed using an etching process. In addition, the second material layer 212b may also be a plastic or polymer material, so the second material layer 212b may also be removed by peeling or other means.
請參閱圖2F至圖2H，之後，形成一導電連接結構330於絕緣層310中，如圖2H所示。導電連接結構330連接於第一線路層230與第二線路層320之間。在圖2H所示的實施例中，導電連接結構330是一種導電盲孔結構(conductive blind via structure)，但是在其他未繪示的實施例中，導電連接結構330也可以是導電通孔結構。因此，圖2A至圖2J所示的導電連接結構330並非用以限定本發明。Referring to FIG. 2F to FIG. 2H, a conductive connection structure 330 is formed in the insulating layer 310, as shown in FIG. 2H. The conductive connection structure 330 is connected between the first circuit layer 230 and the second circuit layer 320. In the embodiment shown in FIG. 2H, the conductive connection structure 330 is a conductive blind via structure, but in other embodiments not shown, the conductive connection structure 330 may also be a conductive via structure. Therefore, the conductive connection structure 330 shown in FIGS. 2A to 2J is not intended to limit the present invention.
有關形成導電連接結構330的方法，其具有多種，而以下將配合圖2F至圖2H介紹其中一種形成導電連接結構330的方法。然而，需事先說明的是，圖2F至圖2H所揭露的形成導電連接結構330的方法只是用來舉例說明，而非限定本發明。There are various methods for forming the conductive connection structure 330, and a method of forming the conductive connection structure 330 will be described below with reference to FIGS. 2F to 2H. However, it should be noted that the method of forming the conductive connection structure 330 disclosed in FIG. 2F to FIG. 2H is for illustrative purposes only and is not intended to limit the invention.
請參閱圖2F與圖2G，首先，對第一線路層230進行一鑽孔製程，以形成至少一盲孔B1，其中盲孔B1從第一線路層230延伸至第二線路層320，且盲孔B1會局部暴露第二線路層320。在本實施例中，第一線路層230可包括至少一環形導電圖案232、多條走線234以及至少一接墊236，而上述鑽孔製程為雷射鑽孔製程，其中圖2F亦繪示出環形導電圖案232的俯視圖。Referring to FIG. 2F and FIG. 2G, first, a drilling process is performed on the first circuit layer 230 to form at least one blind via B1, wherein the blind via B1 extends from the first wiring layer 230 to the second wiring layer 320, and is blind. The hole B1 partially exposes the second wiring layer 320. In this embodiment, the first circuit layer 230 may include at least one annular conductive pattern 232, a plurality of traces 234, and at least one pad 236, and the drilling process is a laser drilling process, wherein FIG. 2F also shows A top view of the annular conductive pattern 232 is taken out.
承上述，當進行雷射鑽孔製程時，可先將雷射對準環形導電圖案232中間區域，如圖2F中的虛線所圍繞的區域。接著，發出雷射光束，將第一材料層212a以及絕緣層310熔燒以形成盲孔B1，其中盲孔B1從環形導電圖案232延伸至第二線路層320。In the above, when performing the laser drilling process, the laser may be first aligned with the intermediate portion of the annular conductive pattern 232, as shown by the dotted line in FIG. 2F. Next, a laser beam is emitted to melt the first material layer 212a and the insulating layer 310 to form a blind via B1, wherein the blind via B1 extends from the annular conductive pattern 232 to the second wiring layer 320.
在形成盲孔B1之後，盲孔B1的底部會殘留一些膠渣，而這些膠渣會降低第一線路層230與第二線路層320之間的電性連接的品質。因此，在盲孔B1形成之後，可以對盲孔B1進行去膠渣(desmear)。如此，可以提高第一線路層230與第二線路層320之間的電性連接的品質。After the blind holes B1 are formed, some of the glue remains at the bottom of the blind holes B1, and these slags reduce the quality of the electrical connection between the first circuit layer 230 and the second circuit layer 320. Therefore, after the blind hole B1 is formed, the blind hole B1 can be desmear. In this way, the quality of the electrical connection between the first circuit layer 230 and the second circuit layer 320 can be improved.
請參閱圖2G與圖2H，接著，形成導電盲孔結構(即導電連接結構330)於盲孔B1內，其中導電連接結構330的材質可以與第一線路層230相同。形成導電連接結構330的方法可包括電鍍法，而當形成導電連接結構330時，同時也會形成一電鍍金屬層340於第一材料層212a上。此外，形成導電連接結構330的另一種方法可包括填塞導電膠或導電膏，例如銅膠、銅膏、碳膠、碳膏、具導電性的高分子導電材料或其他具有流動性及可塑性的導電材料。當形成導電連接結構330後，再進行電鍍製程以形成一電鍍金屬層340於第一材料層212a上。Referring to FIG. 2G and FIG. 2H , a conductive via structure (ie, the conductive connection structure 330 ) is formed in the blind via B1 , and the conductive connection structure 330 may be made of the same material as the first wiring layer 230 . The method of forming the conductive connection structure 330 may include an electroplating method, and when the conductive connection structure 330 is formed, a plated metal layer 340 is also formed on the first material layer 212a. In addition, another method of forming the conductive connection structure 330 may include filling a conductive paste or a conductive paste, such as copper paste, copper paste, carbon paste, carbon paste, conductive polymer conductive material or other conductive and fluid conductive. material. After forming the conductive connection structure 330, an electroplating process is performed to form a plated metal layer 340 on the first material layer 212a.
值得一提的是，上述鑽孔製程也可以是機械鑽孔製程。詳言之，若絕緣層310的厚度太厚，例如超過100微米，則可以利用機械鑽孔製程來形成盲孔B1。另外，導電連接結構330也可以是導電通孔結構。當上述鑽孔製程為機械鑽孔製程時，導電連接結構330可以在不需要環形導電圖案232的條件下，透過機械鑽孔製程而形成。因此，圖2F至圖2H所揭露的形成導電盲孔結構330的方法只是舉例說明，並不是要限定本發明。It is worth mentioning that the above drilling process can also be a mechanical drilling process. In detail, if the thickness of the insulating layer 310 is too thick, for example, more than 100 micrometers, a mechanical drilling process can be utilized to form the blind via B1. In addition, the conductive connection structure 330 may also be a conductive via structure. When the drilling process is a mechanical drilling process, the conductive connection structure 330 can be formed by a mechanical drilling process without requiring the annular conductive pattern 232. Therefore, the method of forming the conductive blind via structure 330 disclosed in FIGS. 2F to 2H is merely illustrative and is not intended to limit the present invention.
請參與圖2H與圖2I，在形成導電連接結構330之後，蝕刻電鍍金屬層340與第一材料層212a，以完全移除承載基板210，並使防蝕阻礙層220裸露出來。由於第一材料層212a的材質與防蝕阻礙層220的材質不同，因此當蝕刻第一材料層212a時，防蝕阻礙層220可以保護第一線路層230免受蝕刻藥劑的侵蝕，以避免第一線路層230的表面變的粗糙。2H and FIG. 2I, after forming the conductive connection structure 330, the plated metal layer 340 and the first material layer 212a are etched to completely remove the carrier substrate 210 and expose the anti-corrosion barrier layer 220. Since the material of the first material layer 212a is different from the material of the anti-corrosion barrier layer 220, when the first material layer 212a is etched, the anti-corrosion barrier layer 220 can protect the first circuit layer 230 from etching agents to avoid the first line. The surface of layer 230 becomes rough.
請參閱圖2I與圖2J，接著，移除防蝕阻礙層220。防蝕阻礙層220可以部分移除，即保留在接墊236上的部分防蝕阻礙層220。當然，視產品的設計與需求，防蝕阻礙層220也可以全部去除。Referring to FIG. 2I and FIG. 2J, the anti-corrosion barrier layer 220 is removed. The anti-corrosion barrier layer 220 may be partially removed, that is, a portion of the anti-corrosion barrier layer 220 remaining on the pads 236. Of course, the anti-corrosion barrier layer 220 can also be completely removed depending on the design and requirements of the product.
防蝕阻礙層220的材質可以是鎳、錫、金、鉻、鈦或其他低化學活性的金屬材料，或者也可以是這些金屬材料的任意組合。當防蝕阻礙層220的材質為鎳時，可以直接在接墊236上鍍金以進行表面處理。這樣可以增加接墊236的抗氧化能力。當防蝕阻礙層220的材質為錫時，防蝕阻礙層220可以應用在無鉛金屬的表面處理。由此可知，部分保留的防蝕阻礙層220能應用在後續的表面處理中。The material of the anti-corrosion barrier layer 220 may be nickel, tin, gold, chromium, titanium or other low-chemically active metal materials, or may be any combination of these metal materials. When the material of the anti-corrosion barrier layer 220 is nickel, gold may be directly plated on the pad 236 for surface treatment. This can increase the oxidation resistance of the pad 236. When the material of the anti-corrosion barrier layer 220 is tin, the anti-corrosion barrier layer 220 can be applied to the surface treatment of the lead-free metal. It can be seen that the partially retained corrosion inhibiting layer 220 can be applied in subsequent surface treatments.
之後，可以形成一防焊層350於第一線路層230與絕緣層310上，而一種線路板300基本上已製造完成。Thereafter, a solder resist layer 350 may be formed on the first wiring layer 230 and the insulating layer 310, and a wiring board 300 is substantially completed.
值得一提的是，本實施例的線路板300可以應用在晶片(chip)的封裝製程中，即線路板300可以是IC載板。當然，線路板300也可以是用來組裝電容、電阻、電感及晶片封裝體(chip package)等電子元件。因此，本實施例的線路板300可以應用在一階、二階或二階以上的封裝製程。It is worth mentioning that the circuit board 300 of the present embodiment can be applied in a chip packaging process, that is, the circuit board 300 can be an IC carrier board. Of course, the circuit board 300 can also be used to assemble electronic components such as capacitors, resistors, inductors, and chip packages. Therefore, the circuit board 300 of the present embodiment can be applied to a first, second or second order packaging process.
圖3A至圖3F是根據本發明第二實施例的線路板的線路結構的製造方法所繪示的流程示意圖。請參閱圖3A，首先，在一承載基板410上形成一防蝕阻礙層420，其中防蝕阻礙層420全面性地覆蓋承載基板410，而防蝕阻礙層420的材質與厚度可以與第一實施例的防蝕阻礙層220相同。3A to 3F are schematic flow charts showing a method of manufacturing a circuit structure of a circuit board according to a second embodiment of the present invention. Referring to FIG. 3A, first, an anti-corrosion barrier layer 420 is formed on a carrier substrate 410, wherein the anti-corrosion barrier layer 420 comprehensively covers the carrier substrate 410, and the material and thickness of the anti-corrosion barrier layer 420 can be the same as that of the first embodiment. The barrier layer 220 is the same.
承載基板410的結構可以與第一實施例的承載基板210相同，即承載基板410可以是二種材料所製成的複合板。當然，承載基板410也可以是僅由單一材料所製成，例如承載基板410可以是單一材質的金屬板、陶瓷板或塑膠板，或者，承載基板410亦可以是由二種以上的材料所製成的複合板。The structure of the carrier substrate 410 may be the same as that of the carrier substrate 210 of the first embodiment, that is, the carrier substrate 410 may be a composite board made of two materials. Of course, the carrier substrate 410 may be made of only a single material. For example, the carrier substrate 410 may be a single material metal plate, a ceramic plate or a plastic plate, or the carrier substrate 410 may be made of two or more materials. Into the composite board.
請參閱圖3B，接著，形成第一線路層430於防蝕阻礙層420上。第一線路層430的形成方法與第一實施例相同，故不再重複敘述。形成第一線路層430之後，一種線路承載基板400基本上已形成。Referring to FIG. 3B, next, a first wiring layer 430 is formed on the anti-corrosion barrier layer 420. The method of forming the first wiring layer 430 is the same as that of the first embodiment, and therefore the description will not be repeated. After the first wiring layer 430 is formed, a wiring carrier substrate 400 is substantially formed.
請參閱圖3C，接著，在形成線路承載基板400之後，壓合線路承載基板400於一絕緣層510上，其中絕緣層510配置於一第二線路層520上，且第一線路層430與第二線路層520分別位於絕緣層510的相對二側。在本實施例中，第一線路層430可包括至少一環形導電圖案432、多條走線434以及至少一接墊436，其中圖3C亦繪示出環形導電圖案432的俯視圖。Referring to FIG. 3C, after the line carrier substrate 400 is formed, the bonding line carrier substrate 400 is disposed on an insulating layer 510, wherein the insulating layer 510 is disposed on a second circuit layer 520, and the first circuit layer 430 is The two circuit layers 520 are respectively located on opposite sides of the insulating layer 510. In this embodiment, the first circuit layer 430 can include at least one annular conductive pattern 432, a plurality of traces 434, and at least one pad 436. FIG. 3C also illustrates a top view of the annular conductive pattern 432.
圖3C所示的第二線路層520可以是線路板的內層線路。不過，在其他未繪示實施例中，第二線路層520也可以是線路板的外層線路，即第一線路層430與第二線路層520可以是雙面線路板所具有的二層線路。因此，圖3A至圖3F所示的第二線路層520僅為舉例說明，並非限定本發明。The second wiring layer 520 shown in FIG. 3C may be an inner layer wiring of the wiring board. However, in other embodiments not shown, the second circuit layer 520 may also be an outer layer of the circuit board, that is, the first circuit layer 430 and the second circuit layer 520 may be two-layer lines of the double-sided circuit board. Therefore, the second circuit layer 520 shown in FIGS. 3A to 3F is merely illustrative and does not limit the present invention.
請參閱圖3C與圖3D，接著，形成一導電連接結構530於絕緣層510中，並且移除承載基板410。導電連接結構530的形成方法以及移除承載基板410的方法皆與第一實施例相似，故不再重複敘述。Referring to FIG. 3C and FIG. 3D, a conductive connection structure 530 is formed in the insulating layer 510, and the carrier substrate 410 is removed. The method of forming the conductive connection structure 530 and the method of removing the carrier substrate 410 are similar to those of the first embodiment, and therefore will not be repeatedly described.
圖3D所示的導電連接結構530雖然是一種導電盲孔結構，但是在其他未繪示的實施例中，導電連接結構530也可以是導電通孔結構。因此，圖3A至圖3F所示的導電連接結構530並非限定本發明。Although the conductive connection structure 530 shown in FIG. 3D is a conductive blind hole structure, in other embodiments not shown, the conductive connection structure 530 may also be a conductive via structure. Therefore, the conductive connection structure 530 shown in FIGS. 3A to 3F does not limit the present invention.
請參閱圖3D與圖3E，接著，將防蝕阻礙層420完全移除，以使第一線路層430、絕緣層510以及導電連接結構530裸露出來。如此，一種線路板500基本上已製造完成。Referring to FIG. 3D and FIG. 3E, the anti-corrosion barrier layer 420 is completely removed to expose the first wiring layer 430, the insulating layer 510, and the conductive connection structure 530. As such, a circuit board 500 has been substantially completed.
請參閱圖3F，之後，可以形成一防焊層540於絕緣層510與第一線路層430上，其中防焊層540會暴露出接墊436，並覆蓋這些走線434以及導電連接結構530。Referring to FIG. 3F, a solder mask 540 may be formed on the insulating layer 510 and the first wiring layer 430. The solder resist layer 540 exposes the pads 436 and covers the traces 434 and the conductive connection structure 530.
綜上所述，當移除承載基板時，防蝕阻礙層能保護第一線路層，以避免第一線路層的表面變的粗糙以及厚度不均勻。相較於習知技術而言，本發明能提高線路板在電性方面的品質，進而提高線路板的良率。In summary, when the carrier substrate is removed, the anti-corrosion barrier layer can protect the first circuit layer to avoid roughening of the surface of the first circuit layer and uneven thickness. Compared with the prior art, the present invention can improve the electrical quality of the circuit board, thereby improving the yield of the circuit board.
此外，防蝕阻礙層可以部份保留，且部分保留的防蝕阻礙層可應用於後續的表面處理，進而縮短後續的表面處理所需的時間。In addition, the anti-corrosion barrier layer may be partially retained, and a portion of the retained anti-corrosion barrier layer may be applied to subsequent surface treatments, thereby reducing the time required for subsequent surface treatment.
雖然本發明已以一些實施例揭露如上，然其並非用以限定本發明，任何熟習本發明所屬領域之具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in some embodiments, and is not intended to limit the scope of the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
100．．．內埋式線路板100. . . Buried circuit board
110a、110b、200、400．．．線路承載基板110a, 110b, 200, 400. . . Line carrier substrate
112a、112b、210、410．．．承載基板112a, 112b, 210, 410. . . Carrier substrate
114a、114b．．．銅金屬層114a, 114b. . . Copper metal layer
116a、116b．．．銅線路層116a, 116b. . . Copper circuit layer
120．．．介電層120. . . Dielectric layer
130a、130b．．．銅電鍍層130a, 130b. . . Copper plating
140．．．油墨材料140. . . Ink material
150a、150b、350、540．．．防焊層150a, 150b, 350, 540. . . Solder mask
210a．．．表面210a. . . surface
212a．．．第一材料層212a. . . First material layer
212b．．．第二材料層212b. . . Second material layer
220、420．．．防蝕阻礙層220, 420. . . Anti-corrosion barrier
230、430．．．第一線路層230,430. . . First circuit layer
232、432．．．環形導電圖案232, 432. . . Circular conductive pattern
234、434．．．走線234, 434. . . Traces
236、436．．．接墊236, 436. . . Pad
240．．．圖案化感光層240. . . Patterned photosensitive layer
300、500．．．線路板300, 500. . . circuit board
310、510．．．絕緣層310, 510. . . Insulation
320、520．．．第二線路層320, 520. . . Second circuit layer
330、530．．．導電連接結構330, 530. . . Conductive connection structure
340．．．電鍍金屬層340. . . Plating metal layer
B1．．．盲孔B1. . . Blind hole
T1．．．導電通孔結構T1. . . Conductive via structure
圖1A至圖1E是根據習知一種內埋式線路板的製造方法所繪示的流程示意圖。1A to FIG. 1E are schematic flow diagrams illustrating a method of manufacturing a buried circuit board according to a conventional method.
圖2A至圖2J是根據本發明第一實施例的線路板的線路結構的製造方法所繪示的流程示意圖。2A to 2J are schematic flow charts showing a method of manufacturing a circuit structure of a circuit board according to a first embodiment of the present invention.
圖3A至圖3F是根據本發明第二實施例的線路板的線路結構的製造方法所繪示的流程示意圖。3A to 3F are schematic flow charts showing a method of manufacturing a circuit structure of a circuit board according to a second embodiment of the present invention.
200．．．線路承載基板200. . . Line carrier substrate
210．．．承載基板210. . . Carrier substrate
212a．．．第一材料層212a. . . First material layer
212b．．．第二材料層212b. . . Second material layer
220．．．防蝕阻礙層220. . . Anti-corrosion barrier
230．．．第一線路層230. . . First circuit layer
310．．．絕緣層310. . . Insulation
320．．．第二線路層320. . . Second circuit layer
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW96144304A TWI425898B (en) | 2007-11-22 | 2007-11-22 | Method for fabricating wiring structure of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW96144304A TWI425898B (en) | 2007-11-22 | 2007-11-22 | Method for fabricating wiring structure of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200924590A TW200924590A (en) | 2009-06-01 |
| TWI425898B true TWI425898B (en) | 2014-02-01 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW96144304A TWI425898B (en) | 2007-11-22 | 2007-11-22 | Method for fabricating wiring structure of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI425898B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI506738B (en) * | 2011-06-09 | 2015-11-01 | Unimicron Technology Corp | Semiconductor package and fabrication method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW556453B (en) * | 2002-02-01 | 2003-10-01 | Shiue-Fang Wu | PCB with inlaid outerlayer circuits and production methods thereof |
| TW200727760A (en) * | 2006-01-05 | 2007-07-16 | Advanced Semiconductor Eng | Circuit substrate and method of fabricating the same |
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2007
- 2007-11-22 TW TW96144304A patent/TWI425898B/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW556453B (en) * | 2002-02-01 | 2003-10-01 | Shiue-Fang Wu | PCB with inlaid outerlayer circuits and production methods thereof |
| TW200727760A (en) * | 2006-01-05 | 2007-07-16 | Advanced Semiconductor Eng | Circuit substrate and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200924590A (en) | 2009-06-01 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |