TWI425887B - Package substrate having supporting body and method of manufacture thereof - Google Patents
Package substrate having supporting body and method of manufacture thereof Download PDFInfo
- Publication number
- TWI425887B TWI425887B TW100144529A TW100144529A TWI425887B TW I425887 B TWI425887 B TW I425887B TW 100144529 A TW100144529 A TW 100144529A TW 100144529 A TW100144529 A TW 100144529A TW I425887 B TWI425887 B TW I425887B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- electrical contact
- opening
- disposed
- metal
- Prior art date
Links
Description
本發明係有關一種半導體封裝基板，尤指一種具有支撐體的封裝基板及其製法。The present invention relates to a semiconductor package substrate, and more particularly to a package substrate having a support and a method of fabricating the same.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化（miniaturization）的封裝需求，係朝降低承載晶片之封裝基板的厚度發展。目前用於承載晶片之封裝基板可分為硬質材與軟質材，一般用於球閘陣列封裝（Ball Grid Array, BGA）之封裝基板係多選擇硬質材。With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, the thickness of the package substrate carrying the wafer is reduced. At present, the package substrate used for carrying the wafer can be divided into a hard material and a soft material, and a package substrate generally used for a Ball Grid Array (BGA) is a hard material selected.
請參閱第1A至1E圖，係為習知封裝結構1之剖面示意圖。Please refer to FIGS. 1A to 1E for a schematic cross-sectional view of a conventional package structure 1.
如第1A圖所示，首先，提供一具有相對之第一表面13a與第二表面13b之芯層13，該芯層13之第一與第二表面13a,13b上分別具有銅層11a,11b。As shown in FIG. 1A, first, a core layer 13 having a first surface 13a and a second surface 13b opposite to each other is provided. The first and second surfaces 13a, 13b of the core layer 13 have copper layers 11a, 11b, respectively. .
如第1B圖所示，於該芯層13之第二表面13b上以雷射形成複數貫穿孔130，以令該第一表面13a之銅層11a外露於該些貫穿孔130。As shown in FIG. 1B, a plurality of through holes 130 are formed by laser on the second surface 13b of the core layer 13 so that the copper layer 11a of the first surface 13a is exposed to the through holes 130.
如第1C圖所示，圖案化該銅層11a,11b，利用導電層10進行電鍍銅材，以於該芯層13之第一及第二表面13a,13b上分別形成第一及第二線路層12,14，且於該些貫穿孔130中形成導電通孔140以電性連接該第一及第二線路層12,14，又該第一及第二線路層12,14分別具有複數第一及第二電性接觸墊120,141。As shown in FIG. 1C, the copper layers 11a, 11b are patterned, and the copper material is plated by the conductive layer 10 to form first and second lines on the first and second surfaces 13a, 13b of the core layer 13, respectively. Layers 12, 14 and conductive vias 140 are formed in the through holes 130 to electrically connect the first and second circuit layers 12, 14, and the first and second circuit layers 12, 14 respectively have a plurality of One and second electrical contact pads 120, 141.
如第1D圖所示，於該芯層13之第一及第二表面13a,13b上分別形成絕緣保護層15，且填滿該導電通孔140。該絕緣保護層15分別具有複數開孔150，以令該些第一及第二電性接觸墊120,141對應外露於各該開孔150，以製成該封裝基板1a。接著，於該些第一及第二電性接觸墊120,141之外露表面上分別形成表面處理層16。As shown in FIG. 1D, an insulating protective layer 15 is formed on the first and second surfaces 13a, 13b of the core layer 13, and the conductive vias 140 are filled. The insulating protective layer 15 has a plurality of openings 150 for respectively exposing the first and second electrical contact pads 120, 141 to the openings 150 to form the package substrate 1a. Next, a surface treatment layer 16 is formed on the exposed surfaces of the first and second electrical contact pads 120, 141, respectively.
如第1E圖所示，係於該絕緣保護層15上承載晶片17並藉由焊線170電性連接該第二電性接觸墊141，再形成封裝膠體18以包覆該晶片17，且於該些第一電性接觸墊120上植接焊球19，以製成封裝結構1。為了符合微小化與可靠度之需求，於目前製程技術中，該芯層13之厚度可縮小至60um。As shown in FIG. 1E, the wafer 17 is carried on the insulating protective layer 15 and electrically connected to the second electrical contact pad 141 by a bonding wire 170, and then the encapsulant 18 is formed to cover the wafer 17, and The first electrical contact pads 120 are implanted with solder balls 19 to form the package structure 1. In order to meet the requirements of miniaturization and reliability, in the current process technology, the thickness of the core layer 13 can be reduced to 60 um.
惟，隨著微小化之需求增加，厚度為60um之芯層13已無法滿足封裝件之微小化需求，但若使該芯層13之厚度小於60um，該封裝基板1a之總板厚R將小於130um，導致生產作業性不佳，例如：該封裝基板1a於各製程作業站中移動時容易卡板，而不利於生產，又即使能夠生產，在運送或封裝時也容易因厚度太薄而彎翹或破裂，導致無法使用或產品不良。However, as the demand for miniaturization increases, the core layer 13 having a thickness of 60 μm cannot satisfy the miniaturization requirement of the package. However, if the thickness of the core layer 13 is less than 60 μm, the total thickness R of the package substrate 1a will be less than 130 um, resulting in poor production workability, for example, the package substrate 1a is easy to jam when moving in each process station, which is unfavorable for production, and even if it can be produced, it is easy to bend due to the thickness when it is transported or packaged. Awkward or ruptured, resulting in unusable or poor product.
因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係揭露一種具有支撐體的封裝基板，係於其一側增設包含銅箔基板片與強化板體之支撐體，且該強化板體具有結合該銅箔基板片之銅層的介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層。該封裝基板復包括形成於該第二金屬剝離層上，並形成有第一開孔之第一絕緣保護層，以令該第二金屬剝離層之部分表面外露於該第一開孔；設於該第一開孔中之第二金屬剝離層上之第一電性接觸墊；設於該第一絕緣保護層與該第一電性接觸墊上之芯層；設於該芯層上的線路層，具有設於該芯層上之第二電性接觸墊、及設於該芯層中並電性連接該第一電性接觸墊之導電盲孔；以及形成於該芯層與該線路層上，且形成有第二開孔之第二絕緣保護層，以令該些第二電性接觸墊外露於該第二開孔。In view of the above-mentioned various deficiencies of the prior art, the present invention discloses a package substrate having a support body, which is provided with a support body including a copper foil substrate piece and a reinforced plate body on one side thereof, and the reinforced plate body has a copper foil bonded thereto. a dielectric layer of a copper layer of the substrate sheet, a first metal release layer disposed on the dielectric layer, and a second metal release layer disposed on the first metal release layer. The package substrate comprises a first insulating protective layer formed on the second metal stripping layer and having a first opening, so that a part of the surface of the second metal stripping layer is exposed on the first opening; a first electrical contact pad on the second metal stripping layer of the first opening; a core layer disposed on the first insulating protective layer and the first electrical contact pad; and a circuit layer disposed on the core layer a second electrical contact pad disposed on the core layer, and a conductive blind hole disposed in the core layer and electrically connected to the first electrical contact pad; and formed on the core layer and the circuit layer And forming a second insulating protective layer with a second opening to expose the second electrical contact pads to the second opening.
本發明復提供一種具有支撐體的封裝基板之製法，係包括：提供兩以其銅層相互疊置之銅箔基板片；於該兩銅箔基板片上結合強化板體，該強化板體具有包覆該兩銅箔基板片以固定該兩銅箔基板片之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層；於該第二金屬剝離層上形成第一絕緣保護層；於該第一絕緣保護層中形成複數第一電性接觸墊；於該第二金屬剝離層與該些第一電性接觸墊上形成芯層；於該芯層上形成具有複數第二電性接觸墊之線路層，且於該芯層中形成導電盲孔以電性連接該些第一電性接觸墊與線路層；於該芯層與線路層上形成第二絕緣保護層，且令該些第二電性接觸墊外露於該第二絕緣保護層；沿該兩銅箔基板片之側邊進行切割，令該兩銅箔基板片相互疊置之銅層分開，以分離出兩封裝基板。The invention provides a method for manufacturing a package substrate having a support body, comprising: providing two copper foil substrate sheets with their copper layers stacked on each other; and bonding a reinforcing plate body to the two copper foil substrate sheets, the reinforcing plate body having a package a dielectric layer covering the two copper foil substrate sheets, a first metal release layer disposed on the dielectric layer, and a second metal release layer disposed on the first metal release layer Forming a first insulating protective layer on the second metal stripping layer; forming a plurality of first electrical contact pads in the first insulating protective layer; forming on the second metal stripping layer and the first electrical contact pads a core layer is formed on the core layer, and a conductive layer is formed in the core layer to electrically connect the first electrical contact pads and the circuit layer; Forming a second insulating protective layer on the layer and the circuit layer, and exposing the second electrical contact pads to the second insulating protective layer; cutting along the sides of the two copper foil substrate sheets to form the two copper foil substrates The copper layers separated from each other are separated to separate two Substrate.
前述之具有支撐體的封裝基板及其製法中，該第一金屬剝離層係以物理方式結合該第二金屬剝離層。In the above package substrate having a support and a method of manufacturing the same, the first metal release layer physically bonds the second metal release layer.
前述之具有支撐體的封裝基板及其製法，可包括於該第二電性接觸墊之外露表面上形成表面處理層。The foregoing package substrate having a support body and a method of manufacturing the same may include forming a surface treatment layer on the exposed surface of the second electrical contact pad.
由上可知，本發明之具有支撐體的封裝基板及其製法，係藉由該支撐體之厚度，使該封裝基板之整體厚度可大於或等於130um，故可避免如習知技術中之生產作業性不佳之問題。As can be seen from the above, the package substrate having the support body of the present invention and the method for manufacturing the same can be made such that the overall thickness of the package substrate can be greater than or equal to 130 um by the thickness of the support body, thereby avoiding the production operation as in the prior art. The problem of poor sex.
再者，本發明之封裝基板減去該支撐體之厚度之後，其它結構之總厚度將大幅縮小，故於後續封裝製程中，將该支撐體移除後，可大幅降低封裝結構之厚度，以滿足微小化之需求。Furthermore, after the thickness of the support substrate is reduced by the thickness of the support body of the present invention, the total thickness of the other structures is greatly reduced. Therefore, after the support body is removed in the subsequent packaging process, the thickness of the package structure can be greatly reduced. Meet the needs of miniaturization.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“側邊”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "side" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to the relative relationship are considered to be within the scope of the invention without departing from the scope of the invention.
請參閱第2A至2F圖，係為本發明之具有支撐體2c的封裝基板2之製法之剖視示意圖。2A to 2F are schematic cross-sectional views showing a method of manufacturing the package substrate 2 having the support 2c of the present invention.
如第2A圖所示，首先，提供兩銅箔基板片（Copper clad laminate, CCL）20與兩強化板體21，各該銅箔基板片20係具有絕緣層200及設於該絕緣層200相對兩側之銅層201,202，該兩銅箔基板片20以其中一銅層201相互疊置，且各該強化板體21具有介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212。As shown in FIG. 2A, first, a copper clad laminate (CCL) 20 and two reinforced panels 21 are provided. Each of the copper foil substrate sheets 20 has an insulating layer 200 and is disposed on the insulating layer 200. The copper layers 201, 202 on both sides, the two copper foil substrate sheets 20 are overlapped with each other by a copper layer 201, and each of the reinforcing plate bodies 21 has a dielectric layer 210 and a first metal stripping provided on the dielectric layer 210. The layer 211 and the second metal stripping layer 212 disposed on the first metal stripping layer 211.
接著，於該兩銅箔基板片20上分別壓合該強化板體21之介電層210，令該兩介電層210合為一體以包覆該兩銅箔基板片20，而固定該兩銅箔基板片20，俾形成支撐結構2b。Then, the dielectric layers 210 of the reinforced plate body 21 are respectively pressed onto the two copper foil substrate sheets 20, and the two dielectric layers 210 are integrated to cover the two copper foil substrate sheets 20, and the two are fixed. The copper foil substrate sheet 20 is formed into a support structure 2b.
於本實施例中，該絕緣層200之材質可例如為雙順丁烯二酸醯亞胺/三氮阱（Bismaleimide triazine，簡稱BT）。然而，有關銅箔基板片之種類繁多，且為業界所熟知，故不再贅述。In this embodiment, the material of the insulating layer 200 can be, for example, Bisaleimide triazine (BT). However, there are many types of copper foil substrate sheets, which are well known in the art and will not be described again.
再者，該介電層210之材質可例如為預浸材（prepreg，簡稱PP），且該介電層210之厚度可例如為100um，而該第一金屬剝離層211與第二金屬剝離層212係為銅材，且兩者之厚度可為18um及3um。The material of the dielectric layer 210 can be, for example, a prepreg (PP for short), and the thickness of the dielectric layer 210 can be, for example, 100 um, and the first metal stripping layer 211 and the second metal stripping layer. The 212 series is copper, and the thickness of both can be 18 um and 3 um.
又，該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212，且該物理方式係為卡合、靜電、吸附、或黏著物等，亦即該第一金屬剝離層211與第二金屬剝離層212之間並無需藉蝕刻分離。Moreover, the first metal stripping layer 211 physically bonds the second metal stripping layer 212, and the physical manner is a bonding, static electricity, adsorption, or adhesion, etc., that is, the first metal stripping layer 211 and The second metal stripping layer 212 does not need to be separated by etching.
如第2B圖所示，於該第二金屬剝離層212上形成第一絕緣保護層25a，並藉由雷射或微影蝕刻的方式於該第一絕緣保護層25a中形成有複數第一開孔250a，且令該第二金屬剝離層212之部分表面外露於該第一開孔250a。接著，藉由第一絕緣保護層25a作為圖案化阻層，並以該第二金屬剝離層212為導電途徑，於該第一開孔250a中之第二金屬剝離層212上電鍍形成複數第一電性接觸墊22。As shown in FIG. 2B, a first insulating protective layer 25a is formed on the second metal stripping layer 212, and a plurality of first openings are formed in the first insulating protective layer 25a by laser or lithography. The hole 250a is formed, and a part of the surface of the second metal peeling layer 212 is exposed to the first opening 250a. Then, the first insulating protective layer 25a is used as a patterned resist layer, and the second metal stripping layer 212 is electrically conductive, and the second metal stripping layer 212 of the first opening 250a is plated to form a plurality of first Electrical contact pads 22.
如第2C圖所示，於該第一絕緣保護層25a與該些第一電性接觸墊22上形成芯層23，且該芯層23具有相對之第一表面23a與第二表面23b，令該芯層23之第一表面23a結合該第一絕緣保護層25a與該些第一電性接觸墊22。As shown in FIG. 2C, a core layer 23 is formed on the first insulating protective layer 25a and the first electrical contact pads 22, and the core layer 23 has opposite first and second surfaces 23a and 23b. The first surface 23a of the core layer 23 is combined with the first insulating protective layer 25a and the first electrical contact pads 22.
接著，於該芯層23之第二表面23b上形成具有複數第二電性接觸墊241之線路層24，且於該芯層23中形成複數導電盲孔240以電性連接該些第一電性接觸墊22與線路層24。Then, a circuit layer 24 having a plurality of second electrical contact pads 241 is formed on the second surface 23b of the core layer 23, and a plurality of conductive vias 240 are formed in the core layer 23 to electrically connect the first electrodes. The contact pads 22 are connected to the circuit layer 24.
於本實施例中，該芯層23係為介電材，且有關線路製程之種類繁多，並無特別限制，故不詳述。In the present embodiment, the core layer 23 is a dielectric material, and there are many types of circuit processes, and there is no particular limitation, so it will not be described in detail.
如第2D圖所示，於該芯層23之第二表面23b與線路層24上形成第二絕緣保護層25b，該第二絕緣保護層25b具有複數第二開孔250b，以令該些第二電性接觸墊241對應外露於各該第二開孔250b。As shown in FIG. 2D, a second insulating protective layer 25b is formed on the second surface 23b of the core layer 23 and the circuit layer 24. The second insulating protective layer 25b has a plurality of second openings 250b. The two electrical contact pads 241 are correspondingly exposed to the second openings 250b.
接著，於該第二開孔250b中之第二電性接觸墊241上形成表面處理層26。於本實施例中，形成該表面處理層26之材質係為鎳/金(Ni/Au)、鎳鈀金(Ni/Pd/Au)或金等選擇，且其形成方式可為化鍍或電鍍等方式，若以化鍍方式形成，則該表面處理層26之材質係為化鎳/金(Ni/Au)、化鎳鈀金(Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG)或直接浸金(Direct Immersion Gold, DIG)，或者，併用化鍍與電鍍方式，即以該第二金屬剝離層212為導電途徑，形成例如電鍍鎳/化鍍鈀/電鍍金的該表面處理層26。Next, a surface treatment layer 26 is formed on the second electrical contact pad 241 in the second opening 250b. In this embodiment, the material of the surface treatment layer 26 is selected from nickel/gold (Ni/Au), nickel palladium gold (Ni/Pd/Au) or gold, and the formation thereof may be plating or plating. In the same manner, if formed by a plating method, the surface treatment layer 26 is made of nickel/gold (Ni/Au), electroless nickel/electroplated gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG) or direct immersion gold. (Direct Immersion Gold, DIG), or by surface plating and electroplating, that is, the second metal stripping layer 212 is used as a conductive path to form the surface treatment layer 26 such as electroplated nickel/palladium plating/gold plating.
如第2E及2F圖所示，沿該兩銅箔基板片20之側邊進行切割，如第2D圖所示之切割線L，令該兩銅箔基板片20相互疊置之銅層201自動分開，使該支撐結構2b分離成兩支撐體2c，以於上、下側分離出具有該支撐體2c的封裝基板2。As shown in FIGS. 2E and 2F, the side of the two copper foil substrate sheets 20 are cut, as shown by the cutting line L shown in FIG. 2D, so that the copper layer 201 of the two copper foil substrate sheets 20 are superposed on each other automatically. Separately, the support structure 2b is separated into two support bodies 2c to separate the package substrate 2 having the support body 2c on the upper and lower sides.
本發明之具有支撐體2c的封裝基板2之製法，藉由該支撐體2c之厚度，使該封裝基板2之整體厚度可大於或等於130um，以避免如習知技術中之生產作業性不佳之種種問題。The method for manufacturing the package substrate 2 having the support 2c of the present invention, the thickness of the support substrate 2c is such that the overall thickness of the package substrate 2 can be greater than or equal to 130 um, so as to avoid poor productivity in the prior art. Various problems.
再者，於該第二金屬剝離層212上先形成第一絕緣保護層25a，再形成第一電性接觸墊22，使該封裝基板2之相對的兩側均具有絕緣保護層（第一與第二絕緣保護層25a,25b）。Further, a first insulating protective layer 25a is formed on the second metal stripping layer 212, and then a first electrical contact pad 22 is formed, so that opposite sides of the package substrate 2 have an insulating protective layer (first and Second insulating protective layer 25a, 25b).
又，於後續進行封裝製程之前，該封裝基板2藉由銅箔基板片20與強化板體21，以提升整體封裝基板2之強度，故於運送時不會破裂。Moreover, before the subsequent packaging process, the package substrate 2 is made of the copper foil substrate sheet 20 and the reinforcing plate body 21 to enhance the strength of the entire package substrate 2, so that it does not break during transportation.
本發明提供一種具有支撐體2c的封裝基板2，係包括：於相對兩側具有銅層201,202之銅箔基板片20、設於該銅箔基板片20之其中一銅層202上之強化板體21、形成於該強化板體21上之第一絕緣保護層25a、設於該強化板體21上之第一電性接觸墊22、設於該第一絕緣保護層25a與第一電性接觸墊22上之芯層23、設於該芯層23上之線路層24、以及設於該芯層23與線路層24上之第二絕緣保護層25b。The present invention provides a package substrate 2 having a support 2c, comprising: a copper foil substrate sheet 20 having copper layers 201, 202 on opposite sides, and a reinforced plate body disposed on one of the copper layers 202 of the copper foil substrate sheet 20. The first insulating protective layer 25a formed on the reinforcing plate body 21, the first electrical contact pad 22 disposed on the reinforcing plate body 21, and the first insulating protective layer 25a are in electrical contact with the first electrical contact layer A core layer 23 on the pad 22, a circuit layer 24 disposed on the core layer 23, and a second insulating protective layer 25b disposed on the core layer 23 and the wiring layer 24.
所述之支撐體2c係包含該銅箔基板片20與該強化板體21。The support body 2c includes the copper foil substrate sheet 20 and the reinforcing plate body 21.
所述之銅箔基板片20復包含絕緣層200，且該銅層201,202係設於該絕緣層200相對兩側。然而，銅箔基板片之種類繁多，並無特別限制。The copper foil substrate sheet 20 further includes an insulating layer 200, and the copper layers 201, 202 are disposed on opposite sides of the insulating layer 200. However, there are many types of copper foil substrate sheets, and there is no particular limitation.
所述之強化板體21係具有結合該銅層202之介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212；於本實施例中，該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212。The reinforced plate body 21 has a dielectric layer 210 bonded to the copper layer 202, a first metal stripping layer 211 disposed on the dielectric layer 210, and a second layer disposed on the first metal stripping layer 211. The metal stripping layer 212; in the embodiment, the first metal stripping layer 211 physically bonds the second metal stripping layer 212.
所述之第一絕緣保護層25a係形成有複數第一開孔250a，且令該第二金屬剝離層212之部分表面外露於該些第一開孔250a。The first insulating protective layer 25a is formed with a plurality of first openings 250a, and a portion of the surface of the second metal stripping layer 212 is exposed to the first openings 250a.
所述之第一電性接觸墊22係設於該些第一開孔中之第二金屬剝離層212上。The first electrical contact pad 22 is disposed on the second metal stripping layer 212 of the first openings.
所述之芯層23係為介電材。The core layer 23 is a dielectric material.
所述之線路層24係具有複數設於該芯層23上之第二電性接觸墊241、及設於該芯層23中且電性連接該第一電性接觸墊22之導電盲孔240。The circuit layer 24 has a plurality of second electrical contact pads 241 disposed on the core layer 23, and a conductive blind via 240 disposed in the core layer 23 and electrically connected to the first electrical contact pads 22. .
所述之第二絕緣保護層25b係具有複數第二開孔250b，以令該些第二電性接觸墊241對應外露於各該第二開孔250b，俾供表面處理層26形成於該第二開孔250b中之第二電性接觸墊241上。The second insulating protective layer 25b has a plurality of second openings 250b, so that the second electrical contact pads 241 are correspondingly exposed to the second openings 250b, and the surface treatment layer 26 is formed on the second surface. The second electrical contact pad 241 of the second opening 250b.
請參閱第3A至3D圖，係為應用本發明之具有支撐體2c的封裝基板2之後續封裝製程之剖視示意圖。於本實施例中，該封裝基板2係具有複數封裝單元2a，如第3C圖所示。Please refer to FIGS. 3A to 3D, which are schematic cross-sectional views showing a subsequent packaging process of the package substrate 2 having the support 2c of the present invention. In the present embodiment, the package substrate 2 has a plurality of package units 2a as shown in FIG. 3C.
如第3A圖所示，接續第2F圖之製程而進行封裝製程，係於第二絕緣保護層25b上設置晶片27，且令該些第二電性接觸墊241藉由焊線270電性連接該晶片27；接著，於該第二絕緣保護層25b上形成封裝膠體28，以包覆該晶片27與焊線270。As shown in FIG. 3A, the package process is performed after the process of FIG. 2F is performed, and the wafers 27 are disposed on the second insulating protective layer 25b, and the second electrical contact pads 241 are electrically connected by the bonding wires 270. The wafer 27 is then formed on the second insulating protective layer 25b to encapsulate the wafer 27 and the bonding wires 270.
如第3B圖所示，分離該第一金屬剝離層211與第二金屬剝離層212，以移除該銅箔基板片20、該介電層210與第一金屬剝離層211，而外露出該第二金屬剝離層212。As shown in FIG. 3B, the first metal stripping layer 211 and the second metal stripping layer 212 are separated to remove the copper foil substrate sheet 20, the dielectric layer 210 and the first metal stripping layer 211, and the outer metal stripping layer 211 is exposed. The second metal stripping layer 212.
於本實施例中，因該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212，故分離該第一金屬剝離層211與第二金屬剝離層212時，僅需以如剝離之物理方式進行分離。In this embodiment, since the first metal stripping layer 211 physically bonds the second metal stripping layer 212, when the first metal stripping layer 211 and the second metal stripping layer 212 are separated, only the stripping is required. Physical separation.
如第3C圖所示，藉由蝕刻方式移除該第二金屬剝離層212，且一併微蝕刻該些第一電性接觸墊22之部分底部，以外露出該第一絕緣保護層25a與該些第一電性接觸墊22’底部。As shown in FIG. 3C, the second metal stripping layer 212 is removed by etching, and a portion of the bottom portions of the first electrical contact pads 22 are microetched, and the first insulating protective layer 25a is exposed. The first electrical contact pads 22' are at the bottom.
如第3D圖所示，沿各該封裝單元2a進行切割，如第3C圖所示之切割線S，以取得複數個封裝結構3，且於該第一電性接觸墊22’上結合焊球29。As shown in FIG. 3D, cutting is performed along each of the package units 2a, such as the cutting line S shown in FIG. 3C, to obtain a plurality of package structures 3, and solder balls are bonded to the first electrical contact pads 22'. 29.
本發明之封裝基板2減去該支撐體2c之厚度之後，其它結構之總厚度（含芯層23、第一絕緣保護層25a、第二絕緣保護層25b）係小於60um，故於封裝製程中，移除支撐體2c（該銅箔基板片20與該強化板體21）之後，可大幅降低封裝結構3之厚度，以滿足微小化之需求。After the thickness of the support body 2c is subtracted from the package substrate 2 of the present invention, the total thickness of the other structures (including the core layer 23, the first insulating protective layer 25a, and the second insulating protective layer 25b) is less than 60 um, so that it is in the packaging process. After the support 2c (the copper foil substrate piece 20 and the reinforced plate body 21) is removed, the thickness of the package structure 3 can be greatly reduced to meet the demand for miniaturization.
再者，該封裝基板2藉由支撐體2c，以提升整體封裝基板2之強度，故於進行封裝製程時不會破裂。Furthermore, the package substrate 2 is supported by the support 2c to increase the strength of the entire package substrate 2, so that it does not break during the packaging process.
又，藉由於該第二金屬剝離層212上形成第一絕緣保護層25a，以當移除該第二金屬剝離層212後，該封裝基板2’成為對稱結構，以避免該封裝基板2’發生翹曲（warpage），且可藉由該第一絕緣保護層25a之保護，以避免該第一電性接觸墊22’之表面刮傷。Moreover, the first insulating protective layer 25a is formed on the second metal stripping layer 212, so that after the second metal stripping layer 212 is removed, the package substrate 2' becomes a symmetrical structure to prevent the package substrate 2' from occurring. Warpage, and can be protected by the first insulating protective layer 25a to avoid scratching the surface of the first electrical contact pad 22'.
綜上所述，本發明具有支撐體的封裝基板及其製法，主要藉由增設支撐體，以使該封裝基板之整體厚度可符合生產作業之需求，故可避免生產作業性不佳之問題。In summary, the package substrate having the support body and the manufacturing method thereof are mainly provided by adding a support body, so that the overall thickness of the package substrate can meet the requirements of the production operation, so that the problem of poor production workability can be avoided.
再者，當於封裝製程中移除支撐體之後，該封裝基板之剩餘結構之總厚度係大幅降低，因而降低封裝結構之厚度，以滿足微小化之需求。Moreover, after the support is removed in the packaging process, the total thickness of the remaining structure of the package substrate is greatly reduced, thereby reducing the thickness of the package structure to meet the demand for miniaturization.
又，於進行封裝製程時，具有該支撐體之封裝基板的強度夠強，故於運送時不會破裂與進行封裝製程時，該封裝基板均不會破裂。Moreover, when the packaging process is performed, the strength of the package substrate having the support is strong enough, so that the package substrate does not break when it is not broken during transportation and the packaging process is performed.
另外，藉由該第一及第二絕緣保護層，使該封裝基板成為對稱結構，以避免封裝基板發生翹曲，且可避免該第一及第二電性接觸墊之表面刮傷。In addition, the first and second insulating protective layers make the package substrate have a symmetrical structure to prevent warpage of the package substrate, and surface scratches of the first and second electrical contact pads can be avoided.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
1,3‧‧‧封裝結構1,3‧‧‧Package structure
1a,2,2’‧‧‧封裝基板1a, 2, 2'‧‧‧ package substrate
10‧‧‧導電層10‧‧‧ Conductive layer
11a,11b,201,202‧‧‧銅層11a, 11b, 201, 202‧‧‧ copper layer
12‧‧‧第一線路層12‧‧‧First line layer
120,22,22’‧‧‧第一電性接觸墊120,22,22’‧‧‧First electrical contact pads
13,23‧‧‧芯層13,23‧‧ ‧ core layer
13a,23a‧‧‧第一表面13a, 23a‧‧‧ first surface
13b,23b‧‧‧第二表面13b, 23b‧‧‧ second surface
130‧‧‧貫穿孔130‧‧‧through holes
14‧‧‧第二線路層14‧‧‧Second circuit layer
140‧‧‧導電通孔140‧‧‧ Conductive through hole
141,241‧‧‧第二電性接觸墊141,241‧‧‧Second electrical contact pads
15‧‧‧絕緣保護層15‧‧‧Insulation protective layer
150‧‧‧開孔150‧‧‧opening
16,26‧‧‧表面處理層16,26‧‧‧Surface treatment layer
17,27‧‧‧晶片17,27‧‧‧ wafer
170,270‧‧‧焊線170,270‧‧‧welding line
18,28‧‧‧封裝膠體18,28‧‧‧Package colloid
19,29‧‧‧焊球19,29‧‧‧ solder balls
2a‧‧‧封裝單元2a‧‧‧Package unit
2b‧‧‧支撐結構2b‧‧‧Support structure
2c‧‧‧支撐體2c‧‧‧Support
20‧‧‧銅箔基板片20‧‧‧copper substrate
200‧‧‧絕緣層200‧‧‧Insulation
21‧‧‧強化板體21‧‧‧Strengthened plate
210‧‧‧介電層210‧‧‧Dielectric layer
211‧‧‧第一金屬剝離層211‧‧‧First metal stripping layer
212‧‧‧第二金屬剝離層212‧‧‧Second metal stripping layer
24‧‧‧線路層24‧‧‧Line layer
240‧‧‧導電盲孔240‧‧‧conductive blind holes
25a‧‧‧第一絕緣保護層25a‧‧‧First insulation protection layer
250a‧‧‧第一開孔250a‧‧‧first opening
25b‧‧‧第二絕緣保護層25b‧‧‧Second insulation protection layer
250b‧‧‧第二開孔250b‧‧‧second opening
L,S‧‧‧切割線L, S‧‧‧ cutting line
R‧‧‧總板厚R‧‧‧ total plate thickness
第1A至1E圖係為習知封裝結構之製法的剖視示意圖；1A to 1E are schematic cross-sectional views showing a method of manufacturing a conventional package structure;
第2A至2F圖係為本發明之具有支撐體的封裝基板之製法的剖視示意圖；以及2A to 2F are schematic cross-sectional views showing a method of manufacturing a package substrate having a support according to the present invention;
第3A至3D圖係為應用本發明之具有支撐體的封裝基板之後續製法的剖視示意圖。3A to 3D are schematic cross-sectional views showing a subsequent process of applying the package substrate having the support of the present invention.
2‧‧‧封裝基板2‧‧‧Package substrate
2c‧‧‧支撐體2c‧‧‧Support
20‧‧‧銅箔基板片20‧‧‧copper substrate
200‧‧‧絕緣層200‧‧‧Insulation
201,202‧‧‧銅層201,202‧‧‧ copper layer
21‧‧‧強化板體21‧‧‧Strengthened plate
210‧‧‧介電層210‧‧‧Dielectric layer
211‧‧‧第一金屬剝離層211‧‧‧First metal stripping layer
212‧‧‧第二金屬剝離層212‧‧‧Second metal stripping layer
22‧‧‧第一電性接觸墊22‧‧‧First electrical contact pads
23‧‧‧芯層23‧‧‧ core layer
24‧‧‧線路層24‧‧‧Line layer
240‧‧‧導電盲孔240‧‧‧conductive blind holes
241‧‧‧第二電性接觸墊241‧‧‧Second electrical contact pads
25a‧‧‧第一絕緣保護層25a‧‧‧First insulation protection layer
250a‧‧‧第一開孔250a‧‧‧first opening
25b‧‧‧第二絕緣保護層25b‧‧‧Second insulation protection layer
250b‧‧‧第二開孔250b‧‧‧second opening
26‧‧‧表面處理層26‧‧‧Surface treatment layer
Claims (6)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100144529A TWI425887B (en) | 2011-12-02 | 2011-12-02 | Package substrate having supporting body and method of manufacture thereof |
| CN201210127399.0A CN103137568B (en) | 2011-12-02 | 2012-04-26 | Package substrate with support and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100144529A TWI425887B (en) | 2011-12-02 | 2011-12-02 | Package substrate having supporting body and method of manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201325328A TW201325328A (en) | 2013-06-16 |
| TWI425887B true TWI425887B (en) | 2014-02-01 |
Family
ID=49033265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100144529A TWI425887B (en) | 2011-12-02 | 2011-12-02 | Package substrate having supporting body and method of manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI425887B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI576302B (en) * | 2015-05-28 | 2017-04-01 | 友達光電股份有限公司 | Plate removing equipment and method for removing plate using the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066767B (en) * | 2021-03-05 | 2022-01-25 | 南通越亚半导体有限公司 | Temporary bearing plate, manufacturing method thereof and manufacturing method of packaging substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
| TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
| TW201121381A (en) * | 2009-12-15 | 2011-06-16 | Samsung Electro Mech | Carrier for manufacturing substrate and method of manufacturing substrate using the same |
-
2011
- 2011-12-02 TW TW100144529A patent/TWI425887B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
| TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
| TW201121381A (en) * | 2009-12-15 | 2011-06-16 | Samsung Electro Mech | Carrier for manufacturing substrate and method of manufacturing substrate using the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI576302B (en) * | 2015-05-28 | 2017-04-01 | 友達光電股份有限公司 | Plate removing equipment and method for removing plate using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201325328A (en) | 2013-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI493671B (en) | Package substrate having holder and fabricating method thereof, package structure having holder and fabricating method thereof | |
| TWI426584B (en) | Semiconductor package and method of forming same | |
| TWI474450B (en) | Package carrier and manufacturing method thereof | |
| TWI446508B (en) | Coreless package substrate and method of making same | |
| TWI416636B (en) | Method of forming package structure | |
| TW201434121A (en) | Package substrate, semiconductor package and methods of manufacturing the same | |
| JP2013138115A (en) | Packaging substrate having support, method of fabricating the same, package structure having support, and method of fabricating the same | |
| JP5003812B2 (en) | Printed wiring board and printed wiring board manufacturing method | |
| TW201628145A (en) | Electronic package structure and the manufacture thereof | |
| TW201320276A (en) | Package substrate and fabrication method thereof | |
| TWI446496B (en) | Package substrate device and method for fabricating the same | |
| TW201407723A (en) | Semiconductor package and method of fabricating the same | |
| TWI425887B (en) | Package substrate having supporting body and method of manufacture thereof | |
| TWI471989B (en) | Semiconductor package and method of forming same | |
| US10096491B2 (en) | Method of fabricating a packaging substrate including a carrier having two carrying portions | |
| TW201401950A (en) | Carrier and method of forming coreless packaging substrate having the carrier | |
| TWI416680B (en) | Package substrate and fabrication method thereof | |
| TW201701438A (en) | Z-connection using electroless plating | |
| TWI566330B (en) | Method of fabricating an electronic package structure | |
| TWI422000B (en) | Coreless packaging substrate and method for manufacturing the same | |
| TWI500128B (en) | Package substrate formed with support body and method of forming same | |
| TWI632624B (en) | Packaging substrate and method for fabricating the same | |
| TWI405273B (en) | Method of fabricating package structure | |
| TW201347124A (en) | Semiconductor package and method for fabricating the same | |
| TWI418006B (en) | Package substrate having single-layered circuits, package structure and method of forming the same |