TWI425878B - Driving circuit of light emitting diode - Google Patents
Driving circuit of light emitting diode Download PDFInfo
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- TWI425878B TWI425878B TW98115406A TW98115406A TWI425878B TW I425878 B TWI425878 B TW I425878B TW 98115406 A TW98115406 A TW 98115406A TW 98115406 A TW98115406 A TW 98115406A TW I425878 B TWI425878 B TW I425878B
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Description
本發明是有關於一種發光二極體的驅動電路,且特別是有關於一種具有雙緣觸發擷取功能的驅動電路。 The present invention relates to a driving circuit for a light emitting diode, and more particularly to a driving circuit having a double edge triggering function.
發光二極體(Light Emitting Diode,LED)的體積小、省電且耐用,而且隨著製程的成熟,價格下降,近來以發光二極體做為光源之產品越來越普遍。此外,發光二極體工作電壓低(僅1.5-3V)、能主動發光且有一定亮度,亮度可用電壓或電流調節,同時具備耐衝擊、抗振動、壽命長(10萬小時)之特點,是以,發光二極體在各種終端設備中被廣泛使用,從汽車前照燈、交通信號燈、文字顯示器、看板及大螢幕視頻顯示器,到普通及建築照明和LCD背光等領域。 Light Emitting Diode (LED) is small, power-saving and durable, and as the process matures, the price drops. Recently, products using light-emitting diodes as light sources are becoming more and more popular. In addition, the light-emitting diode has a low operating voltage (only 1.5-3V), can actively emit light and has a certain brightness, and the brightness can be adjusted by voltage or current, and has the characteristics of impact resistance, vibration resistance and long life (100,000 hours). Light-emitting diodes are widely used in a variety of terminal equipment, from automotive headlights, traffic lights, text displays, billboards and large-screen video displays, to general and architectural lighting and LCD backlighting.
傳統的發光二極體驅動裝置,其資料傳遞僅利用時序信號單一上升緣來進行存取,其資料取樣的示意圖如圖1所示,圖1為根據習知技術之資料取樣示意圖。如圖1所示,時序信號CLK的上升緣會觸發驅動電路擷取資料輸入信號DIN,其取樣點(如S1、S2)會對應於時序信號CLK的上升緣。然而,隨著發光二極體的應用已廣泛的被用來顯示圖案,影像等視覺資訊,為了提高發光二極體驅動顯示灰階的變化或是增加發光二極體驅動裝置的串接數目,使得發光二極體驅動裝置單位時間內的資料傳輸量不斷的增加,意即時序信號頻率必須不斷的提升,由從前的數MHz等級提升到現在的超過30MHz的應用,然而,較高 的操作頻率會增加高頻干擾的影響,造成系統整體的穩定,也增加系統設計的困難。 In the conventional LED driving device, the data transmission is only accessed by using a single rising edge of the timing signal. The schematic diagram of the data sampling is shown in FIG. 1 , and FIG. 1 is a schematic diagram of data sampling according to the prior art. As shown in FIG. 1, the rising edge of the timing signal CLK triggers the driving circuit to capture the data input signal DIN, and the sampling points (such as S1, S2) correspond to the rising edge of the timing signal CLK. However, as the application of the light-emitting diode has been widely used to display visual information such as patterns and images, in order to improve the gray scale change of the LED driving display or increase the number of serial connections of the LED driving device, The data transmission amount per unit time of the LED driving device is continuously increased, that is, the frequency of the timing signal must be continuously increased, from the previous digital MHz level to the current application exceeding 30 MHz, however, higher The operating frequency increases the influence of high frequency interference, resulting in overall system stability and increasing system design difficulties.
本發明提供一種發光二極體的驅動電路,利用雙緣觸發的方式來擷取資料輸入信號,在不增加額外的控制信號的情況下,利用時序信號的上升緣與下降緣來進行觸發以取得兩倍的資料量。在相同資料的傳輸量下,本發明所需的時序信號的頻率僅需傳統發光二極體驅動電路資料擷取方法的一半。 The invention provides a driving circuit for a light-emitting diode, which uses a double-edge triggering method to extract a data input signal, and uses a rising edge and a falling edge of the timing signal to perform triggering without adding an additional control signal. Double the amount of data. Under the transmission of the same data, the frequency of the timing signal required by the present invention requires only half of the data acquisition method of the conventional LED driving circuit.
承上述,本發明提供一種發光二極體的驅動電路,包括一雙緣擷取資料傳遞單元、一信號處理單元以及一發光二極體驅動單元。雙緣擷取資料傳遞單元接收一時序信號與一資料輸入信號,上述雙緣觸發資料傳遞單元係由時序信號的上升緣與下降緣進行觸發以對資料輸入信號進行資料取樣並且依序儲存所擷取之資料輸入信號。信號處理單元耦接於雙緣擷取資料傳遞單元,用以儲存雙緣擷取資料傳遞單元所擷取的資料輸入信號並根據所儲存之資料輸入信號輸出一驅動致能信號。發光二極體驅動單元耦接於信號處理單元,並根據驅動致能信號輸出至少一個驅動信號以驅動至少一個發光二極體。 In view of the above, the present invention provides a driving circuit for a light emitting diode, comprising a double edge data transfer unit, a signal processing unit, and a light emitting diode driving unit. The dual-edge data transmission unit receives a timing signal and a data input signal, and the dual-edge trigger data transmission unit is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the data. Take the data input signal. The signal processing unit is coupled to the dual-edge data transmission unit for storing the data input signal captured by the dual-edge data transmission unit and outputting a driving enable signal according to the stored data input signal. The LED driving unit is coupled to the signal processing unit and outputs at least one driving signal to drive the at least one LED according to the driving enable signal.
在本發明一實施例中,上述雙緣擷取資料傳遞單元包括一脈衝產生電路與一單緣觸發移位暫存器。脈衝產生電路根據時序信號產生一脈衝信號,其中脈衝信號具有複數個第一脈衝與複數個第二脈衝,第一脈衝的時序對應於時序信號的上升緣,第二脈衝的時序對應於時序信號的下降緣。單緣觸發移位暫存器根據脈衝信號對資料輸入信號進行資料取樣並且依序儲存所擷取之資料輸入信號。 In an embodiment of the invention, the dual edge capture data transfer unit includes a pulse generation circuit and a single edge trigger shift register. The pulse generating circuit generates a pulse signal according to the timing signal, wherein the pulse signal has a plurality of first pulses and a plurality of second pulses, the timing of the first pulse corresponds to a rising edge of the timing signal, and the timing of the second pulse corresponds to the timing signal Falling edge. The single-edge trigger shift register performs data sampling on the data input signal according to the pulse signal and sequentially stores the captured data input signal.
在本發明一實施例中,上述雙緣擷取資料傳遞單元包括一雙緣觸發移位暫 存器,由時序信號的上升緣與下降緣進行觸發以對資料輸入信號進行資料取樣並且依序儲存所擷取之資料輸入信號。 In an embodiment of the invention, the double edge extraction data transfer unit includes a double edge trigger shift temporary The buffer is triggered by the rising edge and the falling edge of the timing signal to sample the data input signal and sequentially store the captured data input signal.
在本發明一實施例中,上述驅動電路更包括一時序處理單元,用以接收時序信號並用以輸出同相或反相之時序信號。 In an embodiment of the invention, the driving circuit further includes a timing processing unit for receiving the timing signal and outputting the in-phase or inverted timing signals.
在本發明一實施例中,上述雙緣擷取資料傳遞單元包括一第一雙緣觸發移位暫存器、一第二雙緣觸發移位暫存器、一資料輸入信號處理電路以及一多工器。第一雙緣觸發移位暫存器用以儲存該資料輸入信號中之一影像資料;第二雙緣觸發移位暫存器用以儲存該資料輸入信號中之一命令資料;資料輸入信號處理電路耦接於資料輸入訊號,用以輸出同相或反相之該資料輸入信號;多工器的三個輸入端分別耦接於第一雙緣觸發移位暫存器、第二雙緣觸發移位暫存器與資料輸入信號處理電路的輸出,多工器的一輸出端耦接於一資料輸出端,並根據一選擇信號決定多工器的輸出。 In an embodiment of the invention, the dual-edge data acquisition unit includes a first dual-edge trigger shift register, a second dual-edge trigger shift register, a data input signal processing circuit, and a plurality of Work tool. The first double edge trigger shift register is configured to store one image data in the data input signal; the second double edge trigger shift register is configured to store one of the data input signals; the data input signal processing circuit coupled Connected to the data input signal for outputting the data input signal in phase or inversion; the three input ends of the multiplexer are respectively coupled to the first double edge trigger shift register and the second double edge trigger shift temporary The output of the memory and the data input signal processing circuit, an output end of the multiplexer is coupled to a data output end, and the output of the multiplexer is determined according to a selection signal.
在本發明一實施例中,上述信號處理單元包括一資料儲存電路與一資料運算電路。資料儲存電路用以儲存雙緣擷取資料傳遞單元所擷取的該資料輸入信號;資料運算電路用以輸出驅動致能信號。 In an embodiment of the invention, the signal processing unit includes a data storage circuit and a data operation circuit. The data storage circuit is configured to store the data input signal captured by the double edge data acquisition unit; the data operation circuit is configured to output the drive enable signal.
在本發明一實施例中,上述資料儲存電路包括一第一資料儲存電路與一第二資料儲存電路。第一資料儲存電路根據一第一栓鎖信號儲存資料輸入信號中之一影像資料,第二資料儲存電路根據一第二栓鎖信號儲存資料輸入信號中之一命令資料。 In an embodiment of the invention, the data storage circuit includes a first data storage circuit and a second data storage circuit. The first data storage circuit stores one of the data input signals according to a first latch signal, and the second data storage circuit stores one of the data input signals according to a second latch signal.
在本發明一實施例中,上述資料運算電路包括一計數器與複數個比較器。比較器耦接於計數器與資料儲存電路,用以比較所儲存之資料輸入信號與計數器的輸出以產生驅動致能信號至發光二極體驅動單元。 In an embodiment of the invention, the data operation circuit includes a counter and a plurality of comparators. The comparator is coupled to the counter and the data storage circuit for comparing the stored data input signal with the output of the counter to generate a drive enable signal to the LED driver unit.
在本發明一實施例中,上述資料運算電路包括複數個及閘,該些及閘的輸入分別耦接於資料儲存電路與一致能信號,該些及閘的輸出則耦接於發光二極體驅動單元。 In an embodiment of the present invention, the data operation circuit includes a plurality of gates, and the inputs of the gates are respectively coupled to the data storage circuit and the uniform energy signal, and the outputs of the gates are coupled to the light emitting diodes. Drive unit.
在本發明一實施例中,上述驅動電路更包括一偵測保護單元,用以偵測發光二極體與驅動電路的狀態並輸出一偵測信號至資料傳遞單元,並可根據偵測結果提供保護功能。 In an embodiment of the invention, the driving circuit further includes a detection and protection unit for detecting the state of the LED and the driving circuit and outputting a detection signal to the data transmission unit, and providing the detection result according to the detection result. Protective function.
在本發明一實施例中,上述發光二極體驅動單元更包括發光二極體驅動電路與驅動信號設定電路。其中,發光二極體驅動電路耦接於信號處理單元,根據驅動致能信號輸出驅動信號以驅動上述發光二極體。驅動信號設定電路耦接於發光二極體驅動電路,用以調整發光二極體驅動電路所輸出之驅動信號。 In an embodiment of the invention, the LED driving unit further includes a LED driving circuit and a driving signal setting circuit. The LED driving circuit is coupled to the signal processing unit, and outputs a driving signal according to the driving enable signal to drive the LED. The driving signal setting circuit is coupled to the LED driving circuit for adjusting the driving signal output by the LED driving circuit.
在本發明一實施例中,上述之雙緣擷取資料傳遞單元包括一雙緣觸發移位暫存器、一資料輸入信號處理電路與一多工器。雙緣觸發移位暫存器由時序信號的上升緣與下降緣進行觸發以對資料輸入信號進行資料取樣並且依序儲存所擷取之該資料輸入信號;資料輸入信號處理電路接收資料輸入信號並輸出同相或反相之該資料輸入信號;多工器的輸入端分別耦接於雙緣觸發移位暫存器的輸出與資料輸入信號處理電路的輸出,多工器的輸出端則耦接於資料輸出端。 In an embodiment of the invention, the double edge data acquisition unit includes a dual edge trigger shift register, a data input signal processing circuit and a multiplexer. The dual-edge trigger shift register is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the captured data input signal; the data input signal processing circuit receives the data input signal and Outputting the data input signal in phase or inversion; the input ends of the multiplexer are respectively coupled to the output of the dual-edge trigger shift register and the output of the data input signal processing circuit, and the output end of the multiplexer is coupled to Data output.
在本發明一實施例中,上述驅動信號設定電路包括一參考電壓產生電路、一電流電壓轉換電路與一數位類比轉換電路。數位類比轉換電路耦接於信號處理單元以接收資料輸入信號中之一命令資料;電壓電流轉換電路耦接參考電壓產生電路與數位類比轉換電路,用以調整發光二極體驅動單元所輸出的驅動信號。 In an embodiment of the invention, the driving signal setting circuit includes a reference voltage generating circuit, a current voltage converting circuit and a digital analog converting circuit. The digital analog conversion circuit is coupled to the signal processing unit to receive one of the data input signals; the voltage current conversion circuit is coupled to the reference voltage generating circuit and the digital analog conversion circuit for adjusting the driving output of the LED driving unit. signal.
在本發明一實施例中,上述驅動電路更包括一控制單元,耦接於雙緣擷取資料傳遞單元,用以傳送時序信號與資料輸入信號至雙緣擷取資料傳遞單元。並藉由時序信號與資料輸入信號產生控制信號。 In an embodiment of the invention, the driving circuit further includes a control unit coupled to the dual-edge data transfer unit for transmitting the timing signal and the data input signal to the dual-edge data transfer unit. And generating a control signal by using the timing signal and the data input signal.
基於上述,本發明利用雙緣擷取資料傳遞單元來擷取發光二極體的驅動資料,由於時序信號的上升緣與下降緣皆可觸發雙緣擷取資料傳遞單元來進行資料擷取,因此在相同的資料傳輸量下,本發明所需的時序信號頻率可降低至傳統技術的一半,並可降低電磁干擾(Electromagnetic Interference,EMI)以增加系統整體的穩定,也簡化系統設計複雜度。 Based on the above, the present invention utilizes the dual-edge data acquisition unit to capture the driving data of the LED, and both the rising edge and the falling edge of the timing signal can trigger the dual-edge data transmission unit to perform data acquisition. Under the same data transmission amount, the frequency of the timing signal required by the invention can be reduced to half of the conventional technology, and Electromagnetic Interference (EMI) can be reduced to increase the stability of the whole system and simplify the system design complexity.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
200、400、500、600‧‧‧驅動電路 200, 400, 500, 600‧‧‧ drive circuits
210、410、610‧‧‧雙緣擷取資料傳遞單元 210, 410, 610‧‧‧Double-edge data transfer unit
220、420‧‧‧信號處理單元 220, 420‧‧‧ Signal Processing Unit
230、430、530、630‧‧‧發光二極體驅動單元 230, 430, 530, 630‧‧‧Lighting diode drive unit
440、640‧‧‧時序處理單元 440, 640‧‧‧Time Processing Unit
310‧‧‧單緣觸發移位暫存器 310‧‧‧Single edge trigger shift register
320‧‧‧脈衝產生電路 320‧‧‧Pulse generation circuit
413‧‧‧雙緣擷取移位暫存電路 413‧‧‧Double edge capture shift register circuit
415、615‧‧‧資料輸入信號處理電路 415, 615‧‧‧ data input signal processing circuit
417、617‧‧‧多工器 417, 617‧‧‧ multiplexers
421、621‧‧‧資料儲存電路 421, 621‧‧‧ data storage circuit
422、622‧‧‧資料運算電路 422, 622‧‧‧ data operation circuit
432、532、632‧‧‧發光二極體驅動電路 432, 532, 632‧‧‧Lighting diode driving circuit
450、650‧‧‧偵測保護單元 450, 650‧‧‧Detection protection unit
460、660‧‧‧控制單元 460, 660‧‧‧ control unit
470、570、670‧‧‧驅動信號設定電路 470, 570, 670‧‧‧ drive signal setting circuit
510‧‧‧8位元雙緣擷取移位暫存器 510‧‧8-bit double-edge capture shift register
521‧‧‧8位元資料儲存電路 521‧‧8-bit data storage circuit
522‧‧‧8位元資料運算電路 522‧‧8 bit data operation circuit
613、614‧‧‧雙緣觸發移位暫存器 613, 614‧‧‧ double edge trigger shift register
623‧‧‧第一資料儲存電路 623‧‧‧First data storage circuit
624‧‧‧第二資料儲存電路 624‧‧‧Second data storage circuit
672‧‧‧數位類比轉換電路 672‧‧‧Digital analog conversion circuit
674‧‧‧參考電壓產生電路 674‧‧‧reference voltage generation circuit
676‧‧‧電壓電流轉換電路 676‧‧‧Voltage current conversion circuit
680‧‧‧電源管理系統 680‧‧‧Power Management System
CLK、CKI、CKI1、CKI2‧‧‧時序信號 CLK, CKI, CKI 1 , CKI 2 ‧‧‧ timing signals
CKO‧‧‧時序輸出信號 CKO‧‧‧ timing output signal
DIN‧‧‧資料輸入信號 DIN‧‧‧ data input signal
DO‧‧‧資料輸出信號 DO‧‧‧ data output signal
EN‧‧‧致能信號 EN‧‧‧Enable signal
LAT、LAT1、LAT2‧‧‧栓鎖信號 LAT, LAT 1 , LAT 2 ‧‧‧ latch signal
MODE‧‧‧工作模式信號 MODE‧‧‧ working mode signal
PUS‧‧‧脈衝信號 PUS‧‧‧ pulse signal
P1、P2‧‧‧脈衝 P1, P2‧‧‧ pulse
S1~S3‧‧‧取樣點 S1~S3‧‧‧ sampling point
SEL‧‧‧選擇信號 SEL‧‧‧Selection signal
43b~43z‧‧‧比較器 43b~43z‧‧‧ comparator
43a‧‧‧計數器 43a‧‧‧ counter
圖1為根據習知技術之資料取樣示意圖。 FIG. 1 is a schematic diagram of data sampling according to the prior art.
圖2A為根據本發明第一實施例之發光二極體的驅動電路方塊圖。 2A is a block diagram of a driving circuit of a light emitting diode according to a first embodiment of the present invention.
圖2B為根據本發明第一實施例之資料取樣時序示意圖。 2B is a schematic diagram showing the timing of data sampling according to the first embodiment of the present invention.
圖3A為根據本發明第一實施例之雙緣擷取資料傳輸單元的內部電路圖。 3A is an internal circuit diagram of a dual-edge capture data transmission unit according to a first embodiment of the present invention.
圖3B為根據本實施例之脈衝信號波型圖。 Fig. 3B is a waveform diagram of a pulse signal according to the present embodiment.
圖4為根據本發明第二實施例的驅動電路。 4 is a driving circuit in accordance with a second embodiment of the present invention.
圖5為根據本發明第三實施例之驅動電路圖。 Figure 5 is a diagram showing a driving circuit in accordance with a third embodiment of the present invention.
圖6為根據本發明第四實施例之驅動電路圖。 Figure 6 is a diagram showing a driving circuit in accordance with a fourth embodiment of the present invention.
圖7為根據本發明第四實施例之資料輸出信號波形圖。 Figure 7 is a waveform diagram of a data output signal in accordance with a fourth embodiment of the present invention.
請參照圖2A,圖2A為根據本發明第一實施例之發光二極體的驅動電路方塊圖。驅動電路200包括雙緣擷取資料傳遞單元210、信號處理單元220以及發光二極體驅動單元230。信號處理單元220耦接於雙緣擷取資料傳遞單元210與發光二極體驅動單元230之間,用來儲存雙緣擷取資料傳遞單元210所擷取的資料以及進行資料運算功能。信號處理單元220中會包括多組多位元資料儲存電路以進行資料儲存。其中,資料儲存電路則例如是資料栓鎖器,其位元數則是設計需求而定,本實施例並不受限。 Referring to FIG. 2A, FIG. 2A is a block diagram of a driving circuit of a light emitting diode according to a first embodiment of the present invention. The driving circuit 200 includes a double edge data transfer unit 210, a signal processing unit 220, and a light emitting diode driving unit 230. The signal processing unit 220 is coupled between the dual-edge capture data transfer unit 210 and the LED driver unit 230 for storing data captured by the dual-edge capture data transfer unit 210 and performing data calculation functions. A plurality of sets of multi-bit data storage circuits are included in the signal processing unit 220 for data storage. The data storage circuit is, for example, a data latch, and the number of bits is determined by design requirements, and the embodiment is not limited.
信號處理單元220會儲存雙緣擷取資料傳遞單元210所擷取的資料輸入信號DIN並根據所儲存之資料輸入信號DIN進行運算以輸出驅動致能信號至發光二極體驅動單元230。發光二極體驅動單元230會根據信號處理單元220所輸出的驅動致能信號產生多個驅動信號(例如K個,K為正整數)以驅動發光二極體。發光二極體驅動單元230可透過調整驅動電壓或電流來調整發光二極體的灰階度(亮度)。 The signal processing unit 220 stores the data input signal DIN captured by the dual-edge data transfer unit 210 and operates according to the stored data input signal DIN to output a drive enable signal to the LED driving unit 230. The LED driving unit 230 generates a plurality of driving signals (for example, K, K is a positive integer) according to the driving enable signal outputted by the signal processing unit 220 to drive the LED. The LED driving unit 230 can adjust the gray scale (brightness) of the LED by adjusting the driving voltage or current.
雙緣擷取資料傳遞單元210接收資料輸入信號DIN與時序信號CKI,由時序信號CKI的上升緣與下降緣進行觸發以對資料輸入信號DIN進行資料取樣並且依序儲存所擷取之資料輸入信號DIN。資料取樣時序請參照圖2B,圖2B為根據本發明第一實施例之資料取樣時序示意圖,其中取樣點S1~S3表示雙緣擷取資料傳輸單元210擷取資料輸入信號的DIN的時間點。取樣點S1、S3對應於時序信號CKI的上升緣,取樣點S2即對應於時序信號CKI的下降緣。由圖2B可知,在相同頻率的時序信號CKI下,雙緣擷取資料傳輸單元210會比單緣觸發的電路增加一倍的資料擷取量。若所需擷取的資料量相同,則其時序信號CKI的頻率可降 低為習知時序信號的一半即可讓雙緣擷取資料傳輸單元210擷取到所需的資料量。 The dual-edge data acquisition unit 210 receives the data input signal DIN and the timing signal CKI, and is triggered by the rising edge and the falling edge of the timing signal CKI to sample the data input signal DIN and sequentially store the captured data input signal. DIN. Referring to FIG. 2B, FIG. 2B is a schematic diagram of the sampling timing of the data according to the first embodiment of the present invention, wherein the sampling points S1 to S3 indicate the time point of the DIN of the data input signal captured by the double-edge data transmission unit 210. The sampling points S1, S3 correspond to the rising edge of the timing signal CKI, and the sampling point S2 corresponds to the falling edge of the timing signal CKI. As can be seen from FIG. 2B, under the timing signal CKI of the same frequency, the double-edge data transmission unit 210 will double the data acquisition amount than the single-edge circuit. If the amount of data to be acquired is the same, the frequency of the timing signal CKI can be lowered. A low half of the conventional timing signal allows the dual edge capture data transfer unit 210 to capture the desired amount of data.
雙緣擷取資料傳輸單元210的內部電路可直接利用雙緣觸發移位暫存器來實現,也可利用脈衝產生電路與單緣觸發移位暫存器來實現。請參照3A,圖3A為根據本發明第一實施例之雙緣擷取資料傳輸單元的內部電路圖。雙緣擷取資料傳輸單元210包括脈衝產生電路320與單緣觸發移位暫存器310。脈衝產生電路320耦接於單緣觸發移位暫存器310,用以轉換所接收到的時序信號CKI。脈衝產生電路320會根據時序信號CKI產生一脈衝信號,當時序信號CKI由低準位轉態為高準位(即上升緣)或由高準位轉態為低準位(即下降緣),脈衝產生電路320均會產生一個脈衝。 The internal circuit of the dual-edge data transmission unit 210 can be directly implemented by using a dual-edge trigger shift register, or can be realized by using a pulse generation circuit and a single-edge trigger shift register. Referring to FIG. 3A, FIG. 3A is an internal circuit diagram of a dual-edge capture data transmission unit according to a first embodiment of the present invention. The double edge capture data transfer unit 210 includes a pulse generation circuit 320 and a single edge trigger shift register 310. The pulse generating circuit 320 is coupled to the single-edge trigger shift register 310 for converting the received timing signal CKI. The pulse generating circuit 320 generates a pulse signal according to the timing signal CKI, when the timing signal CKI transitions from a low level to a high level (ie, a rising edge) or a high level to a low level (ie, a falling edge). The pulse generating circuit 320 generates a pulse.
請參照圖3B,圖3B為根據本實施例之脈衝信號波型圖。由圖3B可知,脈衝信號PUS會對應於時序信號CKI的上升緣與下降緣產生對應的脈衝。其中,脈衝P1的時序即對應於時序信號CKI的上升緣,而脈衝P2的時序即對應於時序信號的下降緣。其中,值得注意的是,脈衝信號PUS中每一個脈衝的寬度會小於時序信號CKI的半個週期,避免相鄰脈衝的波形產生重疊的情況。當時序信號CKI中的時脈週期愈小時,所對應產生的脈衝寬度也必須越小。 Please refer to FIG. 3B. FIG. 3B is a waveform diagram of a pulse signal according to the embodiment. As can be seen from FIG. 3B, the pulse signal PUS will generate a corresponding pulse corresponding to the rising edge and the falling edge of the timing signal CKI. The timing of the pulse P1 corresponds to the rising edge of the timing signal CKI, and the timing of the pulse P2 corresponds to the falling edge of the timing signal. Among them, it is worth noting that the width of each pulse in the pulse signal PUS is less than half a cycle of the timing signal CKI, avoiding the overlap of the waveforms of adjacent pulses. When the clock period in the timing signal CKI is smaller, the corresponding pulse width must also be smaller.
由於脈衝產生電路320可將時序信號CKI轉換為具有兩倍脈衝個數的脈衝信號PUS,因此不論單緣觸發移位暫存器310是採用正緣觸發或負緣觸發的方式來擷取資料,皆可藉由脈衝信號PUS達到兩倍資料擷取量的效果。在本實施例中,單緣觸發移位暫存器310是採用正緣觸發的方式來進行擷取,因此在脈衝信號PUS中的每個脈衝的上升緣皆會進行資料取樣的動作,其取樣時間與直接利用雙緣觸發暫存器來實現雙緣擷取資料傳遞單元210的取樣時間與資料取樣率相 同。 Since the pulse generation circuit 320 can convert the timing signal CKI into a pulse signal PUS having twice the number of pulses, the single-edge trigger shift register 310 uses a positive edge trigger or a negative edge trigger to capture data. The effect of twice the amount of data acquisition can be achieved by the pulse signal PUS. In this embodiment, the single-edge trigger shift register 310 performs the method of positive edge triggering. Therefore, the rising edge of each pulse in the pulse signal PUS performs the data sampling operation, and the sampling is performed. Time and direct use of the dual edge trigger register to achieve the sampling time and data sampling rate of the dual edge data transfer unit 210 with.
由於發光二極體顯示器通常具有多個發光二極體,若單一驅動晶片不足以驅動所有發光二極體,通常會串接多個驅動晶片來進行驅動。此時,驅動晶片之間便需要傳遞所接收到的資料輸入信號DIN以達到驅動多個發光二極體的功效。因此,在本實施例中,雙緣擷取資料傳遞單元210可在擷取資料輸入信號DIN之後,依照電路設定將資料輸入信號DIN傳遞至下一級的驅動電路。雙緣擷取資料傳遞單元210在資料輸出端所輸出的信號稱為資料輸出信號DO,其中資料輸出信號DO可為同相或反相的資料輸入信號DIN,也可以輸出將雙緣擷取資料傳遞單元210所擷取的資料。此外,驅動電路200也可以輸出同相或反相之時序信號CKI。 Since a light-emitting diode display usually has a plurality of light-emitting diodes, if a single driving chip is insufficient to drive all of the light-emitting diodes, a plurality of driving wafers are usually connected in series for driving. At this time, the received data input signal DIN needs to be transmitted between the driving chips to achieve the function of driving the plurality of light emitting diodes. Therefore, in this embodiment, the double-edge capture data transfer unit 210 can transfer the data input signal DIN to the drive circuit of the next stage according to the circuit setting after the data input signal DIN is captured. The signal outputted by the dual-edge data transmission unit 210 at the data output end is referred to as a data output signal DO, wherein the data output signal DO may be an in-phase or inverted data input signal DIN, or may output a double-edge data acquisition. The data retrieved by unit 210. In addition, the driving circuit 200 can also output the in-phase or inverted timing signal CKI.
關於資料輸入信號DIN的傳遞請參照圖4,圖4為根據本發明第二實施例的驅動電路。驅動電路400包括雙緣擷取資料傳遞單元410、信號處理單元420、發光二極體驅動單元430、時序處理單元440、偵測保護單元450以及控制單元460。其中,信號處理單元420包括資料儲存電路421與資料運算電路422,而發光二極體驅動單元430包括發光二極體驅動電路432與驅動信號設定電路470。雙緣擷取資料傳遞單元410則包括雙緣擷取移位暫存電路413、資料輸入信號處理電路415與多工器417。多工器417的輸入端分別耦接於雙緣擷取移位暫存電路413與資料輸入信號處理電路415的輸出,多工器417的輸出耦接於驅動電路400的資料輸出端,並根據控制單元460所輸出的選擇信號SEL選擇雙緣擷取移位暫存電路413與資料輸入信號處理電路415其中之一的輸出以產生資料輸出信號DO。 Referring to FIG. 4 for the transmission of the data input signal DIN, FIG. 4 is a driving circuit according to a second embodiment of the present invention. The driving circuit 400 includes a dual edge data transmission unit 410, a signal processing unit 420, a light emitting diode driving unit 430, a timing processing unit 440, a detection protection unit 450, and a control unit 460. The signal processing unit 420 includes a data storage circuit 421 and a data operation circuit 422, and the LED driving unit 430 includes a light emitting diode driving circuit 432 and a driving signal setting circuit 470. The double edge capture data transfer unit 410 includes a double edge capture shift temporary storage circuit 413, a data input signal processing circuit 415, and a multiplexer 417. The input end of the multiplexer 417 is coupled to the output of the dual-edge capture shift register circuit 413 and the data input signal processing circuit 415, and the output of the multiplexer 417 is coupled to the data output end of the drive circuit 400, and The selection signal SEL outputted by the control unit 460 selects the output of one of the double-edge capture shift register circuit 413 and the data input signal processing circuit 415 to generate the data output signal DO.
資料輸入信號處理電路415可依據設定輸出正相或反相的資料輸入信 號DIN,當輸出反相的資料輸入信號DIN時,可有效降低資料輸入信號DIN在傳遞時的衰減問題。讓資料輸入信號DIN在經過數級的驅動電路傳遞後,依然保持資料輸入信號DIN的脈衝寬度與其波形。時序處理單元440則是用來傳遞時序信號CKI,可依據設定輸出正相或反相之時序信號CKI以產生時序輸出信號CKO。同樣地,當輸出反相之時序信號CKI時,可有效降低時序信號CKI在傳遞時的衰減問題。讓時序信號CKI在經過數級的驅動電路傳遞後,依然保持時序信號CKI的脈衝寬度與其波形。 The data input signal processing circuit 415 can output a positive or negative data input signal according to the setting. No. DIN, when outputting the inverted data input signal DIN, it can effectively reduce the attenuation of the data input signal DIN during transmission. After the data input signal DIN is transmitted through the drive circuit of several stages, the pulse width of the data input signal DIN and its waveform are still maintained. The timing processing unit 440 is configured to transmit the timing signal CKI, and may output a timing signal CKI of a positive phase or an inverted phase according to the setting to generate the timing output signal CKO. Similarly, when the inverted timing signal CKI is output, the attenuation problem of the timing signal CKI at the time of transmission can be effectively reduced. After the timing signal CKI is transmitted through the driving circuit of several stages, the pulse width of the timing signal CKI and its waveform are still maintained.
由於製程的變異會造成驅動電路在傳遞信號時有上升緣時間與下降緣時間的差異,因此藉由將信號反相後再進行傳遞,可有效消除因上升緣時間與下降緣時間的差異所造成的信號衰減或失真等問題。 Since the variation of the process causes the drive circuit to have a difference between the rising edge time and the falling edge time when transmitting the signal, the signal can be effectively inverted to eliminate the difference between the rising edge time and the falling edge time by inverting the signal and then transmitting the signal. Problems such as signal attenuation or distortion.
此外,在電路結構中,時序處理單元440可以直接耦接於時序信號CKI與時脈輸出端之間,用來傳遞同相或反相的時序信號CKI至下一級的驅動電路。也就是說,驅動電路400可選擇性的將資料輸入信號DIN與時序信號CKI傳遞至下一級的驅動電路或者透過資料輸出端與時序信號輸出端輸出驅動電路400的內部狀態值給系統以進行監控與調整。 In addition, in the circuit structure, the timing processing unit 440 can be directly coupled between the timing signal CKI and the clock output terminal for transmitting the in-phase or inverted timing signal CKI to the driving circuit of the next stage. That is, the driving circuit 400 can selectively transmit the data input signal DIN and the timing signal CKI to the driving circuit of the next stage or output the internal state value of the driving circuit 400 to the system through the data output terminal and the timing signal output terminal for monitoring. With adjustments.
雙緣擷取移位暫存電路413則可由雙緣移位暫存器所組成或由單緣移位暫存器310與脈衝產生電路320所組成(如圖3所示)。雙緣擷取移位暫存電路413會由時序信號CKI的上升緣與下降緣進行觸發,以雙緣擷取的方式對資料輸入信號DIN進行資料取樣並且依序儲存所擷取之資料輸入信號DIN。 The double edge capture shift register circuit 413 can be composed of a double edge shift register or a single edge shift register 310 and a pulse generating circuit 320 (as shown in FIG. 3). The double-edge capture shift register circuit 413 is triggered by the rising edge and the falling edge of the timing signal CKI, and samples the data input signal DIN in a double-edge manner and sequentially stores the captured data input signal. DIN.
資料儲存電路421耦接於資料運算電路422與雙緣擷取移位暫存電路413之間,並根據控制單元460所輸出的拴鎖信號LAT拴鎖雙緣擷取移位暫存電路413中所暫存的資料,然後傳送至資料運算電路422進行運算。資料運算電路422根據 所擷取之資料輸入信號DIN輸出驅動致能信號至發光二極體動電路432以輸出對應的驅動信號。其中,資料運算電路422可由及閘或數位比較器所組成,但本發明並不限制於此。在本實施例中,發光二極體驅動電路輸出K個驅動信號,K為正整數。 The data storage circuit 421 is coupled between the data operation circuit 422 and the double edge capture shift register circuit 413, and is latched in the shift register circuit 413 according to the latch signal LAT outputted by the control unit 460. The temporarily stored data is then transferred to the data operation circuit 422 for calculation. The data operation circuit 422 is based on The extracted data input signal DIN outputs a drive enable signal to the LED circuit 432 to output a corresponding drive signal. The data operation circuit 422 may be composed of a gate or a digital comparator, but the present invention is not limited thereto. In this embodiment, the LED driving circuit outputs K driving signals, and K is a positive integer.
發光二極體驅動單元430主要由發光二極體驅動電路432與驅動信號設定電路470所組成,驅動信號設定電路470耦接於發光二極體驅動電路432,其中驅動信號設定電路470主要是用來設定發光二極體驅動電路432的驅動電流、電壓或有效致能時間(duty cycle)的大小。驅動信號設定電路470同樣可根據驅動電路400所接收到的資料輸入信號DIN設定所需的參數以調整發光二極體驅動電路432所輸出的驅動信號。驅動信號設定電路470可直接經由雙緣擷取資料傳遞單元410接收所需的命令資料或是經由控制單元460接收不同的工作模式調整信號MODE。 The driving diode setting unit 430 is mainly composed of the LED driving circuit 432 and the driving signal setting circuit 470. The driving signal setting circuit 470 is coupled to the LED driving circuit 432. The driving signal setting circuit 470 is mainly used. The magnitude of the drive current, voltage, or duty cycle of the LED driving circuit 432 is set. The drive signal setting circuit 470 can also set the required parameters according to the data input signal DIN received by the drive circuit 400 to adjust the drive signal output by the LED driver circuit 432. The drive signal setting circuit 470 can receive the required command material directly via the double edge capture data transfer unit 410 or receive a different work mode adjustment signal MODE via the control unit 460.
控制單元460耦接於雙緣擷取資料傳遞單元410、資料儲存電路421與偵測保護單元450。控制單元460可根據資料輸入信號DIN與時序信號CKI的波形組合或所傳遞的數據資料輸出拴鎖信號LAT、工作模式信號MODE與選擇信號SEL等控制信號或參數設定信號。此外,當資料輸入信號DIN與時序信號CKI係為編碼後之資料時,控制單元460也可以用來對資料輸入信號DIN與時序信號CKI進行解碼,然後再將解碼後之資料輸入信號DIN與時序信號CKI傳遞至雙緣擷取資料傳遞單元410。 The control unit 460 is coupled to the dual edge capture data transfer unit 410, the data storage circuit 421, and the detection protection unit 450. The control unit 460 can output a control signal or a parameter setting signal such as the shackle signal LAT, the operation mode signal MODE, and the selection signal SEL according to the waveform combination of the data input signal DIN and the timing signal CKI or the transmitted data. In addition, when the data input signal DIN and the timing signal CKI are encoded data, the control unit 460 can also be used to decode the data input signal DIN and the timing signal CKI, and then input the decoded data input signal DIN and timing. The signal CKI is passed to the double edge capture data transfer unit 410.
由於驅動電路400可具有多種驅動模式,或是多種調整參數值。控制單元460可直接經由資料輸入信號DIN與時序信號CKI來決定其參數值。換句話說,資料輸入信號DIN包括影像資料與命令資料,影像資料用以決定發光二極體的灰階值,而命令資料則是用來設定驅動電路400中的參數值。控制單元460可 根據資料輸入信號DIN中的命令資料輸出模式設定信號MODE以調整偵測保護單元450的工作模式以偵測不同的電路參數與環境狀態值。 Since the driving circuit 400 can have multiple driving modes, or a plurality of adjustment parameter values. The control unit 460 can determine its parameter value directly via the data input signal DIN and the timing signal CKI. In other words, the data input signal DIN includes image data and command data, the image data is used to determine the gray scale value of the light emitting diode, and the command data is used to set the parameter value in the driving circuit 400. The control unit 460 can The mode setting signal MODE is output according to the command data in the data input signal DIN to adjust the working mode of the detecting and protecting unit 450 to detect different circuit parameters and environmental state values.
偵測保護單元450可依照工作模式信號MODE來偵測驅動電路的內部狀態,例如溫度、電壓、電流、電路是否失能等狀態,以及發光二極體的狀態,例如開路、短路、損壞、老化程度等。偵測保護單元450中可增設一般電路內所需的偵測元件與偵測功能以進行電路狀態監控與即時調整。值得注意的是,偵測保護單元450可依照設計者所設定的參數進行電路偵測與電路保護,例如過熱保護或過壓保護等,同時偵測保護單元450可透過雙緣擷取資料傳遞單元410或特定的信號接腳輸出偵測結果。 The detection protection unit 450 can detect the internal state of the driving circuit according to the working mode signal MODE, such as temperature, voltage, current, whether the circuit is disabled, and the state of the LED, such as open circuit, short circuit, damage, aging. Degree and so on. The detection and protection unit 450 can add a detection component and a detection function required in a general circuit for circuit state monitoring and immediate adjustment. It should be noted that the detection and protection unit 450 can perform circuit detection and circuit protection according to parameters set by the designer, such as overheat protection or overvoltage protection, and the detection protection unit 450 can transmit the data transmission unit through the double edge. 410 or a specific signal pin outputs the detection result.
接下來,進一步以8位元的驅動電路為例說明本發明之驅動電路。請參照圖5,圖5為根據本發明第三實施例之驅動電路圖。驅動電路500包括8位元雙緣擷取移位暫存器510、8位元資料儲存電路521、8位元資料運算電路522、發光二極體驅動單元530,其中發光二極體驅動單元530包括發光二極體驅動電路532與驅動信號設定電路570。8位元資料運算電路522耦接於發光二極體驅動單元530與8位元資料儲存電路521之間,8位元資料儲存電路521的另一側則耦接於8位元雙緣擷取移位暫存器510。值得注意的是,發光二極體驅動電路432內可包括8個發光二極體驅動電路以輸出8個驅動信號。 Next, the driving circuit of the present invention will be further described by taking an 8-bit driving circuit as an example. Please refer to FIG. 5. FIG. 5 is a diagram of a driving circuit according to a third embodiment of the present invention. The driving circuit 500 includes an 8-bit dual-edge capture shift register 510, an 8-bit data storage circuit 521, an 8-bit data operation circuit 522, and a light-emitting diode driving unit 530, wherein the light-emitting diode driving unit 530 The illuminating diode driving circuit 532 and the driving signal setting circuit 570 are included. The 8-bit data operation circuit 522 is coupled between the LED driving unit 530 and the 8-bit data storage circuit 521, and the 8-bit data storage circuit 521 is provided. The other side is coupled to the 8-bit dual-edge capture shift register 510. It should be noted that the LED driving circuit 432 may include eight LED driving circuits to output eight driving signals.
8位元資料儲存電路521會根據栓鎖信號LAT來進行資料栓鎖以儲存8位元雙緣擷取移位暫存器510所擷取的資料。資料運算電路522由多個及閘組成,個別及閘的輸入耦接於致能信號EN與資料儲存電路521所輸出的驅動資料。資料運算電路522根據8位元資料儲存電路521所儲存的資料與致能信號EN分別決定發光 二極體驅動電路532是否致能以輸出驅動信號。本實施例中,雖以8位元為例來說明8位元雙緣擷取移位暫存器510以及8位元資料儲存電路521,然而上述電路結構並不受限於8位元,也可適用於更高或更低位元的電路結構。值得注意的是,栓鎖信號LAT與致能信號EN可由控制單元輸出或外部輸入,本實施例並不受限。關於驅動電路500的其餘構件與其操作方式參照上述圖4實施例中說明,在此不加累述。 The 8-bit data storage circuit 521 performs data latching according to the latch signal LAT to store the data captured by the 8-bit dual-edge capture shift register 510. The data operation circuit 522 is composed of a plurality of gates, and the input of the individual gates is coupled to the enable signal EN and the drive data output by the data storage circuit 521. The data operation circuit 522 determines the light emission according to the data stored in the 8-bit data storage circuit 521 and the enable signal EN, respectively. Whether the diode drive circuit 532 is enabled to output a drive signal. In this embodiment, the 8-bit dual-edge capture shift register 510 and the 8-bit data storage circuit 521 are illustrated by taking an 8-bit as an example. However, the above circuit structure is not limited to 8-bit. A circuit structure that can be applied to higher or lower bits. It should be noted that the latch signal LAT and the enable signal EN may be output by the control unit or externally input, and the embodiment is not limited. The remaining components of the drive circuit 500 and the manner of operation thereof are described with reference to the above-described embodiment of FIG. 4, and are not described herein.
由於資料輸入信號可以包含多種資料,包括影像資料與設定工作模式用的命令資料,因此上述驅動電路中之雙緣擷取資料傳遞單元與信號處理單元亦可對應設置兩組資料儲存電路。請參照圖6,圖6為根據本發明第四實施例之驅動電路圖。驅動電路600包括雙緣擷取資料傳遞單元610、資料儲存電路621、資料運算電路622、發光二極體驅動單元630、時序處理單元640、偵測保護單元650、控制單元660以及電源管理系統680。 Since the data input signal can include a plurality of materials, including image data and command data for setting the working mode, the double-edge data transfer unit and the signal processing unit in the driving circuit can also be configured with two sets of data storage circuits. Please refer to FIG. 6. FIG. 6 is a circuit diagram of a driving circuit according to a fourth embodiment of the present invention. The driving circuit 600 includes a dual-edge data transfer unit 610, a data storage circuit 621, a data operation circuit 622, a light-emitting diode driving unit 630, a timing processing unit 640, a detection protection unit 650, a control unit 660, and a power management system 680. .
雙緣擷取資料傳遞單元610包括雙緣觸發移位暫存器613、614、多工器617以及資料輸入信號處理電路615。多工器617的三個輸入端分別耦接於雙緣觸發移位暫存器613、614與資料輸入信號處理電路615,其控制端耦接於控制單元660,多工器617的輸出端則耦接於驅動電路600的資料輸出端以輸出資料輸出信號DO。其中,資料輸入信號處理電路615可透過多工器617將資料輸入信號DIN的同相或反相傳送至驅動電路600的資料輸出端。 The double edge capture data transfer unit 610 includes double edge trigger shift registers 613, 614, a multiplexer 617, and a data input signal processing circuit 615. The three input ends of the multiplexer 617 are respectively coupled to the dual-edge trigger shift register 613, 614 and the data input signal processing circuit 615, and the control end thereof is coupled to the control unit 660, and the output end of the multiplexer 617 is connected. The data output end of the driving circuit 600 is coupled to output a data output signal DO. The data input signal processing circuit 615 can transmit the in-phase or in-phase of the data input signal DIN to the data output end of the driving circuit 600 through the multiplexer 617.
控制單元660根據時序信號CKI分別輸出時序信號CKI1、CKI2以及資料輸入信號DIN至雙緣觸發移位暫存器613、614。雙緣觸發移位暫存器613、614會根據時序信號CKI1、CKI2擷取資料輸入信號DIN並依序傳遞出所擷取資料的資 料。控制單元660也會將資料輸入信號DIN輸出至資料輸入處理電路615,資料輸入處理電路615可輸出同相或反相的資料輸入信號DIN。控制單元660利用選擇信號SEL切換多工器617來選擇性切換所欲輸出的資料輸出信號DO。 The control unit 660 outputs the timing signals CKI 1 , CKI 2 and the data input signal DIN to the double-edge trigger shift registers 613, 614 according to the timing signal CKI, respectively. The dual-edge trigger shift registers 613 and 614 retrieve the data input signal DIN according to the timing signals CKI 1 and CKI 2 and sequentially transmit the data of the captured data. The control unit 660 also outputs the data input signal DIN to the data input processing circuit 615, and the data input processing circuit 615 can output the in-phase or inverted data input signal DIN. The control unit 660 switches the multiplexer 617 with the selection signal SEL to selectively switch the data output signal DO to be output.
雙緣觸發移位暫存器613、614皆是屬於雙緣觸發的暫存器,可由時序信號CKI1、CKI2的上升緣與下降緣進行觸發以進行資料取樣。在本實施例中,雙緣觸發移位暫存器613例如是M個12位元的雙緣觸發移位暫存器,而雙緣觸發移位暫存器614則例如是7位元的雙緣觸發移位暫存器,其中M為正整數,表示驅動信號的個數。值得注意的是,時序信號CKI1、CKI2可由控制單元660根據時序信號CKI產生。 The dual-edge trigger shift registers 613 and 614 are all buffers belonging to the double-edge trigger, and can be triggered by the rising edge and the falling edge of the timing signals CKI 1 and CKI 2 for data sampling. In this embodiment, the double-edge trigger shift register 613 is, for example, M 12-bit dual-edge trigger shift registers, and the double-edge trigger shift register 614 is, for example, a 7-bit double. The edge triggers the shift register, where M is a positive integer representing the number of drive signals. It should be noted that the timing signals CKI 1 , CKI 2 can be generated by the control unit 660 according to the timing signal CKI.
時序處理單元640與上述實施例相同,主要用來傳遞時序信號CKI以產生時序輸出信號CKO。配合資料輸出信號DO與時序輸出信號CKO,驅動電路600可輸出電路內部的狀態值或將資料輸入信號DIN與時序信號CKI傳遞至下一級的驅動電路。時序處理單元640的操作方式與前述實施例相同,在此不加累述。 The timing processing unit 640 is the same as the above embodiment, and is mainly used to transmit the timing signal CKI to generate the timing output signal CKO. In conjunction with the data output signal DO and the timing output signal CKO, the driving circuit 600 can output a state value inside the circuit or transfer the data input signal DIN and the timing signal CKI to the driving circuit of the next stage. The operation of the timing processing unit 640 is the same as that of the previous embodiment, and will not be described here.
資料儲存電路621與資料運算電路622則組成信號處理單元,耦接於雙緣擷取資料傳遞單元610與發光二極體驅動單元630之間。資料儲存電路621中尚包括第一資料儲存電路623與第二資料儲存電路624。第一資料儲存電路623與第二資料儲存電路624可分別根據栓鎖信號LAT1、LAT2栓鎖雙緣觸發移位暫存器613、614所擷取的資料(例如影像資料或命令資料)。第一資料儲存電路623則可包括M個12位元的資料儲存電路以對應儲存雙緣觸發移位暫存器613所擷取的資料。第二資料儲存電路624則例如是7位元的資料儲存電路以對應儲存雙緣觸發移位暫存器614所擷取的資料。值得注意的是,栓鎖信號LAT1、LAT2可由控 制單元660產生,但不受限於由控制單元660產生,亦可由外界(前端電路或系統)提供。 The data storage circuit 621 and the data operation circuit 622 are combined to form a signal processing unit, which is coupled between the dual-edge capture data transfer unit 610 and the light-emitting diode drive unit 630. The data storage circuit 621 further includes a first data storage circuit 623 and a second data storage circuit 624. The first data storage circuit 623 and the second data storage circuit 624 can latch the data (such as image data or command data) captured by the double-edge trigger shift registers 613, 614 according to the latch signals LAT 1 and LAT 2 , respectively. . The first data storage circuit 623 can include M 12-bit data storage circuits to correspond to the data captured by the dual-edge trigger shift register 613. The second data storage circuit 624 is, for example, a 7-bit data storage circuit to correspond to the data captured by the dual edge trigger shift register 614. It should be noted that the latch signals LAT 1 , LAT 2 may be generated by the control unit 660, but are not limited to being generated by the control unit 660, and may also be provided by the outside (front end circuit or system).
資料運算電路622包括計數器43a與複數個比較器43b~43z(例如數位比較器),比較器43b~43z用來比較計數器43a的輸出與第一資料儲存電路623中所栓鎖的資料,然後據以致能發光二極體驅動單元630是否輸出M個驅動信號。資料運算電路622藉由計數器43a與複數個比較器43b~43z來進行影像資料的運算,其功能可視為一脈波寬度調變單元(pulse width modulation unit),用以調整發光二極體驅動單元630所接收到的脈波寬度調整信號。同時也具有致能發光二極體驅動單元630是否輸出驅動信號的功能。 The data operation circuit 622 includes a counter 43a and a plurality of comparators 43b to 43z (for example, digital comparators). The comparators 43b to 43z are used to compare the output of the counter 43a with the data latched in the first data storage circuit 623, and then So that the LED driving unit 630 outputs M driving signals. The data operation circuit 622 performs image data calculation by the counter 43a and the plurality of comparators 43b to 43z, and the function thereof can be regarded as a pulse width modulation unit for adjusting the LED driving unit. 630 received pulse width adjustment signal. At the same time, it also has a function of enabling the light-emitting diode driving unit 630 to output a driving signal.
驅動信號設定電路670包括數位類比轉換電路672、參考電壓產生電路674以及電壓電流轉換電路676。參考電壓產生電路674耦接於電壓電流轉換電路676,數位類比轉換電路672耦接於資料儲存電路624與電壓電流轉換電路676之間。數位類比轉換電路672將儲存在資料儲存電路624中的命令資料轉換為類比信號(例如電壓)以輸出至電壓電流轉換電路676,電壓電流轉換電路676則根據命令資料與參考電壓產生電路674的輸出調整發光二極體驅動電路632的驅動信號。 The drive signal setting circuit 670 includes a digital analog conversion circuit 672, a reference voltage generation circuit 674, and a voltage current conversion circuit 676. The reference voltage generating circuit 674 is coupled to the voltage-current converting circuit 676, and the digital analog converting circuit 672 is coupled between the data storage circuit 624 and the voltage-current converting circuit 676. The digital analog conversion circuit 672 converts the command data stored in the data storage circuit 624 into an analog signal (eg, voltage) for output to the voltage current conversion circuit 676, and the voltage current conversion circuit 676 is based on the command data and the output of the reference voltage generation circuit 674. The driving signal of the light emitting diode driving circuit 632 is adjusted.
此外,值得注意的是,上述雙緣擷取資料傳遞單元610、資料儲存電路621與資料運算電路622中的元件可依照不同的使用需求設計為不同位元的電子元件,其傳輸路徑與資料傳輸方式也依照所需的資料位元數進行調整,本發明並不受限於上述實施例所述之位元數。此外,上述資料輸入信號DIN的類型可以是一般邏輯信號或是差動信號,本實施例並不受限。 In addition, it should be noted that the components in the dual-edge data transfer unit 610, the data storage circuit 621, and the data operation circuit 622 can be designed as electronic components of different bits according to different usage requirements, and the transmission path and data transmission. The method is also adjusted according to the required number of data bits, and the present invention is not limited to the number of bits described in the above embodiments. In addition, the type of the data input signal DIN may be a general logic signal or a differential signal, and the embodiment is not limited.
電源管理系統680主要用來管理驅動電路600的電源供給,其例如為調變式電源管理系統(PWM power manager)或線性電源管理系統(Linear power manager)。控制單元660可依照所接收的資料輸入信號DIN與時序信號CKI的組合取得一工作模式資料,並據此輸出一工作模式信號MODE至偵測保護單元650以進行工作模式的切換或參數設定或電路狀態偵測。偵測保護單元650可將所偵測到的參數值回存到雙緣擷取資料傳遞單元610,然後透過資料輸出信號DO輸出。 The power management system 680 is mainly used to manage the power supply of the driving circuit 600, such as a PWM power manager or a linear power management system. Manager). The control unit 660 can obtain an operating mode data according to the combination of the received data input signal DIN and the timing signal CKI, and output an operating mode signal MODE to the detecting and protecting unit 650 to perform operation mode switching or parameter setting or circuit. Status detection. The detection protection unit 650 can restore the detected parameter values to the dual edge capture data transfer unit 610 and then output the data output signal DO.
此外,值得注意的是,時脈輸出信號CKO與資料輸出信號DO可依照參數設定為輸出同相的時序信號CKI與資料輸入信號DIN或是輸出反相的時序信號CKI與資料輸入信號DIN。此外,若資料輸入信號DIN與資料輸出信號DO需進行編解碼,控制單元660中也可加設解碼器,而驅動電路600的輸出端可以加設編碼器以進行資料的編解碼。圖6中所述的驅動電路600的其餘電路操作細節則如上述第一、二實施例所述,在此不在累述。 In addition, it is worth noting that the clock output signal CKO and the data output signal DO can be set according to the parameter to output the in-phase timing signal CKI and the data input signal DIN or the output inverted timing signal CKI and the data input signal DIN. In addition, if the data input signal DIN and the data output signal DO need to be coded and decoded, a decoder may be added to the control unit 660, and an output of the driving circuit 600 may be provided with an encoder for encoding and decoding data. The remaining circuit operation details of the driving circuit 600 described in FIG. 6 are as described in the first and second embodiments above, and are not described here.
接下來,請參照圖7、圖7為根據本發明第四實施例之資料輸出信號波形圖。以12位元的影像資料與8個驅動信號(發光二極體驅動電路630可輸出8個的驅動信號)為例,當驅動電路600依序輸出雙緣擷取移位暫存電路613中所擷取的資料時,資料輸出信號DO會比資料輸入信號DIN延遲96個位元的時間。由於雙緣擷取移位暫存電路613是以雙緣觸發的方式進行資料取樣,因此雙緣擷取移位暫存電路613僅需48個週期的時序信號CKI即可完成96個位元資料的取樣。 Next, please refer to FIG. 7 and FIG. 7 for waveform diagrams of data output signals according to a fourth embodiment of the present invention. Taking 12-bit image data and 8 driving signals (the LED driving circuit 630 can output 8 driving signals) as an example, when the driving circuit 600 sequentially outputs the double-edge capturing shift temporary storage circuit 613 When the data is retrieved, the data output signal DO is delayed by 96 bits from the data input signal DIN. Since the double-edge capture shift register circuit 613 performs data sampling in a double-edge trigger manner, the double-edge capture shift register circuit 613 can complete 96 bit data only by using the 48-cycle timing signal CKI. Sampling.
綜上所述,本發明所提出的發光二極體驅動電路由於具有雙緣觸發的擷取電路,因此可以較低頻率的時序信號來進行資料存取,藉此可降低高頻信號對驅動電路的電磁干擾以及增加驅動電路的穩定度。 In summary, the LED driving circuit of the present invention has a dual-edge triggering circuit, so that data access can be performed with a lower frequency timing signal, thereby reducing the high frequency signal to the driving circuit. Electromagnetic interference and increased stability of the drive circuit.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之 更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application.
600‧‧‧驅動電路 600‧‧‧ drive circuit
610‧‧‧雙緣擷取資料傳遞單元 610‧‧‧Double-edge data transfer unit
613、614‧‧‧雙緣觸發移位暫存器 613, 614‧‧‧ double edge trigger shift register
615‧‧‧資料輸入信號處理電路 615‧‧‧Data input signal processing circuit
617‧‧‧多工器 617‧‧‧Multiplexer
621‧‧‧資料儲存電路 621‧‧‧Data storage circuit
622‧‧‧資料運算電路 622‧‧‧Data operation circuit
623‧‧‧第一資料儲存電路 623‧‧‧First data storage circuit
624‧‧‧第二資料儲存電路 624‧‧‧Second data storage circuit
630‧‧‧發光二極體驅動單元 630‧‧‧Lighting diode drive unit
632‧‧‧發光二極體驅動電路 632‧‧‧Lighting diode drive circuit
640‧‧‧時序處理單元 640‧‧‧Time Processing Unit
650‧‧‧偵測保護單元 650‧‧‧Detection protection unit
660‧‧‧控制單元 660‧‧‧Control unit
670‧‧‧驅動信號設定電路 670‧‧‧Drive signal setting circuit
672‧‧‧數位類比轉換電路 672‧‧‧Digital analog conversion circuit
674‧‧‧參考電壓產生電路 674‧‧‧reference voltage generation circuit
676‧‧‧電壓電流轉換電路 676‧‧‧Voltage current conversion circuit
680‧‧‧電源管理系統 680‧‧‧Power Management System
CKI、CKI1、CKI2‧‧‧時序信號 CKI, CKI 1 , CKI 2 ‧‧‧ timing signals
CKO‧‧‧時序輸出信號 CKO‧‧‧ timing output signal
DIN‧‧‧資料輸入信號 DIN‧‧‧ data input signal
DO‧‧‧資料輸出信號 DO‧‧‧ data output signal
LAT1、LAT2‧‧‧栓鎖信號 LAT 1 , LAT 2 ‧‧‧ latch signal
MODE‧‧‧工作模式信號 MODE‧‧‧ working mode signal
SEL‧‧‧選擇信號 SEL‧‧‧Selection signal
43b~43z‧‧‧比較器 43b~43z‧‧‧ comparator
43a‧‧‧計數器 43a‧‧‧ counter
Claims (13)
Priority Applications (1)
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TW98115406A TWI425878B (en) | 2009-05-08 | 2009-05-08 | Driving circuit of light emitting diode |
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TW98115406A TWI425878B (en) | 2009-05-08 | 2009-05-08 | Driving circuit of light emitting diode |
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TW201041445A TW201041445A (en) | 2010-11-16 |
TWI425878B true TWI425878B (en) | 2014-02-01 |
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TWI470609B (en) * | 2012-09-14 | 2015-01-21 | My Semi Inc | Led driver circuit and driver system having the same |
TWI491304B (en) * | 2012-11-09 | 2015-07-01 | My Semi Inc | Led driver circuit and driver system |
CN110768879B (en) * | 2018-07-26 | 2021-11-19 | 深圳市爱协生科技有限公司 | Communication control link |
CN110782828B (en) * | 2018-07-26 | 2021-05-11 | 深圳市爱协生科技有限公司 | Display device |
Citations (4)
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US20030066945A1 (en) * | 2001-10-05 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Average light sensing for pwm control of rgb led based white light luminaries |
TWI227452B (en) * | 2001-08-28 | 2005-02-01 | Sharp Kk | Drive unit and display module including same |
TWI242294B (en) * | 2004-12-07 | 2005-10-21 | Silicon Touch Tech Inc | An accelerated circuit for lightening/turning off LED |
TWI259030B (en) * | 2005-07-19 | 2006-07-21 | Aimtron Technology Corp | Dimming control circuit for light-emitting diodes |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI227452B (en) * | 2001-08-28 | 2005-02-01 | Sharp Kk | Drive unit and display module including same |
US20030066945A1 (en) * | 2001-10-05 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Average light sensing for pwm control of rgb led based white light luminaries |
TWI242294B (en) * | 2004-12-07 | 2005-10-21 | Silicon Touch Tech Inc | An accelerated circuit for lightening/turning off LED |
TWI259030B (en) * | 2005-07-19 | 2006-07-21 | Aimtron Technology Corp | Dimming control circuit for light-emitting diodes |
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