TWI425751B

TWI425751B - Power supply with open-loop protection

Info

Publication number: TWI425751B
Application number: TW99106127A
Authority: TW
Inventors: Wei Hsuan Huang; Meng Jen Tsai; Chien Yuan Lin; Chuan Chang Li
Original assignee: System General Corp
Priority date: 2010-03-03
Filing date: 2010-03-03
Publication date: 2014-02-01
Also published as: TW201131950A

Description

具有開迴路保護的電源供應器Power supply with open circuit protection

本發明係關於一種電源供應器，其係尤指一種具有開迴路保護的電源供應器。The present invention relates to a power supply, and more particularly to a power supply with open circuit protection.

一般電源供應器能夠提供穩定的電壓與電流。為了符合安全規範(safety)，電源供應器必須提供開迴路保護(open-loop protection)與輸入電壓過低保護(Brown out protection)，以確保電源供應器本身與負載端的應用電路不受影響。參考第1圖，其為習知具有開迴路保護的電源供應器的電路圖。習知的電源供應器包含變壓器T₁ 、驅動電路14、訊號產生電路10、振盪器12、功率開關Q₁ 、回授偵測電路16及延遲電路18。A typical power supply provides stable voltage and current. In order to comply with safety regulations, the power supply must provide open-loop protection and brown out protection to ensure that the power supply itself and the application circuitry at the load are unaffected. Referring to Figure 1, it is a circuit diagram of a conventional power supply with open loop protection. The conventional power supply includes a transformer T ₁ , a drive circuit 14 , a signal generating circuit 10 , an oscillator 12 , a power switch Q ₁ , a feedback detection circuit 16 , and a delay circuit 18 .

如第1圖所示，變壓器T₁ 具有一次側繞組N_P 與二次側繞組N_S ，用以儲存能量與功率轉換。變壓器T₁ 耦接至電源供應器的輸入電壓V_IN 。功率開關Q₁ 對變壓器T₁ 進行切換動作，將變壓器T₁ 一次側繞組N_P 儲存的能量轉換至二次側繞組N_S 。轉換至二次側繞組N_S 的能量透過輸出整流器D_O 與輸出電容C_O 整流並產生輸出電壓V_O 。電流感測裝置R_S 與功率開關Q₁ 串聯連接。電流感測裝置R_S 根據變壓器T₁ 的一次側切換電流I_P 產生電流訊號V_CS 。另外，電源供應器之輸出電壓V_O 透過回授方式提供回授訊號V_FB 至驅動電路14與回授偵測電路16。As shown in Fig. 1, the transformer T ₁ has a primary side winding N _P and a secondary side winding N _S for storing energy and power conversion. The transformer T _{1 is} coupled to the input voltage V _{IN of the} power supply. The power switch Q ₁ switches the transformer T ₁ to convert the energy stored in the primary winding N _{P of the} transformer T ₁ to the secondary winding N _S . The energy converted to the secondary winding N _S is rectified by the output rectifier D _O and the output capacitor C _{O to} generate an output voltage V _O . The current sensing device R _{S is} connected in series with the power switch Q ₁ . The current sensing device R _S generates a current signal V _CS according to the primary side switching current I _{P of the} transformer T ₁ . In addition, the output voltage V _{O of the} power supply provides the feedback signal V _FB to the driving circuit 14 and the feedback detecting circuit 16 through a feedback manner.

驅動電路14由邏輯電路144、功率限制比較器146及PWM(Pulse Width Modulation)比較器148組成。驅動電路14依據電流訊號V_CS 、功率限制訊號V_LMT 與回授訊號V_FB 產生清除訊號CLR，以截止切換訊號V_PWM 。功率限制比較器146與PWM比較器148的一輸入端耦接到電流感測裝置R_S ，以接收電流訊號V_CS 。功率限制比較器146的另一輸入端接收功率限制訊號V_LMT 。PWM比較器148的另一輸入端接收回授訊號V_FB 。The drive circuit 14 is composed of a logic circuit 144, a power limit comparator 146, and a PWM (Pulse Width Modulation) comparator 148. The driving circuit 14 generates a clear signal CLR according to the current signal V _CS , the power limiting signal V _LMT and the feedback signal V _FB to turn off the switching signal V _PWM . The power limit comparator 146 and an input of the PWM comparator 148 are coupled to the current sensing device R _S to receive the current signal V _CS . The other input of the power limit comparator 146 receives the power limit signal _VLMT . The other input of the PWM comparator 148 receives the feedback signal V _FB .

當電流訊號V_CS 大於功率限制訊號V_LMT 時，功率限制比較器146的輸出端將輸出低準位的過電流訊號OC。另外，當電流訊號V_CS 大於回授訊號V_FB 時，PWM比較器148的輸出端將產生低準位的回授控制訊號CNTR。邏輯電路144的兩輸入端分別耦接功率限制比較器146及PWM比較器148的輸出端。因此邏輯電路144的輸出端將依據過電流訊號OC與/或回授控制訊號CNTR產生低準位的清除訊號CLR，以截止切換訊號V_PWM 。換句話說，驅動電路14根據回授控制訊號CNTR之邏輯準位或過電流訊號OC之邏輯準位決定清除訊號CLR之邏輯準位。When the current signal V _{CS is} greater than the power limit signal V _LMT , the output of the power limit comparator 146 will output a low level over current signal OC. In addition, when the current signal V _{CS is} greater than the feedback signal V _FB , the output of the PWM comparator 148 will generate a low level feedback control signal CNTR. The two input ends of the logic circuit 144 are respectively coupled to the outputs of the power limit comparator 146 and the PWM comparator 148. Therefore, the output of the logic circuit 144 will generate a low-level clear signal CLR according to the over-current signal OC and/or the feedback control signal CNTR to turn off the switching signal V _PWM . In other words, the driving circuit 14 determines the logic level of the clear signal CLR according to the logic level of the feedback control signal CNTR or the logic level of the overcurrent signal OC.

訊號產生電路10包含邏輯電路101、正反器103與邏輯電路105。邏輯電路101為反相器，其輸入端耦接振盪器12以接收振盪器12輸出的時脈訊號PLS。邏輯電路101之輸出端耦接正反器103之時脈輸入端CK，以驅動正反器103。正反器103之輸入端D耦接延遲電路18之輸出端。正反器103之輸出端Q耦接邏輯電路105之一輸入端，邏輯電路105之另一輸入端經由邏輯電路101接收時脈訊號PLS。邏輯電路105之輸出端產生切換訊號V_PWM 。邏輯電路105為及閘(AND gate)。正反器103之重置輸入端R耦接驅動電路14的輸出端，以接收清除訊號CLR。訊號產生電路10耦接振盪器12與驅動電路14的輸出端。訊號產生電路10根據振盪器12輸出的時脈訊號PLS產生切換訊號V_PWM 。切換訊號V_PWM 控制功率開關Q₁ 的切換。訊號產生電路10根據驅動電路14輸出的清除訊號CLR週期性地調整切換訊號V_PWM 之脈波寬度，使電源供應器的輸出電壓V_O 得到穩定調整，並且限制輸出功率。The signal generating circuit 10 includes a logic circuit 101, a flip-flop 103, and a logic circuit 105. The logic circuit 101 is an inverter, and its input terminal is coupled to the oscillator 12 to receive the clock signal PLS output by the oscillator 12. The output end of the logic circuit 101 is coupled to the clock input terminal CK of the flip-flop 103 to drive the flip-flop 103. The input terminal D of the flip-flop 103 is coupled to the output of the delay circuit 18. The output terminal Q of the flip-flop 103 is coupled to one input of the logic circuit 105, and the other input of the logic circuit 105 receives the clock signal PLS via the logic circuit 101. The output of the logic circuit 105 produces a switching signal _VPWM . The logic circuit 105 is an AND gate. The reset input terminal R of the flip-flop 103 is coupled to the output of the drive circuit 14 to receive the clear signal CLR. The signal generating circuit 10 is coupled to the output of the oscillator 12 and the driving circuit 14. The signal generating circuit 10 generates the switching signal V _PWM according to the clock signal PLS output from the oscillator 12. Switching signal V _PWM control of the power switch Q ₁ '. The signal generating circuit 10 periodically adjusts the pulse width of the switching signal V _PWM according to the clear signal CLR outputted by the driving circuit 14, so that the output voltage V _{O of} the power supply is stably adjusted, and the output power is limited.

請參考第1圖，回授偵測電路16之兩輸入端分別接收回授訊號V_FB 與臨界訊號V_TH 以產生拉高(pull-high)訊號S_PH 。當電源供應器為正常操作時，回授訊號V_FB 低於臨界訊號V_TH 。此時，回授偵測電路16之輸出端產生低準位的拉高訊號S_PH 。延遲電路18接收低準位的拉高訊號S_PH 後不會進行計數，並直接輸出高準位的截止訊號S_OFF 到訊號產生電路10。訊號產生電路10接收高準位的截止訊號S_OFF 並不會栓鎖切換訊號V_PWM 。但當電源供應器的輸出端發生開迴路(Open Loop)狀態時，回授訊號V_FB 之準位會透過拉高電阻R_PH 而被拉高到供應電壓V_CC 。當回授訊號V_FB 之準位被拉高而大於臨界訊號V_TH 時，回授偵測電路16的輸出端產生高準位的拉高訊號S_PH 。延遲電路18將根據高準位的拉高訊號S_PH 進行計數，並在一延遲時間之後產生低準位的截止訊號S_OFF 。訊號產生電路10將依據低準位的截止訊號S_OFF 栓鎖切換訊號V_PWM 。因此，回授偵測電路16與延遲電路18在回授訊號V_FB 之準位被拉高時，將驅使訊號產生電路10栓鎖切換訊號V_PWM 進行開迴路保護。Referring to FIG. 1 , the two input terminals of the feedback detection circuit 16 respectively receive the feedback signal V _FB and the threshold signal V _TH to generate a pull-high signal S _PH . When the power supply is in normal operation, the feedback signal V _{FB is} lower than the critical signal V _TH . At this time, the output of the feedback detection circuit 16 generates a low-level pull-up signal S _PH . The delay circuit 18 does not count after receiving the low-level pull-up signal S _PH , and directly outputs the high-level cutoff signal S _OFF to the signal generating circuit 10. The signal generating circuit 10 receives the high-level cutoff signal S _OFF and does not latch the switching signal V _PWM . However, when the output of the power supply has an Open Loop state, the level of the feedback signal V _FB is pulled up to the supply voltage V _CC by pulling the high resistance R _PH . When the level of the feedback signal V _FB is pulled higher than the threshold signal V _TH , the output of the feedback detection circuit 16 generates a high-level pull-up signal S _PH . The delay circuit 18 counts the pull-up signal S _PH according to the high level and generates a low-level cutoff signal S _OFF after a delay time. The signal generating circuit 10 latches the switching signal V _PWM according to the low-level cutoff signal S _OFF . Therefore, when the feedback detection circuit 16 and the delay circuit 18 are pulled high when the level of the feedback signal V _FB is pulled high, the signal generation circuit 10 is driven to latch the switching signal V _PWM for open loop protection.

此外，電源供應器具有輸入電壓過低保護電路(圖未示)，其在電源供應器的輸入電壓V_IN 過低，且計數到延遲時間後會進行輸入電壓過低保護，而栓鎖切換訊號V_PWM ，輸入電壓過低保護所須的延遲時間較長於開迴路保護所須的延遲時間。實際的應用上，若輸入電壓過低發生的時間低於輸入電壓過低保護之延遲時間時，並不需要進行輸入電壓過低保護，即不需要栓鎖切換訊號V_PWM 。但由於輸入電壓過低時，回授訊號V_FB 之準位也會透過拉高電阻R_PH 被拉高到供應電壓V_CC ，且開迴路保護所須延遲時間較短於輸入電壓過低保護所需的延遲時間，因此會造成開迴路保護會搶先在輸入電壓過低保護之前進行栓鎖切換訊號V_PWM 的動作，而誤栓鎖切換訊號V_PWM 。在輸入電壓過低保護的延遲時間無法縮短的情況下，如何使電源供應器正確的區分開迴路保護與輸入電壓過低保護，實為當今電源供應器設計時重要的課題。In addition, the power supply has an input voltage under-voltage protection circuit (not shown), and the input voltage V _{IN of the} power supply is too low, and after the delay time is counted, the input voltage is too low, and the latching switching signal is V _PWM , the input voltage under-protection requires a longer delay than the open-loop protection. In practical applications, if the input voltage is too low for a period of time lower than the delay time of the input voltage too low protection, the input voltage is not required to be protected too low, that is, the latching switching signal V _PWM is not required. However, since the input voltage is too low, the level of the feedback signal V _FB is also pulled up to the supply voltage V _CC through the pull-up resistor R _PH , and the delay time required for the open circuit protection is shorter than the input voltage is too low. The required delay time will cause the open loop protection to preempt the latching switching signal V _PWM before the input voltage is too low, and the mis-locking switching signal V _PWM . In the case that the delay time of the input voltage under-protection cannot be shortened, how to make the power supply correctly distinguish between the loop protection and the input voltage under-protection is an important issue in the design of the current power supply.

本發明之一目的，在於提供具有開迴路保護的電源供應器，本發明的具有開迴路保護的電源供應器在回授訊號V_FB 被拉高時，利用一低壓偵測電路偵測電源供應器之輸入電壓是否過低，以決定是否進行開迴路保護。An object of the present invention is to provide a power supply with open circuit protection. The power supply with open circuit protection of the present invention uses a low voltage detection circuit to detect a power supply when the feedback signal V _FB is pulled high. Whether the input voltage is too low to determine whether to open circuit protection.

本發明具有開迴路保護的電源供應器包含一變壓器、一開關、一訊號產生電路、一回授偵測電路、一低壓偵測電路與一延遲電路。變壓器接收一輸入電壓。開關耦接變壓器並切換變壓器。訊號產生電路產生一切換訊號控制開關切換。回授偵測電路依據電源供應器之一回授訊號產生一拉高訊號。低壓偵測電路依據拉高訊號與輸入電壓產生一延遲訊號。延遲電路依據延遲訊號計數一延遲時間之後，產生一截止訊號至訊號產生電路，以拴鎖切換訊號。本發明利用低壓偵測電路偵測輸入電壓是否過低，以在回授訊號被拉高為高準位時，作為決定是否進行開迴路保護的參考。The power supply device with circuit protection of the invention comprises a transformer, a switch, a signal generating circuit, a feedback detecting circuit, a low voltage detecting circuit and a delay circuit. The transformer receives an input voltage. The switch is coupled to the transformer and switches the transformer. The signal generating circuit generates a switching signal to control the switching of the switch. The feedback detection circuit generates a pull-up signal according to one of the power supply feedback signals. The low voltage detection circuit generates a delay signal according to the pull-up signal and the input voltage. After the delay circuit counts a delay time according to the delay signal, a cutoff signal is generated to the signal generating circuit to lock the switching signal. The invention utilizes a low voltage detection circuit to detect whether the input voltage is too low, as a reference for deciding whether to perform open loop protection when the feedback signal is pulled high to a high level.

茲為使　貴審查委員對本發明之技術特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：In order to give the reviewer a better understanding and understanding of the technical features of the present invention and the efficacies achieved, the following is a description of the preferred embodiment and a detailed description.

請參閱第2圖，係本發明具有開迴路保護的電源供應器的電路圖。本發明除了第1圖所示之習知技術之外，增加了低壓偵測(Brown out detection)電路20。低壓偵測電路20包括週期比較器210、輸入比較器220、第一邏輯電路230與第二邏輯電路240。低壓偵測電路20用於偵側輸入電壓V_IN 並產生過低訊號S_OL 。第一邏輯電路230之較佳實施例為一反及閘(NAND gate)，第二邏輯電路240之較佳實施例為一及閘(AND gate)。週期比較器210的正端耦接振盪器12，用以接收鋸齒訊號V_OSC 。週期比較器210的負端接收第一訊號V_T1 。當鋸齒訊號V_OSC 小於第一訊號V_T1 時，週期比較器210的輸出端所產生的週期訊號S_DUTY 為低準位。其中，週期訊號S_DUTY 為低準位所維持的一段時間稱為截止週期(off-time period)。當鋸齒訊號V_OSC 大於第一訊號V_T1 時，週期比較器210的輸出端產生高準位的週期訊號S_DUTY 。其中，週期訊號S_DUTY 為高準位所維持的一段時間稱為導通週期(on-time period)。更重要的是，鋸齒訊號V_OSC 之切換週期為固定切換週期，第一訊號V_T1 為預設的一固定值。因此，週期訊號S_DUTY 之脈波寬度為一固定的脈波寬度。Please refer to FIG. 2, which is a circuit diagram of a power supply with open circuit protection according to the present invention. In addition to the prior art shown in FIG. 1, the present invention adds a Brown Out detection circuit 20. The low voltage detection circuit 20 includes a period comparator 210, an input comparator 220, a first logic circuit 230, and a second logic circuit 240. The low voltage detection circuit 20 is configured to detect the input voltage V _IN and generate a low signal S _OL . The preferred embodiment of the first logic circuit 230 is a NAND gate, and the preferred embodiment of the second logic circuit 240 is an AND gate. The positive terminal of the period comparator 210 is coupled to the oscillator 12 for receiving the sawtooth signal V _OSC . The negative terminal of the period comparator 210 receives the first signal V _T1 . When the sawtooth signal V _{OSC is} smaller than the first signal V _T1 , the periodic signal S _DUTY generated at the output of the period comparator 210 is at a low level. The period in which the periodic signal S _DUTY is maintained at the low level is called an off-time period. When the sawtooth signal V _{OSC is} greater than the first signal V _T1 , the output of the period comparator 210 generates a high level periodic signal S _DUTY . The period during which the periodic signal S _DUTY is maintained at a high level is called an on-time period. More importantly, the switching period of the sawtooth signal V _OSC is a fixed switching period, and the first signal V _T1 is a preset fixed value. Therefore, the pulse width of the periodic signal S _DUTY is a fixed pulse width.

輸入比較器220的正端接收第二訊號V_T2 。輸入比較器220的負端耦接於電流感測裝置R_S ，用以接收電流訊號V_CS 。當電流訊號V_CS 小於第二訊號V_T2 時，輸入比較器220的輸出端產生高準位的輸入訊號S_BO 。其中，第二訊號V_T2 為預設的一固定值，而電流訊號V_CS 係相關於變壓器T₁ 的一次側切換電流I_P ，因此電流訊號V_CS 的峰值大小係相關於電源供應器的輸入電壓V_IN 的高低。也就是說，輸入電壓V_IN 愈高，電流訊號V_CS 的峰值愈大；輸入電壓V_IN 愈低，電流訊號V_CS 的峰值愈小。因此，當電流訊號V_CS 小於第二訊號V_T2 ，輸入比較器220的輸出端產生高準位的輸入訊號S_BO 時，表示電源供應器的輸入電壓V_IN 小於第二訊號V_T2 而過低。所以，低壓偵測電路20可用於偵測輸入電壓V_IN 。The positive terminal of the input comparator 220 receives the second signal V _T2 . The negative terminal of the input comparator 220 is coupled to the current sensing device R _S for receiving the current signal V _CS . When the current signal V _{CS is} smaller than the second signal V _T2 , the output of the input comparator 220 generates a high level input signal S _BO . The second signal V _T2 is a preset fixed value, and the current signal V _CS is related to the primary side switching current I _{P of the} transformer T ₁ , so the peak value of the current signal V _CS is related to the input of the power supply. The voltage V _IN is high or low. That is to say, the higher the input voltage V _IN , the larger the peak value of the current signal V _CS ; the lower the input voltage V _IN , the smaller the peak value of the current signal V _CS . Therefore, when the current signal V _{CS is} smaller than the second signal V _T2 , the input terminal of the input comparator 220 generates the high-level input signal S _BO , indicating that the input voltage V _{IN of the} power supply is lower than the second signal V _T2 and is too low. . Therefore, the low voltage detection circuit 20 can be used to detect the input voltage V _IN .

第一邏輯電路230的輸入端耦接到週期比較器210、輸入比較器220與訊號產生電路10的輸出端。第一邏輯電路230依據週期訊號S_DUTY 、輸入訊號S_BO 與切換訊號V_PWM 來產生過低訊號S_OL 。第二邏輯電路240的輸入端耦接到回授偵測電路16之輸出端與第一邏輯電路230之輸出端。第二邏輯電路240依據拉高訊號S_PH 與過低訊號S_OL 來產生延遲訊號S_DELAY 。延遲電路18依據延遲訊號S_DELAY 的準位高低來決定是否進行計數並產生截止訊號S_OFF 。換言之，延遲電路18即依據拉高訊號S_PH 與過低訊號S_OL 之準位而計數延遲時間，並在計數延遲時間之後產生截止訊號S_OFF 。截止訊號S_OFF 的準位高低用來決定訊號產生電路10是否對切換訊號V_PWM 進行栓鎖。當低準位的截止訊號S_OFF 被產生時，訊號產生電路10將依據低準位的截止訊號S_OFF 栓鎖切換訊號V_PWM 。The input of the first logic circuit 230 is coupled to the output of the period comparator 210, the input comparator 220, and the signal generating circuit 10. The first logic circuit 230 generates the low signal S _OL according to the periodic signal S _DUTY , the input signal S _BO and the switching signal V _PWM . The input of the second logic circuit 240 is coupled to the output of the feedback detection circuit 16 and the output of the first logic circuit 230. The second logic circuit 240 generates the delay signal S _DELAY according to the pull-up signal S _PH and the low-low signal S _OL . The delay circuit 18 determines whether to count and generate the cutoff signal S _OFF according to the level of the delay signal S _DELAY . In other words, the delay circuit 18 counts the delay time according to the level of the pull-up signal S _PH and the low-low signal S _OL , and generates the cut-off signal S _OFF after the count delay time. The level of the cutoff signal S _OFF is used to determine whether the signal generating circuit 10 latches the switching signal V _PWM . When the low level OFF signal S _OFF is generated, the signal generation circuit 10 based on the low level OFF signal S _OFF switch latch signal V _PWM.

第3圖係本發明之一實施例之延遲電路18的電路圖。延遲電路18包含正反器182、184、…186。其中正反器182、184、…186的時脈端CK連接到振盪器12(參閱第2圖)，以接收時脈訊號PLS的時間基準(time base)進行計數。正反器182的輸入端D接收供應電壓V_CC 。正反器184與186的輸入端D耦接至上一級正反器的輸出端Q。舉例來說，正反器184之輸入端D耦接至正反器182的輸出端Q。正反器186的反相輸出端/Q產生截止訊號S_OFF 。另外，正反器182、184、…186的重置端R共同耦接至第二邏輯電路240的輸出端(參閱第2圖)，用以接收延遲訊號S_DELAY 。Figure 3 is a circuit diagram of a delay circuit 18 in accordance with one embodiment of the present invention. The delay circuit 18 includes flip-flops 182, 184, ... 186. The clock terminal CK of the flip-flops 182, 184, ... 186 is connected to the oscillator 12 (see FIG. 2), and is counted by receiving the time base of the clock signal PLS. The input terminal D of the flip flop 182 receives the supply voltage V _CC . The input terminals D of the flip-flops 184 and 186 are coupled to the output terminal Q of the upper-stage flip-flop. For example, the input terminal D of the flip flop 184 is coupled to the output terminal Q of the flip flop 182. The inverting output /Q of the flip flop 186 generates a cutoff signal _SOFF . In addition, the reset terminals R of the flip-flops 182, 184, . . . 186 are coupled to the output of the second logic circuit 240 (see FIG. 2) for receiving the delay signal S _DELAY .

請參考第2圖，當延遲電路18接收到低準位的延遲訊號S_DELAY 後，造成正反器182、184、…186被重置而禁能延遲電路18。因此延遲電路18並不會作計數動作。最後一級的正反器186的反相輸出端/Q直接輸出高準位的截止訊號S_OFF 到訊號產生電路10。相反地，當延遲電路18接收到高準位的延遲訊號S_DELAY 後，並不會重置正反器182、184、…186。此時延遲電路18開始進行計數動作。延遲電路18計數到一段延遲時間T_D 之後，最後一級的正反器186的反相輸出端/Q直接輸出低準位的截止訊號S_OFF 到訊號產生電路10。訊號產生電路10將依據低準位的截止訊號S_OFF 栓鎖切換訊號V_PWM 。Referring to FIG. 2, when the delay circuit 18 receives the low level delay signal S _DELAY , the flip-flops 182, 184, ... 186 are reset and the delay circuit 18 is disabled. Therefore, the delay circuit 18 does not perform a counting operation. The inverted output terminal /Q of the flip-flop 186 of the last stage directly outputs the high-level cutoff signal S _OFF to the signal generating circuit 10. Conversely, when the delay circuit 18 receives the high level delay signal S _DELAY , the flip flops 182, 184, ... 186 are not reset. At this time, the delay circuit 18 starts the counting operation. After the delay circuit 18 counts for a delay time T _D , the inverted output terminal /Q of the flip-flop 186 of the last stage directly outputs the low-level cutoff signal S _OFF to the signal generating circuit 10. The signal generating circuit 10 latches the switching signal V _PWM according to the low-level cutoff signal S _OFF .

當電源供應器正常操作時，回授信號V_FB 會低於臨界訊號V_TH (參閱第2圖)。此時，回授偵測電路16的輸出端產生低準位的拉高訊號S_PH 。第二邏輯電路240接收低準位的拉高訊號S_PH 後，不論過低訊號S_OL 的準位高或低，第二邏輯電路240會直接產生低準位的延遲訊號S_DELAY 。延遲電路18接收到低準位的延遲訊號S_DELAY 後，正反器182、184、…186(參閱第3圖)將被重置。因此延遲電路18並不會進行計數，並直接輸出高準位的截止訊號S_OFF 到訊號產生電路10。所以，在電源供應器操作正常時，訊號產生電路10並不會對切換訊號V_PWM 與電源供應器進行拴鎖。另外，在開迴路狀態或是輸入電壓過低，回授信號V_FB 之準位都會被拉高到供應電壓V_CC ，且回授偵測電路16產生高準位的拉高訊號S_PH 。當電源供應器的輸出端發生開迴路狀態，回授偵測電路16會產生高準位的拉高訊號S_PH 。低壓偵測電路20根據切換訊號V_PWM 、鋸齒訊號V_OSC 以及電流訊號V_CS 進行判斷輸入電壓V_IN 是否過低。當電流訊號V_CS 大於第二訊號V_T2 時，表示電源供應器的輸入電壓V_IN 供電正常。When the power supply is operating normally, the feedback signal V _FB will be lower than the critical signal V _TH (see Figure 2). At this time, the output of the feedback detection circuit 16 generates a low-level pull-up signal S _PH . After the second logic circuit 240 receives the low-level pull-up signal S _PH , the second logic circuit 240 directly generates the low-level delay signal S _DELAY regardless of whether the level of the low-level signal S _OL is high or low. After the delay circuit 18 receives the low level delay signal S _DELAY , the flip-flops 182, 184, ... 186 (see Figure 3) will be reset. Therefore, the delay circuit 18 does not count and directly outputs the high-level cutoff signal S _OFF to the signal generating circuit 10. Therefore, when the power supply is operating normally, the signal generating circuit 10 does not lock the switching signal V _PWM and the power supply. In addition, in the open circuit state or the input voltage is too low, the level of the feedback signal V _FB is pulled up to the supply voltage V _CC , and the feedback detection circuit 16 generates the high level pull signal S _PH . When the output of the power supply has an open circuit state, the feedback detection circuit 16 generates a high-level pull-up signal S _PH . The low voltage detecting circuit 20 determines whether the input voltage V _IN is too low according to the switching signal V _PWM , the sawtooth signal V _{OSC ,} and the current signal V _CS . When the current signal V _{CS is} greater than the second signal V _T2 , it indicates that the input voltage V _{IN of the} power supply is normally supplied.

請參考第4A圖與第4B圖，其為本發明之電源供應器的波形圖。請一併參閱第2圖，如第4A圖所示，只要週期訊號S_DUTY 、輸入訊號S_BO 或切換訊號V_PWM 其中一個為低準位時，第一邏輯電路230的輸出端就會產生高準位的過低訊號S_OL 。換言之，只要鋸齒訊號V_OSC 低於第一訊號V_T1 、電流訊號V_CS 高於第二訊號V_T2 或切換訊號V_PWM 為低準位時，低壓偵測電路20會致能過低訊號S_OL 。經過適當的設計第一訊號V_T1 與第二訊號V_T2 ，在一個切換週期內，可以達成持續高準位的過低訊號S_OL 。也就是說，當輸入電壓V_IN 供電正常時過低訊號S_OL 會維持高準位，再配合高準位的拉高訊號S_PH ，低壓偵測電路20會產生持續高準位的延遲訊號S_DELAY ，本發明即判斷電源供應器發生開迴路狀態。而延遲電路18接收到高準位的延遲訊號S_DELAY 後開始進行計數，延遲電路18計數一段延遲時間T_D 之後，延遲電路18產生低準位的截止訊號S_OFF 到訊號產生電路10，以對切換訊號V_PWM 進行拴鎖。Please refer to FIG. 4A and FIG. 4B, which are waveform diagrams of the power supply of the present invention. Please refer to FIG. 2 together. As shown in FIG. 4A, the output of the first logic circuit 230 is generated as long as one of the periodic signal S _DUTY , the input signal S _BO or the switching signal V _{PWM is at} a low level. The position is too low signal S _OL . In other words, as long as the sawtooth signal V _{OSC is} lower than the first signal V _T1 , the current signal V _{CS is} higher than the second signal V _T2 or the switching signal V _PWM is at a low level, the low voltage detecting circuit 20 enables the low signal S _OL . After properly designing the first signal V _T1 and the second signal V _T2 , a low-level signal S _{OL of} a continuous high level can be achieved in one switching cycle. That is to say, when the input voltage V _{IN is} normally supplied, the low signal S _OL will maintain a high level, and in conjunction with the high level pull signal S _PH , the low voltage detecting circuit 20 will generate a continuous high level delay signal S. _DELAY , the invention determines the open circuit state of the power supply. The delay circuit 18 starts counting after receiving the high level delay signal S _DELAY. After the delay circuit 18 counts a delay time T _D , the delay circuit 18 generates a low level cutoff signal S _OFF to the signal generating circuit 10 to The switching signal V _PWM is shackled.

另外，如第4B圖所示，當開迴路狀態未發生，而輸入電壓V_IN 過低時，低壓偵測電路20根據切換訊號V_PWM 、鋸齒訊號V_OSC 以及電流訊號V_CS 進行判斷輸入電壓V_IN 是否過低。當電流訊號V_CS 小於第二訊號V_T2 時，表示電源供應器的輸入電壓V_IN 過低，輸入訊號S_BO 一直維持高準位。只要週期訊號S_DUTY 、輸入訊號S_BO 或切換訊號V_PWM 其中一個為低準位時，第一邏輯電路230的輸出端就會產生高準位的過低訊號S_OL 。當週期訊號S_DUTY 、輸入訊號S_BO 與切換訊號V_PWM 同時皆為高準位時，第一邏輯電路230的輸出端就會產生低準位的過低訊號S_OL 。換言之，鋸齒訊號V_OSC 高於第一訊號V_T1 、電流訊號V_CS 小於第二訊號V_T2 以及切換訊號V_PWM 為高準位時，低壓偵測電路20會禁能過低訊號S_OL 。當過低訊號S_OL 禁能後，延遲訊號S_DELAY 將被禁能。In addition, as shown in FIG. 4B, when the open loop state does not occur and the input voltage V _{IN is} too low, the low voltage detecting circuit 20 determines the input voltage V according to the switching signal V _PWM , the sawtooth signal V _{OSC ,} and the current signal V _CS . _{Is IN} too low? When the current signal V _{CS is} smaller than the second signal V _T2 , it indicates that the input voltage V _{IN of the} power supply is too low, and the input signal S _{BO is} always maintained at a high level. As long as one of the periodic signal S _DUTY , the input signal S _BO or the switching signal V _{PWM is at} a low level, the output of the first logic circuit 230 generates a low-level signal S _{OL of} a high level. When the periodic signal S _DUTY , the input signal S _BO and the switching signal V _{PWM are} both at a high level, the output of the first logic circuit 230 generates a low level signal S _OL of low level. In other words, when the sawtooth signal V _{OSC is} higher than the first signal V _T1 , the current signal V _{CS is lower} than the second signal V _{T2 ,} and the switching signal V _PWM is at a high level, the low voltage detecting circuit 20 disables the low signal S _OL . When the low signal S _{OL is} disabled, the delay signal S _DELAY will be disabled.

因此，在一個切換週期內，第一邏輯電路230的輸出端會產生高準位與低準位交替的過低訊號S_OL 。由於第二邏輯電路240的較佳實施例為及閘，因此第二邏輯電路240的輸出端也會產生高準位與低準位交替的延遲訊號S_DELAY 。延遲電路18接收到高準位與低準位交替的延遲訊號S_DELAY 後並不會輸出低準位的截止訊號S_OFF 。也就是說，高準位的延遲訊號S_DELAY 驅使延遲電路18進行計數但還未計數到延遲時間T_D ，低準位的延遲訊號S_DELAY 就會禁能延遲電路18，而驅使延遲電路18停止計數。因此，延遲電路18沒有機會輸出低準位的截止訊號S_OFF ，而一直維持輸出高準位的截止訊號S_OFF 到訊號產生電路10。也就是說，在某些造成輸入電壓過低的狀態使拉高訊號S_PH 為高準位時，訊號產生電路10並不會對切換訊號V_PWM 進行拴鎖。Therefore, during one switching cycle, the output of the first logic circuit 230 generates a low-level signal S _{OL that} alternates between a high level and a low level. Since the preferred embodiment of the second logic circuit 240 is a NAND gate, the output of the second logic circuit 240 also generates a delay signal S _DELAY alternating between a high level and a low level. The delay circuit 18 does not output the low-level cutoff signal S _OFF after receiving the delay signal S _DELAY alternating between the high level and the low level. That is to say, the high-level delay signal S _DELAY drives the delay circuit 18 to count but has not counted the delay time T _D , and the low-level delay signal S _DELAY disables the delay circuit 18 and drives the delay circuit 18 to stop. count. Therefore, the delay circuit 18 does not have the opportunity to output the low level cutoff signal _SOFF while maintaining the output high level cutoff signal _SOFF to the signal generating circuit 10. That is to say, the signal generating circuit 10 does not lock the switching signal V _PWM when the pull-up signal S _PH is at a high level in a state in which the input voltage is too low.

故本發明實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出發明專利申請，祈　鈞局早日賜准專利，至感為禱。Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the requirements of patent applications for patent law in China. It is undoubtedly to file an invention patent application according to law, and the Prayer Council will grant patents as soon as possible.

惟以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10．．．訊號產生電路10. . . Signal generation circuit

101．．．邏輯電路101. . . Logic circuit

103．．．正反器103. . . Positive and negative

105．．．邏輯電路105. . . Logic circuit

12．．．振盪器12. . . Oscillator

14．．．驅動電路14. . . Drive circuit

144．．．邏輯電路144. . . Logic circuit

146．．．功率限制比較器146. . . Power limit comparator

148．．．PWM比較器148. . . PWM comparator

16．．．回授偵測電路16. . . Feedback detection circuit

18．．．延遲電路18. . . Delay circuit

182．．．正反器182. . . Positive and negative

184．．．正反器184. . . Positive and negative

186．．．正反器186. . . Positive and negative

Q₁ ．．．功率開關Q ₁ . . . Power switch

R_PH ．．．拉高電阻R _PH . . . Pull high resistance

R_S ．．．電流感測裝置R _S . . . Current sensing device

S_BO ．．．輸入訊號S _BO . . . Input signal

S_DELAY ．．．延遲訊號S _DELAY . . . Delay signal

S_DUTY ．．．週期訊號S _DUTY . . . Periodic signal

S_OFF ．．．截止訊號S _OFF . . . Cutoff signal

S_PH ．．．拉高訊號S _PH . . . Pull high signal

T₁ ．．．變壓器T ₁ . . . transformer

T_D ．．．延遲時間T _D . . . delay

S_OL ．．．過低訊號S _OL . . . Too low signal

20．．．低壓偵測電路20. . . Low voltage detection circuit

210．．．週期比較器210. . . Period comparator

220．．．輸入比較器220. . . Input comparator

230．．．第一邏輯電路230. . . First logic circuit

240．．．第二邏輯電路240. . . Second logic circuit

C_O ．．．輸出電容C _O . . . Output capacitor

CLR．．．清除訊號CLR. . . Clear signal

CNTR．．．回授控制訊號CNTR. . . Feedback control signal

D_O ．．．輸出整流器D _O . . . Output rectifier

I_P ．．．一次側切換電流I _P . . . Primary side switching current

N_P ．．．一次側繞組N _P . . . Primary winding

N_S ．．．二次側繞組N _S . . . Secondary winding

OC．．．過電流訊號OC. . . Over current signal

PLS．．．時脈訊號PLS. . . Clock signal

V_CC ．．．供應電壓V _CC . . . Supply voltage

V_CS ．．．電流訊號V _CS . . . Current signal

V_FB ．．．回授訊號V _FB . . . Feedback signal

V_IN ．．．輸入電壓V _IN . . . Input voltage

V_LMT ．．．功率限制訊號V _LMT . . . Power limit signal

V_O ．．．輸出電壓V _O . . . The output voltage

V_OSC ．．．鋸齒訊號V _OSC . . . Sawtooth signal

V_PWM ．．．切換訊號V _PWM . . . Switching signal

V_T1 ．．．第一訊號V _T1 . . . First signal

V_T2 ．．．第二訊號V _T2 . . . Second signal

第1圖係習知具有開迴路保護的電源供應器的電路圖；Figure 1 is a circuit diagram of a conventional power supply with open circuit protection;

第2圖係本發明之一實施例具有開迴路保護的電源供應器的電路圖；2 is a circuit diagram of a power supply with open circuit protection according to an embodiment of the present invention;

第3圖係本發明之一實施例之延遲電路的電路圖；以及Figure 3 is a circuit diagram of a delay circuit of an embodiment of the present invention;

第4A與第4B圖係本發明之具有開迴路保護的電源供應器的波形圖。4A and 4B are waveform diagrams of the power supply with open circuit protection of the present invention.

10．．．訊號產生電路10. . . Signal generation circuit

101．．．邏輯電路101. . . Logic circuit

103．．．正反器103. . . Positive and negative

105．．．邏輯電路105. . . Logic circuit

12．．．振盪器12. . . Oscillator

14．．．驅動電路14. . . Drive circuit

144．．．邏輯電路144. . . Logic circuit

146．．．功率限制比較器146. . . Power limit comparator

148．．．PWM比較器148. . . PWM comparator

16．．．回授偵測電路16. . . Feedback detection circuit

18．．．延遲電路18. . . Delay circuit

20．．．低壓偵測電路20. . . Low voltage detection circuit

PLS．．．時脈訊號PLS. . . Clock signal

Q₁ ．．．功率開關Q ₁ . . . Power switch

R_PH ．．．拉高電阻R _PH . . . Pull high resistance

R_S ．．．電流感測裝置R _S . . . Current sensing device

S_BO ．．．輸入訊號S _BO . . . Input signal

S_DELAY ．．．延遲訊號S _DELAY . . . Delay signal

S_DUTY ．．．週期訊號S _DUTY . . . Periodic signal

S_OFF ．．．截止訊號S _OFF . . . Cutoff signal

S_OL ．．．過低訊號S _OL . . . Too low signal

S_PH ．．．拉高訊號S _PH . . . Pull high signal

T₁ ．．．變壓器T ₁ . . . transformer

210．．．週期比較器210. . . Period comparator

220．．．輸入比較器220. . . Input comparator

230．．．第一邏輯電路230. . . First logic circuit

240．．．第二邏輯電路240. . . Second logic circuit

C_O ．．．輸出電容C _O . . . Output capacitor

CLR．．．清除訊號CLR. . . Clear signal

CNTR．．．回授控制訊號CNTR. . . Feedback control signal

D_O ．．．輸出整流器D _O . . . Output rectifier

I_P ．．．一吹側切換電流I _P . . . One blow side switching current

N_P ．．．一吹側繞組N _P . . . One blow side winding

N_S ．．．二吹側繞組N _S . . . Blowing side winding

OC．．．過電流訊號OC. . . Over current signal

V_CC ．．．供應電壓V _CC . . . Supply voltage

V_CS ．．．電流訊號V _CS . . . Current signal

V_FB ．．．回授訊號V _FB . . . Feedback signal

V_IN ．．．輸入電壓V _IN . . . Input voltage

V_LMT ．．．功率限制訊號V _LMT . . . Power limit signal

V_O ．．．輸出電壓V _O . . . The output voltage

V_OSC ．．．鋸齒訊號V _OSC . . . Sawtooth signal

V_PWM ．．．切換訊號V _PWM . . . Switching signal

V_T1 ．．．第一訊號V _T1 . . . First signal

V_T2 ．．．第二訊號V _T2 . . . Second signal

Claims

一種具有開迴路保護的電源供應器，其包含：一變壓器，接收一輸入電壓；一開關，耦接該變壓器並切換該變壓器；一訊號產生電路，產生一切換訊號控制該開關切換；一回授偵測電路，依據該電源供應器之一回授訊號產生一拉高訊號；一低壓偵測電路，依據該拉高訊號與該輸入電壓產生一延遲訊號；一延遲電路，依據該延遲訊號計數一延遲時間，以產生一截止訊號至該訊號產生電路，以拴鎖該切換訊號。A power supply with open circuit protection, comprising: a transformer for receiving an input voltage; a switch coupled to the transformer and switching the transformer; a signal generating circuit for generating a switching signal to control the switching of the switch; The detecting circuit generates a pull-up signal according to the feedback signal of one of the power supplies; a low-voltage detecting circuit generates a delay signal according to the pull-up signal and the input voltage; and a delay circuit that counts according to the delay signal A delay time is generated to generate a cutoff signal to the signal generating circuit to lock the switching signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，其中該拉高訊號為高準位且該低壓偵測電路偵測該輸入電壓高於一第二訊號時，該延遲電路依據該延遲訊號計數該延遲時間，以產生該截止訊號拴鎖該切換訊號。The power supply device with open loop protection according to claim 1, wherein the pull-up signal is at a high level and the low-voltage detecting circuit detects that the input voltage is higher than a second signal, the delay circuit The delay time is counted according to the delay signal to generate the cutoff signal to lock the switching signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，其中該低壓偵測電路偵測該輸入電壓低於一第二訊號時，驅使該延遲電路不計數該延遲時間，該截止訊號不拴鎖該切換訊號。The power supply device with open loop protection according to claim 1, wherein the low voltage detecting circuit detects that the input voltage is lower than a second signal, and drives the delay circuit to not count the delay time. The signal does not lock the switching signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，更包含一振盪器，該振盪器產生一時脈訊號，該訊號產生電路依據該時脈訊號產生該切換訊號。The power supply device with circuit protection according to claim 1 further includes an oscillator, wherein the oscillator generates a clock signal, and the signal generating circuit generates the switching signal according to the clock signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，更包含一驅動電路，該驅動電路依據該電源供應器之一電流訊號、一功率限制訊號與該回授訊號產生一清除訊號，以截止該切換訊號。The power supply device with circuit protection according to claim 1 further includes a driving circuit, and the driving circuit generates a clearing according to a current signal, a power limiting signal and the feedback signal of the power supply. Signal to end the switching signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，其中該回授偵測電路依據該回授訊號與一臨界訊號產生該拉高訊號。The power supply device with open loop protection according to claim 1, wherein the feedback detection circuit generates the pull-up signal according to the feedback signal and a threshold signal.

如申請專利範圍第1項所述之具有開迴路保護的電源供應器，其中該低壓偵測電路係依據一鋸齒訊號、一電流訊號與該切換訊號產生一過低訊號，該低壓偵測電路依據該過低訊號與該拉高訊號產生該延遲訊號，該電流訊號關聯於該輸入電壓。The power supply device with open loop protection according to claim 1, wherein the low voltage detecting circuit generates a low signal according to a sawtooth signal, a current signal and the switching signal, and the low voltage detecting circuit is based on The low signal and the pull signal generate the delay signal, and the current signal is associated with the input voltage.

如申請專利範圍第7項所述之具有開迴路保護的電源供應器，其中該鋸齒訊號高於一第一訊號、該電流訊號低於一第二訊號以及該切換訊號為高準位時，該低壓偵測電路禁能該過低訊號，以驅使該延遲電路停止計數該延遲時間，且該切換訊號不被拴鎖。The power supply with circuit protection according to claim 7, wherein the sawtooth signal is higher than a first signal, the current signal is lower than a second signal, and the switching signal is at a high level, The low voltage detection circuit disables the low signal to drive the delay circuit to stop counting the delay time, and the switching signal is not blocked.

如申請專利範圍第7項所述之具有開迴路保護的電源供應器，其中該拉高訊號為高準位，且該鋸齒訊號低於一第一訊號、該電流訊號高於一第二訊號或該切換訊號為低準位時，該低壓偵測電路致能該延遲訊號，以驅使該延遲電路計數該延遲時間，以產生該截止訊號拴鎖該切換訊號。The power supply device with open loop protection according to claim 7 , wherein the pull-up signal is at a high level, and the sawtooth signal is lower than a first signal, the current signal is higher than a second signal, or When the switching signal is at a low level, the low voltage detecting circuit enables the delay signal to drive the delay circuit to count the delay time to generate the cutoff signal to lock the switching signal.

如申請專利範圍第7項所述之具有開迴路保護的電源供應器，其中該低壓偵測電路更包含：一週期比較器，比較該鋸齒訊號與一第一訊號，並產生一週期訊號；一輸入比較器，比較該電流訊號與一第二訊號，並產生一輸入訊號；以及一第一邏輯電路，依據該週期訊號、該輸入訊號與該切換訊號產生該過低訊號。The power supply device with open loop protection according to claim 7 , wherein the low voltage detecting circuit further comprises: a period comparator, comparing the sawtooth signal with a first signal, and generating a period signal; Inputting a comparator, comparing the current signal with a second signal, and generating an input signal; and a first logic circuit generating the low signal according to the periodic signal, the input signal and the switching signal.

如申請專利範圍第10項所述之具有開迴路保護的電源供應器，更包含：一第二邏輯電路，依據該拉高訊號與該過低訊號產生該延遲訊號，該延遲電路依據該延遲訊號計數該延遲時間，以產生該截止訊號。The power supply device with circuit protection according to claim 10, further comprising: a second logic circuit, generating the delay signal according to the pull-up signal and the low-level signal, the delay circuit is based on the delay signal The delay time is counted to generate the cutoff signal.