TWI422133B - An ultra-low power conversion controller and associated method - Google Patents
An ultra-low power conversion controller and associated method Download PDFInfo
- Publication number
- TWI422133B TWI422133B TW097146361A TW97146361A TWI422133B TW I422133 B TWI422133 B TW I422133B TW 097146361 A TW097146361 A TW 097146361A TW 97146361 A TW97146361 A TW 97146361A TW I422133 B TWI422133 B TW I422133B
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- controller
- power consumption
- voltage
- power conversion
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Description
本發明有關於電源轉換控制器之耗電，特別是有關於一種極低耗電(ultra-low power)之電源轉換控制器與相關方法。The invention relates to power consumption of a power conversion controller, and more particularly to a power conversion controller and related method for an ultra-low power.
第一圖顯示習知技藝之顯示器內部的顯示電路方塊圖100，包含電源電路110、縮放控制器120以及背光模組130，電源電路110經由交流電源112供電轉換成適當電壓114、116，而分別供電給背光模組130及縮放控制器120之運作。顯示電路方塊圖100可以應用於電腦監視器(monitor)、類比電視或者數位電視當中。在節能減碳的世界潮流中，眾廠商皆致力於顯示器於待機狀態下的耗電量之節省，習知技藝利用交流/直流轉換(AC/DC conversion)之電源電路110進行省電。The first figure shows a display circuit block diagram 100 inside a display of a conventional technology, including a power supply circuit 110, a zoom controller 120, and a backlight module 130. The power supply circuit 110 is converted to an appropriate voltage 114, 116 via an AC power source 112, respectively. Power is supplied to the operation of the backlight module 130 and the zoom controller 120. The display circuit block diagram 100 can be applied to a computer monitor, an analog television, or a digital television. In the world trend of energy saving and carbon reduction, all manufacturers are working on the power consumption of the display in the standby state, and the conventional technology uses the AC/DC conversion power supply circuit 110 to save power.
因此十分殷切需要發展出一套可以低成本實現的極低耗電之顯示電路與相關方法。Therefore, it is very urgent to develop a display circuit and related methods that can achieve low power consumption at low cost.
本發明提出一種極低耗電電源轉換控制器，包括遲滯比較器、比較器、及閘、內部電壓調節器、控制電路及電流源；遲滯比較器，具有第一遲滯參考電壓與第二遲滯參考電壓，用以產生遲滯比較輸出訊號；比較器接收外部補償訊號，與回授參考電壓比較產生回授控制訊號；及閘，用以接收遲滯比較輸出訊號以及回授控制訊號，產生電源控制訊號；內部電壓調節器耦接至及閘，根據電源控制訊號決定是否產生內部工作電壓；控制電路，包含或閘、第一反相器與第二反相器，控制電路根據遲滯比較輸出訊號與回授控制訊號控制電流源之啟動與關閉。極低耗電電源轉換控制器更包含振盪器、SR正反器、比較器，正反器耦接於振盪器與比較器之輸出，振盪器可以經由補償訊號被禁能，或者振盪器之輸出頻率可以經由補償訊號所控制；比較器比較補償(COMP)訊號與電流感測(CS)訊號以產生比較輸出；較佳地，當補償訊號被主張時，電源轉換控制器進入極低耗電模式，其耗電量低於電源轉換控制器處於操作模式下之耗電量之十分之一。The invention provides a very low power consumption power conversion controller, comprising a hysteresis comparator, a comparator, a gate, an internal voltage regulator, a control circuit and a current source; a hysteresis comparator having a first hysteresis reference voltage and a second hysteresis reference The voltage is used to generate a hysteresis comparison output signal; the comparator receives the external compensation signal, and generates a feedback control signal compared with the feedback reference voltage; and the gate is configured to receive the hysteresis comparison output signal and the feedback control signal to generate the power control signal; The internal voltage regulator is coupled to the AND gate, and determines whether to generate an internal working voltage according to the power control signal; the control circuit includes a gate, a first inverter and a second inverter, and the control circuit compares the output signal and the feedback according to the hysteresis The control signal controls the start and stop of the current source. The extremely low power consumption power conversion controller further includes an oscillator, an SR flip-flop, and a comparator. The flip-flop is coupled to the output of the oscillator and the comparator, and the oscillator can be disabled through the compensation signal, or the output of the oscillator. The frequency can be controlled by the compensation signal; the comparator compares the compensation (COMP) signal with the current sensing (CS) signal to generate a comparison output; preferably, when the compensation signal is asserted, the power conversion controller enters a very low power consumption mode The power consumption is less than one tenth of the power consumption of the power conversion controller in the operating mode.
本發明更提出一種極低耗電電源控制方法，包括：導通電流源達第一預定期間，可以根據該回授控制訊號與一遲滯比較輸出訊號控制該電流源之開啟與關閉；致能電源轉換控制器內之電壓調節器達一第二預定期間，並於該第二預定期間產生驅動訊號，例如脈波寬度調變訊號或者脈波頻率調變訊號；主張回授控制訊號上使得電源轉換控制器進入極低耗電模式，例如禁能電源轉換控制器內之電壓調節器與振盪器，使得電源轉換控制器之耗電量低於電源轉換控制器處於操作模式下之耗電量之十分之一；以及解除主張回授控制訊號以使電源轉換控制器恢復成正常運作 達第三預定期間。The invention further provides a method for controlling a very low power consumption power source, comprising: turning on a current source for a first predetermined period, and controlling the opening and closing of the current source according to the feedback control signal and a hysteresis comparison output signal; enabling power conversion The voltage regulator in the controller reaches a second predetermined period, and generates a driving signal, such as a pulse width modulation signal or a pulse frequency modulation signal, during the second predetermined period; and asserts a feedback control signal to enable power conversion control The device enters a very low power consumption mode, such as a voltage regulator and an oscillator in the disable power conversion controller, so that the power consumption of the power conversion controller is lower than the power consumption of the power conversion controller in the operation mode. One; and dismiss the claim feedback control signal to restore the power conversion controller to normal operation Up to the third scheduled period.
為了使 鈞局能更進一步瞭解本發明特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖，然而所附圖式僅提供參考與說明，並非用來對本發明加以限制。The detailed description of the present invention and the accompanying drawings are to be understood as the
第二圖顯示根據本發明具體實施例之極低耗電顯示控制電路300，交流電源302供應交流電壓給經過整流器310，例如80至220伏交流電壓；經過整流器310整流輸出直流電壓給偏壓電路320與變壓器(transformer)330，例如是120至375伏直流電壓，整流器310例如是全橋式整流器；經過偏壓電路320偏壓為直流電壓訊號VDDP供電給電源轉換控制器340運作，直流電壓訊號VDDP例如是20伏直流電壓，電源轉換控制器340為類比電路晶片，通常封裝為八個腳位，由於成本考量有腳位數量之限制。變壓器330利用線圈感應將其一次側之高壓直流電壓轉換成其他適當的直流電壓於二次側輸出，供其他電路運作，例如輸出直流電壓訊號VCC14V與VCC5V，分別提供14伏與5伏直流電壓，14伏直流電壓可供應背光模組之運作，例如冷陰極燈管或者發光二極體之背光模組之運作。直流電壓訊號VCC5V經過，穩壓器350，例如低壓差線性穩壓器(low drop-out regulator，簡稱LDO)350，穩壓輸出直流電壓訊號3V3而供電給縮放控制器360之運作。縮放控制器360根據變壓器330輸出之直流電壓訊號VCC5V上的電壓狀況控制電源轉換控制器340之運作，舉例而言，將直流電壓訊號VCC5V經過電阻R5、R6之分壓訊號VCC5Vsense送進縮放控制器360之逐步逼近暫存器類比數位轉換器(successive approximation ADC，簡稱SAR ADC)偵測直流電壓訊號VCC5V上的電壓狀況，熟知此技藝人士可以了解逐步逼近暫存器類比數位轉換器是低成本可以實現的低速類比數位轉換器，或者，將分壓訊號VCC5Vsense送進縮放控制器360之一比較器(未示出)與一參考電壓，例如4伏，偵測直流電壓訊號VCC5V上的電壓狀況；然後，縮放控制器360可利用通用型輸入輸出(general purpose I/O，簡稱GPIO)腳位經過光耦合元件(opto-coupler或稱photocoupler)370控制電源轉換控制器340之補償腳位COMP，回授控制電源轉換控制器340之開啟運作時機，達到極低耗電之目的。應注意到，熟知此技藝人士可以了解電源轉換控制器340為類比電路晶片，通常封裝為八個腳位，其中補償腳位COMP於電源轉換控制器340內部提供有電流源342，例如為200微安培(Ma)之電流源。偏壓電路320包括電阻R11、R12、R13、二極體D21、D22、電晶體Q1、Q2、Q3。偏壓電路320利用電阻R11、R12、電晶體Q1路徑將高壓直流電壓偏壓為直流電壓訊號VDDP供電給電源轉換控制器340運作。The second figure shows a very low power consumption display control circuit 300 in accordance with an embodiment of the present invention. The AC power source 302 supplies an AC voltage to a rectifier 310, such as an AC voltage of 80 to 220 volts; and a rectified output DC voltage through a rectifier 310 to a bias voltage. The circuit 320 and the transformer 330 are, for example, a DC voltage of 120 to 375 volts, and the rectifier 310 is, for example, a full bridge rectifier; and is biased by the bias circuit 320 to supply a DC voltage signal VDDP to the power conversion controller 340 for operation, DC. The voltage signal VDDP is, for example, a 20 volt DC voltage. The power conversion controller 340 is an analog circuit chip, and is usually packaged in eight pins, which is limited by the number of pins due to cost considerations. The transformer 330 converts the high-voltage DC voltage of the primary side into other appropriate DC voltages on the secondary side by coil induction for other circuits, for example, outputting DC voltage signals VCC14V and VCC5V, respectively providing 14 volts and 5 volts DC voltage. The 14 volt DC voltage can supply the operation of the backlight module, such as the operation of a cold cathode lamp or a backlight module of a light emitting diode. The DC voltage signal VCC5V passes through a voltage regulator 350, such as a low drop-out regulator (LDO) 350, and the regulated output DC voltage signal 3V3 is supplied to the operation of the scaling controller 360. The scaling controller 360 controls the operation of the power conversion controller 340 according to the voltage condition on the DC voltage signal VCC5V outputted by the transformer 330. For example, the DC voltage signal VCC5V is sent to the scaling controller via the voltage dividing signal VCC5Vsense of the resistors R5 and R6. 360 gradually approaches the register analog converter (SAR ADC) to detect the voltage condition on the DC voltage signal VCC5V. It is well known to those skilled in the art that it is low-cost to gradually approach the register analog digital converter. The low-speed analog-to-digital converter is implemented, or the voltage dividing signal VCC5Vsense is sent to a comparator (not shown) of the scaling controller 360 and a reference voltage, for example, 4 volts, to detect the voltage condition on the DC voltage signal VCC5V; Then, the scaling controller 360 can control the compensation pin COMP of the power conversion controller 340 through an optical-coupled component (opto-coupler or photocoupler) 370 using a general-purpose input/output (GPIO) pin. The control power conversion controller 340 is turned on to operate at a very low power consumption. It should be noted that those skilled in the art will appreciate that the power conversion controller 340 is an analog circuit chip, typically packaged in eight pins, wherein the compensation pin COMP is provided with a current source 342 inside the power conversion controller 340, for example, 200 micro. Ampere (Ma) current source. The bias circuit 320 includes resistors R11, R12, R13, diodes D21, D22, and transistors Q1, Q2, Q3. The bias circuit 320 uses the resistors R11, R12 and the transistor Q1 path to bias the high voltage DC voltage to the DC voltage signal VDDP to supply power to the power conversion controller 340.
電源轉換控制器340利用電容器C1所儲存的電荷，於電晶體Q1關閉而停止供電時，可以短暫供應電源轉換控制器340之運作，但是，熟知此技藝人士可以了解電容器C1亦關係到電源啟動時，真正開始供應正常直流電壓運作所需要的時間，所以電容器C1也不能太大，例如為22微法拉(μF)。而縮放控制器360則可以利用電容器C2，於切斷電源時，可以短暫供應縮放控制器360之運作，典型地電容器C2相當大，例如為2000微法拉(μF)，應注意到電容器C2可提供的儲存電力遠較電容器C1大。The power conversion controller 340 utilizes the charge stored by the capacitor C1 to temporarily supply the operation of the power conversion controller 340 when the transistor Q1 is turned off to stop the power supply. However, those skilled in the art can understand that the capacitor C1 is also related to the power source startup. , really start to supply the time required for normal DC voltage operation, so the capacitor C1 can not be too large, for example 22 microfarads (μF). The zoom controller 360 can utilize the capacitor C2. When the power is turned off, the operation of the zoom controller 360 can be temporarily supplied. Typically, the capacitor C2 is relatively large, for example, 2000 microfarads (μF), and it should be noted that the capacitor C2 can provide The stored power is much larger than the capacitor C1.
第二圖所顯示之極低耗電顯示控制電路300，在關閉系統電源後，利用電容器C2短暫供電於縮放控制器360之運作，經過穩壓器350穩壓輸出直流電壓訊號3V3而供電給縮放控制器360之運作，只要直流電壓訊號VCC5V經過穩壓器350穩壓輸出之直流電壓訊號3V3高於縮放控制器360之工作電壓之狀況下，皆可運作縮放控制器360，穩壓器350之耗電量極低，並使得直流電壓訊號VCC5V與直流電壓訊號3V3間之電壓降LDODrop極小。假設縮放控制器360之工作電壓為3.3伏，經由電容器C2之逐漸放電，只要直流電壓訊號VCC5V超過(3.3伏+LDODrop)，皆可使縮放控制器360運作。The extremely low power consumption display control circuit 300 shown in the second figure, after the system power is turned off, is temporarily powered by the capacitor C2 to operate the scaling controller 360, and is regulated by the regulator 350 to output a DC voltage signal 3V3 to supply power to the zoom. The operation of the controller 360 can operate the scaling controller 360 and the voltage regulator 350 as long as the DC voltage signal VCC5V is regulated by the regulator 350 and the DC voltage signal 3V3 is higher than the operating voltage of the scaling controller 360. The power consumption is extremely low, and the voltage drop LDODrop between the DC voltage signal VCC5V and the DC voltage signal 3V3 is extremely small. Assuming that the operating voltage of the scaling controller 360 is 3.3 volts, the gradual discharge via the capacitor C2 allows the scaling controller 360 to operate as long as the DC voltage signal VCC5V exceeds (3.3 volts + LDODrop).
在關閉系統電源後，縮放控制器360利用GPIO腳位送出訊號AC_OFF將縮放控制器360之電壓狀態，經由電阻R4以及光耦合元件370反應給電源轉換控制器340端以汲取電流，電源轉換控制器340則利用補償腳位COMP使電流源342經由電阻R13、二極體D21、D22與電晶體Q3供應此電流，舉例而言，光耦合元件370之電流轉換比例(current transfer ration，簡稱CTR)為1:1，則光耦合元件370兩側所汲取之電流為1:1，訊號AC_OFF之主張(assertion)期間相關於直流電壓訊號VCC5V之位準。當電源轉換控制器340於補償腳位COMP感測到縮放控制器360之電壓低於一預定位準時，短暫驅動訊號DRV以打開電晶體Q4，短暫啟動變壓器330之一次側汲取外部電源，以對電容C1充電以及對變壓器330之二次側之大電容C2充電，以供下個循環期間縮放控制器360之運作。第二圖中箭頭方向標示出幾個電路分析中的主要電流流向，使得熟知此技藝人士可以更了解本實施例之運作。After the system power is turned off, the scaling controller 360 uses the GPIO pin to send the signal AC_OFF to scale the voltage state of the controller 360, and reacts to the power conversion controller 340 via the resistor R4 and the optical coupling component 370 to draw current. The power conversion controller 340 uses the compensation pin COMP to supply the current source 342 to the current through the resistor R13, the diodes D21, D22 and the transistor Q3. For example, the current transfer ratio (CTR) of the optical coupling element 370 is 1:1, the current drawn by the two sides of the optical coupling element 370 is 1:1, and the assertion of the signal AC_OFF is related to the level of the DC voltage signal VCC5V. When the power conversion controller 340 senses that the voltage of the scaling controller 360 is lower than a predetermined level at the compensation pin COMP, the signal DRV is briefly driven to turn on the transistor Q4, and the primary side of the transformer 330 is briefly activated to extract the external power source. Capacitor C1 is charged and the large capacitor C2 on the secondary side of transformer 330 is charged for operation of scaling controller 360 during the next cycle. The direction of the arrows in the second figure indicates the main current flow in several circuit analyses, so that those skilled in the art will be more aware of the operation of this embodiment.
對於電源轉換控制器340，當主張訊號AC_OFF時，例如為高位準，光耦合元件370產生耦合電流，經由節點A、二極體D21、D22與光耦合元件370汲取所需之耦合電流，使得電晶體Q3之基極電壓下降，導通電晶體Q3與二極體D21、D22，使得補償腳位COMP上電壓下降，關閉電晶體Q2，使得電晶體Q1之基極電位下降而關閉電晶體Q1；電晶體Q3具有電流放大之作用，可以加速電流源342之放電速度，如果電源轉換控制器340內之電流源342之電流能力低，則可以省掉電晶體Q3，直接靠二極體D22進行放電。另一方面，當解除主張訊號AC_OFF時，例如為低位準，無感應電流產生，導通電晶體Q1而對電容C1充電，然後補償腳位COMP上電壓逐漸上升，導通電晶體Q2，使得電晶體Q1之基極接地而關閉電晶體Q1，使得電源轉換控制器340使用電容C1所儲存之電力，使得電容C1放電；因此，藉由訊號AC_OFF之主張與否控制電源轉換控制器340運作與否，以控制電容C1充電、放電循環運作。For the power conversion controller 340, when the signal AC_OFF is asserted, for example, a high level, the optical coupling element 370 generates a coupling current, and the required coupling current is drawn through the node A, the diodes D21, D22 and the optical coupling element 370, so that the electricity is generated. The base voltage of the crystal Q3 drops, and the conductive crystal Q3 and the diodes D21 and D22 are turned on, so that the voltage on the compensation pin COMP drops, and the transistor Q2 is turned off, so that the base potential of the transistor Q1 drops and the transistor Q1 is turned off; The crystal Q3 has a function of current amplification, which can accelerate the discharge speed of the current source 342. If the current capability of the current source 342 in the power conversion controller 340 is low, the transistor Q3 can be omitted and discharged directly by the diode D22. On the other hand, when the assertion signal AC_OFF is released, for example, a low level, no induced current is generated, the transistor Q1 is energized to charge the capacitor C1, and then the voltage on the compensating pin COMP gradually rises, and the transistor Q2 is turned on, so that the transistor Q1 is turned on. The base is grounded to turn off the transistor Q1, so that the power conversion controller 340 uses the power stored by the capacitor C1 to discharge the capacitor C1; therefore, the power conversion controller 340 is controlled by the assertion of the signal AC_OFF to Control capacitor C1 charging and discharging cycle operation.
第三圖顯示關於第二圖之極低耗電顯示控制電路300之主要波形圖，包括訊號AC_OFF、電壓訊號VDDP、訊號DRV、電壓訊號VCC5V、感測訊號VCC5Vsense之間的波形關係圖。配合第二圖之極低耗電顯示控制電路300進行說明，於此實施例中，訊號AC_OFF拉高之後，透過二極體D21、D22與光耦合元件370快速地強迫電源轉換控制器340內之電流源342放電拉低電位並關閉電晶體Q1，強迫切斷外部電源對電源轉換控制器340之供電，且電壓訊號VDDP被快速的拉低，持續維持在0伏一段相當長的時間，達到省電的目的。訊號AC_OFF拉低之後，開啟電晶體Q1，對電容C1充電，使得電壓訊號VDDP快速上升，到達最高的電壓後，例如20伏，補償腳位COMP上電壓上升到預定位準，電源轉換控制器340短暫地主張訊號DRV，例如由電源轉換控制器340內之脈波寬度調變(pulse width modulation，簡稱PWM)控制器短暫地產生高低位準寬度調變之訊號DRV，或者由脈波頻率調變(pulse frequency modulation，簡稱PFM)控制器產生頻率不同之訊號DRV，短暫地導通電晶體Q4，使得變壓器330之一次側短暫導通對電容C1充電以及對二次側的大電容C2充電，例如將電壓訊號VCC5V快速地拉升到5伏，其可藉由與一比較器與一參考電壓比較達成，或者例如對二次側的大電容C2充電一預定期間；只要在電壓訊號VCC5V放電到預定電壓之前，縮放控制器360皆可正常運作監控感測訊號VCC5Vsense之變化，如此持續循環運作，舉例而言，只要確保整個過程當中電壓訊號VCC5V皆大於(3.3伏+電壓降LDODrop)，即可正常運作。感測訊號VCC5Vsense則顯示對應電壓訊號VCC5V的充放電變化。應注意到，電壓訊號VDDP持續維持在0伏一段相當長的時間，使得訊號DRV之驅動期間相隔很遠，可以完全隔絕外部電源之消耗，達到極低耗電之目的，經過電路模擬，總電力消耗約可達150毫瓦(mW)以下，而實際需要支出的額外成本甚低，兼顧成本與效能兩者之考量。本實施例中其他輔助元件之運作，例如熔絲F1、負溫係數電阻NTC、電阻R2、電容C4等等，可以為熟知此技藝人士所了解便不再贅述。The third figure shows the main waveform diagram of the extremely low power consumption display control circuit 300 of the second figure, including the waveform relationship between the signal AC_OFF, the voltage signal VDDP, the signal DRV, the voltage signal VCC5V, and the sensing signal VCC5Vsense. The low power consumption display control circuit 300 of the second figure is described. In this embodiment, after the signal AC_OFF is pulled high, the power conversion controller 340 is quickly forced through the diodes D21 and D22 and the optical coupling element 370. The current source 342 discharges the low potential and turns off the transistor Q1, forcibly cuts off the power supply of the external power source to the power conversion controller 340, and the voltage signal VDDP is rapidly pulled down, and is maintained at 0 volts for a relatively long period of time. The purpose of electricity. After the signal AC_OFF is pulled low, the transistor Q1 is turned on, and the capacitor C1 is charged, so that the voltage signal VDDP rises rapidly. After reaching the highest voltage, for example, 20 volts, the voltage on the compensation pin COMP rises to a predetermined level, and the power conversion controller 340 The signal DRV is asserted briefly, for example, by a pulse width modulation (PWM) controller in the power conversion controller 340, which temporarily generates a high and low level modulation signal DRV, or is modulated by a pulse frequency. The pulse frequency modulation (PFM) controller generates a signal DRV with a different frequency, and briefly conducts the crystal Q4, so that the primary side of the transformer 330 is briefly turned on to charge the capacitor C1 and charge the large capacitor C2 on the secondary side, for example, the voltage. The signal VCC5V is rapidly pulled up to 5 volts, which can be achieved by comparison with a comparator and a reference voltage, or for example, charging the secondary side of the large capacitor C2 for a predetermined period; as long as the voltage signal VCC5V is discharged to a predetermined voltage The zoom controller 360 can normally operate to monitor the change of the sensing signal VCC5Vsense, so that the loop operation is continued, for example, as long as it is ensured Process a voltage signal which are greater than VCC5V (+ 3.3 volt voltage drop LDODrop), to work properly. The sensing signal VCC5Vsense displays the charge and discharge changes of the corresponding voltage signal VCC5V. It should be noted that the voltage signal VDDP is continuously maintained at 0 volts for a relatively long period of time, so that the driving period of the signal DRV is far apart, the external power supply can be completely isolated, and the power consumption is extremely low. The consumption can be as low as 150 milliwatts (mW) or less, and the extra cost of actual expenditure is very low, taking into account both cost and performance considerations. The operation of other auxiliary components in this embodiment, such as fuse F1, negative temperature coefficient resistor NTC, resistor R2, capacitor C4, etc., may be omitted for those skilled in the art.
第四圖顯示根據本發明之另一具體實施例之極低耗電顯示控制電路400，相較於第二圖之實施例之差異在於偏壓電路420，利用電阻R18提供偏壓控制，並省略電晶體Q3，而最右端則顯示來自個人電腦的5伏訊號PC5V可以透過二極體D6耦接於電壓訊號VCC5V，對電容C2充電；而縮放控制器360也可被廣泛整合於顯示控制器(display controller)，應用於類比電視與數位電視，並不跳脫本發明之範疇。The fourth figure shows a very low power consumption display control circuit 400 in accordance with another embodiment of the present invention. The difference from the embodiment of the second embodiment is that the bias circuit 420 provides bias control using resistor R18, and The transistor Q3 is omitted, and the 5V signal from the personal computer PC5V can be coupled to the voltage signal VCC5V through the diode D6 to charge the capacitor C2. The zoom controller 360 can also be widely integrated into the display controller. (display controller), applied to analog televisions and digital televisions, does not depart from the scope of the present invention.
第五圖顯示根據本發明之另一具體實施例之極低耗電顯示控制電路500，其主要係源自第二圖實施例之概念。類似的訊號亦採用前面訊號之標號，有助於了解本實施例之運作。主要差異在於電源轉換控制器540整合了第二圖中偏壓電路320之類似元件，而顯示控制器560直接偵側電壓訊號VDD3V3，節省逐步逼近暫存器類比數位轉換器或者比較器之腳位；如前面實施例所揭示，由顯示控制器560偵側電壓訊號VDD3V3之變化，舉例而言，確保偵側電壓訊號VDD3V3高於3.3伏。舉例而言，在電壓訊號VDD3V3高於3.3伏前，可由顯示控制器560利用GPIO腳位主張訊號AC_OFF，經由光耦合元件570、補償腳位COMP令電源轉換控制器540停止汲取外部電源；在電壓訊號VDD3V3快落到3.3伏前，由顯示控制器560解除主張訊號AC_OFF，電源轉換控制器540藉由打開內部開關(未示出)經由高壓電源腳位HV由節點B短暫地汲取外部電源，使得電源轉換控制器540內部的受控電流源542，經由電壓訊號VDDp’對電容C1充電，短暫地驅動訊號DRV，啟動變壓器530之一次側，使得變壓器530對電容C1充電以及對二次側之大電容C2充電達一預定電壓或者充電一預定期間。電源轉換控制器540長時間地切斷外部電源，可以大幅降低耗電。箭頭方向標示出幾個電路分析中的主要電流流向，使得熟知此技藝人士可以更了解本實施例之運作。The fifth figure shows a very low power consumption display control circuit 500 in accordance with another embodiment of the present invention, which is primarily derived from the concepts of the second embodiment. Similar signals are also labeled with the preceding signals to help understand the operation of this embodiment. The main difference is that the power conversion controller 540 integrates similar components of the bias circuit 320 in the second figure, and the display controller 560 directly detects the voltage signal VDD3V3, saving the step closer to the register analog digital converter or the comparator. As shown in the previous embodiment, the display controller 560 detects the change of the voltage signal VDD3V3, for example, to ensure that the detection side voltage signal VDD3V3 is higher than 3.3 volts. For example, before the voltage signal VDD3V3 is higher than 3.3 volts, the GPIO pin position signal AC_OFF can be utilized by the display controller 560, and the power conversion controller 540 stops the external power supply via the optical coupling element 570 and the compensation pin COMP; Before the signal VDD3V3 falls to 3.3 volts, the display controller 560 releases the assertion signal AC_OFF, and the power conversion controller 540 temporarily draws the external power source from the node B via the high voltage power supply pin HV by turning on an internal switch (not shown). The controlled current source 542 inside the power conversion controller 540 charges the capacitor C1 via the voltage signal VDDp', and briefly drives the signal DRV to start the primary side of the transformer 530, so that the transformer 530 charges the capacitor C1 and the secondary side. Capacitor C2 is charged to a predetermined voltage or charged for a predetermined period of time. The power conversion controller 540 cuts off the external power supply for a long time, and the power consumption can be greatly reduced. The direction of the arrows indicates the main current flow in several circuit analyses, so that those skilled in the art will be more aware of the operation of this embodiment.
根據以上諸多實施例之揭示，熟知此技藝人士可以做出許多可能變化，仍不跳脫本發明之範疇。舉例而言，顯示控制器560利用GPIO腳位控制訊號AC_OFF，經由電阻R4、光耦合元件570，回授控制補償腳位COMP，而控制電源轉換控制器540是否汲取外部電源，可以有其他變化之可能，舉例而言，可以修改光耦合元件570附近之電路，使得訊號AC_OFF之高低位準相對於電源轉換控制器540之運作相反；或者，搭配輔助電路使得GPIO腳位間接控制光耦合元件570汲取電流之運作；或者，以上諸多實施例係由GPIO腳位輸出控制訊號AC_OFF之位準，藉由修改光耦合元件570附近之電路，可使得GPIO腳位為輸入方式運作，如第六圖所示，光耦合元件570經由電阻R72耦接於顯示控制器560之GPIO腳位，經由電晶體Q8控制是否導通放電，當控制訊號CTRL被主張，導通電晶體Q8，於訊號COMP引發電源轉換控制器540類似前述實施例之運作。Many variations are possible in light of the above-described embodiments, without departing from the scope of the invention. For example, the display controller 560 uses the GPIO pin control signal AC_OFF to feedback the control compensation pin COMP via the resistor R4 and the optical coupling component 570, and controls whether the power conversion controller 540 captures the external power supply, and may have other changes. For example, the circuit in the vicinity of the optical coupling element 570 can be modified such that the high and low levels of the signal AC_OFF are opposite to the operation of the power conversion controller 540; or, in conjunction with the auxiliary circuit, the GPIO pin indirectly controls the optical coupling element 570. The operation of the current; or, the above embodiments are controlled by the GPIO pin output control signal AC_OFF, by modifying the circuit near the optical coupling component 570, the GPIO pin can be operated as an input mode, as shown in the sixth figure. The optical coupling component 570 is coupled to the GPIO pin of the display controller 560 via the resistor R72, and controls whether the discharge is turned on via the transistor Q8. When the control signal CTRL is asserted, the transistor Q8 is turned on, and the power conversion controller 540 is triggered by the signal COMP. Similar to the operation of the previous embodiment.
第七圖顯示根據本發明之具體實施例之極低耗電顯示控制方法之流程圖。於步驟702，感測變壓器二次側之直流電壓位準，舉例而言，可以感測第二圖中訊號VCC5V之變化，或者直接感測訊號VDD3V3之變化，舉例而言，確保訊號VDD3V3皆高於3.3伏；於步驟704，顯示控制器藉由GPIO腳位導通光耦合元件，控制電源轉換控制器之補償腳位，而關閉電源轉換控制器之運作，舉例而言，如第五圖所示，顯示控制器560可藉由GPIO腳位主張訊號AC_OFF增加光耦合元件570之耦合電流之大小，而關閉電源轉換控制器540之運作，或者，如第六圖所示，光耦合元件570耦接於顯示控制器560之GPIO腳位，藉由電晶體Q8形成放電路徑，而關閉電源轉換控制器540之運作；於步驟706，當直流電壓位準下降到達一預定位準時，經由GPIO腳位降低光耦合元件之耦合電流之大小，控制電源轉換控制器之補償腳位，而啟動電源轉換控制器之運作；於步驟708，短暫導通變壓器之一次側，對第一電容與第二電容短暫充電，舉例而言，如第五圖所示，藉由脈波寬度調變或者脈波頻率調變控制電晶體Q4之閘極，使得變壓器530對第一電容C1與二次側之第二電容C2充電。The seventh figure shows a flow chart of a very low power consumption display control method in accordance with an embodiment of the present invention. In step 702, the DC voltage level of the secondary side of the transformer is sensed. For example, the change of the signal VCC5V in the second figure or the change of the direct sense signal VDD3V3 can be sensed. For example, the signal VDD3V3 is high. At step 704, the display controller turns on the optical coupling component by the GPIO pin to control the compensation pin of the power conversion controller, and turns off the operation of the power conversion controller, for example, as shown in FIG. The display controller 560 can turn off the operation of the power conversion controller 540 by increasing the coupling current of the optical coupling element 570 by the GPIO pin position signal AC_OFF, or, as shown in the sixth figure, the optical coupling element 570 is coupled. In the GPIO pin of the display controller 560, the discharge path is formed by the transistor Q8, and the operation of the power conversion controller 540 is turned off; in step 706, when the DC voltage level falls to a predetermined level, the GPIO pin is lowered. The coupling current of the optical coupling component controls the compensation pin of the power conversion controller to activate the operation of the power conversion controller; in step 708, one of the transient conduction transformers On the side, the first capacitor and the second capacitor are briefly charged. For example, as shown in FIG. 5, the gate of the transistor Q4 is controlled by the pulse width modulation or the pulse frequency modulation, so that the transformer 530 is A capacitor C1 is charged with a second capacitor C2 on the secondary side.
第八圖顯示根據本發明之一具體實施例之極低耗電電源轉換控制器800，具有HV、VDDp、DRV、CS、COMP及GND等腳位，當應用到第五圖之實施例運作，第八圖各腳位外部電路之運作如前述實施例所述。極低耗電電源轉換控制器800包含比較器810、820、遲滯比較器830、振盪器840、電流源842、電壓調節器850、正反器860、及閘870、872、緩衝器880、控制電路890、電阻R80、R82、齊鈉二極體D80。The eighth diagram shows a very low power consumption power conversion controller 800 having HV, VDDp, DRV, CS, COMP, and GND pins according to an embodiment of the present invention. When applied to the embodiment of the fifth figure, The operation of the external circuit of each pin in the eighth figure is as described in the foregoing embodiment. The extremely low power consumption power conversion controller 800 includes comparators 810, 820, hysteresis comparator 830, oscillator 840, current source 842, voltage regulator 850, flip flop 860, and gates 870, 872, buffer 880, control Circuit 890, resistors R80, R82, and sodium diode D80.
第九圖顯示第八圖中極低耗電電源轉換控制器800運作之主要訊號波形圖，V(VDDP)、V(COMP)、I(HV)、I(VDDp)、V(DRV)、5V訊號分別代表VDDp腳位之電壓訊號、COMP腳位上之電壓訊號、HV腳位之電流大小、VDDp腳位之電流大小、DRV腳位之電壓訊號、5V電壓訊號。電源轉換控制器800剛啟動時，HV腳位經由電流源842對VDDp腳位外之電容(未示出)充電，當電位逐漸升高到遲滯比較器830之正端輸入電壓高於第一遲滯參考電壓VDDH，遲滯比較器830之輸出位準為高，使得及閘870之輸出為高，致能電壓調節器850輸出工作電壓於訊號852供電源轉換控制器800內部之運作；而且，遲滯比較器830之輸出高位準經由或閘892與反相器894，關閉電流源842，終止HV腳位從外部汲取電流，此或閘892與反相器894控制路徑保證只要遲滯比較器830之輸出高位準會關閉電流源842阻絕外部之耗電。振盪器840產生一方波訊號輸出給SR正反器860之S輸入端，而SR正反器860之R輸入端一開始為低位準，Q輸出端轉為高位準，當DRV腳位上被拉高位準，外部連接的電晶體(未示出)會被導通，電流感測(CS)腳位也會因此跟著被拉高位準，經過比較器810，SR正反器860之R輸入端會轉變為高位準，當SR正反器860下一次接受觸發時，R正反器860之S輸入端與R輸入端分別為低位準與高位準，觸發後，Q輸出端轉為低位準，也就是說，此電路之運作，S輸入端與R輸入端之輸入為準於觸發時剛好都反相，以產生脈波寬度調變訊號於DRV腳位上。舉例而言，方波訊號為1MHz之方波訊號，降低極低耗電電源轉換控制器800於待機模式下的功耗，透過及閘872與緩衝器880將方波訊號於DRV腳位上輸出。接著，VDDp腳位外之電容(未示出)將所儲存的電力緩慢釋出，直到遲滯比較器830之正端輸入電壓到達第二遲滯參考電壓VDDL，使得遲滯比較器830之輸出位準由高轉低，使得及閘870之輸出為低，及閘872之輸出為低，DRV腳位之輸出為低，關閉連接於其上的外部電晶體(未示出)而關閉外部變壓器(未示出)之一次側，如第九圖所示，I(HV)訊號一開始汲取充電電流Icharge，於V(VDDP)從電壓VDDH到電壓VDDL，I(HV)訊號(從外部電源)消耗電流驟降為Ihv_off。I(VDDp)對應釋放出來的電流為Istartup與Iop，電流Iop供應電源轉換控制器800驅動DRV腳位上的方波訊號。The ninth figure shows the main signal waveforms of the very low power consumption power conversion controller 800 in the eighth figure, V (VDDP), V (COMP), I (HV), I (VDDp), V (DRV), 5V. The signals represent the voltage signal of the VDDp pin, the voltage signal on the COMP pin, the current of the HV pin, the current of the VDDp pin, the voltage signal of the DRV pin, and the 5V voltage signal. When the power conversion controller 800 is just started, the HV pin charges the capacitor (not shown) outside the VDDp pin via the current source 842, and the potential is gradually increased to the positive terminal input voltage of the hysteresis comparator 830 is higher than the first hysteresis. The reference voltage VDDH, the output level of the hysteresis comparator 830 is high, so that the output of the AND gate 870 is high, and the voltage regulator 850 is enabled to output the operating voltage to the signal 852 for operation inside the power conversion controller 800; and, hysteresis comparison The output high level of the 830 is passed through the OR gate 892 and the inverter 894, the current source 842 is turned off, and the HV pin is terminated to draw current from the outside. The OR gate 892 and the inverter 894 control path ensure that the output of the hysteresis comparator 830 is high. The current source 842 is turned off to block external power consumption. The oscillator 840 generates a one-wave signal output to the S input terminal of the SR flip-flop 860, and the R input terminal of the SR flip-flop 860 is initially at a low level, and the Q output is turned to a high level, when the DRV pin is pulled. The high level, externally connected transistor (not shown) will be turned on, and the current sense (CS) pin will therefore be pulled high. After the comparator 810, the R input of the SR flip-flop 860 will change. For the high level, when the SR flip-flop 860 receives the trigger next time, the S input end and the R input end of the R flip-flop 860 are respectively low level and high level. After the trigger, the Q output end is turned to the low level, that is, Said that the operation of this circuit, the input of the S input and the R input is just opposite to the trigger, so as to generate the pulse width modulation signal on the DRV pin. For example, the square wave signal is a 1 MHz square wave signal, which reduces the power consumption of the very low power consumption power conversion controller 800 in the standby mode, and outputs the square wave signal to the DRV pin through the gate 872 and the buffer 880. . Then, a capacitor (not shown) outside the VDDp pin slowly releases the stored power until the positive input voltage of the hysteresis comparator 830 reaches the second hysteresis reference voltage VDDL, so that the output level of the hysteresis comparator 830 is High to low, so that the output of the gate 870 is low, and the output of the gate 872 is low, the output of the DRV pin is low, the external transistor (not shown) connected thereto is turned off and the external transformer is turned off (not shown) On the primary side of the output, as shown in the ninth figure, the I (HV) signal initially draws the charging current Icharge, and the current is consumed by the voltage (VDDP) from the voltage VDDH to the voltage VDDL, and the I (HV) signal (from the external power source). Drop to Ihv_off. The currents released by I(VDDp) are Istartup and Iop, and the current Iop supply power conversion controller 800 drives the square wave signal on the DRV pin.
接著，外部變壓器之一次側導通過後，二次側的顯示控制器(未示出)方獲得電力而可以運作，可以控制V(COMP)訊號。藉由前述實施例揭露的COMP腳位之控制，經由控制COMP腳位上的補償訊號，可以讓產生脈波寬度調變訊號的時間間隔拉長、產生的真正時間長度也縮短，但是仍讓電源轉換控制器800完全受監控的方式下運作，不致於讓整個系統失控無法喚醒。Then, after the primary side conductor of the external transformer passes, the display controller (not shown) on the secondary side can obtain power to operate, and can control the V (COMP) signal. By controlling the COMP pin disclosed in the foregoing embodiment, by controlling the compensation signal on the COMP pin, the time interval for generating the pulse width modulation signal can be lengthened, and the actual time length generated is also shortened, but the power is still supplied. The switch controller 800 operates in a fully monitored manner so that the entire system is out of control and cannot be woken up.
當V(COMP)訊號之電壓拉低，強迫關閉振盪器840之運作，或者，回應於V(COMP)訊號之電位高低而調變振盪器840之輸出頻率之高低，舉例而言，V(COMP)訊號之電位高則輸出頻率變高，V(COMP)訊號之電位低則輸出頻率變低，或反向運作，因此可以V(COMP)訊號之電位高低可以影響電源轉換控制器800之耗電量；而且控制比較器820將正端電壓與回授參考電壓Voff比較後，低位準輸出於回授控制訊號822，使得及閘870之輸出為低位準，禁能電壓調節器850之運作，關閉電源轉換控制器800之內部電力供應，使得電源轉換控制器800進入極低耗電模式，電流I(VDDp)瞬間降低至Ioff，較佳地電流Ioff小於電流0.1*Iop，或者更低，V(VDDP)電位的下降速度變的十分緩慢，也就是V(VDDP)電位下降斜率變小，而且藉由控制V(COMP)訊號可以大幅拉長下次開始對外部電容充電的時間，降低整個系統之耗電；應注意到，拉低V(COMP)訊號可以使得低位準輸出於回授控制訊號822經由反相器896與或閘892強迫關閉電流源842，終止HV腳位從外部汲取電流，因為此時遲滯比較器830之輸出正處於高位準，已經關閉電流源842之運作。也就是說，簡單的控制電路890包含或閘892以及反相器894、896可以適時控制電流源842啟動與關閉的時機。When the voltage of the V (COMP) signal is pulled low, the operation of the oscillator 840 is forcibly turned off, or the output frequency of the oscillator 840 is modulated in response to the potential of the V (COMP) signal, for example, V (COMP) When the potential of the signal is high, the output frequency becomes high, and the potential of the V(COMP) signal is low, the output frequency becomes low, or the reverse operation, so the potential of the V(COMP) signal can affect the power consumption of the power conversion controller 800. And the control comparator 820 compares the positive terminal voltage with the feedback reference voltage Voff, and the low level output is output to the feedback control signal 822, so that the output of the AND gate 870 is at a low level, and the operation of the disable voltage regulator 850 is turned off. The internal power supply of the power conversion controller 800 causes the power conversion controller 800 to enter a very low power consumption mode, and the current I (VDDp) is instantaneously reduced to Ioff, preferably the current Ioff is less than the current 0.1*Iop, or lower, V ( The falling speed of the VDDP) potential becomes very slow, that is, the slope of the V(VDDP) potential decreases, and by controlling the V(COMP) signal, the time for charging the external capacitor next time can be greatly lengthened, and the entire system is lowered. Power consumption; It is noted that pulling the V(COMP) signal low can cause the low level output to be output to the feedback control signal 822 via the inverter 896 and the OR gate 892 to force the current source 842 to be turned off, terminating the HV pin to draw current from the outside because the hysteresis is compared at this time. The output of 830 is at a high level and the operation of current source 842 has been turned off. That is, the simple control circuit 890 includes the OR gate 892 and the inverters 894, 896 can control the timing at which the current source 842 is turned on and off in due course.
再回到第八圖中，當停止拉低V(COMP)訊號之動作，也就是當控制COMP腳位上的電壓高過回授參考電壓Voff後，回授控制訊號822位準為高，電流I(VDDp)恢復為Iop，外部大電容(未示出)再次恢復供應電源轉換控制器800之運作電力，電源轉換控制器800正常運作到V(VDDP)電壓為VDDL，此時，遲滯比較器830之正端輸入電壓到達第二遲滯參考電壓VDDL，才使得遲滯比較器830之輸出位準由高轉低，使得及閘870之輸出為低，及閘872之輸出為低，DRV腳位之輸出轉為低位準。Returning to the eighth figure, when the operation of pulling down the V (COMP) signal is stopped, that is, when the voltage on the control COMP pin is higher than the feedback reference voltage Voff, the feedback control signal 822 is high, the current is I (VDDp) is restored to Iop, and an external large capacitor (not shown) resumes the operation power supplied to the power conversion controller 800. The power conversion controller 800 operates normally until the V (VDDP) voltage is VDDL. At this time, the hysteresis comparator The positive input voltage of 830 reaches the second hysteresis reference voltage VDDL, so that the output level of the hysteresis comparator 830 is turned from high to low, so that the output of the gate 870 is low, and the output of the gate 872 is low, and the DRV pin is The output goes to a low level.
然後，HV腳位經由電流源842對腳位VDDp外之電容(未示出)短暫充電之後，V(VDDP)電位從VDDL充電到VDDH，電流I(VDDp)開始進行放電如此循環運作。而COMP腳位可以先經過增益放大器811，例如增益1/2之增益調整，此增益調整可以依照實際電路設計而調整，進入比較器810之比較後，控制SR正反器860之R輸入端，1伏特(V)只是例示比較器810進行比較電壓的範圍，於此實施例中，比較器810將CS腳位電壓與COMP電壓與1V電壓兩個位準範圍內進行比較，熟知此技術之人士當可作出可能的電路更改變化。Then, after the HV pin is temporarily charged to the capacitor (not shown) outside the pin VDDp via the current source 842, the V(VDDP) potential is charged from VDDL to VDDH, and the current I (VDDp) starts to discharge as described above. The COMP pin can first pass through the gain amplifier 811, for example, a gain adjustment of gain 1/2. The gain adjustment can be adjusted according to the actual circuit design. After the comparison of the comparator 810, the R input terminal of the SR flip-flop 860 is controlled. 1 volt (V) is only a range in which the comparator 810 compares the voltage. In this embodiment, the comparator 810 compares the CS pin voltage with the COMP voltage and the 1 V voltage. The person skilled in the art is known. When possible circuit change changes can be made.
第十圖顯示根據本發明之一具體實施例之極低耗電之電源轉換方法流程圖，於步驟1020，導通一電流源達第一預定期間，例如充電到達電壓VDDH；於步驟1030，致能一電源轉換控制器內之電壓調節器達第二預定期間，並於第二預定期間產生驅動訊號，例如為脈波寬度調變訊號或者脈波頻率調變訊號；於步驟1040，主張(assert)回授控制訊號，例如為第八圖中之回授控制訊號822，禁能電壓調節器，使得電源轉換控制器進入一極低耗電模式，較佳地，極低耗電模式下所消耗的電流低於正常運作之電流大小之十分之一，或者更低，較佳地，主張回授控制訊號亦可強迫關閉電流源；於步驟1060，然後解除主張回授控制訊號讓電源轉換控制器恢復正常運作到達外部電容放電到電壓VDDL，也就是運作達第三預定期間，控制外部電容從電壓VDDL充電到電壓VDDH。FIG. 10 is a flow chart showing a very low power consumption power conversion method according to an embodiment of the present invention. In step 1020, a current source is turned on for a first predetermined period, for example, a charge reaching voltage VDDH; and in step 1030, a voltage regulator in the power conversion controller for a second predetermined period of time, and generating a driving signal, such as a pulse width modulation signal or a pulse frequency modulation signal, in the second predetermined period; in step 1040, asserting The feedback control signal, for example, the feedback control signal 822 in the eighth figure, disables the voltage regulator, so that the power conversion controller enters a very low power consumption mode, preferably, in a very low power consumption mode. The current is lower than one tenth of the normal operating current, or lower. Preferably, the feedback control signal is also forced to turn off the current source; in step 1060, the claim feedback control signal is then released to allow the power conversion controller Returning to normal operation until the external capacitor discharges to the voltage VDDL, that is, for the third predetermined period of operation, the external capacitor is controlled to be charged from the voltage VDDL to the voltage VDDH.
綜上所述，本發明揭示一種極低耗電電源轉換控制器，包括遲滯比較器、比較器、邏輯閘、內部電壓調節器、控制電路及電流源；遲滯比較器，具有第一遲滯參考電壓與第二遲滯參考電壓，用以產生遲滯比較輸出訊號；比較器接收外部補償訊號，與回授參考電壓比較產生回授控制訊號；邏輯閘可為及閘，用以接收遲滯比較輸出訊號以及回授控制訊號，產生電源控制訊號；內部電壓調節器耦接至及閘，根據電源控制訊號決定是否產生內部工作電壓；控制電路，包含或閘、第一反相器與第二反相器，控制電路根據遲滯比較輸出訊號與回授控制訊號控制電流源之啟動與關閉。極低耗電電源轉換控制器更包含振盪器、SR正反器、比較器，正反器耦接於振盪器與比較器之輸出，振盪器可以經由補償訊號被禁能，或者振盪器之輸出頻率可以經由補償訊號所控制；比較器比較補償(COMP)訊號與電流感測(CS)訊號以產生比較輸出；較佳地，當補償訊號被主張時，電源轉換控制器進入極低耗電模式，其耗電量低於電源轉換控制器處於操作模式下之耗電量之十分 之一。In summary, the present invention discloses a very low power consumption power conversion controller including a hysteresis comparator, a comparator, a logic gate, an internal voltage regulator, a control circuit, and a current source; a hysteresis comparator having a first hysteresis reference voltage And the second hysteresis reference voltage is used to generate a hysteresis comparison output signal; the comparator receives the external compensation signal, and generates a feedback control signal compared with the feedback reference voltage; the logic gate can be a gate and is used to receive the hysteresis comparison output signal and back The control signal is generated to generate a power control signal; the internal voltage regulator is coupled to the AND gate, and the internal working voltage is determined according to the power control signal; the control circuit includes a gate, a first inverter and a second inverter, and is controlled The circuit controls the start and stop of the current source according to the hysteresis comparison output signal and the feedback control signal. The extremely low power consumption power conversion controller further includes an oscillator, an SR flip-flop, and a comparator. The flip-flop is coupled to the output of the oscillator and the comparator, and the oscillator can be disabled through the compensation signal, or the output of the oscillator. The frequency can be controlled by the compensation signal; the comparator compares the compensation (COMP) signal with the current sensing (CS) signal to generate a comparison output; preferably, when the compensation signal is asserted, the power conversion controller enters a very low power consumption mode , its power consumption is lower than the power consumption of the power conversion controller in the operating mode one.
本發明更揭示一種極低耗電電源控制方法，包括：導通電流源達第一預定期間，可以根據該回授控制訊號與一遲滯比較輸出訊號控制該電流源之開啟與關閉；致能電源轉換控制器內之電壓調節器達一第二預定期間，並於該第二預定期間產生驅動訊號，例如脈波寬度調變訊號或者脈波頻率調變訊號；主張回授控制訊號上使得電源轉換控制器進入極低耗電模式，例如禁能電源轉換控制器內之電壓調節器與振盪器，使得電源轉換控制器之耗電量低於電源轉換控制器處於操作模式下之耗電量之十分之一；以及解除主張回授控制訊號以使電源轉換控制器恢復成正常運作達第三預定期間。The invention further discloses a method for controlling a very low power consumption power supply, comprising: turning on a current source for a first predetermined period, and controlling the opening and closing of the current source according to the feedback control signal and a hysteresis comparison output signal; enabling power conversion The voltage regulator in the controller reaches a second predetermined period, and generates a driving signal, such as a pulse width modulation signal or a pulse frequency modulation signal, during the second predetermined period; and asserts a feedback control signal to enable power conversion control The device enters a very low power consumption mode, such as a voltage regulator and an oscillator in the disable power conversion controller, so that the power consumption of the power conversion controller is lower than the power consumption of the power conversion controller in the operation mode. And releasing the claim feedback control signal to restore the power conversion controller to normal operation for a third predetermined period.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種更動與潤飾，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. The scope of the present invention is defined by the scope of the appended claims, unless otherwise claimed.
100．．．顯示電路方塊圖100. . . Display circuit block diagram
112．．．交流電源112. . . AC power
110．．．電源電路110. . . Power circuit
114、116．．．電壓訊號114, 116. . . Voltage signal
120．．．縮放控制器120. . . Zoom controller
130．．．背光模組130. . . Backlight module
300、400、500．．．顯示控制電路300, 400, 500. . . Display control circuit
302．．．交流電源302. . . AC power
310．．．整流器310. . . Rectifier
320、420．．．偏壓電路320, 420. . . Bias circuit
330、530．．．變壓器330, 530. . . transformer
340、540、800．．．電源轉換控制器340, 540, 800. . . Power conversion controller
342、542、842．．．電流源342, 542, 842. . . Battery
350、550．．．穩壓器350, 550. . . Stabilizer
360．．．縮放控制器360. . . Zoom controller
370、570．．．光耦合元件370, 570. . . Optical coupling element
560．．．顯示控制器560. . . Display controller
810、820．．．比較器810, 820. . . Comparators
830．．．遲滯比較器830. . . Hysteresis comparator
812、822、852．．．訊號812, 822, 852. . . Signal
811．．．增益放大器811. . . Gain amplifier
840．．．振盪器840. . . Oscillator
850．．．電壓調節器850. . . Voltage Regulator
860．．．正反器860. . . Positive and negative
870、872．．．及閘870, 872. . . Gate
880．．．緩衝器880. . . buffer
890．．．控制電路890. . . Control circuit
892．．．或閘892. . . Gate
894、896．．．反相器894, 896. . . inverter
F1．．．熔絲F1. . . Fuse
A、B．．．節點A, B. . . node
NTC．．．電阻NTC. . . resistance
VDDP、VCC14V、VDD3V3、VCC5Vsense、COMP、HV、AC_OFF、DRV．．．訊號VDDP, VCC14V, VDD3V3, VCC5Vsense, COMP, HV, AC_OFF, DRV. . . Signal
R11、R12、R13、R2、R4、R5、R6、R72、R80、R82．．．電阻R11, R12, R13, R2, R4, R5, R6, R72, R80, R82. . . resistance
D1、D21、D22、D3、D4、D5、D80．．．二極體D1, D21, D22, D3, D4, D5, D80. . . Dipole
Q1、Q2、Q3、Q4、Q8．．．電晶體Q1, Q2, Q3, Q4, Q8. . . Transistor
C1、C2、C3、C4．．．電容C1, C2, C3, C4. . . capacitance
本案得藉由下列圖式及說明，俾得一更深入之了解：第一圖顯示習知技藝之顯示器內部的顯示電路方塊圖。In this case, a more in-depth understanding can be obtained from the following figures and descriptions: The first figure shows a block diagram of the display circuit inside the display of the conventional art.
第二圖顯示根據本發明具體實施例之極低耗電顯示控制電路。The second figure shows a very low power consumption display control circuit in accordance with an embodiment of the present invention.
第三圖顯示相關於第二圖實施例之主要波形圖。The third diagram shows the main waveform diagram associated with the second embodiment.
第四圖顯示根據本發明另一具體實施例之極低耗電顯示控制電路。The fourth figure shows a very low power consumption display control circuit in accordance with another embodiment of the present invention.
第五圖顯示根據本發明另一具體實施例之極低耗電顯示控制電路。The fifth figure shows a very low power consumption display control circuit in accordance with another embodiment of the present invention.
第六圖顯示根據本發明另一具體實施例之極低耗電顯示控制電路。The sixth figure shows a very low power consumption display control circuit in accordance with another embodiment of the present invention.
第七圖顯示根據本發明之具體實施例之極低耗電顯示控制方法之流程圖。The seventh figure shows a flow chart of a very low power consumption display control method in accordance with an embodiment of the present invention.
第八圖顯示根據本發明之一具體實施例之極低耗電電源轉換控制器。The eighth figure shows a very low power consumption power conversion controller in accordance with an embodiment of the present invention.
第九圖顯示第八圖中極低耗電電源轉換控制運作之主要訊號波形圖。The ninth figure shows the main signal waveform diagram of the extremely low power consumption power conversion control operation in the eighth figure.
第十圖顯示根據本發明之一具體實施例之極低耗電之電源轉換方法流程圖。The tenth diagram shows a flow chart of a very low power consumption power conversion method in accordance with an embodiment of the present invention.
800．．．電源轉換控制器800. . . Power conversion controller
810、820．．．比較器810, 820. . . Comparators
830．．．遲滯比較器830. . . Hysteresis comparator
812、822、852．．．訊號812, 822, 852. . . Signal
811．．．增益放大器811. . . Gain amplifier
840．．．振盪器840. . . Oscillator
850．．．電壓調節器850. . . Voltage Regulator
860．．．正反器860. . . Positive and negative
870、872．．．及閘870, 872. . . Gate
880．．．緩衝器880. . . buffer
890．．．控制電路890. . . Control circuit
892．．．或閘892. . . Gate
894、896．．．反相器894, 896. . . inverter
842．．．電流源842. . . Battery
Claims (18)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097146361A TWI422133B (en) | 2008-11-28 | 2008-11-28 | An ultra-low power conversion controller and associated method |
| KR1020090032638A KR20100061286A (en) | 2008-11-28 | 2009-04-15 | An ultra-low power conversion controller and associated method |
| US12/556,702 US8654113B2 (en) | 2008-09-19 | 2009-09-10 | Ultra-low-power display control circuit and associated method |
| EP09011950.4A EP2175550B1 (en) | 2008-09-19 | 2009-09-18 | Ultra-low-power power conversion controller and associated method |
| EP09011952A EP2166822A3 (en) | 2008-09-19 | 2009-09-18 | Ultra-low-power display control circuit and associated method |
| EP09011951.2A EP2166821B1 (en) | 2008-09-19 | 2009-09-18 | Ultra-low-power display control circuit and associated method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097146361A TWI422133B (en) | 2008-11-28 | 2008-11-28 | An ultra-low power conversion controller and associated method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201021393A TW201021393A (en) | 2010-06-01 |
| TWI422133B true TWI422133B (en) | 2014-01-01 |
Family
ID=42362083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097146361A TWI422133B (en) | 2008-09-19 | 2008-11-28 | An ultra-low power conversion controller and associated method |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20100061286A (en) |
| TW (1) | TWI422133B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101300741B1 (en) * | 2011-06-27 | 2013-08-28 | 인하대학교 산학협력단 | Cmos linear regulation and method for operating the same |
| CN110070815B (en) * | 2018-01-22 | 2022-08-12 | 矽创电子股份有限公司 | Reference voltage generator for display device |
| CN116191631B (en) * | 2023-01-31 | 2023-09-29 | 深圳市凌鑫电子有限公司 | Low-cost power supply charging circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| US20030076316A1 (en) * | 2001-10-20 | 2003-04-24 | Samsung Electronics Co., Ltd. | Display apparatus with power supply having a power saving mode |
| US20040042239A1 (en) * | 2002-08-28 | 2004-03-04 | Saburou Kitano | Switching power supply apparatus |
| US20050162874A1 (en) * | 2003-03-28 | 2005-07-28 | Sony Corporation | Switching power supply apparatus |
| US20060067091A1 (en) * | 2004-09-27 | 2006-03-30 | Sanyo Electric Co., Ltd. | Switching power supply |
| US20080175026A1 (en) * | 2007-01-19 | 2008-07-24 | System General Corp. | Control circuit having an impedance modulation controlling power converter for saving power |
| US20090300400A1 (en) * | 2008-05-29 | 2009-12-03 | Igo, Inc. | Primary side control circuit and method for ultra-low idle power operation |
-
2008
- 2008-11-28 TW TW097146361A patent/TWI422133B/en active
-
2009
- 2009-04-15 KR KR1020090032638A patent/KR20100061286A/en not_active Application Discontinuation
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| US20030076316A1 (en) * | 2001-10-20 | 2003-04-24 | Samsung Electronics Co., Ltd. | Display apparatus with power supply having a power saving mode |
| US20040042239A1 (en) * | 2002-08-28 | 2004-03-04 | Saburou Kitano | Switching power supply apparatus |
| US20050162874A1 (en) * | 2003-03-28 | 2005-07-28 | Sony Corporation | Switching power supply apparatus |
| US20060067091A1 (en) * | 2004-09-27 | 2006-03-30 | Sanyo Electric Co., Ltd. | Switching power supply |
| US20080175026A1 (en) * | 2007-01-19 | 2008-07-24 | System General Corp. | Control circuit having an impedance modulation controlling power converter for saving power |
| US20090300400A1 (en) * | 2008-05-29 | 2009-12-03 | Igo, Inc. | Primary side control circuit and method for ultra-low idle power operation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20100061286A (en) | 2010-06-07 |
| TW201021393A (en) | 2010-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI455087B (en) | Low power display control method and associated display controller | |
| US8654113B2 (en) | Ultra-low-power display control circuit and associated method | |
| TWI398764B (en) | Apparatus and method for reducing the standby power consumption of a display, and display with low standby power consumption | |
| US9553511B2 (en) | Method of forming a switched mode power supply controller device with an off mode and structure therefor | |
| US8559200B2 (en) | Method and apparatus of low current startup circuit for switching mode power supplies | |
| JP5488274B2 (en) | Semiconductor integrated circuit and switching power supply device | |
| TWI390818B (en) | Apparatus and method for improving the standby efficiency of a charger, and ultra low standby power charge | |
| US20060245220A1 (en) | DC-AC converter and controller IC therefor | |
| CN112803773B (en) | Control method of PSR flyback switching power supply, secondary side controller device and switching power supply | |
| US20090167259A1 (en) | Dc-dc converter, dc-dc converter control method, and electronic device | |
| US10447145B1 (en) | SMPS power-on with energy saver | |
| WO2010125751A1 (en) | Switching power supply device | |
| TWI505613B (en) | Start-up supply, system comprising the start-up supply, and method for operating the start-up supply | |
| US8830706B2 (en) | Soft-start circuit | |
| TW201109908A (en) | Power management integrated circuit and power management method | |
| US20110149612A1 (en) | Control Method and Controller with constant output current control | |
| TWI422133B (en) | An ultra-low power conversion controller and associated method | |
| TWI422134B (en) | Ultra-low power display control circuit and associated method | |
| US20080031028A1 (en) | DC-AC Converter and Controller IC Thereof | |
| CN101989406B (en) | Display control circuit with extremely low power consumption and related method thereof | |
| US10700595B2 (en) | Controller for extending a protection period of a power converter and operational method thereof | |
| TWI415050B (en) | Ultra-low power display control circuit and associated methed | |
| CN101753031B (en) | Power conversion controller with very low power consumption and related method | |
| CN113839455B (en) | Charging device for supporting power transmission | |
| TW202406281A (en) | Boost switching power supply and boost controller thereof |