TWI422013B - 具有一個或多個非定值摻雜濃度分佈的相變化記憶體 - Google Patents
具有一個或多個非定值摻雜濃度分佈的相變化記憶體 Download PDFInfo
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- TWI422013B TWI422013B TW099120696A TW99120696A TWI422013B TW I422013 B TWI422013 B TW I422013B TW 099120696 A TW099120696 A TW 099120696A TW 99120696 A TW99120696 A TW 99120696A TW I422013 B TWI422013 B TW I422013B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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Description
本發明係關於以包含硫屬化物之相變化材料為基礎的記憶體裝置,以及用於製造此裝置的方法。
以相變化為基礎的材料,例如以硫屬化物為基礎的材料或相似的材料,可以使用於積體電路中所提供適當大小的電流,來引發在非晶相與結晶相之間的相變化。非晶相通常的特徵是具有比結晶相更高的電阻,其可以很容易地被感應以指示資料。此特性已引起廣泛的注意,尤其是對於使用可程式化電阻材料以形成非揮發式記憶體電路,其可利用隨機存取方式來讀取及寫入。
由非晶相至結晶相的改變通常是使用較小電流的操作。由結晶相至非晶相的改變,在此稱為重置,通常是使用較高電流的操作,其包含一個短且高電流密度脈衝以熔化或打斷此晶相結構,在此相變化材料快速的冷卻之後,退火此熔化的相變化材料且允許至少一部份的相變化材料穩定至非晶相。
重置操作所需的電流密度可由降低在記憶胞內相變化材料元件的大小及/或在電極及相變化材料之間的接觸面積,故而使用較小電極接觸面積可以有較高的電流密度穿過此相變化材料。
相變化裝置所引起的一個問題是資料保持能力。相變化記憶體會因為電阻隨著時間偏移而產生問題,此時主動區域的組成會因為此裝置所曝露的環境因素由非晶相轉變為結晶相。舉例而言,一記憶胞的主動區域被重置至大致為非晶態或許在一段時間之後會在主動區域中發展出結晶區域的分佈。假如這些結晶區域連接在一起而在主動區域中形成一低電阻路徑的話,當此記憶胞被讀取時就會偵測到一低電阻狀態而產生資料錯誤。可參見Gleixner的論文"Phase Change Memory Reliability",22nd NVSMW,2007。
相變化記憶胞所引起的另一個問題是由非晶態與結晶態之間的材料密度差異所引發的問題。如此體積的改變是因為非晶態至結晶態轉變導致相變化材料中及與電極介面之間的應力所產生。於操作時,重複之設置與重置操作導致相變化材料中空洞的產生,其會造成裝置失效且限制記憶胞的循環承受力。此外,於製造時,高溫的後段製程可以導致先前沈積之非晶態轉變為高密度的結晶態,其也可以產生導致裝置失效的空洞。
硫屬化物及其他的相變化材料可以與添加物結合以改善導電性、轉換溫度、熔化溫度及其他材料特性。與添加物結合的相變化材料通常稱為"摻入雜質"或是"添加摻雜物"。這些名詞"添加物"、"雜質"或是"摻雜物"可以於此說明書中交互的使用。硫屬化物中所使用的代表性添加物包括氮、矽、氧、氧化矽、氮化矽、銅、銀、金、鋁、氧化鋁、鉭、氧化鉭、氮化鉭、鈦及氧化鈦。舉例而言,可參閱美國專利第6800504號(摻雜金屬)及美國專利申請公開第2005/0029502號(摻雜氮)。已有許多研究進行以藉由調整相變化材料中的摻雜濃度提供可以在低電流操作之記憶裝置。
Ovshinsky等人的美國專利第6087674號及其母案第5825046號描述形成複合記憶材料的方法,其中相變化材料與相對高濃度的介電材料混合以管理此複合記憶材料的電阻值。這些專利中所描述的複合記憶材料之本質為何並不清楚,但是其描述可以利用多層結構或是混合結構的方式進行複合。這些專利中所描述的介電材料包含一個廣泛的範圍。
許多研究已對於使用氧化矽摻雜的硫屬化物展開以減少記憶裝置操作時所需的重置電流。可參閱Ryu等人的論文"SiO2 Incorporation Effects in Ge2Sb2Te5 Films Prepared by Magnetron Sputtering for Phase Change Random Access Memory Device",Electrochemical and Solid-State Letters,9(8) G259~G261(2006);Lee等人的論文"Separate domain doemation in Ge2Sb2Te5-SiO2 mixed layer",Appl. Phys. Lett. 89,163503(2006);Czubatyj等人的論文"Current Reduction in Ovonic Memory Device",E*PCOS06(2006);以及Noh等人的論文"Modification of Ge2Sb2Te5 by the Addition of SiOx for Improved Operation of Phase Change Random Access Memory Device",Mater. Res. Soc.Symp.Proc. Vol. 888(2006)。這些參考資料建議相對低濃度的氧化矽摻雜於Ge2Sb2Te5(GST)中導致電阻的顯著增加及重置電流的對應降低。Czubatyj等人的論文建議摻雜約10%體積百分比(6.7%原子數百分比)氧化矽的GST合金結構可以改善其電阻,且報導對於最高達30%體積百分比氧化矽摻雜進行測試,但是並沒有提供其細節。Lee等人的論文則描述約為8.4%原子數百分比之相對高摻雜濃度的一種現象,其中在高溫退火之後氧化矽似乎會自GST中分離,以形成GST區域在邊界主要由氧化矽所包圍。摻雜氧化矽也會導致此材料結晶相中的粒子大小降低,且改善其可製造性。
Hudgens的美國專利申請公開第2005/0029502號描述一種複合的摻雜GST,其中宣稱氮或氮及氧會導致粒子大小降低,而第二摻雜物如鈦,以可增加設置程式化速度的方式施加。在Hudgens專利申請案中的第二摻雜物施加係用來抵消由摻雜氮所增加的設置程式化時間。然而,發現到如氮或氧之氣相摻雜物雖然可以降低沈積材料中之粒子大小,但是並不可靠,且會在使用時於材料中生成空洞。
Chen等人的於2009年3月10日發證的美國專利第7501648號"PHASE CHANGE METERIAL AND ASSOCIATED MEMORY DEVICES"中描述使用氮化合物摻雜的相變化材料會影響其轉變速度。
本案發明人的另一於2008年10月2日申請之美國專利申請第12/286874號"DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY"中描述使用相對高濃度的氧化矽摻雜,及提出與上述改變相變化記憶材料成分相關的一些問題。
雖然使用添加物可以大幅地改善良率,但是會造成資料保持及可靠性等問題。此外,與未摻雜的相變化材料相較,使用添加物會對許多記憶體性能產生不良的影響,例如設置程式化速度及臨界電壓等,因而限制了相變化為基礎的記憶電路無法在某些應用中的使用。
因此,最好是能提供一種記憶胞,其能夠解決上述良率、資料保持及可靠性等問題。
本發明描述一個相變化記憶裝置,其包含一具有例如是硫屬化物GST之相變化材料主體及一個或多個添加物的記憶元件,其中添加物具有一沿著通過記憶元件之電極間電流路徑的非定值添加濃度分佈。此裝置包括一第一電極、一相變化記憶元件與該第一電極連接、及一第二電極與相變化記憶元件連接。此記憶元件具有一相變化材料主體,其具有不同的區域特性,在裝置操作時具有極不同的熱性、電性和相轉變等特性。一第一區域鄰接該第一電極、一第二區域包圍該主動區域、一第三區域介於該主動區域與該第二電極之間及一第四區域鄰接該第二電極。此處之名詞"非定值"添加物濃度分佈的使用可以根據不同的應力性、熱性和電性,以及相轉變等條件而在不同區域中摻雜不同的材料或濃度。
在此處所描述的一實施例中,該相變化記憶材料包含一基礎相變化記憶材料具有一第一添加物濃度分佈在鄰接該第一電極的一第一層及一第二添加物濃度分佈在鄰接該第二電極的一第二層。該相變化記憶材料的該主動區域於該第一層內。該第一添加物濃度分佈是用於改善該較低電阻相的電阻值穩定性,且該第二添加物濃度分佈是用於改善該記憶胞的循環承受力。在一範例中,該基礎相變化記憶材料是鍺銻碲(GST),該第一層中的添加物是矽,而在該第一層及第二層中的另一添加物是氧化矽。如此提供記憶胞在多次設置/重置循環中於低電阻狀態的改善阻抗穩定性,同時又可以避免空洞的形成。此外,在第二層中沒有矽摻雜的存在減少記憶胞整體的電阻值。
本發明係揭露一種積體電路記憶體裝置其係以具有非定值添加物濃度分佈的相變化記憶裝置為基礎。
本發明其它的目的及優點係見於以下圖示、實施方式及申請專利範圍所述。
本發明以下的實施例描述係搭配第1到11圖進行說明。
第1圖為一個概要圖示,其描述一個記憶胞100之一部份的剖面圖,其包含一具有相變化材料主體的記憶元件116,相變化材料主體包括一沿著通過記憶元件116之電極間電流路徑的非定值添加濃度分佈。如同之前所描述的,非定值添加濃度分佈包含一第一添加濃度分佈於主動區域110中及一第二添加濃度分佈於主動區域110外的非主動區域113中。
此記憶胞100包括一第一電極120延伸穿透介電層130以接觸記憶元件116的底表面,及一第二電極140於記憶元件116之上。此第一及第二電極120、140,可以包含舉例而言,氮化鈦或氮化鉭。替代地,此第一及第二電極120、140,每一個可以包含鎢、氮化鎢、氮化鈦鋁、或是氮化鉭鋁,或是包含,對進一步的範例而言,一個或多個元素選自下列群組摻雜-Si、Si、C、Ge、Cr、Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O以及Ru及其組合。
如第1圖中所示,第一電極120相對窄的寬度122(在某些實施例中為直徑)導致此第一電極與記憶元件的接觸區域係小於記憶元件116與頂電極140的接觸區域。因此電流係集中於記憶元件116靠近第一電極120的部分,導致主動區域110是靠近或是與第一電極120接觸,如圖中所示。此記憶元件116也包括一非主動區域113於主動區域110之外,其所謂的非主動是指在操作時不會進行相變化。此記憶元件包括一基礎相變化材料,其可以被特徵為具有四個區間。區間1是相變化材料與第一電極120之界面、區間2是包圍記憶元件主動區域的一層、區間3是介於主動區域與第二電極140界面的一層而區間4是與第二電極140之界面。區間1~4可以在此裝置的製造及操作時具有極不同的熱性、電性、結晶性和應力性。每一個區間因此可以作為基礎相變化材料不同添加物的候選人以增進其效能。根據此記憶胞的結構及相變化材料中主動區域的位置,此介面區間1和4可以包括主動區域的一部份。此外,對一遠離電極的主動區域,可以在主動區域與各自的第一和第二電極之間具有兩個中間區間。
記憶元件116的基礎相變化材料在此範例中為Ge2
Sb2
Te5
。這些基礎材料可以定義為選取作為相變化材料的元素組合,且沈積具有定義該材料特性的濃度分佈。因為添加物是組合的,基礎材料中的相對元素濃度並不會改變。而是,在此範例中基礎相變化材料摻雜之添加物是沿著底電極120與頂電極140之間的電極間路徑之具有非定值濃度分佈的氧化矽,如第2圖中所示。在此非定值濃度分佈中,氧化矽中矽與氧成分的整體濃度在區間1和區間2是約為15%原子數百分比,且在區間3的非主動區域中濃度下降,而在區間4靠近第二電極140處更下降至接近0%。也可以使用其他硫屬化物或是添加物。
舉例而言,其他的基礎相變化材料可以包括Gex
Sb2y
Tex+3y
,其中x和y是整數(包括0)。也可以使用GeSbTe為基礎以外的其他的基礎相變化材料,包括Gax
Sb2y
Tex+3y
,其中x和y是整數。替代地,此基礎相變化材料可以選自包括Agx
Iny
Sb2
Te3
,其中x和y是小於1的分數。
第2圖顯示使用氧化矽作為添加物之一非定值添加物濃度分佈的第一實施例。如第2圖中所示,氧化矽的濃度在底電極120與記憶元件116界面處較頂電極140與記憶元件116界面處為高。在第2圖的所示範例中,相變化材料的添加物在底電極120與記憶元件116界面處具有矽濃度約5±2%原子數百分比,氧濃度約10±4%原子數百分比。而氧化矽的濃度隨後向下轉變至在與頂電極界面處的大致未摻雜的GST,導致圖中所示的非定值添加物濃度分佈。
主動區域110包含相變化材料結晶相區域與富含介電質網狀結構(未示),係由氧化矽摻雜自相變化合金分離所導致,細節可參閱美國專利申請第12/286874號,名稱為"DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY",在此作為參考資料。
在此記憶胞100的重置操作,偏壓電路(可參閱,例如第10圖中的具有控制器撘配1034的偏壓電路之電壓及電流源1036)與第一及第二電極120、140耦接以誘發電流經由記憶元件116通過第一與第二電極120、140之間足以誘發一通常為高電阻的非晶相於主動區域的相變化區域中以在此記憶胞100建立高電阻重置狀態。
GST為基礎的記憶材料通常包含兩個結晶相,一較低轉換溫度的面心立方(FCC)相及一較高轉換溫度的六方最密堆積(HCP)相,此六方最密堆積(HCP)相的密度高於面心立方(FCC)相。在通常情況下,並不希望發生自面心立方(FCC)相至六方最密堆積(HCP)相的轉換,因為記憶材料體積的減少會導致記憶材料內及電極與記憶材料界面間的應力。未摻雜的Ge2
Sb2
Te5
,其自面心立方(FCC)相至六方最密堆積(HCP)相的轉換是發生在低於退火溫度400℃以下。因為包含未摻雜的Ge2
Sb2
Te5
之記憶胞在設置操作時或許會經歷大於400℃的溫度,轉換至六方最密堆積(HCP)相或許會對記憶胞產生一些可靠性問題。此外,轉換至六方最密堆積(HCP)相的速度也會較慢。
於一記憶胞的壽命期間,如此的體積變化會於主動區域內產生空洞,因而造成裝置的失效。
曾發現Ge2
Sb2
Te5
若含有10%~20%原子數百分比的氧化矽,可以在高達400℃的退火溫度時仍保持面心立方(FCC)相。更進一步而言,具有10%~20%原子數百分比的氧化矽摻雜之Ge2
Sb2
Te5
與未摻雜的Ge2
Sb2
Te5
比較,具有較小的結晶尺寸。其結果是,包含10%~20%原子數百分比的氧化矽摻雜之Ge2
Sb2
Te5
的記憶胞在後段製程或是設置操作時可以在高達400℃的溫度退火以避免高密度六方最密堆積(HCP)相,且與未摻雜的Ge2
Sb2
Te5
比較,因此經歷較少的應力和具有增加的可靠性及較高切換速度。
一相變化材料的結構會傾向在裝置主動區域內改變,而不是在主動區域外,因為在其內部具有較劇烈熱條件,因此材料會根據熱環境遷移至較穩定的狀態。藉由將第一添加物濃度分佈摻雜於主動區域內,其藉由抑制空洞遷移傾向強化此相變化材料,此記憶裝置的良率、耐力及保持力會顯著地改善。
第3圖顯示使用氧化矽和矽的組合作為添加物之一非定值添加物濃度分佈的第二實施例。如第3圖所示的範例中,相變化材料的添加物在底電極120與記憶元件116界面處具有矽濃度約5±2%原子數百分比,氧濃度約10±4%原子數百分比。在此範例中,除了原本氧化矽中的矽組成之外,矽添加物的最大濃度約1~5%原子數百分比之間。
因此,此材料組合後的元素矽和氧以及GST基底的濃度分佈包括10%原子數百分比矽、10%原子數百分比氧和80%原子數百分比的GST元素。可以發現矽添加物改善了保持時間及承受力,但是會傷害設置時間。將較高濃度的矽加入主動區域110中可以改善主動區域的保持能力,而不會嚴重地影響遠離主動區域的保持力。此外,降地遠離主動區域之區域的矽摻雜濃度可以降低記憶胞的整體電阻值,且改善此技術微縮至更低操作電壓時的穩定性。
第4圖顯示使用氧化矽和銀的組合作為添加物之一非定值添加物濃度分佈的第三實施例。如第4圖所示的範例中,相變化材料的添加物在底電極120與記憶元件116界面處具有矽濃度約5±2%原子數百分比,氧濃度約10±4%原子數百分比。發現銀添加物改善了保持時間,但是會使得記憶胞的臨界電壓變得太高而無法實際應用在晶片上。改變銀的非定值添加物濃度分佈或許可以降低臨界電壓至一現實可用之值而仍能為記憶胞提供好的保持力。
第5圖顯示使用氧化矽和氮化矽的組合作為添加物之一非定值添加物濃度分佈的第四實施例。如第5圖所示的範例中,相變化材料的氧化矽添加物在底電極120與記憶元件116界面處具有矽濃度約5±2%原子數百分比,氧濃度約10±4%原子數百分比。在此範例中,氮化矽添加物的最大濃度中的矽組成約5±2%原子數百分比,而氮組成約8.3±3.3%原子數百分比。發現摻雜氮化矽的GST具有較摻雜氧化矽的GST更佳的保持時間,但是此裝置會較摻雜氧化矽的GST更早失效。第5圖的實施例中可以較在整個主動區域摻雜定量氮化矽時提供更佳的承受力和保持時間,藉由在鄰近第一和第二電極的界面區域摻雜氧化矽,在主動區域中摻雜氮化矽而沒有大量氧化矽分佈於此主動區域中。此外在此範例中介於氮化矽摻雜區域與頂電極界面的大塊區域是僅摻雜氧化矽。
其他的添加物也可以使用於此非定值添加物濃度分佈中。舉例而言,也可以使用InGeTe中的In添加於GST基礎的相變化材料中提供較高溫度保持。也發現Ge可以和矽類似的方式改善保持能力。
第6圖顯示具有此處所描述之非定值添加物濃度分佈的記憶胞之製造流程圖,此記憶胞具有與第1圖類似的結構。故使用與第1圖元件相同的參考標號。
在步驟600,形成具有寬度或直徑122的第一電極120延伸穿過介電層130。在此例示實施例中,第一電極120包含氮化鈦而介電層130包含氮化矽。在其他的實施例中,第一電極120具有採用次微影技術產生的寬度或直徑122。
第一電極120延伸穿過介電層130至底層的存取電路(未示)。此底層的存取電路可以使用業界所熟知的製程形成,且存取電路元件的組態係取決於此處所描述之記憶胞實際應用的記憶陣列之組態。通常而言,存取電路可以包括例如是電晶體和二極體之存取裝置、字元線和源極線、導電栓塞、及摻雜區域於一半導體基板內。
此第一電極120及介電層130可以由舉例而言於2007年6月18日申請之美國專利申請第11/764678號(現為公開號2008/0191187)的”Method for Manufacturing a Phase Change Memory Device with Pillar Bottom Electrode”所揭露的方法、製程及材料形成,在此引為參考資料。舉例而言,一電極材料層可以形成於存取電路(未示)的上表面,之後再使用標準微影製程圖案化一層光阻於電極層之上以形成一光阻幕罩於第一電極120位置之上。之後光阻幕罩,舉例而言使用氧氣電漿進行圖案化,以形成具有次微影尺寸的幕罩結構於第一電極120位置之上。之後,此電極材料層使用圖案化後的光阻幕罩結構進行蝕刻,因此形成具有次微影直徑122的第一電極120。最後形成介電層130及進行平坦化。
此第一電極120及介電層130可以由另一範例於2007年9月14日申請之美國專利申請第11/855979號(現為公開號2009/0072215)的”Phase Change Memory Cell in Via Array with Self-Aligned,Self-Converged Bottom Electrode and Method for Manufacturing”所揭露的方法、製程及材料形成,在此引為參考資料。舉例而言,介電層130可以形成於存取電路(未示)的上表面,之後再形成一隔離層和犧牲層。之後,具有開口接近於製程最小特徵尺寸的幕罩被形成以產生幕罩於犧牲層之上,開口係位於第一電極120位置上方。使用此幕罩選擇性地蝕刻隔離層和犧牲層,因此形成一介層孔於隔離層和犧牲層之中且裸露出介電層130的上表面。於移除幕罩之後,於介層孔中進行一選擇性地側削蝕刻使得隔離層被蝕刻而保留犧牲層和介電層130。然後在介層孔中形成一填充材料,因為選擇性地側削蝕刻製程的緣故,導致自動對準之空洞的填充材料形成在介層孔中。之後,在此填充材料進行非均向蝕刻以開啟此空洞,且繼續蝕刻直到低於空洞的填充材料被裸露出來為止,因此形成填充材料的側壁間隔物在介層孔中。此側壁間隔物具有一開口尺寸大致由空洞的尺寸所決定,且因此可以小於製程最小特徵尺寸。之後,使用側壁間隔物作為蝕刻幕罩對介電層130進行蝕刻,因此形成一具有小於製程最小特徵尺寸的開口於介電層130中。之後,一電極材料層形成於開口內的介電層130之上。進行一例如是化學機械研磨的平坦化製程以除去隔離層和犧牲層而形成此第一電極120。
在步驟610形成一相變化元件,包含一基礎的相變化材料Ge2
Sb2
Te5
具有非定值添加物濃度分佈。
非定值添加物濃度分佈可以使用多種技術形成。舉例而言,將基礎GST材料共同濺鍍而成,是在相同的反應室中使用不同的濺鍍槍而具有添加物,且藉由開啟或關閉各自的摻雜濺鍍槍來調整添加物濃度分佈。在另一範例中,藉由在一反應室中使用單一的摻雜GST濺鍍槍,然後移至另一反應室中使用其他的摻雜/未摻雜GST濺鍍槍等等。在另一範例中,藉由在一反應室中使用單一的未摻雜GST濺鍍槍,然後移至另一反應室中使用單一的摻雜GST濺鍍槍,然後再移至第三反應室中使用另一的摻雜GST濺鍍槍等等。替代地,此記憶材料可以使用複合靶材進行濺鍍。此外,也可以使用其他的沈積技術,包括化學氣相沈積、原子層沈積等等。
之後,在步驟620形成一第二電極,且在步驟630進行後段製程以完成此晶片的半導體製程步驟,導致如第1圖所示的結構。此後段製程可以使用業界所熟知的標準製程形成,且所進行的製程係取決於此處所描述之記憶胞實際應用的記憶陣列之組態。通常而言,由此後段製程所形成的結構可以包括例如是接點、層間介電層及此晶片中的內連線之不同的金屬層接,其包含用以將此記憶胞與周邊電路耦接的電路。這些後段製程科以包括在升溫時沈積介電材料,例如在400℃或以上沈積氮化矽,或是在500℃或以上的高密度電漿沈積氧化矽。由於這些製程的結果,第10圖中所示的控制電路和偏壓電路形成於此裝置上。
在第1圖中的香菇狀記憶胞中,電流係在底電極集中,導致主動區域110是鄰接於底電極。因此,如第2~5圖中所示的非定值添加物濃度分佈可以抑制空洞遷移於主動區域110內。
對於對稱的結構,以下所討論之如此的橋或柱結構,此主動區域可以與電極遠離。在這種情況下,添加物濃度分佈可以是對主動區域相對稱的。舉例而言,施加第2圖中第一實施例所示的概念至橋或柱結構裝置,添加物濃度分佈(自第一電極至第二電極)可以是未摻雜GST、具有增加氧化矽添加物的GST、具有定值氧化矽添加物的GST、具有減少氧化矽添加物的GST、及未摻雜GST。因此,對香菇狀記憶胞而言,最熱的點是靠近底電極處,且添加物濃度分佈相對於最熱點而改變。對橋或柱結構記憶胞而言,此添加物濃度分佈根據主動區域的位置自香菇狀記憶胞的分佈做調整。
第7~9圖顯示具有非定值添加物濃度分佈的記憶胞的替代結構,具有包含相變化區域嵌於富含介電質網狀結構內的主動區域。描述於第1圖中的元件可以應用於第7~9圖的記憶胞中,且因此不重複詳細地描述這些材料。
第7圖為一個記憶胞700之一部份的剖面圖,其包含一具有相變化材料主體的記憶元件716,相變化材料主體包括一沿著通過記憶元件716之電極間電流路徑的非定值添加濃度分佈。此非定值添加濃度分佈包含一第一添加濃度分佈於主動區域710中及一第二添加濃度分佈於主動區域710外的非主動區域713中。此主動區域710包含相變化區域嵌於富含介電質網狀結構區域內(未示),是由氧化矽摻雜自相變化合金分離所導致,細節可參閱美國專利申請第12/286874號,名稱為"DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY",在此作為參考資料。
此記憶胞700包括一介電間隔物715分隔第一和第二電極720、740。記憶元件716延伸穿越介電間隔物715以接觸第一和第二電極720、740,因此定義出一介於第一和第二電極720、740之間的電極間電流路徑,其具有由此介電間隔物715寬度717所定義的一長度。在操作時,電流會通過第一和第二電極720、740之間且通過記憶元件716,此主動區域710會較記憶元件716的其餘部分(如非主動區域713)更快地加熱。
第8圖為一個記憶胞800之一部份的剖面圖,其包含一具有相變化材料主體的記憶元件816,相變化材料主體具有一沿著通過記憶元件816之電極間電流路徑的非定值添加濃度分佈。此非定值添加濃度分佈包含一第一添加濃度分佈於主動區域810中及一第二添加濃度分佈於主動區域810外的非主動區域813中。此主動區域810包含相變化區域嵌於富含介電質的網狀結構區域內(未示),是由氧化矽摻雜自相變化合金分離所導致。
此記憶胞800包括一柱狀記憶元件816與第一和第二電極820、840分別在底表面和頂表面822、824接觸。記憶元件816具有一寬度817大致與第一和第二電極820、840相同以定義出由介電層(未示)所環繞的一多層柱狀物。此處所使用的名詞"大致"是想要用來表示製程偏差的容許值。在操作時,電流會通過第一和第二電極820、840之間且通過記憶元件816,此主動區域810會較記憶元件816的其餘部分(如非主動區域813)更快地加熱。
第9圖為一個記憶胞900之一部份的剖面圖,其包含一具有相變化材料主體的記憶元件916,相變化材料主體包括一沿著通過記憶元件916之電極間電流路徑的非定值添加濃度分佈。此非定值添加濃度分佈包含一第一添加濃度分佈於主動區域910中及一第二添加濃度分佈於主動區域910外的非主動區域913中。此主動區域910包含相變化區域嵌於富含介電質的網狀結構區域(未示),是由氧化矽摻雜自相變化合金分離所導致。
此記憶胞900包括一多孔狀記憶元件916由介電層(未示)所環繞且與第一和第二電極920、940分別在底表面和頂表面接觸。記憶元件916具有一寬度小於第一和第二電極的寬度,且在操作時,電流會通過第一和第二電極之間且通過記憶元件,此主動區域會較記憶元件的其餘部分更快地加熱。
必須理解的是,此處所描述的非定值添加濃度分佈並不侷限於此處所描述的記憶胞結構,且通常包括記憶胞具有包含相變化材料的主動區域,其中主動區域內會發生具有可偵測之電性特性的固態相之間的轉換。
第10圖係可應用本發明之積體電路1010的簡化方塊圖。此積體電路1010包括使用此處所描述之非定值添加濃度分佈記憶胞之記憶體陣列1012。一字元線解碼器及驅動器1014具有讀取、重置及設置模式,係耦接至複數條字元線1016,其間並形成電性連接,且沿著記憶體陣列1012之列方向排列。一位元線(行)解碼器1018係耦接並電性連接至複數條沿著記憶體陣列1012之行排列之複數條位元線1020,以讀取、設置和重置此陣列1012中之相變化記憶胞(未示)。位址係經由匯流排1022提供至字元線解碼器及驅動器1014和位元線解碼器1018。方塊1024中的感應電路與資料輸入結構,包括讀取、重置及設置模式的電壓及/或電流源,係透過資料匯流排1026耦接至位元線解碼器1018。資料係由積體電路1010上的輸入/輸出埠或其他內部或外部之資料來源,透過資料輸入線1028傳送至方塊1024之資料輸入結構。積體電路1010亦可包括其他電路1030,如一般用途之處理器、特定用途的應用電路或是可提供此記憶胞陣列1012所支持之系統單晶片功能之複數模組的組合。資料係由方塊1024中的感應放大器,透過資料輸出線1032,傳送至積體電路1010上的輸入/輸出埠或其他積體電路1010內或外之資料目的地。
積體電路1010中也包括此記憶胞陣列1012對於讀取、重置及設置模式之控制器1034。在此實施例中,此控制器1034係利用偏壓調整狀態機構來實施控制偏壓電路電壓及電流源1036,以施加如讀取、程式化、抹除、抹除驗證及程式化驗證等模式的電壓及/或電流至字元線及位元線。此外,熔化/冷卻循環的調整偏壓也可如同前述般應用。控制器1034可以利用技術領域中已知的特殊目的邏輯電路來實作。於其他實施方式中,控制器1034可包括一般用途之處理器以執行電腦程式來控制元件的操作,而該處理器可以實作於相同的積體電路上。於另外的實施方式中,控制器1034可利用特殊目的邏輯電路與一般用途之處理器的組合來實作。
如第11圖所示,記憶體陣列1012中的每一記憶胞包括一場效電晶體(或是其他的存取裝置例如是二極體)及一相變化記憶元件其具有主動區域110包含相變化材料區域嵌於富含介電質的網狀結構內。第11圖中顯示四個記憶胞1130、1132、1134、1136,如圖中所示每一個記憶胞具有各自的記憶元件1140、1142、1144、1146,代表陣列305中的一小區段其可以包含上百萬個記憶胞。
記憶胞1130、1132、1134、1136中每一個存取電晶體的源極與共同源極線1154耦接,此共同源極線終止於一例如是接地端點的源極線終端電路1155。在另一實施例中,存取電晶體的源極並沒有電性連接,而是可以單獨的控制。此源極線終端電路1155可以包含一偏壓電路例如電壓源或是電流源,以及解碼電路以施加調整偏壓至某些實施例接地端點以外的共同源極線1154。
複數條字元線包含字元線1156、1158平行地延伸於一第一方向且與字元線解碼器1014電性通訊。記憶胞1130和1134中存取電晶體的閘極與字元線1156耦接,記憶胞1132和1136中存取電晶體的閘極與字元線1158耦接。
複數條位元線包含位元線1160、1162平行地延伸於一第二方向且與位元線解碼器1018電性通訊。在此例示實施例中,每一個記憶元件是將對應的位元線與對應的存取電晶體的汲極耦接。替代地,記憶元件可以是將對應的位元線與對應的存取電晶體的源極耦接。
必須明白的是記憶陣列1012並不侷限於第11圖中所示的陣列組態,且其他的組態也可以替代地被使用。此外,MOS場效電晶體以外,雙極接面電晶體在某些實施例也可以用來作為存取裝置。
在操作中,陣列1012中的每一記憶胞根據對應記憶元件的電阻值來儲存資料。此資料可以由,例如比較一選取記憶胞之位元線電流與一由感應放大器1024所感應之合適的參考電流來決定。此參考電流可以被建立使得一預定之電流範圍與邏輯"0"對應,而另一不同的預定電流範圍與邏輯"1"對應。
讀取或寫入陣列1012中的一個記憶胞可以藉由施加合適的電壓至字元線1156、1158之一者且耦接位元線1160、1162之一者至一電壓以使得電流流入所選取之記憶胞來達成。舉例而言,通過所選取之記憶胞(在此範例中為1130及其對應之記憶元件為1140)的電流路徑1180係藉由施加足以開啟記憶胞1130之電晶體的電壓至位元線1160、字元線1156、源極線1154,以誘發電流自位元線1160流至源極線1154,或反之亦然,來建立此路徑1180。所施加的電壓大小及持續時間係根據所執行的操作,例如是讀取操作或是寫入操作,來決定。
在記憶胞1130的一重置(或抹除)操作時,字元線解碼器1014提供字元線1156一個合適的電壓以開啟記憶胞1130的存取電晶體。位元線解碼器1018提供位元線1160一個合適的電壓大小及持續時間以誘發電流通過記憶元件1140,此電流足以提高主動區域的溫度超過此記憶元件1140,之相變化材料的轉換溫度,且高於熔化溫度以將此主動區域置於一液態。此電流然後被終止,舉例而言,停止施加在字元線1156與位元線1160的電壓,導致相對短的冷卻時間而使主動區域很快地冷卻而穩定在大致為高電阻的非晶相,以在記憶胞1130中建立高電阻重置狀態。
此重置操作也可以包含一個或多個電壓脈衝施加至此位元線,舉例而言使用一組脈衝。
在記憶胞1130的一設置(或程式化)操作時,字元線解碼器1014提供字元線1156一個合適的電壓以開啟記憶胞1130的存取電晶體。位元線解碼器1018提供位元線1160一個合適的電壓大小及持續時間以誘發電流通過記憶元件1140,此電流足以導致主動區域的至少一部分自非晶相轉變至結晶相,此轉變降低此記憶元件1140的電阻且將此記憶胞1130設置為所預期的狀態。
在此記憶胞1130的讀取(或感應)操作時,字元線解碼器1014提供字元線1156一個合適的電壓以開啟記憶胞1130的存取電晶體。位元線解碼器1018提供位元線1160一個合適的電壓大小及持續時間以誘發電流通過記憶元件1140,此電流並不會導致記憶元件1140進行電阻態改變。通過此位元線1160及記憶胞1130的電流係根據此記憶胞的電阻,即與記憶胞相關的資料狀態而決定。因此,此記憶胞1130的資料狀態可以由舉例而言,由方塊1024中的感應放大器比較位元線1160電流與一合適的參考電流來決定。
在此處所描述實施例中是使用具有一個或多個添加物的基礎相變化材料Ge2
Sb2
Te5
。也可以使用其他添加物或是其他硫屬化物。硫屬化物係任意選自由四種元素氧(O)、硫(S)、硒(Se)及碲(Te)組成之群,形成周期表VIA族之群。硫屬化物包含硫屬與更具有正電性元件或自由基的化合物。硫屬合金包含硫屬與其它材料,例如轉換金屬,的組成。硫屬合金通常包含一個或多個選自元件週期表IVA族的元素,例如鍺或錫。通常,硫屬合金包含至少一種選自銻、鎵、銦、銀的組合物。以相變化為基礎的記憶體材料已被描述於許多技術文獻中,包含Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te,Sn/Sb/Te,In/Sb/Ge,Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te以及Te/Ge/Sb/S的合金。在Ge/Sb/Te合金的家族中,可適用的合金組成範圍相當的廣。此組成可以被定義為Tea
Geb
Sb100-(a+b)
。某一學者提出了最適用的合金係為在沉積的材料中Te的平均濃度低於70%,通常是低於60%,且範圍通常是介於23%至58%之間,最好是介於48%至58%之間。在此材料中,Ge的濃度係高於約5%且平均範圍由低至8%至30%上下的濃度,而殘蝕的材料通常小於50%。最好是,Ge的濃度大約由8%至40%。剩餘的主要組成元件為Sb。這些百分比為原子百分比,其構成100%組成元件的原子。請見Ovshinsky所提出之美國專利5687112案號第10-11欄。由其它學者所提出的合金包含Ge2
Sb2
Te5
、GeSb2
Te4
、GeSb4
Te7
。請參考Noboru Yamada於1997年在SPIE v.3109第28/37頁所提出的”Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-Rate Recording”。通常,轉換金屬,例如鉻、鐵、鎳、鈮、鈀、鉑或上述之組合可以和Ge/Sb/Te組合以形成具有可程式電阻特徵的相變化合金。適用的記憶體材料可見於Ovshinsky於11-13欄之112,其在此作為參考之範例。
以下的表1顯示可以在裝置之主動區域中發現的可能化合物,其具有之前所描述之摻雜矽和氧化矽的Ge2
Sb2
Te5
相變化材料。可以發現,Si2
Te3
相較於此表中的其他可能化合物具有較高的熔化點及重新結晶轉換溫度。因此,在主動區域中形成Si2
Te3
傾向增加主動區域中記憶材料的熔化點及重新結晶轉換溫度。如此現象相信可以穩定主動區域及抑制空洞的形成。
以下的表2顯示介於矽與不同的元素Gex
Sby
Tez
、鍺、銻、碲的鍵結能量。可以發現,矽-碲鍵結相較於碲與記憶材料中其他成份的鍵結而言是較強的。因為是一較強鍵結的結果,可以改善記憶體的承受力及資料保持特性。
如同以上所描述的,許多穩定的材料,例如是介電材料,包括氧化鋁、碳化矽和氮化矽等具有高混合熱可以被用作為添加物以降低顆粒大小及分離顆粒邊界而限制空洞在相變化材料中形成。此外,許多傾向與相變化材料中的元素反應及抑制空洞在主動區域中形成之活性添加物可以被使用。對硫屬化物為基礎的相變化材料而言,此種活性添加物可以包括傾向與碲強烈鍵結以在記憶胞的主動區域內形成較高熔化點化合物的材料可能包括鈧、鈦、釩、鉻、錳、鐵和鎵,以及其他自週期表元素14至33中(除了鈍氣之外)所選取的材料。
雖然本發明係參照較佳實施例及範例來加以描述,應了解這些範例係用於說明而非限縮之用。對於依據本發明之精神及下述申請專利範圍內的修改及組合,將為熟習此項技藝之人士顯而易知。申請專利範圍如以下所述。
100、700、800、900...記憶胞
110、710、810、910...主動區域
113、713、813、913...非主動區域
116、716、816、916...記憶元件
120、720、820、920...第一電極
122...第一電極的寬度
130...介電層
140、740、840、940...第二電極
715...介電間隔物
717...電流路徑長度
817...記憶元件寬度
822...底表面
824...頂表面
1010...積體電路
1012...具有非定值摻雜分佈之相變化記憶胞陣列
1014...字元線解碼器及驅動器
1016...字元線
1018...位元線解碼器
1020...位元線
1022...匯流排
1024...感應放大器/資料輸入結構
1026...資料匯流排
1028...資料輸入線
1030...其它電路
1032...資料輸出線
1034...控制器
1036...偏壓電路之電壓及電流源
1130、1132、1134、1136...記憶胞
1140、1142、1144、1146...記憶元件
1154...源極線
1155...源極線終端
1156、1158...字元線
1160、1162...位元線
1180...電流路徑
第1圖為一個記憶胞之一部份的簡要剖面示意圖,其具有不同的區域特性,在裝置操作時具有極不同的熱性、電性和相轉變等特性。
第2圖顯示使用一基礎相變化材料及單一添加物之濃度分佈的第一實施例。
第3圖顯示使用一基礎相變化材料及兩種添加物組合之濃度分佈的第二實施例。
第4圖顯示使用一基礎相變化材料及另兩種不同添加物組合之濃度分佈的第三實施例。
第5圖顯示使用一基礎相變化材料及另兩種不同添加物組合之濃度分佈的第四實施例。
第6圖顯示具有此處所描述之非定值添加物濃度分佈的記憶胞之製造流程圖。
第7圖為一第一實施例中記憶胞之一部份的剖面圖,其包含一具有非定值添加濃度分佈之相變化材料記憶元件。
第8圖為一第二實施例中記憶胞之一部份的剖面圖,其包含一具有非定值添加濃度分佈之相變化材料記憶元件。
第9圖為一第三實施例中記憶胞之一部份的剖面圖,其包含一具有非定值添加濃度分佈之相變化材料記憶元件。
第10圖係可應用本發明之積體電路的簡化方塊圖。此積體電路包括使用此處所描述之非定值添加濃度分佈記憶胞之記憶體陣列。
第11圖係為具有此處所描述之非定值添加濃度分佈記憶胞之記憶體陣列的簡要示意圖。
100...記憶胞
110...主動區域
113...非主動區域
116...記憶元件
120...第一電極
122...第一電極的寬度
130...介電層
140...第二電極
Claims (9)
- 一種記憶體裝置,具有一第一電極、一第二電極和記憶元件,該記憶元件包含:一相變化記憶材料與該第一電極和第二電極連接,該相變化記憶材料包含一基礎相變化記憶材料及一添加物濃度分佈介於該第一電極和第二電極之間,對一個或以上的添加物其添加物濃度分佈是不均勻的;其中該基礎相變化記憶材料是鍺銻碲(GST),該添加物之一是矽,在該相變化記憶材料的一主動區域內具有較高濃度而在鄰接該第二電極具有較低濃度,及另一添加物是氧化矽,在該主動區域內和介於該主動區域與該第二電極之間的一區域具有較高濃度。
- 如申請專利範圍第1項所述之裝置,其中該添加物濃度分佈包含至少兩種添加物具有各自的濃度分佈,在介於該第一電極和第二電極之間其濃度分佈是不均勻的。
- 如申請專利範圍第1項所述之裝置,其中該相變化記憶材料具有一第一區域鄰接該第一電極、一第二區域包圍該主動區域、一第三區域介於該主動區域與該第二電極之間及一第四區域鄰接該第二電極,該添加物濃度分佈在該第一、第二、第三、及第四區域變動。
- 一種積體電路記憶體裝置,包含:一記憶胞陣列,其中於該陣列中的一記憶胞包含一記 憶裝置,具有一第一電極、一第二電極和記憶元件,且該記憶元件包含相變化記憶材料與該第一電極和第二電極連接,該相變化記憶材料包含一基礎相變化記憶材料及添加物濃度分佈介於該第一電極和第二電極之間,對一個或以上的添加物其添加物分佈是不均勻的;解碼電路,與該陣列耦接以響應位址而存取該陣列中的所選取之記憶胞;以及一控制器及支援電路,與該陣列耦接以響應命令而在該陣列中的所選取之記憶胞中執行讀取、設置和重置操作;其中該基礎相變化記憶材料是鍺銻碲(GST),該添加物之一是矽,在該相變化記憶材料的一主動區域內具有較高濃度而在鄰接該第二電極具有較低濃度,及另一添加物是氧化矽,在該主動區域內和介於該主動區域與該第二電極之間的一區域具有較高濃度。
- 如申請專利範圍第4項所述之裝置,其中該添加物濃度分佈包含至少兩種添加物具有各自的濃度分佈,在介於該第一電極和第二電極之間其濃度分佈是不均勻的。
- 如申請專利範圍第4項所述之裝置,其中該相變化記憶材料具有一第一區域鄰接該第一電極、一第二區域包圍該主動區域、一第三區域介於該主動區域與該第二電極之間及一第四區域鄰接該第二電極,該添加物濃度分佈在該第一、第二、第三、及第四區域變動。
- 一種積體電路記憶體裝置,包含:一記憶胞陣列,其中於該陣列中的一記憶胞包含一記憶裝置,具有一第一電極、一第二電極和一記憶元件,且該記憶元件包含相變化記憶材料與該第一電極和第二電極連接及一主動區域,該相變化記憶材料包含一基礎相變化記憶材料的一第一層鄰接該第一電極與一基礎相變化記憶材料的一第二層鄰接該第二電極,具有一第一添加物濃度分佈於包括一第一添加物的該第一層中、及一第二添加物濃度分佈於包括一第二添加物的該第二層中;其中該基礎相變化記憶材料是鍺銻碲(GST),該第一添加物是矽,在該相變化記憶材料的一主動區域內具有較高濃度而在鄰接該第二電極具有較低濃度,及該第二添加物是氧化矽,在該主動區域內和介於該主動區域與該第二電極之間的一區域具有較高濃度。
- 一種積體電路記憶體裝置,包含:一記憶胞陣列,其中於該陣列中的一記憶胞包含一記憶裝置,具有一第一電極、一第二電極和一記憶元件,且該記憶元件包含相變化記憶材料與該第一電極和第二電極連接及一主動區域,該相變化記憶材料包含一基礎相變化記憶材料及一添加物,該添加物具有一分佈介於該第一電極和第二電極之間是不均勻的;以及其中該添加物分佈包含矽濃度為5±2%原子數百分比,氧濃度為10±4%原子數百分比於該主動區域內。
- 如申請專利範圍第8項所述之裝置,其中該基礎相變化材料是鍺銻碲(GST)。
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US8363463B2 (en) | 2013-01-29 |
US20100328996A1 (en) | 2010-12-30 |
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