TWI420793B - Voltage spike restraining circuit and transforming control circuit - Google Patents
Voltage spike restraining circuit and transforming control circuit Download PDFInfo
- Publication number
- TWI420793B TWI420793B TW099139261A TW99139261A TWI420793B TW I420793 B TWI420793 B TW I420793B TW 099139261 A TW099139261 A TW 099139261A TW 99139261 A TW99139261 A TW 99139261A TW I420793 B TWI420793 B TW I420793B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- voltage
- control circuit
- switching unit
- surge suppression
- Prior art date
Links
Landscapes
- Dc-Dc Converters (AREA)
Description
本發明係關於一種突波抑制電路及轉換控制電路，尤指一種用以抑制電感元件所造成的電位高頻震盪訊號之突波抑制電路及轉換控制電路。The present invention relates to a surge suppression circuit and a conversion control circuit, and more particularly to a surge suppression circuit and a conversion control circuit for suppressing a potential high frequency oscillation signal caused by an inductance component.
請參見第一圖，為傳統的直流轉直流降壓轉換電路之電路示意圖。直流轉直流降壓轉換電路包含一控制器10、電晶體M1、M2、一電感L及一輸出電容Cout。電晶體M1、M2串聯於一輸入電源Vin及接地電位，而電感L的一端耦接電晶體M1、M2的連接點，另一端耦接輸出電容Cout以輸出一輸出電壓Vout。控制器10根據輸出電壓Vout及電晶體M1、M2的連接點的電壓訊號Vp產生一控制訊號UG、LG，以分別控制電晶體M1、M2導通與截止。當電晶體M1導通而電晶體M2截止時，一電流藉由路徑由輸入電源Vin流經電晶體M1、電感L而至輸出電容Cout儲存。當電晶體M2導通而電晶體M1截止時，電流藉由路徑續流，由接地電位流經電晶體M2、電感L而至輸出電容Cout儲存。Please refer to the first figure, which is a circuit diagram of a conventional DC-to-DC buck conversion circuit. The DC-to-DC buck conversion circuit includes a controller 10, transistors M1, M2, an inductor L, and an output capacitor Cout. The transistors M1 and M2 are connected in series to an input power source Vin and a ground potential, and one end of the inductor L is coupled to the connection point of the transistors M1 and M2, and the other end is coupled to the output capacitor Cout to output an output voltage Vout. The controller 10 generates a control signal UG, LG according to the output voltage Vout and the voltage signal Vp of the connection point of the transistors M1, M2 to respectively control the on and off of the transistors M1, M2. When the transistor M1 is turned on and the transistor M2 is turned off, a current is passed through the path. The input power source Vin flows through the transistor M1 and the inductor L to the output capacitor Cout for storage. When the transistor M2 is turned on and the transistor M1 is turned off, the current is passed through the path. The freewheeling current is stored by the ground potential through the transistor M2 and the inductor L to the output capacitor Cout.
理論上，當電晶體M1導通而電晶體M2截止時，電壓訊號Vp幾乎等於輸入電源Vin之電壓；當電晶體M2導通而電晶體M1截止時，電壓訊號Vp幾乎等於接地電位之電壓。若電晶體M1、M2若無法於同一時間點導通、截止，透過電晶體M1、M2的體二極體，電壓訊號Vp應可以被箝制於Vin+Vd以及-Vd之間，其中Vd為電晶體M1、M2的體二極體之順向導通電壓。然而由於電感L以及線路、電路上的寄生電感、電容(例如：電晶體M1、M2的寄生電容)會產生高頻的電壓震盪。請參見第二圖，為第一圖所示直流轉直流降壓轉換電路的控制訊號及連接點電壓之波形圖。當控制訊號UG由高準位轉為低準位而控制訊號LG由低準位轉為高準位時，即電晶體M2轉為導通而電晶體M1轉為截止時，電壓訊號Vp會下降至低於-Vd，並且於零電位之上下進行震盪(在此忽略電晶體M2的導通壓降)。當控制訊號LG由高準位轉為低準位而控制訊號UG由低準位轉為高準位時，即電晶體M1轉為導通而電晶體M2轉為截止時，電壓訊號Vp會上升至高於Vin+Vd，並且於Vin之上下進行震盪(在此忽略電晶體M1的導通壓降)。造成此現象，一般稱之為突波(Spike)，之原因在於電感L以及線路、電路上的寄生電感、電容造成的電壓震盪的頻率相當高，電晶體M1、M2及其體二極體的反應速度較低而無法濾除。在一些應用上，高頻電壓震盪的震幅甚至超過0.5*Vin，也就是電壓訊號Vp的實際電壓範圍為-0.5*Vin～1.5Vin。Theoretically, when the transistor M1 is turned on and the transistor M2 is turned off, the voltage signal Vp is almost equal to the voltage of the input power source Vin; when the transistor M2 is turned on and the transistor M1 is turned off, the voltage signal Vp is almost equal to the voltage of the ground potential. If the transistors M1 and M2 cannot be turned on and off at the same time point, the voltage signal Vp should be clamped between Vin+Vd and -Vd through the body diodes of the transistors M1 and M2, where Vd is a transistor. The forward voltage of the body diodes of M1 and M2. However, due to the inductance L and the parasitic inductance on the line, the circuit, and the capacitance (for example, the parasitic capacitance of the transistors M1 and M2), high-frequency voltage oscillation occurs. Please refer to the second figure, which is the waveform diagram of the control signal and connection point voltage of the DC-to-DC buck converter circuit shown in the first figure. When the control signal UG is changed from the high level to the low level and the control signal LG is changed from the low level to the high level, that is, when the transistor M2 is turned on and the transistor M1 is turned off, the voltage signal Vp is lowered to Below -Vd, and oscillating above zero potential (here the conduction voltage drop of transistor M2 is ignored). When the control signal LG changes from the high level to the low level and the control signal UG changes from the low level to the high level, that is, when the transistor M1 is turned on and the transistor M2 is turned off, the voltage signal Vp rises to a high level. At Vin+Vd, and under the Vin is oscillated (the conduction voltage drop of the transistor M1 is ignored here). This phenomenon is generally called a spur (Spike). The reason is that the inductance L and the parasitic inductance on the circuit, the circuit, and the voltage oscillation caused by the capacitor are quite high. The transistors M1 and M2 and their body diodes The reaction rate is low and cannot be filtered out. In some applications, the amplitude of the high-frequency voltage oscillation is even more than 0.5*Vin, that is, the actual voltage range of the voltage signal Vp is -0.5*Vin~1.5Vin.
這樣的現象會導致電晶體M1、M2的耐壓等級，甚至如第一圖所示實施例中的控制器10連接到電晶體M1、M2的連接點時，控制器10的耐壓等級也需同時提高。這不僅會增加整體的電路成本，而且電壓訊號Vp的電壓範圍會隨不同電路設計而有所不同，仍可能超過控制器及電晶體的耐壓而造成使用壽命縮短，甚至毀損。Such a phenomenon may result in a withstand voltage level of the transistors M1, M2, and even when the controller 10 in the embodiment shown in the first embodiment is connected to the connection point of the transistors M1, M2, the withstand voltage level of the controller 10 is also required. At the same time improve. This will not only increase the overall circuit cost, but also the voltage range of the voltage signal Vp will vary with different circuit design, and may exceed the voltage resistance of the controller and the transistor, resulting in shortened service life or even damage.
鑑於先前技術中的電路，因電感元件，例如：轉換電路的電感或電路中的寄生電感，電晶體於切換會造成高頻電壓震盪而影響電晶體或接收高頻電壓震盪之電路的使用壽命及增加毀損風險，本發明利用突波抑制電路，縮減高頻電壓震盪的震幅大小，以避免上述先前技術中的問題。In view of the circuit in the prior art, due to the inductance component, such as the inductance of the conversion circuit or the parasitic inductance in the circuit, the switching of the transistor causes high-frequency voltage oscillation and affects the service life of the transistor or the circuit receiving the high-frequency voltage oscillation. In order to increase the risk of damage, the present invention utilizes a surge suppression circuit to reduce the magnitude of the amplitude of the high-frequency voltage oscillation to avoid the problems in the prior art described above.
為達上述本發明之目的，本發明提供了一種突波抑制電路，用以濾除一電感元件所造成之電壓震盪。突波抑制電路包含一釋能路經以及一偵測電路。釋能路經的一端耦接一電路之一連接端，另一端耦接一參考電位。偵測電路耦接連接端，且切換單元偵測電路具有一高通元件，用以於切換單元連接端之電壓具高頻率訊號時導通切換單元釋能路經。To achieve the above object of the present invention, the present invention provides a surge suppression circuit for filtering voltage oscillations caused by an inductive component. The surge suppression circuit includes a release path and a detection circuit. One end of the release path is coupled to one of the terminals of the circuit, and the other end is coupled to a reference potential. The detecting circuit is coupled to the connecting end, and the switching unit detecting circuit has a high-pass component for turning on the switching unit to release the energy when the voltage of the connecting end of the unit has a high frequency signal.
本發明也提供了一種轉換控制電路，用以控制一轉換電路將來自一輸入電源之電力傳送至一輸出端，其中切換單元轉換電路包含一電感元件。切換單元轉換控制電路包含至少一切換單元、一控制電路、一驅動電路及一突波抑制電路。一控制電路，根據代表切換單元輸出端之一輸出電壓或一輸出電流之一迴授訊號，產生至少一工作週期訊號。至少一切換單元耦接切換單元輸入電源及切換單元轉換電路，驅動電路根據切換單元至少一工作週期訊號切換切換單元至少一切換單元以切換單元至少一切換單元以控制傳送至切換單元輸出端之電力大小，使切換單元輸出電壓或切換單元輸出電流穩定於一預定值。突波抑制電路之一端耦接切換單元至少一切換單元，並偵測切換單元端之一端電壓，用以於切換單元端電壓具有一高頻率訊號時，降低切換單元高頻率訊號之震幅。The present invention also provides a conversion control circuit for controlling a conversion circuit to transfer power from an input power source to an output terminal, wherein the switching unit conversion circuit includes an inductance element. The switching unit switching control circuit includes at least one switching unit, a control circuit, a driving circuit and a surge suppression circuit. A control circuit generates at least one duty cycle signal according to one of an output voltage or an output current of one of the output terminals of the switching unit. The at least one switching unit is coupled to the switching unit input power and the switching unit switching circuit, and the driving circuit switches the switching unit by at least one switching unit according to the switching unit at least one duty cycle to switch the unit at least one switching unit to control the power transmitted to the output of the switching unit. The size is such that the switching unit output voltage or the switching unit output current is stabilized at a predetermined value. One end of the surge suppression circuit is coupled to at least one switching unit of the switching unit, and detects one terminal voltage of the switching unit end, so as to reduce the amplitude of the high frequency signal of the switching unit when the switching unit terminal voltage has a high frequency signal.
發明也提供了另一種轉換控制電路，用以控制一轉換電路將來自一輸入電源之電力傳送至一輸出端，其中切換單元轉換電路包含一電感元件。切換單元轉換控制電路包含至少一切換單元、一控制電路及一突波抑制電路。至少一切換單元，耦接切換單元輸入電源及切換單元轉換電路。控制電路具有一第一偵測端及一第二偵測端，切換單元第一偵測端接收代表切換單元輸出端之一輸出電壓或一輸出電流之一迴授訊號，切換單元第二偵測端耦接切換單元電感元件，切換單元控制電路根據切換單元迴授訊號切換切換單元至少一切換單元以控制傳送至切換單元輸出端之電力大小，使切換單元輸出電壓或切換單元輸出電流穩定於一預定值。突波抑制電路之一端耦接切換單元第二偵測端，用以抑制切換單元第二偵測端之電壓變化量，使切換單元二偵測端不超過一第一預定電壓或不低於一預定第二電壓。The invention also provides another conversion control circuit for controlling a conversion circuit to transfer power from an input power source to an output terminal, wherein the switching unit conversion circuit includes an inductance element. The switching unit switching control circuit includes at least one switching unit, a control circuit, and a surge suppression circuit. At least one switching unit is coupled to the switching unit input power and the switching unit switching circuit. The control circuit has a first detecting end and a second detecting end, and the first detecting end of the switching unit receives one of the output voltage of the output of the switching unit or one of the output currents, and the second detecting unit of the switching unit The end coupling is coupled to the switching unit inductance component, and the switching unit control circuit switches the switching unit according to the switching unit feedback signal to control at least one switching unit to control the power level transmitted to the output end of the switching unit, so that the switching unit output voltage or the switching unit output current is stabilized at one Predetermined value. One end of the surge suppression circuit is coupled to the second detecting end of the switching unit for suppressing the voltage variation of the second detecting end of the switching unit, so that the detecting unit 2 detecting end does not exceed a first predetermined voltage or not lower than one The second voltage is predetermined.
以上的概述與接下來的詳細說明皆為示範性質，是為了進一步說明本發明的申請專利範圍。而有關本發明的其他目的與優點，將在後續的說明與圖示加以闡述。The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.
請參見第三圖，為本發明之一較佳實施例之轉換控制電路之電路示意圖。本實施例之轉換控制電路係用以控制一轉換電路將來自一輸入電源Vin之電力傳送至一輸出端Vo以提供穩定的輸出電壓Vout或穩定的輸出電流Iout，其中轉換電路包含一電感L及一輸出電容Cout。轉換控制電路包含兩切換單元SW1、SW2、一控制電路110及一突波抑制電路150，其中控制電路110及一突波抑制電路150可以封裝於單一封裝體之中成為一控制器100。兩切換單元SW1、SW2串接於輸入電源Vin及接地電位之間，而兩切換單元SW1、SW2的連接點耦接電感L之一端，電感之另一端耦接輸出電容Cout。控制電路110具有一第一偵測端PN1及一第二偵測端PN2，第一偵測端PN1耦接輸出端Vo以接收一迴授訊號FB，第二偵測端PN2耦接切換單元SW1、SW2之連接點，以接收連接點的電壓訊號Vp。其中，迴授訊號FB代表輸出端Vo之輸出電壓Vout或輸出電流Iout大小，控制電路110據此來切換切換單元SW1、SW2，藉此控制由輸入電源Vin傳送至Vo輸出端之電力大小，使輸出電壓Vout或輸出電流Iout穩定於一預定值。突波抑制電路150之一端耦接第二偵測端PN2，用以抑制第二偵測端PN2之電壓變化量，使第二偵測端的電壓不超過一第一預定電壓或/及不低於一預定第二電壓。Please refer to the third figure, which is a circuit diagram of a conversion control circuit according to a preferred embodiment of the present invention. The conversion control circuit of the embodiment is configured to control a conversion circuit to transmit power from an input power source Vin to an output terminal Vo to provide a stable output voltage Vout or a stable output current Iout, wherein the conversion circuit includes an inductor L and An output capacitor Cout. The switching control circuit includes two switching units SW1, SW2, a control circuit 110 and a surge suppression circuit 150. The control circuit 110 and a surge suppression circuit 150 can be packaged in a single package to form a controller 100. The two switching units SW1 and SW2 are connected in series between the input power source Vin and the ground potential, and the connection points of the two switching units SW1 and SW2 are coupled to one end of the inductor L, and the other end of the inductor is coupled to the output capacitor Cout. The control circuit 110 has a first detection terminal PN1 and a second detection terminal PN2. The first detection terminal PN1 is coupled to the output terminal Vo for receiving a feedback signal FB, and the second detection terminal PN2 is coupled to the switching unit SW1. , the connection point of SW2, to receive the voltage signal Vp of the connection point. The feedback signal FB represents the output voltage Vout or the output current Iout of the output terminal Vo, and the control circuit 110 switches the switching units SW1 and SW2 accordingly, thereby controlling the magnitude of the power transmitted from the input power source Vin to the Vo output terminal. The output voltage Vout or the output current Iout is stabilized at a predetermined value. One end of the surge suppression circuit 150 is coupled to the second detection terminal PN2 for suppressing the voltage variation of the second detection terminal PN2, so that the voltage of the second detection terminal does not exceed a first predetermined voltage or/and is not lower than A predetermined second voltage is predetermined.
在本實施例中，切換單元SW1、SW2可以是金氧半場效電晶體，第一預定電壓可以設定等於切換單元SW2的汲極-源極的耐壓或以下，第二預定電壓可以設定等於輸入電源Vin的電壓減去切換單元SW1的汲極-源極的耐壓或以上，如此即可達到保護切換單元SW1、SW2之作用。如果控制電路110的耐壓能力小於切換單元SW1、SW2的耐壓能力，則可以控制電路110的耐壓能力來設定第一預定電壓及一預定第二電壓。In this embodiment, the switching units SW1 and SW2 may be gold-oxide half field effect transistors, and the first predetermined voltage may be set equal to or less than the drain-source voltage of the switching unit SW2, and the second predetermined voltage may be set equal to the input. The voltage of the power source Vin is subtracted from the drain-source withstand voltage of the switching unit SW1 or more, so that the functions of the protection switching units SW1 and SW2 can be achieved. If the withstand voltage capability of the control circuit 110 is less than the withstand voltage capability of the switching units SW1, SW2, the withstand voltage capability of the circuit 110 can be controlled to set the first predetermined voltage and a predetermined second voltage.
接著請參見第四圖，為根據本發明之一第一實施例之突波抑制電路之電路示意圖。突波抑制電路包含一釋能路徑及一偵測電路，其中釋能路徑包含一電晶體M，偵測電路包含一電容Cf、一電阻Rf以及一比較器150a。電阻Rf一端接地，另一端連接電容Cf及比較器150a的非反向輸入端。電晶體M一端連接電容Cf的另一端及連接如第三圖所示的連接點，以接收該點之電壓訊號Vp，電晶體M的另一端耦接一參考電位，例如：接地。比較器150a的反向端接收一第一參考電壓Vr1，輸出端耦接電晶體M的控制端，以控制其導通或截止。當電壓訊號Vp載有一高頻的電壓訊號時，因電容Cf的高通特性，電壓訊號的電壓變化直接施加在電阻Rf之上。當電阻Rf的電壓高於第一參考電壓Vr1時，比較器輸出高準位訊號以導通電晶體M，以抑制電壓訊號Vp的上升，使電壓訊號Vp的準位被限制在第一預定電壓或以下。Next, please refer to the fourth figure, which is a circuit diagram of a surge suppression circuit according to a first embodiment of the present invention. The surge suppression circuit includes an energy release path and a detection circuit, wherein the energy release path includes a transistor M, and the detection circuit includes a capacitor Cf, a resistor Rf, and a comparator 150a. The resistor Rf is grounded at one end, and the other end is connected to the capacitor Cf and the non-inverting input terminal of the comparator 150a. One end of the transistor M is connected to the other end of the capacitor Cf and connected to the connection point as shown in the third figure to receive the voltage signal Vp at the point, and the other end of the transistor M is coupled to a reference potential, for example, ground. The opposite end of the comparator 150a receives a first reference voltage Vr1, and the output end is coupled to the control terminal of the transistor M to control its turn-on or turn-off. When the voltage signal Vp carries a high-frequency voltage signal, the voltage change of the voltage signal is directly applied to the resistor Rf due to the high-pass characteristic of the capacitor Cf. When the voltage of the resistor Rf is higher than the first reference voltage Vr1, the comparator outputs a high level signal to conduct the crystal M to suppress the rise of the voltage signal Vp, so that the level of the voltage signal Vp is limited to the first predetermined voltage or the following.
接著請參見第五圖，為根據本發明之一第二實施例之突波抑制電路之電路示意圖。突波抑制電路包含一釋能路徑及一偵測電路，其中釋能路徑包含一電晶體M，偵測電路包含一電容Cf、一電阻Rf以及一比較器150b。相較於第四圖所示之突波抑制電路，本實施例之參考電位由接地電位改為輸入電源Vin，而比較器150b之非反向端接收一第二參考電壓Vr2，反向端連接電容Cf及電阻Rf之連接點。當電壓訊號Vp載有一高頻的電壓訊號使電容Cf及電阻Rf之連接點的電壓低於第二參考電壓Vr2時，比較器150b輸出高準位訊號以導通電晶體M，以抑制電壓訊號Vp的下降，使電壓訊號Vp的準位被限制在第二預定電壓或以上。Next, please refer to a fifth diagram, which is a circuit diagram of a surge suppression circuit according to a second embodiment of the present invention. The surge suppression circuit includes an energy release path and a detection circuit, wherein the energy release path includes a transistor M, and the detection circuit includes a capacitor Cf, a resistor Rf, and a comparator 150b. Compared with the surge suppression circuit shown in FIG. 4, the reference potential of the embodiment is changed from the ground potential to the input power source Vin, and the non-inverting terminal of the comparator 150b receives a second reference voltage Vr2, and the reverse terminal is connected. The connection point between the capacitor Cf and the resistor Rf. When the voltage signal Vp carries a high-frequency voltage signal such that the voltage at the junction of the capacitor Cf and the resistor Rf is lower than the second reference voltage Vr2, the comparator 150b outputs a high-level signal to conduct the crystal M to suppress the voltage signal Vp. The drop is such that the level of the voltage signal Vp is limited to a second predetermined voltage or more.
第四圖及第五圖之實施例分別用以抑制過高壓及過低壓的突波，實際使用時可依據電路的使用環境來單獨濾除過高壓或過低壓之突波，或者結合第四圖及第五圖之實施例來同時濾除過高壓及過低壓的突波。The embodiments of the fourth and fifth figures are respectively used to suppress the overshoot of the high voltage and the low voltage. In actual use, the surge of the high voltage or the low voltage may be separately filtered according to the use environment of the circuit, or the fourth diagram may be combined. And the embodiment of the fifth figure simultaneously filters out surges of high pressure and low pressure.
請參見第六圖，為第三圖所示的突波抑制電路150同時包含第四圖及第五圖所示之突波抑制電路時，電壓訊號Vp之波形圖。請同時參見第三圖到第五圖，當切換單元SW2導通而 切換單元SW1截止，電壓訊號Vp由Vin快速往0V下降。當電壓訊號Vp低於第二參考電壓Vr2時，比較器150b導通電晶體M，使電壓訊號Vp的變化速度變緩慢(即濾除了高頻的訊號)，並同時降低的電壓震盪的震幅大小，致使震幅大小在一預定值之內。當切換單元SW1導通而切換單元SW2截止，電壓訊號Vp由0V快速往Vin上升。當電壓訊號Vp高於第一參考電壓Vr1時，比較器150a導通電晶體M，使電壓訊號Vp的變化速度變緩慢並同時降低的電壓震盪的震幅大小，致使震幅大小在一預定值之內。因此，如上說明般，本發明的突波抑制電路可有效抑制突波的大小而達到保護切換單元SW1、SW2以及其他連接到此連接點之電路之優點。Please refer to the sixth figure, which is a waveform diagram of the voltage signal Vp when the surge suppression circuit 150 shown in the third figure includes the surge suppression circuit shown in the fourth and fifth figures. Please also refer to the third to fifth figures, when the switching unit SW2 is turned on. The switching unit SW1 is turned off, and the voltage signal Vp is rapidly decreased from Vin to 0V. When the voltage signal Vp is lower than the second reference voltage Vr2, the comparator 150b conducts the crystal M, so that the rate of change of the voltage signal Vp is slow (that is, the high frequency signal is filtered out), and at the same time, the amplitude of the voltage oscillation is reduced. , causing the magnitude of the shock to be within a predetermined value. When the switching unit SW1 is turned on and the switching unit SW2 is turned off, the voltage signal Vp rises rapidly from 0V to Vin. When the voltage signal Vp is higher than the first reference voltage Vr1, the comparator 150a conducts the crystal M, so that the rate of change of the voltage signal Vp becomes slow and simultaneously reduces the magnitude of the amplitude of the voltage oscillation, so that the magnitude of the amplitude is at a predetermined value. Inside. Therefore, as described above, the surge suppressing circuit of the present invention can effectively suppress the magnitude of the glitch to the advantage of protecting the switching units SW1, SW2 and other circuits connected to the connection point.
請參見第七圖，為根據本發明之一第三實施例之突波抑制電路之電路示意圖。相較於第四圖所示之突波抑制電路，主要之差異點在於省略比較器150a。由於電容Cf具有高通效果，所以高頻的突波所造成的電壓變化會主要落在電阻Rf之上，而使電晶體M導通而達到抑制突波之作用。因此，本發明也可以省略比較器以降低突波抑制電路的成本。請參見第八圖，為根據本發明之一第四實施例之突波抑制電路之電路示意圖。相較於第四圖所示之突波抑制電路，主要之差異點在於比較器150a以串聯兩反向器之判斷電路150c所取代。由於反向器之反應速度高於比較器150a之反應速度，因此可具有更佳的突波抑制效果。Referring to the seventh figure, there is shown a circuit diagram of a surge suppression circuit according to a third embodiment of the present invention. The main difference is that the comparator 150a is omitted as compared with the surge suppression circuit shown in the fourth figure. Since the capacitor Cf has a high-pass effect, the voltage change caused by the high-frequency spurt mainly falls on the resistor Rf, and the transistor M is turned on to suppress the glitch. Therefore, the present invention can also omit the comparator to reduce the cost of the surge suppression circuit. Please refer to the eighth figure, which is a circuit diagram of a surge suppression circuit according to a fourth embodiment of the present invention. Compared with the surge suppression circuit shown in the fourth figure, the main difference is that the comparator 150a is replaced by the determination circuit 150c of the two inverters in series. Since the reaction speed of the inverter is higher than the reaction speed of the comparator 150a, it is possible to have a better surge suppression effect.
請參見第九圖，為本發明之另一較佳實施例之轉換控制電路之電路示意圖。本實施例之轉換控制電路係用以控制一轉換電路將來自一輸入電源Vin之電力傳送至一輸出端Vo以提供穩定的輸出電壓Vout或穩定的輸出電流Iout，其中轉換電路包含一電感L及一輸出電容Cout。轉換控制電路包含一控制電路200以及一電晶體模組220。控制電路200接收一迴授訊號FB，其中迴授訊號FB代表輸出端Vo之輸出電壓Vout或輸出電流Iout大小。控制電路200據此產生至少一工作週期訊 號PM至電晶體模組220，而工作週期訊號PM可以是脈寬調變(Pulse Width Modulated)訊號、脈頻調變(Pulse Frequency Modulated)訊號或其組合。電晶體模組220包含一驅動電路、切換單元SW1、SW2以及一突波抑制電路250，其中驅動電路包含一脈寬控制電路225、一第一驅動電路230以及一第二驅動電路235。為了使第一驅動電路230能順利導通切換單元SW1，第一驅動電路230可耦接至一自舉升壓電路(Bootstrap Circuit)，以提供一高於電壓訊號Vp之電壓，其中自舉升壓電路包含一二極體D及一升壓電容Cboot，耦接於輸入電壓Vin及切換單元SW1、SW2的連接點之間。脈寬控制電路225耦接切換單元SW1、SW2之連接點，以根據工作週期訊號PM及電壓訊號Vp，透過第一驅動電路230以及第二驅動電路235來切換切換單元SW1、SW2，藉此控制由輸入電源Vin傳送至Vo輸出端之電力大小，使輸出電壓Vout或輸出電流Iout穩定於一預定值。突波抑制電路250之一端耦接切換單元SW1、SW2之連接點，用以抑制切換單元SW1、SW2連接點之電壓變化量，使切換單元SW1、SW2連接點的電壓不超過第一預定電壓或不低於預定第二電壓。Please refer to the ninth figure, which is a circuit diagram of a conversion control circuit according to another preferred embodiment of the present invention. The conversion control circuit of the embodiment is configured to control a conversion circuit to transmit power from an input power source Vin to an output terminal Vo to provide a stable output voltage Vout or a stable output current Iout, wherein the conversion circuit includes an inductor L and An output capacitor Cout. The conversion control circuit includes a control circuit 200 and a transistor module 220. The control circuit 200 receives a feedback signal FB, wherein the feedback signal FB represents the output voltage Vout or the output current Iout of the output terminal Vo. The control circuit 200 generates at least one working cycle accordingly The PM is to the transistor module 220, and the duty cycle signal PM can be a Pulse Width Modulated signal, a Pulse Frequency Modulated signal, or a combination thereof. The transistor module 220 includes a driving circuit, switching units SW1 and SW2, and a surge suppression circuit 250. The driving circuit includes a pulse width control circuit 225, a first driving circuit 230, and a second driving circuit 235. In order to enable the first driving circuit 230 to smoothly turn on the switching unit SW1, the first driving circuit 230 can be coupled to a bootstrap circuit to provide a voltage higher than the voltage signal Vp, wherein the bootstrap voltage is boosted. The circuit includes a diode D and a boost capacitor Cboot coupled between the input voltage Vin and the connection points of the switching units SW1 and SW2. The pulse width control circuit 225 is coupled to the connection point of the switching units SW1 and SW2 to switch the switching units SW1 and SW2 through the first driving circuit 230 and the second driving circuit 235 according to the duty cycle signal PM and the voltage signal Vp. The magnitude of the power transmitted from the input power source Vin to the Vo output terminal stabilizes the output voltage Vout or the output current Iout to a predetermined value. One end of the surge suppression circuit 250 is coupled to the connection point of the switching units SW1 and SW2 for suppressing the voltage variation of the connection point of the switching units SW1 and SW2 so that the voltage of the connection point of the switching units SW1 and SW2 does not exceed the first predetermined voltage or Not lower than the predetermined second voltage.
相較於第三圖所示之轉換控制電路，第九圖所示之電晶體模組220，可以為單一封裝結構內，如此也可以使控制電路200的耐壓需求不需提升到輸入電源Vin之電壓。因此控制電路200的耐壓要求可以降低而達到降低整體電路成本之優點。Compared with the conversion control circuit shown in FIG. 3 , the transistor module 220 shown in FIG. 9 can be in a single package structure, so that the withstand voltage requirement of the control circuit 200 does not need to be increased to the input power source Vin. The voltage. Therefore, the withstand voltage requirement of the control circuit 200 can be reduced to achieve the advantage of reducing the overall circuit cost.
除上述的實施例之突波抑制電路外，本發明亦可以直接使用晶片設計中常見的靜電放電電路作為突波抑制電路，如此可以不需額外增加晶片面積。或者，亦可以由外加離散元件的方式來達到相同之突波抑制。In addition to the surge suppression circuit of the above embodiment, the present invention can also directly use the electrostatic discharge circuit commonly used in the wafer design as the surge suppression circuit, so that the additional wafer area can be eliminated. Alternatively, the same surge suppression can be achieved by adding discrete components.
請參見第十圖，為根據本發明之一較佳實施例之直流轉直流升壓轉換電路之電路示意圖。直流轉直流升壓轉換電路包含一控制器300、一突波抑制電路350、切換單元SW、一電感L、一二極體D及一輸出電容Cout。電感L一端耦接一輸入電源 Vin，另一端耦接二極體D之正端及切換單元SW之一端，而切換單元SW之另一端接地。二極體D之負端耦接輸出電容Cout之一端以形成一輸出端Vo。控制電路300接收代表輸出端Vo之輸出電壓Vout或輸出電流Iout大小之一迴授訊號FB，以據此來切換切換單元SW，如此，控制電路300可控制由輸入電源Vin傳送至Vo輸出端之電力大小，使輸出電壓Vout或輸出電流Iout穩定於一預定值。突波抑制電路350包含串聯之一電阻元件R及一電容元件C，耦接於電感L及切換單元SW之連接點及接地之間，用以抑制電感L及切換單元SW之連接點之電壓訊號Vp的變化量，使電壓訊號Vp不超過一第一預定電壓或不低於一預定第二電壓。Please refer to the tenth figure, which is a circuit diagram of a DC-to-DC boost converter circuit according to a preferred embodiment of the present invention. The DC-to-DC boost converter circuit includes a controller 300, a surge suppression circuit 350, a switching unit SW, an inductor L, a diode D, and an output capacitor Cout. One end of the inductor L is coupled to an input power source Vin, the other end is coupled to the positive terminal of the diode D and one end of the switching unit SW, and the other end of the switching unit SW is grounded. The negative terminal of the diode D is coupled to one end of the output capacitor Cout to form an output terminal Vo. The control circuit 300 receives the feedback signal FB representing the output voltage Vout or the output current Iout of the output terminal Vo to switch the switching unit SW accordingly. Thus, the control circuit 300 can control the transmission from the input power source Vin to the Vo output terminal. The power is sized to stabilize the output voltage Vout or the output current Iout to a predetermined value. The surge suppression circuit 350 includes a resistor element R and a capacitor C connected in series, and is coupled between the connection point of the inductor L and the switching unit SW and the ground to suppress the voltage signal of the connection point between the inductor L and the switching unit SW. The amount of change of Vp is such that the voltage signal Vp does not exceed a first predetermined voltage or not less than a predetermined second voltage.
另外，請參見第十一圖，為根據本發明之一第四實施例之突波抑制電路之電路示意圖。本實施例之突波抑制電路包含一齊納二極體(Zener Diode)ZD，一端耦接欲抑制突波的連接點，另一端接地，使電壓訊號Vp被抑制在齊納二極體的雪崩電壓(Breakdown Voltage)附近。In addition, please refer to FIG. 11 , which is a circuit diagram of a surge suppression circuit according to a fourth embodiment of the present invention. The surge suppression circuit of this embodiment includes a Zener Diode ZD, one end is coupled to the connection point for suppressing the surge, and the other end is grounded, so that the voltage signal Vp is suppressed to the avalanche voltage of the Zener diode. (Breakdown Voltage) nearby.
縱上所述，對於電路中的電感元件，例如：電感、變壓器、壓電變壓器或者電路中的寄生電感等具有電感值之元件，於切換單元切換時可能造成過高的突波而影響元件壽命之問題，本發明利用突波抑制電路，縮減突波中的高頻電壓震盪的震幅大小，而達到避免突波影響電路元件的壽命之優點。In the vertical direction, for an inductive component in a circuit, such as an inductor, a transformer, a piezoelectric transformer, or a parasitic inductance in a circuit, an element having an inductance value may cause an excessive surge when the switching unit is switched to affect the life of the component. The problem of the present invention is to use the surge suppression circuit to reduce the magnitude of the amplitude of the high-frequency voltage oscillation in the surge, thereby achieving the advantage of avoiding the influence of the surge on the life of the circuit component.
本發明在上文中已以較佳實施例揭露，然熟習本項技術者應理解的是，該實施例僅用於描繪本發明，而不應解讀為限制本發明之範圍。應注意的是，舉凡與該實施例等效之變化與置換，均應設為涵蓋於本發明之範疇內。因此，本發明之保護範圍當以下文之申請專利範圍所界定者為準。The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.
10．．．控制器10. . . Controller
M1、M2．．．電晶體M1, M2. . . Transistor
L．．．電感L. . . inductance
Cout．．．輸出電容Cout. . . Output capacitor
Vin．．．輸入電源Vin. . . Input power
Vout．．．輸出電壓Vout. . . The output voltage
Vp．．．電壓訊號Vp. . . Voltage signal
UG、LG．．．控制訊號UG, LG. . . Control signal
．．．路徑 . . . path
100、300．．．控制器100, 300. . . Controller
110、200．．．控制電路110, 200. . . Control circuit
150、250、350．．．突波抑制電路150, 250, 350. . . Surge suppression circuit
150a、150b．．．比較器150a, 150b. . . Comparators
150c．．．判斷電路150c. . . Judging circuit
220．．．電晶體模組220. . . Transistor module
225．．．脈寬控制電路225. . . Pulse width control circuit
230．．．第一驅動電路230. . . First drive circuit
235．．．第二驅動電路235. . . Second drive circuit
Vin．．．輸入電源Vin. . . Input power
Vo．．．輸出端Vo. . . Output
Vout．．．輸出電壓Vout. . . The output voltage
Iout．．．輸出電流Iout. . . Output current
L．．．電感L. . . inductance
Cout．．．輸出電容Cout. . . Output capacitor
SW、SW1、SW2．．．切換單元SW, SW1, SW2. . . Switching unit
PN1．．．第一偵測端PN1. . . First detection end
PN2．．．第二偵測端PN2. . . Second detection end
FB．．．迴授訊號FB. . . Feedback signal
Vp．．．電壓訊號Vp. . . Voltage signal
M．．．電晶體M. . . Transistor
Cf．．．電容Cf. . . capacitance
Rf．．．電阻Rf. . . resistance
D．．．二極體D. . . Dipole
Cboot．．．升壓電容Cboot. . . Boost capacitor
R．．．電阻元件R. . . Resistance element
C．．．電容元件C. . . Capacitive component
PM．．．工作週期訊號PM. . . Work cycle signal
ZD‧‧‧齊納二極體ZD‧‧‧Zina diode
Vr1‧‧‧第一參考電壓Vr1‧‧‧ first reference voltage
Vr2‧‧‧第二參考電壓Vr2‧‧‧second reference voltage
第一圖為傳統的直流轉直流降壓轉換電路之電路示意圖。The first picture shows the circuit diagram of a conventional DC-to-DC buck conversion circuit.
第二圖為第一圖所示直流轉直流降壓轉換電路的控制訊號及連接點電壓之波形圖。The second figure is the waveform diagram of the control signal and the connection point voltage of the DC-to-DC buck conversion circuit shown in the first figure.
第三圖為本發明之一較佳實施例之轉換控制電路之電路示意圖。The third figure is a circuit diagram of a conversion control circuit in accordance with a preferred embodiment of the present invention.
第四圖為根據本發明之一第一實施例之突波抑制電路之電路示意圖。The fourth figure is a circuit diagram of a surge suppression circuit according to a first embodiment of the present invention.
第五圖為根據本發明之一第二實施例之突波抑制電路之電路示意圖。Figure 5 is a circuit diagram of a surge suppression circuit in accordance with a second embodiment of the present invention.
第六圖為第三圖所示的突波抑制電路的電壓訊號Vp之波形圖。The sixth figure is a waveform diagram of the voltage signal Vp of the surge suppression circuit shown in the third figure.
第七圖為根據本發明之一第三實施例之突波抑制電路之電路示意圖。Figure 7 is a circuit diagram of a surge suppression circuit in accordance with a third embodiment of the present invention.
第八圖為根據本發明之一第四實施例之突波抑制電路之電路示意圖。Figure 8 is a circuit diagram of a surge suppression circuit in accordance with a fourth embodiment of the present invention.
第九圖為本發明之另一較佳實施例之轉換控制電路之電路示意圖。Figure 9 is a circuit diagram of a conversion control circuit in accordance with another preferred embodiment of the present invention.
第十圖為根據本發明之一較佳實施例之直流轉直流升壓轉換電路之電路示意圖Figure 11 is a circuit diagram of a DC-to-DC boost converter circuit according to a preferred embodiment of the present invention.
第十一圖為根據本發明之一第四實施例之突波抑制電路之電路示意圖。Figure 11 is a circuit diagram showing a surge suppression circuit according to a fourth embodiment of the present invention.
100．．．控制器100. . . Controller
110．．．控制電路110. . . Control circuit
150．．．突波抑制電路150. . . Surge suppression circuit
Vin．．．輸入電源Vin. . . Input power
Vo．．．輸出端Vo. . . Output
Vout．．．輸出電壓Vout. . . The output voltage
Iout．．．輸出電流Iout. . . Output current
L．．．電感L. . . inductance
Cout．．．輸出電容Cout. . . Output capacitor
SW1、SW2．．．切換單元SW1, SW2. . . Switching unit
PN1．．．第一偵測端PN1. . . First detection end
PN2．．．第二偵測端PN2. . . Second detection end
FB．．．迴授訊號FB. . . Feedback signal
Vp．．．電壓訊號Vp. . . Voltage signal
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099139261A TWI420793B (en) | 2010-11-16 | 2010-11-16 | Voltage spike restraining circuit and transforming control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099139261A TWI420793B (en) | 2010-11-16 | 2010-11-16 | Voltage spike restraining circuit and transforming control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201223090A TW201223090A (en) | 2012-06-01 |
| TWI420793B true TWI420793B (en) | 2013-12-21 |
Family
ID=46725404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099139261A TWI420793B (en) | 2010-11-16 | 2010-11-16 | Voltage spike restraining circuit and transforming control circuit |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI420793B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777461A (en) * | 1996-12-31 | 1998-07-07 | Intel Corporation | DC-DC converter for mobile application |
| TW200807845A (en) * | 2006-07-26 | 2008-02-01 | Benq Corp | Low acoustic noise solution for snubber circuit |
| TWM339149U (en) * | 2007-12-31 | 2008-08-21 | Universal Scient Ind Co Ltd | Over-voltage protection device |
| TWM390613U (en) * | 2010-04-30 | 2010-10-11 | Anmax Lightning Tech Corporation | Optimizing structure for series connection type surge suppression |
| TW201039547A (en) * | 2009-04-28 | 2010-11-01 | Feeling Technology Corp | Power conversion method and device capable of adapting pulse width control |
-
2010
- 2010-11-16 TW TW099139261A patent/TWI420793B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777461A (en) * | 1996-12-31 | 1998-07-07 | Intel Corporation | DC-DC converter for mobile application |
| TW200807845A (en) * | 2006-07-26 | 2008-02-01 | Benq Corp | Low acoustic noise solution for snubber circuit |
| TWM339149U (en) * | 2007-12-31 | 2008-08-21 | Universal Scient Ind Co Ltd | Over-voltage protection device |
| TW201039547A (en) * | 2009-04-28 | 2010-11-01 | Feeling Technology Corp | Power conversion method and device capable of adapting pulse width control |
| TWM390613U (en) * | 2010-04-30 | 2010-10-11 | Anmax Lightning Tech Corporation | Optimizing structure for series connection type surge suppression |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201223090A (en) | 2012-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10581318B2 (en) | Resonant converter including capacitance addition circuits | |
| US20150061613A1 (en) | Dc-dc converter and method of controlling dc-dc converter | |
| US9391525B2 (en) | Power system switch protection using output driver regulation | |
| US11018592B2 (en) | Flyback converter controller, flyback converter and methods of operation | |
| JP2012039761A (en) | Switching power supply device | |
| TWI466424B (en) | Dc-dc controller and dc-dc converter | |
| KR101758808B1 (en) | Intelligent Power Module And Power Driving Module Thereof | |
| TWI439023B (en) | Low noise step-down converter and low noise voltage supply assembly | |
| US20120106008A1 (en) | Spike suppression circuit and conversion control circuit | |
| US10432081B2 (en) | Waveform shaping circuit, semiconductor device, and switching power supply device | |
| TWI527495B (en) | Can be adjusted by a resistor output current ripple of the PWM controller and LED driver circuit | |
| JP2016539617A (en) | Flyback type switching power supply circuit and backlight driving device using the same | |
| TWI420793B (en) | Voltage spike restraining circuit and transforming control circuit | |
| KR101274212B1 (en) | Power Factor Correction Circuit | |
| US10008922B2 (en) | Switching power supply | |
| JP5741199B2 (en) | Rectifier snubber circuit | |
| JP5309923B2 (en) | Semiconductor device drive circuit | |
| US10171001B2 (en) | AC-to-DC power converter and related control circuits | |
| JP6191542B2 (en) | Power converter | |
| JP5927142B2 (en) | Switching power supply device and control method thereof | |
| US10447138B2 (en) | Converter configured to convert a DC input voltage to a DC output voltage and including at least one resistive element | |
| WO2024048018A1 (en) | Power conversion device | |
| JP6206000B2 (en) | LED drive circuit | |
| JP4803290B2 (en) | Switching power supply | |
| JP7021562B2 (en) | Power converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |