TWI420475B

TWI420475B - System and method for driving a display panel

Info

Publication number: TWI420475B
Application number: TW98107373A
Authority: TW
Inventors: Cheng Chi Yen
Original assignee: Himax Display Inc
Priority date: 2008-07-04
Filing date: 2009-03-06
Publication date: 2013-12-21
Also published as: TW201003623A

Description

顯示面板的驅動系統及方法Display panel driving system and method

本發明係有關一種顯示面板，特別是關於一種具多分支(multi-branch)像素結構之矽基液晶(LCoS)面板的驅動系統及方法。The present invention relates to a display panel, and more particularly to a drive system and method for a liquid crystal on silicon (LCoS) panel having a multi-branch pixel structure.

本申請案根據先申請案(申請案號97125263，申請日2008/7/4，發明名稱「顯示面板及其多分支像素結構」)以主張國內優先權。This application claims domestic priority based on the prior application (Application No. 97125263, Application Date 2008/7/4, Invention Name "Display Panel and Multi-Branch Pixel Structure").

矽基液晶(liquid crystal on silicon,LCoS或LCOS)為一種反射式技術，由於其可以較低成本以產生解析度高於液晶顯示器(LCD)的影像，因此普遍作為微型投影機(micro-projector)或微型顯示系統(micro-display system)的光機(optical engine)。LCoS的結構類似於LCD，通常包含排列成行列矩陣形式的多個像素。第一圖顯示一個傳統LCoS的像素單元10，其包含一電晶體QA，受到掃描線(或閘極線)12上的掃描信號Scan所存取(addressed)。像素單元10還包含一儲存電容C，其經由電晶體QA而接收及儲存資料線(或源極線)14所提供的影像資料Data。位於同一列電晶體QA之閘極藉由掃描線12而連接在一起，並受控於掃描驅動器或閘極驅動器(未顯示於圖式中)。位於同一行電晶體QA之源極藉由資料線14而連接在一起，並受控於資料驅動器或源極驅動器(未顯示於圖式中)。於操作時，電晶體QA首先受到掃描信號Scan的存取，因而將電晶體QA開啟(on)，而影像資料則儲存於儲存電容C中。接著，儲存於儲存電容C的電荷經轉移而得以顯示。Liquid crystal on silicon (LCoS or LCOS) is a reflective technology that is commonly used as a micro-projector because it can produce images with higher resolution than liquid crystal displays (LCDs) at a lower cost. Or an optical engine of a micro-display system. The structure of the LCoS is similar to an LCD and typically includes a plurality of pixels arranged in a matrix of rows and columns. The first figure shows a conventional LCoS pixel cell 10 that includes a transistor QA that is addressed by a scan signal Scan on a scan line (or gate line) 12. The pixel unit 10 further includes a storage capacitor C that receives and stores the image data Data provided by the data line (or source line) 14 via the transistor QA. The gates of the same column of transistors QA are connected together by scan lines 12 and are controlled by a scan driver or gate driver (not shown). The sources of the same row of transistors QA are connected by a data line 14 and are controlled by a data driver or a source driver (not shown). In operation, the transistor QA is first accessed by the scan signal Scan, thus turning on the transistor QA, and the image data is stored in the storage capacitor C. Then, the charge stored in the storage capacitor C is transferred and displayed.

由於液晶對於影像資料需要反應時間，因此操作速度成為LCoS或其他顯示系統於效能增進的一個重要指標。特別是當LCoS的解析度增高時，對操作速度的要求將更為嚴格。鑑於此，因此亟需提出一種新的結構以增加LCoS的操作速度。另外，達到高容量之像素單元也是LCoS或其他顯示系統的重要議題。Since liquid crystals require reaction time for image data, the operation speed becomes an important indicator of performance improvement of LCoS or other display systems. Especially when the resolution of LCoS is increased, the requirements for operating speed will be more stringent. In view of this, it is urgent to propose a new structure to increase the operating speed of the LCoS. In addition, reaching high-capacity pixel cells is also an important issue for LCoS or other display systems.

鑑於上述發明背景，本發明的目的之一為提出一種具多分支結構之顯示面板(例如LCoS)的驅動系統及方法，用以增加操作速度及減少耦合(coupling)效應。In view of the above background, one object of the present invention is to provide a driving system and method for a display panel (e.g., LCoS) having a multi-branched structure for increasing operating speed and reducing coupling effects.

本發明另一目的在於提出一種新穎的多分支像素結構，用以降低像素間距及節省晶片面積。Another object of the present invention is to provide a novel multi-branch pixel structure for reducing pixel pitch and saving wafer area.

根據本發明實施例，顯示面板(例如LCoS)的多分支像素結構包含排列成矩陣形式的複數個像素單元，且每一像素單元包含至少二分支(branches)。此二分支依次進入存取模式及顯示模式。顯示面板包含一組次資料線(sub-data lines)，其對應於每一行的像素單元，且次資料線可控地分別耦接至該二分支。於操作時，於一圖框中存取第一分支，使得第一次資料線所提供之影像資料得以轉移及儲存於第一分支中，並同時顯示第二分支所儲存的影像資料。接下來，於一相鄰圖框中存取第二分支，使得第二次資料線所提供之影像資料得以轉移及儲存於第二分支中，並同時顯示第一分支所儲存的影像資料。In accordance with an embodiment of the invention, a multi-branch pixel structure of a display panel (eg, LCoS) includes a plurality of pixel cells arranged in a matrix, and each pixel cell includes at least two branches. The two branches enter the access mode and the display mode in sequence. The display panel includes a set of sub-data lines corresponding to the pixel units of each row, and the secondary data lines are controllably coupled to the two branches, respectively. During operation, the first branch is accessed in a frame, so that the image data provided by the first data line is transferred and stored in the first branch, and the image data stored in the second branch is simultaneously displayed. Next, the second branch is accessed in an adjacent frame, so that the image data provided by the second data line is transferred and stored in the second branch, and the image data stored in the first branch is simultaneously displayed.

根據本發明另一實施例，顯示面板的每一像素單元包含至少二分支(branches)。對於每一行，二條次資料線(sub-data line)耦接至資料驅動器，並對應於二分支。多工器將位在相鄰像素單元間的二條次資料線進行多工分派(multiplex)，並將多工器之多工輸出耦接至一共享資料線，藉此得以降低像素間距。於操作時，將位在相鄰像素單元間的二條次資料線進行多工分派，並將多工輸出耦接至一共享資料線，其共享於相鄰的像素單元間。於存取模式期間，存取多工輸出之次資料線所對應的分支，使得多工輸出次資料線的影像資料得以儲存於存取分支。於顯示模式期間，顯示所儲存之影像資料。According to another embodiment of the invention, each pixel unit of the display panel comprises at least two branches. For each row, two sub-data lines are coupled to the data driver and correspond to the two branches. The multiplexer multiplexes the two secondary data lines located between adjacent pixel units, and couples the multiplexer output of the multiplexer to a shared data line, thereby reducing the pixel pitch. In operation, two secondary data lines located between adjacent pixel units are multiplexed, and the multiplexed output is coupled to a shared data line, which is shared between adjacent pixel units. During the access mode, the branch corresponding to the secondary data line of the multiplex output is accessed, so that the image data of the multiplexed output data line is stored in the access branch. During the display mode, the stored image data is displayed.

第二A圖顯示矽基液晶(LCoS)面板之多分支(multi-branch)像素結構200，第二B圖則顯示第二A圖之多分支像素結構的一個像素單元20。雖然此處以LCoS作為說明，然而所屬技術領域中具有通常知識者當可以將所說明之結構應用於其他反射式/穿透式顯示面板，例如液晶顯示器(LCD)。於第二A圖中，LCoS面板之多分支像素結構200包含排列成行列矩陣形式的多個像素或像素胞20。位於同一列的像素20受控於掃描線(或閘極線)22A及22B上的掃描信號(ScanA n及ScanB n,n=0,1,2等)；位於同一行的像素20則電性連接至資料線(或源極線)24。掃描線22A及22B受控於掃描驅動器(或閘極驅動器)220，資料線24則受控於資料驅動器(或源極驅動器)240。The second A diagram shows a multi-branch pixel structure 200 of a liquid crystal on silicon (LCoS) panel, and the second B diagram shows a pixel unit 20 of a multi-branch pixel structure of the second A diagram. Although LCoS is used herein as an illustration, those of ordinary skill in the art can apply the illustrated structure to other reflective/transmissive display panels, such as liquid crystal displays (LCDs). In the second diagram, the multi-branch pixel structure 200 of the LCoS panel includes a plurality of pixels or pixel cells 20 arranged in a matrix of rows and columns. The pixels 20 in the same column are controlled by scanning signals (ScanA n and ScanB n, n=0, 1, 2, etc.) on the scanning lines (or gate lines) 22A and 22B; the pixels 20 in the same row are electrically Connect to the data line (or source line) 24. Scan lines 22A and 22B are controlled by a scan driver (or gate driver) 220, and data lines 24 are controlled by a data driver (or source driver) 240.

參閱第二B圖，像素單元20包含至少二分支(branches)，亦即A分支及B分支。以A分支為例，其包含一存取(addressing)電晶體QA_A (例如金屬氧化半導體(MOS)電晶體)，位於掃描線22A上的掃描信號ScanA可藉由存取電晶體QA_A 的閘極而存取該存取電晶體QA_A 。存取電晶體QA_A 的通道一端(例如源極)則電性耦接至資料線24。Referring to the second B diagram, the pixel unit 20 includes at least two branches, that is, an A branch and a B branch. Taking the A branch as an example, it includes an addressing transistor QA _A (for example, a metal oxide semiconductor (MOS) transistor), and the scan signal ScanA on the scan line 22A can be accessed by the gate of the transistor QA _A The access transistor QA _{A is} accessed extremely. One end of the channel (eg, the source) of the access transistor QA _A is electrically coupled to the data line 24.

A分支還包含一儲存電容C_A ，其藉由存取電晶體QA_A 而接收位於資料線24上的影像資料。儲存電容C_A 的一端電性耦接至存取電晶體QA_A 通道的另一端(例如汲極)。儲存電容C_A 的另一端則電性耦接至參考電壓V_ref 或接地。The A branch also includes a storage capacitor C _A that receives image data located on the data line 24 by accessing the transistor QA _A. One end of the storage capacitor C _A is electrically coupled to the other end of the access transistor QA _A channel (eg, a drain). The other end of the storage capacitor C _A is electrically coupled to the reference voltage V _ref or to ground.

A分支更包含一顯示(displaying)電晶體QD_A (例如MOS電晶體)，儲存於儲存電容C_A 的影像資料可藉由顯示電晶體QD_A 而得以顯示。顯示電晶體QD_A 係用以緩衝儲存影像資料，直到開始顯示為止。顯示電晶體QD_A 的閘極係由一控制信號DA所控制。顯示電晶體QD_A 通道的一端(例如源極)電性耦接至存取電晶體QA_A 的汲極，且耦接至儲存電容C_A 的一端。顯示電晶體QD_A 通道的另一端(例如源極)則電性耦接至像素電極(pixel electrode)P。液晶電容C_1c 代表位於像素電極P與共電極(common electrode)之間的液晶等效電容量。顯示面板的共電極係與像素電極P互為相向，且耦接至共電壓VCOM。儲存之影像資料施加於相對應的像素電極P後將會改變位於其上液晶的穿透度或反射度。上述關於A分支的描述也適用於B分支當中的存取電晶體QA_B 、儲存電容C_B 、顯示電晶體QD_B 、掃描信號ScanB及控制信號DB。The A branch further includes a display transistor QD _A (for example, a MOS transistor), and the image data stored in the storage capacitor C _A can be displayed by displaying the transistor QD _A . The display transistor QD _A is used to buffer the stored image data until the display is started. The gate of the display transistor QD _A is controlled by a control signal DA. One end (eg, a source) of the display transistor QD _A channel is electrically coupled to the drain of the access transistor QA _A and coupled to one end of the storage capacitor C _A . The other end (eg, the source) of the display transistor QD _A channel is electrically coupled to the pixel electrode P. The liquid crystal capacitor C _1c represents a liquid crystal equivalent capacitance between the pixel electrode P and a common electrode. The common electrode of the display panel and the pixel electrode P are opposite to each other and coupled to the common voltage VCOM. The application of the stored image data to the corresponding pixel electrode P will change the transmittance or reflectance of the liquid crystal located thereon. The above description about the A branch also applies to the access transistor QA _B , the storage capacitor C _B , the display transistor QD _B , the scan signal ScanB, and the control signal DB among the B branches.

第三A圖及第三B圖顯示第二B圖像素單元20的操作。第四圖例示第三A圖、第三B圖相關操作的時序圖。The third A and third B diagrams show the operation of the second B-picture pixel unit 20. The fourth figure illustrates a timing chart of the related operations of the third A picture and the third B picture.

對於第三A圖及第四圖的圖框N，A分支進入存取(addressing)模式，此時掃描信號ScanA開啟(ON)存取電晶體QA_A ，使得資料線24提供的影像資料Data得以儲存於儲存電容C_A 中。同時，顯示電晶體QD_A 被邏輯低位準之控制信號DA所關閉(OFF)，此可避免所儲存之影像資料影響到其他分支(例如B分支)。掃描驅動器220依序產生掃描信號(ScanA 0、ScanA 1、ScanA 2等)，用以依序(例如從上至下)掃描(或存取)每一列的像素單元20。For the frame N of the third A picture and the fourth picture, the A branch enters an addressing mode, at which time the scanning signal ScanA turns ON the access transistor QA _A , so that the image data provided by the data line 24 can be obtained. Stored in storage capacitor C _A. At the same time, the display transistor QD _A is turned off (OFF) by the logic low level control signal DA, which prevents the stored image data from affecting other branches (for example, the B branch). The scan driver 220 sequentially generates scan signals (ScanA 0, ScanA 1, ScanA 2, etc.) for scanning (or accessing) the pixel units 20 of each column sequentially (for example, from top to bottom).

當A分支處於存取模式時，B分支則是進入顯示(displaying)模式，此時邏輯低位準之掃描信號(ScanB 0、ScanB 1、ScanB 2等)關閉(OFF)存取電晶體QA_B ，而邏輯高位準之控制信號DB則開啟(ON)顯示電晶體QD_B ，使得儲存於儲存電容C_B 的前一圖框影像資料(未顯示於圖式中)得以顯示。When the A branch is in the access mode, the B branch enters the display mode. At this time, the logic low scan signal (ScanB 0, ScanB 1, ScanB 2, etc.) turns off (OFF) the access transistor QA _B , The logic high level control signal DB turns ON the display transistor QD _B so that the previous frame image data (not shown in the figure) stored in the storage capacitor C _B is displayed.

接下來，對於第三B圖及第四圖的圖框N+1，A分支現在進入顯示模式，此時邏輯低位準之掃描信號(ScanA O、ScanA 1、ScanA 2等)關閉(OFF)存取電晶體QA_A ，而邏輯高位準之控制信號DA則開啟(ON)顯示電晶體QD_A ，使得儲存於儲存電容C_A 的圖框N影像資料得以顯示。Next, for the frame N+1 of the third B picture and the fourth picture, the A branch now enters the display mode, at which time the logic low scan signal (ScanA O, ScanA 1, ScanA 2, etc.) is turned off (OFF). The transistor QA _{A is taken} , and the logic high level control signal DA turns ON the display transistor QD _A so that the frame N image data stored in the storage capacitor C _A is displayed.

當A分支處於顯示模式時，B分支則是進入存取模式，此時掃描信號ScanB開啟(ON)存取電晶體QA_B ，使得資料線24提供的影像資料Data得以儲存於儲存電容C_B 中。同時，顯示電晶體QD_B 被邏輯低位準之控制信號DB所關閉(OFF)，此可避免所儲存之影像資料影響到其他分支(例如A分支)。掃描驅動器220依序產生掃描信號(ScanB 0、ScanB 1、ScanB 2等)，用以依序(例如從上至下)掃描(或存取)每一列的像素單元20。When the A branch is in the display mode, the B branch enters the access mode, at which time the scan signal ScanB turns ON (ON) the access transistor QA _B , so that the image data Data provided by the data line 24 is stored in the storage capacitor C _B . . At the same time, the display transistor QD _B is turned off (OFF) by the logic low level control signal DB, which prevents the stored image data from affecting other branches (for example, the A branch). The scan driver 220 sequentially generates scan signals (ScanB 0, ScanB 1, ScanB 2, etc.) for scanning (or accessing) the pixel units 20 of each column sequentially (for example, from top to bottom).

根據上述LCoS面板的多分支像素結構200，由於存取及顯示可以分別在不同的分支中於同一期間進行，因此得以增加其操作速度。According to the multi-branch pixel structure 200 of the LCoS panel described above, since the access and display can be performed in different branches in the same period, the operation speed can be increased.

第五圖顯示和第三A圖像素單元20相同的操作，但是額外考量存取電晶體QA_B 的雜散電容C_ds 。此雜散電容C_ds 會將資料線24上的影像資料耦合(coupling)至儲存電容C_B ，因而干擾影響了儲存電容C_B 內的儲存電荷，進而降低顯示品質。The fifth figure shows the same operation as the pixel cell 20 of the third A-picture, but additionally considers the stray capacitance C _{ds of the} access transistor QA _B . The stray capacitance C _ds couples the image data on the data line 24 to the storage capacitor C _B , so that the interference affects the stored charge in the storage capacitor C _B , thereby degrading the display quality.

第六A圖顯示本發明實施例LCoS面板之多分支像素結構600，第六B圖則顯示第六A圖之多分支像素結構的一個像素單元60。本實施例LCoS面板之多分支像素結構600係用以改善前述LCoS面板200的耦合(coupling)效應，但仍然保有其優點，亦即，高操作速度。第六A圖、第六B圖與第二A圖、第二B圖類似的元件係使用相同的元件符號。雖然此實施例以LCoS作為說明，然而所屬技術領域中具有通常知識者當可以將所說明之結構應用於其他形式的顯示面板，例如液晶顯示器(LCD)。於第六A圖中，LCoS面板之多分支像素結構600包含排列成行列矩陣形式的多個像素或像素胞60。位於同一列的像素60受控於掃描線22A及22B上的掃描信號(ScanA n及ScanB n,n=0,1,2等)；位於同一行的像素60則電性連接至一組次資料線(sub-data lines)24A、24B。每一組次資料線24A、24B則藉由一組開關(SWA、SWB)而合併至單一資料線24。掃描線22A及22B受控於掃描驅動器(或閘極驅動器)220，資料線24則受控於資料驅動器(或源極驅動器)240。FIG. 6A shows a multi-branch pixel structure 600 of the LCoS panel of the embodiment of the present invention, and the sixth B diagram shows a pixel unit 60 of the multi-branch pixel structure of the sixth A diagram. The multi-branch pixel structure 600 of the LCoS panel of the present embodiment is used to improve the coupling effect of the aforementioned LCoS panel 200, but still retains its advantages, that is, high operating speed. The elements of the sixth and sixth B drawings, which are similar to the second and second B, use the same component symbols. While this embodiment is illustrated with LCoS, those of ordinary skill in the art can apply the illustrated structure to other forms of display panels, such as liquid crystal displays (LCDs). In Figure 6A, the multi-branch pixel structure 600 of the LCoS panel includes a plurality of pixels or pixel cells 60 arranged in a matrix of rows and columns. The pixels 60 in the same column are controlled by the scanning signals on the scanning lines 22A and 22B (ScanA n and ScanB n, n=0, 1, 2, etc.); the pixels 60 in the same row are electrically connected to a set of secondary data. Sub-data lines 24A, 24B. Each set of secondary data lines 24A, 24B is merged into a single data line 24 by a set of switches (SWA, SWB). Scan lines 22A and 22B are controlled by a scan driver (or gate driver) 220, and data lines 24 are controlled by a data driver (or source driver) 240.

參閱第六B圖，像素單元60包含至少二分支，於本實施例中為A分支及B分支。以A分支為例，其包含一存取電晶體QA_A ，位於掃描線22A上的掃描信號ScanA可藉由存取電晶體QA_A 的閘極而存取該存取電晶體QA_A 。存取電晶體QA_A 的通道一端(例如源極)則電性耦接至次資料線24A。Referring to FIG. 6B, the pixel unit 60 includes at least two branches, which are an A branch and a B branch in this embodiment. Taking the A branch as an example, it includes an access transistor QA _A , and the scan signal ScanA on the scan line 22A can access the access transistor QA _A by accessing the gate of the transistor QA _A . One end of the channel (eg, the source) of the access transistor QA _A is electrically coupled to the secondary data line 24A.

A分支還包含一儲存電容C_A 及一顯示電晶體QD_A ，其和第二B圖的結構相同因此不再贅述。The A branch further includes a storage capacitor C _A and a display transistor QD _A which are identical in structure to the second B diagram and therefore will not be described again.

第七A圖及第七B圖顯示第六B圖像素單元60的操作。第八圖例示第七A圖、第七B圖相關操作的時序圖。The seventh A diagram and the seventh B diagram show the operation of the sixth B-picture pixel unit 60. The eighth diagram illustrates a timing chart of the operations related to the seventh A diagram and the seventh B diagram.

對於第七A圖及第八圖的圖框N，A分支進入存取(addressing)模式，此時掃描信號ScanA開啟(ON)存取電晶體QA_A ，A分支的開關SWA為閉路(close)，而B分支的開關SWB則為開路(open)，這將使得影像資料Data得以藉由資料線24、次資料線24A而儲存於儲存電容C_A 中。同時，顯示電晶體QD_A 被邏輯低位準之控制信號DA所關閉(OFF)，此可避免所儲存之影像資料影響到其他分支(例如B分支)。掃描驅動器220依序產生掃描信號(ScanA 0、ScanA 1、ScanA 2等)，用以依序(例如從上至下)掃描(或存取)每一列的像素單元60。For frame N of Figure 7A and Figure 8, the A branch enters the addressing mode. At this time, the scan signal ScanA turns ON (ON) the access transistor QA _A , and the switch SW of the A branch is closed. The switch SWB of the B branch is open, which causes the image data Data to be stored in the storage capacitor C _A by the data line 24 and the secondary data line 24A. At the same time, the display transistor QD _A is turned off (OFF) by the logic low level control signal DA, which prevents the stored image data from affecting other branches (for example, the B branch). The scan driver 220 sequentially generates scan signals (ScanA 0, ScanA 1, ScanA 2, etc.) for scanning (or accessing) the pixel units 60 of each column sequentially (for example, from top to bottom).

當A分支處於存取模式時，B分支則是進入顯示(displaying)模式，此時邏輯低位準之掃描信號(ScanB 0、ScanB 1、ScanB2等)關閉(OFF)存取電晶體QA_B ，而邏輯高位準之控制信號DB則開啟(ON)顯示電晶體QD_B ，使得儲存於儲存電容C_B 的前一圖框影像資料(未顯示於圖式中)得以顯示。When the A branch is in the access mode, the B branch is in the display mode, at which time the logic low scan signal (ScanB 0, ScanB 1, ScanB2, etc.) turns off (OFF) the access transistor QA _B , and The logic high level control signal DB turns ON the display transistor QD _B so that the previous frame image data (not shown in the figure) stored in the storage capacitor C _B is displayed.

接下來，對於第七B圖及第八圖的圖框N+1，A分支現在進入顯示模式，此時邏輯低位準之掃描信號(ScanA 0、ScanA 1、ScanA 2等)關閉(OFF)存取電晶體QA_A ，而邏輯高位準之控制信號DA則開啟(ON)顯示電晶體QD_A 。再者，A分支的開關SWA為開路(open)，而B分支的開關SWB則為閉路(close)，這將使得儲存於儲存電容C_A 的圖框N影像資料得以顯示。Next, for the frame N+1 of the seventh and eighth diagrams, the A branch now enters the display mode, at which time the logic low scan signal (ScanA 0, ScanA 1, ScanA 2, etc.) is turned off (OFF). The transistor QA _{A is taken} , and the logic high level control signal DA turns ON (displays) the transistor QD _A . Furthermore, the switch SWA of the A branch is open, and the switch SWB of the B branch is closed, which causes the frame N image data stored in the storage capacitor C _A to be displayed.

當A分支處於顯示模式時，B分支則是進入存取模式，此時掃描信號ScanB開啟(ON)存取電晶體QA_B ，這將使得影像資料Data得以藉由資料線24、次資料線24B而儲存於儲存電容C_B 中。同時，顯示電晶體QD_B 被邏輯低位準之控制信號DB所關閉(OFF)，此可避免所儲存之影像資料影響到其他分支(例如A分支)。掃描驅動器220依序產生掃描信號(ScanB 0、ScanB 1、ScanB 2等)，用以依序(例如從上至下)掃描(或存取)每一列的像素單元60。When the A branch is in the display mode, the B branch enters the access mode, and the scan signal ScanB turns ON (ON) the access transistor QA _B , which will enable the image data Data to pass through the data line 24 and the secondary data line 24B. It is stored in the storage capacitor C _B . At the same time, the display transistor QD _B is turned off (OFF) by the logic low level control signal DB, which prevents the stored image data from affecting other branches (for example, the A branch). The scan driver 220 sequentially generates scan signals (ScanB 0, ScanB 1, ScanB 2, etc.) for scanning (or accessing) the pixel units 60 of each column sequentially (for example, from top to bottom).

根據上述LCoS面板的多分支像素結構600，由於存取及顯示可以分別在不同的分支中於同一期間進行，因此得以增加其操作速度。再者，由於次資料線24A、24B係分別連接至存取電晶體QA_A 、存取電晶體QA_B ，因此第五圖所示的資料線耦合效應因而得以避免，或者大體上可以得到改善。According to the multi-branch pixel structure 600 of the LCoS panel described above, since access and display can be performed in different branches in the same period, the operation speed can be increased. Furthermore, since the secondary data lines 24A, 24B are respectively connected to the access transistor QA _A and the access transistor QA _B , the data line coupling effect shown in the fifth figure is thus avoided or substantially improved.

第九圖顯示多分支像素結構的像素單元90。像素單元90包含至少二分支：A分支及B分支。A分支包含存取電晶體QA_A 、顯示電晶體QD_A 及儲存電容C_A 。存取電晶體QA_A 可藉由其閘極而受到A分支掃描線上的掃描信號ScanA所存取。其中，存取電晶體QA_A 通道的一端(例如源極)電性耦接至A分支的資料線Datal。儲存電容C_A 可經由存取電晶體QA_A 及開關POL1而接收資料線Data1上的影像資料。其中，儲存電容C_A 的第一極板電性耦接至存取電晶體QA_A 通道的另一端(例如汲極)。儲存電容C_A 的第二極板則電性耦接至地或參考電壓。儲存於儲存電容C_A 的影像資料經由顯示電晶體QD_A 而得以顯示出來。顯示電晶體QD_A 係於顯示之前，用以緩衝儲存影像資料之用。其中，顯示電晶體QD_A 的閘極受控於控制信號DA。顯示電晶體QD_A 通道的一端(例如源極)電性耦接至存取電晶體QA_A 的汲極，且耦接至儲存電容C_A 的第一極板。顯示電晶體QD_A 通道的另一端(例如汲極)則電性耦接至像素電極P。上述關於A分支的描述也適用於B分支當中的存取電晶體QA_B 、儲存電容C_B 、顯示電晶體QD_B 、掃描信號ScanB、控制信號DB及資料線Data2。根據第九圖所示的多分支像素結構，每一行需要使用二資料線(亦即，Data1及Data2)，其佔用晶片面積且增加橫向(相鄰)像素間距。The ninth diagram shows a pixel unit 90 of a multi-branch pixel structure. The pixel unit 90 includes at least two branches: an A branch and a B branch. The A branch includes an access transistor QA _A , a display transistor QD _{A ,} and a storage capacitor C _A . The access transistor QA _A can be accessed by the scan signal ScanA on the A-branch scan line by its gate. The one end (for example, the source) of the access transistor QA _A channel is electrically coupled to the data line Data1 of the A branch. The storage capacitor C _A can receive the image data on the data line Data1 via the access transistor QA _A and the switch POL1. The first plate of the storage capacitor C _A is electrically coupled to the other end of the access transistor QA _A channel (eg, the drain). The second plate of the storage capacitor C _A is electrically coupled to the ground or reference voltage. The image data stored in the storage capacitor C _A is displayed via the display transistor QD _A . The display transistor QD _A is used to buffer the stored image data before being displayed. Wherein, the gate of the display transistor QD _A is controlled by the control signal DA. One end (eg, a source) of the display transistor QD _A channel is electrically coupled to the drain of the access transistor QA _A and coupled to the first plate of the storage capacitor C _A . The other end (eg, the drain) of the display transistor QD _A channel is electrically coupled to the pixel electrode P. The above description about the A branch also applies to the access transistor QA _B , the storage capacitor C _B , the display transistor QD _B , the scan signal ScanB, the control signal DB, and the data line Data2 among the B branches. According to the multi-branch pixel structure shown in FIG. 9, each row requires the use of two data lines (i.e., Data1 and Data2), which occupy the wafer area and increase the lateral (adjacent) pixel pitch.

第十A圖顯示本發明實施例LCoS面板之多分支像素結構1000，第十B圖則顯示第十A圖之多分支像素結構的部分細節。本實施例所揭露之LCoS面板多分支像素結構1000係用以改善像素間距及晶片面積。雖然此處以LCoS作為說明，然而所屬技術領域中具有通常知識者當可以將所說明之結構應用於其他平面顯示器，例如液晶顯示器(LCD)。FIG. 10A shows a multi-branch pixel structure 1000 of the LCoS panel of the embodiment of the present invention, and FIG. 10B shows a partial detail of the multi-branch pixel structure of FIG. The LCoS panel multi-branch pixel structure 1000 disclosed in this embodiment is used to improve pixel pitch and chip area. Although LCoS is used herein as an illustration, those of ordinary skill in the art can apply the illustrated structure to other flat panel displays, such as liquid crystal displays (LCDs).

參閱第十A圖，LCoS面板1000包含排列成行列矩陣形式的多個像素或像素胞90。位於同一列的像素90受控於掃描線22A及22B上的掃描信號(ScanA n及ScanB n,n=0,1,2等)，其又受控於掃描驅動器(或閘極驅動器)220。位於同一行的像素90則電性耦接至一組資料線25，且相鄰係素90共享相同的資料線25，如第十A圖、第十B圖所示。以行Xch1(第十B圖)為例，資料驅動器(或源極驅動器)240藉由第一次資料線(sub-data line)Xch1a及第二次資料線Xch1b而提供二個資料。類似的情形，對於另一行Xch2，資料驅動器240藉由第一次資料線Xch2a及第二次資料線Xch2b而提供二個資料。某行(例如Xch1)的第二次資料線(例如Xch1b)和相鄰行(例如Xch2)的第一次資料線(例如Xch2a)經由一多工器Mux(1b2a)而被多工分派(multiplex)。多工器Mux(1b2a)的輸出耦接至相鄰像素單元(例如單元1與單元2)之間的共享資料線25。此共享資料線25可藉由(重疊)結合單元1存取電晶體QA_B 之汲極和單元2存取電晶體QA_A 之源極而得，如第十C圖所示。此佈局示意圖顯示了單元1與單元2中各電晶體的閘極，以及共享的源/汲極(亦即，共享資料線)。由於相鄰像素單元共享其源/汲極，因此得以大量地降低晶片面積，以及實質地降低橫向像素間距。Referring to FIG. 10A, the LCoS panel 1000 includes a plurality of pixels or pixel cells 90 arranged in a matrix of rows and columns. Pixels 90 located in the same column are controlled by scan signals (ScanA n and ScanB n, n = 0, 1, 2, etc.) on scan lines 22A and 22B, which in turn are controlled by scan drivers (or gate drivers) 220. The pixels 90 located in the same row are electrically coupled to a set of data lines 25, and the adjacent velocities 90 share the same data line 25, as shown in FIG. 10A and FIG. Taking the line Xch1 (Fig. 10B) as an example, the data driver (or source driver) 240 provides two pieces of data by the first sub-data line Xch1a and the second data line Xch1b. Similarly, for another row Xch2, the data driver 240 provides two pieces of data by the first data line Xch2a and the second data line Xch2b. The second data line (eg Xch1b) of a row (eg Xch1) and the first data line (eg Xch2a) of an adjacent row (eg Xch2) are multiplexed via a multiplexer Mux (1b2a) (multiplex ). The output of the multiplexer Mux (1b2a) is coupled to a shared data line 25 between adjacent pixel units (eg, unit 1 and unit 2). The shared data line 25 can be obtained by (overlap) the bonding unit 1 accessing the drain of the transistor QA _B and the cell 2 accessing the source of the transistor QA _A as shown in the tenth C. This layout diagram shows the gates of each transistor in cell 1 and cell 2, as well as the shared source/drain (ie, shared data line). Since adjacent pixel cells share their source/drain, it is possible to greatly reduce the wafer area and substantially reduce the lateral pixel pitch.

第十一A圖至第十一D圖顯示LCoS面板之多分支像素結構1000(第十A/B圖)的操作。如第十一A圖所示，A分支進入存取(addressing)模式，於此期間，掃描信號(ScanA)開啟存取電晶體QA_A ，但關閉其餘電晶體。位於第一(或A分支)次資料線Xchna(n=1,2等)的資料可通過多工器Mux，並經由存取電晶體QA_A 而儲存於儲存電容C_A 。在此同時，位於第二(或B分支)次資料線Xchnb(n=1,2等)的資料則被擋住。The eleventh through eleventh through Dth graphs illustrate the operation of the multi-branch pixel structure 1000 (tenth A/B map) of the LCoS panel. As shown in FIG. 11A, the A branch enters an addressing mode during which the scan signal (ScanA) turns on the access transistor QA _A but turns off the remaining transistors. The data located at the first (or A branch) secondary data line Xchna (n = 1, 2, etc.) can be stored in the storage capacitor C _A via the multiplexer Mux and via the access transistor QA _A. At the same time, the data located at the second (or B branch) secondary data line Xchnb (n = 1, 2, etc.) is blocked.

於完成所有像素列之A分支存取模式操作後，A分支會進入顯示(displaying)模式，如第十一B圖所示。於此期間，控制信號DA開啟顯示電晶體QD_A ，但關閉其餘電晶體。藉此，儲存於所有像素列之儲存電容C_A 的影像資料即被顯示出來。After completing the A branch access mode operation of all the pixel columns, the A branch will enter the display mode, as shown in FIG. During this time, the control signal DA turns on the display transistor QD _A but turns off the remaining transistors. Thereby, the image data stored in the storage capacitor C _A of all the pixel columns is displayed.

接下來，如第十一C圖所示，B分支進入存取模式，於此期間，掃描信號(ScanB)開啟存取電晶體QA_B ，但關閉其餘電晶體。位於第二(或B分支)次資料線Xchnb(n=1,2等)的資料可通過多工器Mux，並經由存取電晶體QA_B 而儲存於儲存電容C_B 。在此同時，位於第一(或A分支)次資料線Xchna(n=1,2等)的資料則被擋住。Next, as shown in FIG. 11C, the B branch enters the access mode, during which the scan signal (ScanB) turns on the access transistor QA _B but turns off the remaining transistors. The data located in the second (or B-branch) secondary data line Xchnb (n = 1, 2, etc.) can be stored in the storage capacitor C _B via the multiplexer Mux and via the access transistor QA _B. At the same time, the data located in the first (or A branch) secondary data line Xchna (n = 1, 2, etc.) is blocked.

於完成所有像素列之B分支存取模式操作後，B分支會進入顯示模式，如第十一D圖所示。於此期間，控制信號DB開啟顯示電晶體QD_B ，但關閉其餘電晶體。藉此，儲存於所有像素列之儲存電容C_B 的影像資料即被顯示出來。本發明並不限定於上述第十一A圖至第十一D圖所示的存取、顯示模式操作，亦即，多分支像素結構100可以依照其他的存取、顯示模式順序來操作。After completing the B-branch access mode operation of all the pixel columns, the B-branch enters the display mode as shown in FIG. 11D. During this time, the control signal DB turns on the display transistor QD _B but turns off the remaining transistors. Thereby, the image data stored in the storage capacitor C _B of all the pixel columns is displayed. The present invention is not limited to the access and display mode operations shown in the above-described eleventh to eleventhth drawings, that is, the multi-branch pixel structure 100 can be operated in accordance with other access and display mode sequences.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10．．．像素單元10. . . Pixel unit

12．．．掃描線12. . . Scanning line

14．．．資料線14. . . Data line

20．．．像素單元20. . . Pixel unit

22A．．．(A分支)掃描線22A. . . (A branch) scan line

22B．．．(B分支)掃描線22B. . . (B branch) scan line

24．．．資料線twenty four. . . Data line

24A．．．(A分支)資料線24A. . . (A branch) data line

24B．．．(B分支)資料線24B. . . (B branch) data line

200．．．多分支像素結構200. . . Multi-branch pixel structure

220．．．掃描驅動器220. . . Scan drive

240．．．資料驅動器240. . . Data driver

60．．．像素單元60. . . Pixel unit

600．．．多分支像素結構600. . . Multi-branch pixel structure

90．．．像素單元90. . . Pixel unit

1000．．．多分支像素結構1000. . . Multi-branch pixel structure

25．．．共享資料線25. . . Shared data line

Data．．．影像資料Data. . . video material

Scan．．．掃描信號Scan. . . Scanning signal

ScanA．．．(A分支)掃描信號ScanA. . . (A branch) scan signal

ScanB．．．(B分支)掃描信號ScanB. . . (B branch) scan signal

QA．．．電晶體QA. . . Transistor

QA_A ．．．(A分支)存取電晶體QA _A . . . (A branch) access transistor

QA_B ．．．(B分支)存取電晶體QA _B. . . (B branch) access transistor

QD_A ．．．(A分支)顯示電晶體QD _A . . . (A branch) display transistor

QD_B ．．．(B分支)顯示電晶體QD _B. . . (B branch) display transistor

C．．．儲存電容C. . . Storage capacitor

C_A ．．．(A分支)儲存電容C _A . . . (A branch) storage capacitor

C_B ．．．(B分支)儲存電容C _B . . . (B branch) storage capacitor

C_1c ．．．液晶電容C _1c . . . Liquid crystal capacitor

C_ds ．．．雜散電容C _ds . . . Stray capacitance

V_ref ．．．參考電壓V _ref . . . Reference voltage

DA．．．(A分支)控制信號DA. . . (A branch) control signal

DB．．．(B分支)控制信號DB. . . (B branch) control signal

P．．．像素電極P. . . Pixel electrode

VCOM．．．共電壓VCOM. . . Common voltage

SWA．．．(A分支)開關SWA. . . (A branch) switch

SWB．．．(B分支)開關SWB. . . (B branch) switch

Data1、Data2．．．資料線Data1, Data2. . . Data line

POL1、POL2．．．開關POL1, POL2. . . switch

Mux．．．多工器Mux. . . Multiplexer

Xchn．．．(第n)像素行Xchn. . . (nth) pixel row

Xchna．．．(第n行)第一(或A分支)次資料線Xchna. . . (nth line) first (or A branch) secondary data line

Xchnb．．．(第n行)第二(或B分支)次資料線Xchnb. . . (nth line) second (or B branch) secondary data line

第一圖顯示一個傳統LCoS的像素單元。The first image shows a pixel unit of a traditional LCoS.

第二A圖顯示本發明之多分支像素結構。Figure 2A shows the multi-branched pixel structure of the present invention.

第二B圖顯示第二A圖之多分支像素結構的一個像素單元。The second B-picture shows one pixel unit of the multi-branch pixel structure of the second A-picture.

第三A圖及第三B圖顯示第二B圖像素單元的操作。The third A diagram and the third B diagram show the operation of the pixel unit of the second B-picture.

第四圖例示第三A圖、第三B圖相關操作的時序圖。The fourth figure illustrates a timing chart of the related operations of the third A picture and the third B picture.

第五圖顯示和第三A圖相同的LCoS操作，但是額外考量存取電晶體QA_B 的雜散電容C_ds 。The fifth figure shows the same LCoS operation as the third A picture, but additionally considers the stray capacitance C _{ds of the} access transistor QA _B .

第六A圖顯示本發明實施例之多分支像素結構。Figure 6A shows a multi-branch pixel structure in accordance with an embodiment of the present invention.

第六B圖顯示第六A圖之多分支像素結構的一個像素單元。Figure 6B shows one pixel unit of the multi-branch pixel structure of Figure 6A.

第七A圖及第七B圖顯示第六B圖像素單元的操作。The seventh A diagram and the seventh B diagram show the operation of the pixel unit of the sixth B diagram.

第八圖例示第七A圖、第七B圖相關操作的時序圖。The eighth diagram illustrates a timing chart of the operations related to the seventh A diagram and the seventh B diagram.

第九圖顯示多分支像素結構的像素單元。The ninth figure shows a pixel unit of a multi-branch pixel structure.

第十A圖顯示本發明實施例LCoS面板之多分支像素結構。FIG. 10A shows a multi-branch pixel structure of an LCoS panel according to an embodiment of the present invention.

第十B圖顯示第十A圖之多分支像素結構的部分細節。Figure 10B shows a partial detail of the multi-branch pixel structure of Figure 10A.

第十C圖之佈局示意圖顯示相鄰像素單元共享其源/汲極。The layout diagram of the tenth C diagram shows that adjacent pixel units share their source/drain.

第十一A圖至第十一D圖顯示LCoS面板之多分支像素結構(第十A/B圖)的操作。The eleventh to eleventhth drawings show the operation of the multi-branch pixel structure (tenth A/B diagram) of the LCoS panel.

22A．．．(A分支)掃描線22A. . . (A branch) scan line

22B．．．(B分支)掃描線22B. . . (B branch) scan line

24．．．資料線twenty four. . . Data line

24A．．．(A分支)資料線24A. . . (A branch) data line

24B．．．(B分支)資料線24B. . . (B branch) data line

60．．．像素單元60. . . Pixel unit

25．．．共享資料線25. . . Shared data line

Data．．．影像資料Data. . . video material

ScanA．．．(A分支)掃描信號ScanA. . . (A branch) scan signal

ScanB．．．(B分支)掃描信號ScanB. . . (B branch) scan signal

QA_A ．．．(A分支)存取電晶體QA _A . . . (A branch) access transistor

QA_B ．．．(B分支)存取電晶體QA _B. . . (B branch) access transistor

QD_A ．．．(A分支)顯示電晶體QD _A . . . (A branch) display transistor

QD_B ．．．(B分支)顯示電晶體QD _B. . . (B branch) display transistor

C_A ．．．(A分支)儲存電容C _A . . . (A branch) storage capacitor

C_B ．．．(B分支)儲存電容C _B . . . (B branch) storage capacitor

C_lc ．．．液晶電容C _lc . . . Liquid crystal capacitor

C_ds ．．．雜散電容C _ds . . . Stray capacitance

V_ref ．．．參考電壓V _ref . . . Reference voltage

DA．．．(A分支)控制信號DA. . . (A branch) control signal

DB．．．(B分支)控制信號DB. . . (B branch) control signal

P．．．像素電極P. . . Pixel electrode

VCOM．．．共電壓VCOM. . . Common voltage

SWA．．．(A分支)開關SWA. . . (A branch) switch

SWB．．．(B分支)開關SWB. . . (B branch) switch

Mux．．．多工器Mux. . . Multiplexer

Xchn．．．(第n)像素行Xchn. . . (nth) pixel row

Claims

一種顯示面板的驅動系統，包含：複數個像素單元，排列成矩陣形式，每一該像素單元包含至少二分支(branches)，該二分支依次進入存取模式及顯示模式；一組次資料線(sub-data lines)，對應於每一行的該像素單元，該次資料線可控地分別耦接至該二分支，其中該組次資料線可控地合併為單一資料線；及一組開關，用以分別控制該二分支與該單一資料線之間的連接。 A driving system for a display panel, comprising: a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least two branches, the two branches sequentially entering an access mode and a display mode; and a set of secondary data lines ( Sub-data lines), corresponding to the pixel unit of each row, the data lines are controllably coupled to the two branches, wherein the group of data lines are controllably combined into a single data line; and a set of switches, Used to separately control the connection between the two branches and the single data line.

如申請專利範圍第1項所述顯示面板的驅動系統，其中上述之顯示面板為矽基液晶(LCoS)面板。 The driving system of the display panel according to claim 1, wherein the display panel is a liquid crystal on silicon (LCoS) panel.

如申請專利範圍第1項所述顯示面板的驅動系統，更包含至少二掃描線，其對應於每一列的該像素單元，其中該像素單元的二分支分別對應耦接至該二掃描線。 The driving system of the display panel of claim 1, further comprising at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines.

如申請專利範圍第3項所述顯示面板的驅動系統，其中上述每一像素單元包含：一存取電晶體，受到對應掃描線之存取(addressed)；一儲存電容，用以接收及儲存對應之次資料線上的影像資料；及一顯示電晶體，藉以讓該儲存之影像資料得以顯示。 The driving system of the display panel of claim 3, wherein each of the pixel units comprises: an access transistor, which is accessed by a corresponding scan line; a storage capacitor for receiving and storing image data on the corresponding data line; and a display transistor for displaying the stored image data.

如申請專利範圍第4項所述顯示面板的驅動系統，其中：該存取電晶體之閘極耦接至對應的掃描線；該存取電晶體之通道的第一端耦接至對應的次資料線；及該存取電晶體之通道的第二端耦接至該儲存電容的一端。 The driving system of the display panel of claim 4, wherein: the gate of the access transistor is coupled to the corresponding scan line; and the first end of the channel of the access transistor is coupled to the corresponding one. The data line; and the second end of the channel of the access transistor is coupled to one end of the storage capacitor.

如申請專利範圍第5項所述顯示面板的驅動系統，其中：該顯示電晶體的閘極耦接至一控制信號，該控制信號啟動該顯示模式；該顯示電晶體之通道的第一端耦接至該存取電晶體之通道的第二端；及該顯示電晶體之通道的第二端耦接至一像素電極(pixel electrode)。 The driving system of the display panel of claim 5, wherein: the gate of the display transistor is coupled to a control signal, the control signal activates the display mode; and the first end of the channel of the display transistor is coupled The second end of the channel connected to the access transistor; and the second end of the channel of the display transistor is coupled to a pixel electrode.

如申請專利範圍第4項所述顯示面板的驅動系統，更包含：一裝置用以提供掃描信號，以開啟其中一分支的存取電晶體，而同時關閉另一分支的存取電晶體；及一裝置用以提供控制信號，以關閉其中一分支的顯示電晶體，而同時開啟另一分支的顯示模式。 The driving system of the display panel according to item 4 of the patent application scope further includes: a device for providing a scan signal to turn on an access transistor of one of the branches while simultaneously turning off the access transistor of the other branch; and a device for providing a control signal to turn off the display transistor of one of the branches, At the same time, the display mode of another branch is turned on.

一種顯示面板的驅動方法，該顯示面板包含複數個像素單元，排列成矩陣形式，每一該像素單元包含至少第一分支及第二分支，其中第一次資料線(sub-data line)可控地對應至該第一分支，且第二次資料線可控地對應至該第二分支，該驅動方法包含：於一圖框中存取該第一分支，使得該第一次資料線所提供之影像資料得以轉移及儲存於該第一分支中，並同時顯示該第二分支所儲存的影像資料；及於一相鄰圖框中存取該第二分支，使得該第二次資料線所提供之影像資料得以轉移及儲存於該第二分支中，並同時顯示該第一分支所儲存的影像資料。 A driving method of a display panel, the display panel comprising a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least a first branch and a second branch, wherein the first sub-data line is controllable Corresponding to the first branch, and the second data line controllably corresponding to the second branch, the driving method includes: accessing the first branch in a frame, so that the first data line provides The image data is transferred and stored in the first branch, and the image data stored in the second branch is simultaneously displayed; and the second branch is accessed in an adjacent frame, so that the second data line is The provided image data is transferred and stored in the second branch, and the image data stored in the first branch is simultaneously displayed.

如申請專利範圍第8項所述顯示面板的驅動方法，其中上述之顯示面板為矽基液晶(LCoS)面板。 The driving method of the display panel according to claim 8, wherein the display panel is a liquid crystal on silicon (LCoS) panel.

如申請專利範圍第8項所述顯示面板的驅動方法，其中上述之影像資料係儲存於該第一或第二分支的儲存電容。 The method for driving a display panel according to claim 8, wherein the image data is stored in a storage capacitor of the first or second branch.

如申請專利範圍第8項所述顯示面板的驅動方法，更包含：當該第一分支被存取時，緩衝(buffer)該第一分支所儲存的影像資料；及當該第二分支被存取時，緩衝該第二分支所儲存的影像資料。 The driving method of the display panel of claim 8, further comprising: buffering the image data stored in the first branch when the first branch is accessed; and when the second branch is stored When capturing, the image data stored in the second branch is buffered.

如申請專利範圍第11項所述顯示面板的驅動方法，其中上述之儲存影像資料受到緩衝，用以避免所儲存之影像資料連接至像素電極。 The driving method of the display panel according to claim 11, wherein the stored image data is buffered to prevent the stored image data from being connected to the pixel electrode.

如申請專利範圍第11項所述顯示面板的驅動方法，其中：位於同一列的第一分支受到第一掃描線的第一掃描信號所存取；及位於同一列的第二分支受到第二掃描線的第二掃描信號所存取。 The driving method of the display panel according to claim 11, wherein: the first branch located in the same column is accessed by the first scan signal of the first scan line; and the second branch located in the same column is subjected to the second scan The second scan signal of the line is accessed.

如申請專利範圍第13項所述顯示面板的驅動方法，其中：位於第一次資料線之影像資料藉由第一開關轉移至同一行的第一分支；及位於第二次資料線之影像資料藉由第二開關轉移至同一行的第二分支。 The driving method of the display panel according to claim 13, wherein: The image data located on the first data line is transferred to the first branch of the same line by the first switch; and the image data of the second data line is transferred to the second branch of the same line by the second switch.

一種顯示面板的驅動系統，包含：複數個像素單元，排列成矩陣形式，每一該像素單元包含至少二分支(branches)；二條次資料線(sub-data line)，耦接至一資料驅動器並對應於該像素單元的一行，該二條次資料線分別對應至該二分支；及一多工器，用以將位在相鄰像素單元間的該二條次資料線進行多工分派(multiplex)，並將該多工器之多工輸出耦接至一共享資料線，其共享於相鄰的該像素單元。 A driving system for a display panel, comprising: a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least two branches; a sub-data line coupled to a data driver and Corresponding to a row of the pixel unit, the two secondary data lines respectively correspond to the two branches; and a multiplexer for multiplexing the two secondary data lines located between adjacent pixel units. And multiplexing the multiplexer output of the multiplexer to a shared data line, which is shared by the adjacent pixel unit.

如申請專利範圍第15項所述顯示面板的驅動系統，其中上述之二分支分別耦接至該分享資料線。 The driving system of the display panel of claim 15, wherein the two branches are respectively coupled to the shared data line.

如申請專利範圍第15項所述顯示面板的驅動系統，其中上述之顯示面板為矽基液晶(LCoS)面板。 The driving system of the display panel according to claim 15, wherein the display panel is a liquid crystal on silicon (LCoS) panel.

如申請專利範圍第15項所述顯示面板的驅動系統，更包含至少二掃描線，其對應於每一列的該像素單元，其中該像素單元的二分支分別對應耦接至該二掃描線。 The driving system of the display panel of claim 15, further comprising at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines.

如申請專利範圍第18項所述顯示面板的驅動系統，其中上述每一分支包含：一存取電晶體，受到對應掃描線之存取(addressed)；一儲存電容，用以接收及儲存對應之共享資料線上的影像資料；及一顯示電晶體，藉以讓該儲存之影像資料得以顯示。 The driving system of the display panel of claim 18, wherein each of the branches comprises: an access transistor, accessed by a corresponding scan line; and a storage capacitor for receiving and storing the corresponding Sharing the image data on the data line; and displaying a transistor to display the stored image data.

如申請專利範圍第19項所述顯示面板的驅動系統，其中：該存取電晶體之閘極耦接至對應的掃描線；該存取電晶體之通道的第一端耦接至對應的共享資料線；及該存取電晶體之通道的第二端耦接至該儲存電容的一端。 The driving system of the display panel of claim 19, wherein: the gate of the access transistor is coupled to the corresponding scan line; and the first end of the channel of the access transistor is coupled to the corresponding share The data line; and the second end of the channel of the access transistor is coupled to one end of the storage capacitor.

如申請專利範圍第20項所述顯示面板的驅動系統，其中：該顯示電晶體的閘極耦接至一控制信號，該控制信號啟動該顯示模式；該顯示電晶體之通道的第一端耦接至該存取電晶體之通道的第二端；及該顯示電晶體之通道的第二端耦接至一像素電極(pixel electrode)。 The driving system of the display panel according to claim 20, wherein: The gate of the display transistor is coupled to a control signal, the control signal activates the display mode; the first end of the channel of the display transistor is coupled to the second end of the channel of the access transistor; and the display The second end of the channel of the transistor is coupled to a pixel electrode.

如申請專利範圍第21項所述顯示面板的驅動系統，其中第一像素單元第二分支的存取電晶體通道第一端共享於第二像素單元第一分支的存取電晶體通道第一端，其中該第一像素單元相鄰於該第二像素單元。 The driving system of the display panel according to claim 21, wherein the first end of the access transistor channel of the second branch of the first pixel unit is shared with the first end of the access transistor channel of the first branch of the second pixel unit The first pixel unit is adjacent to the second pixel unit.

一種顯示面板的驅動方法，該顯示面板包含複數個像素單元，排列成矩陣形式，每一該像素單元包含至少二分支，該驅動方法包含：將位在相鄰像素單元間的二條次資料線(sub-data line)進行多工分派(multiplex)，並將多工輸出耦接至一共享資料線，其共享於相鄰的像素單元間，其中一像素行對應有二條次資料線，且該二條次資料線耦接至一資料驅動器；存取該多工輸出之次資料線所對應的分支，使得該多工輸出次資料線的影像資料得以儲存於該存取分支；及顯示該儲存影像資料。 A driving method of a display panel, the display panel comprising a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least two branches, the driving method comprising: placing two sub-data lines between adjacent pixel units ( Sub-data line) performs multiplex and couples the multiplexed output to a shared data line, which is shared between adjacent pixel units, wherein one pixel row corresponds to two secondary data lines, and the two The secondary data line is coupled to a data driver; accessing the branch corresponding to the secondary data line of the multiplex output, so that the image data of the multiplexed output data line is stored in the access branch; The stored image data is displayed.

如申請專利範圍第23項所述顯示面板的驅動方法，其中上述之顯示面板為矽基液晶(LCoS)面板。 The driving method of the display panel according to claim 23, wherein the display panel is a liquid crystal on silicon (LCoS) panel.

如申請專利範圍第23項所述顯示面板的驅動方法，更包含至少二掃描線，其對應於每一列的該像素單元，其中該像素單元的二分支分別對應耦接至該二掃描線。 The driving method of the display panel of claim 23, further comprising at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines.

如申請專利範圍第25項所述顯示面板的驅動方法，其中上述每一分支包含：一存取電晶體，受到對應掃描線之存取(addressed)；一儲存電容，用以接收及儲存對應之共享資料線上的影像資料；及一顯示電晶體，藉以讓該儲存之影像資料得以顯示。 The method for driving a display panel according to claim 25, wherein each of the branches comprises: an access transistor, accessed by a corresponding scan line; and a storage capacitor for receiving and storing the corresponding Sharing the image data on the data line; and displaying a transistor to display the stored image data.

如申請專利範圍第26項所述顯示面板的驅動方法，於存取模式期間，該存取電晶體被開啟，而該顯示電晶體被關閉。 The driving method of the display panel according to claim 26, wherein during the access mode, the access transistor is turned on and the display transistor is turned off.

如申請專利範圍第26項所述顯示面板的驅動方法，於顯示模式期間，該顯示電晶體被開啟，而該存取電晶體被關閉。 The driving method of the display panel according to claim 26, wherein during the display mode, the display transistor is turned on and the access transistor is turned off.