TWI419302B - 封裝製程 - Google Patents
封裝製程 Download PDFInfo
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- TWI419302B TWI419302B TW099104480A TW99104480A TWI419302B TW I419302 B TWI419302 B TW I419302B TW 099104480 A TW099104480 A TW 099104480A TW 99104480 A TW99104480 A TW 99104480A TW I419302 B TWI419302 B TW I419302B
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- Prior art keywords
- semiconductor substrate
- pads
- carrier
- forming
- wafers
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- 238000000034 method Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 170
- 239000000758 substrate Substances 0.000 claims description 157
- 235000012431 wafers Nutrition 0.000 claims description 72
- 229910000679 solder Inorganic materials 0.000 claims description 37
- 239000008393 encapsulating agent Substances 0.000 claims description 31
- 238000012858 packaging process Methods 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000084 colloidal system Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 46
- 239000012790 adhesive layer Substances 0.000 description 12
- 238000004806 packaging method and process Methods 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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Description
本發明是有關於一種封裝結構,且特別是有關於一種堆疊式半導體元件封裝結構。
在現今的資訊社會中,使用者均是追求高速度、高品質、多功能性的電子產品。就產品外觀而言,電子產品的設計是朝向輕、薄、短、小的趨勢邁進。因此,電子封裝技術發展出諸如堆疊式半導體元件封裝等多半導體元件封裝技術。
堆疊式半導體元件封裝是利用垂直堆疊的方式將多個半導體元件封裝於同一封裝結構中,如此可提升封裝密度以使封裝體小型化,且可利用立體堆疊的方式縮短半導體元件之間的訊號傳輸的路徑長度,以提升半導體元件之間訊號傳輸的速度,並可將不同功能的半導體元件組合於同一封裝體中。
習知一種堆疊式半導體元件封裝的製作方法是將晶片堆疊於具有直通矽晶穿孔(Through Silicon Via,TSV)的晶圓載板上,以進行晶圓級的封裝,並且在完成封裝後對晶圓載板連同其上的封膠進行切割,以形成多個獨立的封裝單元。每個獨立的封裝單元可以藉由形成在晶圓底面的銲球與外部的電路板連接。
然而,已知技術是先在晶圓載板底部形成銲球,之後直接將帶有銲球的晶圓載板配置於載具上,並使晶圓載板上的銲球埋入載具上的黏著膠層內,直到完成晶圓級封裝步驟,且晶圓載板與載具分離之後,才露出位於晶圓載板底面的銲球。因此,當晶圓載板的底面形成尺寸較大的銲球時,此大尺寸的銲球將難以與載具上的黏著膠層穩固結合,從而影響製程可靠度。
本發明提供一種封裝製程,其可以避免習知堆疊式半導體元件封裝應用晶圓級封裝製程時,因為採用大尺寸銲球,而導致晶圓載板與載具之間接合不良,影響製程可靠度的問題。
為具體描述本發明之內容,在此提出一種封裝製程。首先,將一半導體基材配置於一載具上,其中半導體基材具有面向載具的一第一表面以及位於第一表面上的多個接點。由半導體基材相對於第一表面的背側來薄化半導體基材,其中薄化後的半導體基材具有相對於第一表面的一第二表面。形成多個直通矽穿孔(Through Silicon Via,TSV)於薄化後的該半導體基材中。直通矽穿孔分別對應並連接接點。接著,形成多個第一接墊於半導體基材的第二表面上,所述第一接墊分別對應並連接直通矽穿孔。接合多個晶片至半導體基材的第二表面,其中所述晶片分別電性連接至所對應的第一接墊。形成一封裝膠體於半導體基材的第二表面上,其中封裝膠體覆蓋晶片以及第一接墊。分離半導體基材與載具,然後形成多個銲球於半導體基材的第一表面上,其中所述銲球分別電性連接至所對應的接點。之後,同時裁切封裝膠體以及半導體基材,以形成多個封裝單元。
在本發明之一實施例中,所述封裝製程更包括在將半導體基材配置於載具之前,形成一重佈線層於半導體基材的第一表面上。此重佈線層的表面具有多個第二接墊,且第二接墊分別電性連接至接點。此外,所述封裝製程更可在每一第二接墊上形成一球底金屬層。
在本發明之一實施例中,所述封裝製程更包括在分離半導體基材與載具之後並且在形成銲球之前,形成一重佈線層於半導體基材的第一表面上。所述重佈線層的表面具有多個第二接墊,且第二接墊分別電性連接至接點。此外,所述封裝製程更包括在每一第二接墊上形成一球底金屬層。
在本發明之一實施例中,所述之封裝製程更包括在每一第一接墊上形成一球底金屬層。
在本發明之一實施例中,接合晶片至半導體基材的方法包括以覆晶倒裝接合技術將每一晶片經由多個導電凸塊接合至所對應的第一接墊。
在本發明之一實施例中,所述封裝製程更包括在接合晶片至半導體基材之後並且在形成封裝膠體之前,形成一底膠於每一晶片與半導體基材之間,其中底膠包覆導電凸塊。
基於上述,本發明是先將半導體基材配置於載具上,並待完成晶圓級封裝步驟,且半導體基材與載具分離之後,才形成銲球於半導體基材的第一表面上。因此,本發明提出的封裝製程可以避免採用大尺寸銲球可能導致的半導體基材與載具之間接合不良的問題,有助於提升製程可靠度。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
相較於已知技術先在晶圓載板底部形成銲球,並將帶有銲球的晶圓載板配置於載具上,使晶圓載板上的銲球埋入載具上的黏著膠層內的製程,本發明是先將半導體基材與載具接合,待完成晶圓級封裝製程且半導體基材與載具分離之後,再於半導體基材底部的第一表面上形成銲球。以下列舉多個實施例來說明本發明之製程方法。
圖1A~1K依序繪示依據本發明之一實施例的一種封裝製程。
首先,如圖1A所示,提供半導體基材110,其例如是常見的矽晶圓或是由其他半導體材料製成。半導體基材110具有一第一表面110a以及位於第一表面110a上的多個接點112。半導體基材110內部可依現有技術製作內連線結構或是內埋主動或被動元件(未繪示)。此外,半導體基材110的第一表面110a上可覆蓋保護層114,以保護接點112。
需注意的是,本實施例的半導體基材110做為晶圓級封裝製程的載板,可同時與一或多個晶片進行封裝,惟因圖面大小的限制,本實施例僅繪出局部的半導體基材110。
接著,如圖1B所示,在某些情況下,本實施例可以選擇在半導體基材110的第一表面110a上,即保護層114上,另外製作一重佈線層(Redistribution Layer)120。重佈線層120的表面具有多個第二接墊122,其藉由重佈線層120內部的線路分別電性連接至半導體基材110的第一表面110a上的接點112,用以重新調整半導體基材110之對外接點的位置。在此,第二接墊122上還可以形成球底金屬層(Under Bump Metallurgy Layer,UBM layer)122a,藉以增加後續形成的銲球與第二接墊122的接著效果。
本實施例之後的步驟係以半導體基材110表面形成有重佈線層(Redistribution Layer)120的情況接續說明。
承上述,接著,如圖1C所示,將半導體基材110的第一表面110a朝向載具130而配置於載具130上。載具130表面例如塗佈有黏著層132,而半導體基材110藉由黏著層132被固定於載具130上,其中位於重佈線層120表面的第二接墊122直接與黏著層132接觸。同時,由半導體基材110相對於第一表面110a的背側來薄化半導體基材110,使得薄化後的半導體基材110具有相對於第一表面110a的一第二表面110b。
然後,如圖1D所示,形成多個直通矽穿孔(Through Silicon Via,TSV)140於半導體基材110中。直通矽穿孔140分別對應並連接至接點112,並且分別藉由重佈線層120內部的線路連接至第二接墊122。
接著,如圖1E所示,形成多個第一接墊116於半導體基材110的第二表面110b上。第一接墊116分別對應並連接直通矽穿孔140。此外,本實施例可以選擇在第一接墊116上形成球底金屬層116a,藉以增加後續晶片上的凸塊與第一接墊116的接著效果。
之後,如圖1F所示,接合多個晶片150至半導體基材110的第二表面110b,使晶片150電性連接至第二表面110b上的第一接墊116。在本實施例中,例如是以覆晶倒裝接合技術將每一晶片150經由其底部的多個導電凸塊152接合至所對應的第一接墊116。
然後,如圖1G所示,本實施例可以選擇形成一底膠160於每一晶片150與半導體基材110之間,使底膠160包覆導電凸塊152。然而,本實施例也可以選擇不形成底膠160而直接進行後續製程。
如圖1H所示,在接合晶片150與半導體基材110之後,形成一封裝膠體170於半導體基材110的第二表面110b上,使封裝膠體170覆蓋半導體基材110上所有的晶片150、導電凸塊152以及第一接墊116。若本實施例選擇在形成封裝膠體170之前形成底膠160於晶片150與半導體基材110之間,則此處形成的封裝膠體170會覆蓋底膠160。反之,若本實施例選擇不進行如圖1G所示的步驟,則此處形成的封裝膠體170會取代底膠160,直接填入導電凸塊152之間的空隙。
接著,如圖1I所示,分離半導體基材110與載具120,以暴露出重佈線層120上的第二接墊122。並且,如圖1J在分離半導體基材110與載具120之後,形成多個銲球180於重佈線層120上的第二接墊122,使銲球180經由重佈線層120分別電性連接至所對應的接點112。
之後,如圖1K所示,進行一單體化製程,即同時裁切封裝膠體170以及半導體基材110,以形成多個封裝單元102。由於封裝膠體170以及半導體基材110是同時被裁切,因此封裝膠體170的側面179會與半導體基材110的側面119對齊,而晶片150被包覆於封裝膠體170內。
基於上述,本實施例先將半導體基材110配置於載具120上,並待完成圖1D~1I的晶圓級封裝步驟之後,才形成銲球180於半導體基材110的第一表面110a上。因此,本實施例不需考慮在半導體基材110底部製作大尺寸銲球180可能導致的半導體基材110與載具120之間接合不良的問題,有助於提升製程可靠度與選擇性。
前述實施例在將半導體基材配置於載具之前,便先在半導體基材上形成重佈線層,然而本發明並不限於此。舉例而言,本發明亦可以選擇在完成晶圓級封裝且分離半導體基材與載具之後,再形成重佈線層於半導體基材上。下文將再舉另一實施例進行說明。
圖2A~2K依序繪示依據本發明之另一實施例的一種封裝製程。
首先,如圖2A所示,提供半導體基材210,其例如是常見的矽晶圓或是由其他半導體材料製成。半導體基材210具有一第一表面210a以及位於第一表面210a上的多個接點212。半導體基材210內部可依現有技術製作製作內連線結構或是內埋主動或被動元件(未繪示)。此外,半導體基材210的第一表面210a上可覆蓋保護層214,以保護接點212。
需注意的是,本實施例的半導體基材210做為晶圓級封裝製程的載板,可同時與一或多個晶片進行封裝,惟因圖面大小的限制,本實施例僅繪出局部的半導體基材210。
接著,如圖2B所示,將半導體基材210的第一表面210a朝向載具230而配置於載具230上。載具230表面例如塗佈有黏著層232,而半導體基材210藉由黏著層232被固定於載具230上,其中位於半導體基材210的第一表面210a上的接點212直接與黏著層232接觸。同時,由半導體基材210相對於第一表面210a的背側來薄化半導體基材210,使得薄化後的半導體基材210具有相對於第一表面210a的一第二表面210b。
然後,如圖2C所示,形成多個直通矽穿孔(Through Silicon Via,TSV)240於半導體基材210中。直通矽穿孔240分別對應並連接至接點212。
接著,如圖2D所示,形成多個第一接墊216於半導體基材210的第二表面210b上。第一接墊216分別對應並連接直通矽穿孔240。此外,本實施例可以選擇在第一接墊216上形成球底金屬層216a,藉以增加後續晶片上的凸塊與第一接墊216的接著效果。
之後,如圖2E所示,接合多個晶片250至半導體基材210的第二表面210b,使晶片250電性連接至第二表面210b上的第一接墊216。在本實施例中,例如是以覆晶倒裝接合技術將每一晶片250經由其底部的多個導電凸塊252接合至所對應的第一接墊216。
然後,如圖2F所示,本實施例可以選擇形成一底膠260於每一晶片250與半導體基材210之間,使底膠260包覆導電凸塊252。然而,在其他實施例中,也可以選擇不形成底膠260而直接進行後續製程。
如圖2G所示,在接合晶片250與半導體基材210之後,形成一封裝膠體270於半導體基材210的第二表面210b上,使封裝膠體覆蓋晶片250、導電凸塊252以及第一接墊216。若本實施例選擇在形成封裝膠體270之前形成底膠260於晶片250與半導體基材210之間,則此處形成的封裝膠體270會覆蓋底膠260。反之,若本實施例選擇不進行如圖2F所示的步驟,則此處形成的封裝膠體270會取代底膠260,直接填入導電凸塊252之間的空隙。
接著,如圖2H所示,分離半導體基材210與載具220,以暴露出半導體基材210的第一表面210a上的接點212。並且,如圖2I所示,在某些情況下,本實施例可以選擇在半導體基材210的第一表面210a上,即保護層214上,另外製作一重佈線層220。重佈線層220的表面具有多個第二接墊222,其藉由重佈線層220內部的線路分別電性連接至半導體基材210的第一表面210a上的接點212,用以重新調整半導體基材210之對外接點的位置。在此,第二接墊222上還可以形成球底金屬層222a,藉以增加後續形成的銲球與第二接墊222的接著效果。
本實施例之後的步驟係以半導體基材110表面形成有重佈線層(Redistribution Layer)120的情況接續說明。
之後,如圖2J所示,在分離半導體基材210與載具220之後,形成多個銲球280於重佈線層220上的第二接墊222,使銲球280經由重佈線層220分別電性連接至所對應的接點212。
然後,如圖2K所示,進行一單體化製程,即同時裁切封裝膠體270以及半導體基材210,以形成多個封裝單元202。由於封裝膠體270以及半導體基材210是同時被裁切,因此封裝膠體270的側面279會與半導體基材210的側面219對齊,而晶片250被包覆於封裝膠體270內。
基於上述,本實施例先將半導體基材210配置於載具220上,並待完成圖2C~2I的晶圓級封裝步驟之後,才形成銲球280於半導體基材210的第一表面210a上。因此,本實施例不需考慮在半導體基材210底部製作大尺寸銲球280可能導致的半導體基材210與載具220之間接合不良的問題,有助於提升製程可靠度與選擇性。另一方面,相較於前述實施例,本實施例選擇在完成晶圓級封裝且分離半導體基材與載具之後,才形成重佈線層於半導體基材上。
前述多個實施例是選擇先對半導體基材進行薄化,再於半導體基材中製作多個直通矽穿孔。然而,在本發明其他實施例中,亦可以先在半導體基材中製作導電孔道,再對半導體基材進行薄化,使導電孔道露出半導體基材,形成多個直通矽穿孔。
圖3A~3E依序繪示依據本發明之一實施例的一種封裝製程的部份流程。
首先,如圖3A所示,提供半導體基材310,其例如是常見的矽晶圓或是由其他半導體材料製成。半導體基材310具有一第一表面310a以及位於第一表面310a上的多個接點312。半導體基材310內還具有多個導電孔道342,分別對應並連接至接點312,且半導體基材310內部可依現有技術製作製作內連線結構或是內埋主動或被動元件(未繪示)。此外,半導體基材310的第一表面310a上可覆蓋保護層314,以保護接點312。
需注意的是,本實施例的半導體基材310做為晶圓級封裝製程的載板,可同時與一或多個晶片進行封裝,惟因圖面大小的限制,本實施例僅繪出局部的半導體基材310。
接著,如圖3B所示,如同前述實施例所述,本實施例可以選擇在半導體基材310的第一表面310a上,即保護層314上,另外製作一重佈線層(Redistribution Layer)320。重佈線層320的表面具有多個接墊322,其藉由重佈線層320內部的線路分別電性連接至半導體基材310的第一表面310a上的接點312,用以重新調整半導體基材310之對外接點的位置。在此,接墊322上還可以形成球底金屬層322a,藉以增加後續形成的銲球與接墊322的接著效果。
本實施例之後的步驟係以半導體基材310表面形成有重佈線層320的情況接續說明。
承上述,接著,如圖3C所示,將半導體基材310的第一表面310a朝向載具330而配置於載具330上。載具330表面例如塗佈有黏著層332,而半導體基材310藉由黏著層332被固定於載具330上,其中位於重佈線層320表面的接墊322直接與黏著層332接觸。
並且,如圖3D所示,由半導體基材310相對於第一表面310a的背側來薄化半導體基材310,其中薄化後的半導體基材310具有相對於第一表面310a的一第二表面310b,且每一導電孔道342的一端342a凸出第二表面310b而成為一直通矽穿孔340。直通矽穿孔340分別藉由重佈線層320內部的線路連接至接墊322。
然後,如圖3E所示,接合多個晶片350至露出的直通矽穿孔340。在本實施例中,例如是以覆晶倒裝接合技術將每一晶片350經由其底部的多個導電凸塊352接合至所對應的直通矽穿孔340。導電凸塊352與所對應的直通矽穿孔340例如藉由銲料370連接。導電凸塊352可以是如圖1D中所繪示的柱狀凸塊或是其他型態的凸塊。
之後,可進行如圖1G~1K的步驟,以形成如圖1K所繪示的封裝單元102。詳細技術內容可參照前述實施例的描述,此處不再贅述。
另外,請參考圖2A~2K所繪示的實施例,除了在將半導體基材配置於載具之前,便先在半導體基材上形成重佈線層的技術方案之外,結合前述之直通矽穿孔的製作方法,本發明亦可以選擇在完成晶圓級封裝且分離半導體基材與載具之後,才形成重佈線層於半導體基材上。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102、202...封裝單元
110、210、310...半導體基材
110a、210a、310a...第一表面
110b、210b、310b...第二表面
112、212、312...接點
114、214、314...保護層
116、216...第一接墊
116a、216a...球底金屬層
119、219...半導體基材的側面
120、220、320‧‧‧重佈線層
122、222‧‧‧第二接墊
322‧‧‧接墊
122a、222a、322a‧‧‧球底金屬層
130、230、330‧‧‧載具
132、232、332‧‧‧黏著層
140、240、340‧‧‧直通矽穿孔
342‧‧‧導電孔道
342a‧‧‧導電孔道的一端
150、250、350‧‧‧晶片
152、252、352‧‧‧導電凸塊
160、260‧‧‧底膠
170、270‧‧‧封裝膠體
370‧‧‧銲料
179、279‧‧‧封裝膠體的側面
180、280‧‧‧銲球
圖1A~1K依序繪示依據本發明之一實施例的一種封裝製程。
圖2A~2K依序繪示依據本發明之另一實施例的一種封裝製程。
圖3A~3E依序繪示依據本發明之一實施例的一種封裝製程的部份流程。
102...封裝單元
110...半導體基材
110a...第一表面
110b...第二表面
112...接點
114...保護層
116...第一接墊
116a...球底金屬層
119...半導體基材的側面
120...重佈線層
122...第二接墊
122a...球底金屬層
140...直通矽穿孔
150...晶片
152...導電凸塊
160...底膠
170...封裝膠體
179...封裝膠體的側面
180...銲球
Claims (9)
- 一種封裝製程,包括:將一半導體基材配置於一載具上,其中該半導體基材具有面向該載具的一第一表面以及位於該第一表面上的多個接點,其中在將該半導體基材配置於該載具之前,形成一重佈線層於該半導體基材的該第一表面上,該重佈線層的表面具有多個第二接墊,該些第二接墊分別電性連接至該些接點;由該半導體基材相對於該第一表面的背側來薄化該半導體基材,薄化後的該半導體基材具有相對於該第一表面的一第二表面;形成多個直通矽穿孔(Through Silicon Via,TSV)於該半導體基材中,該些直通矽穿孔分別對應並連接該些接點;形成多個第一接墊於該半導體基材的該第二表面上,該些第一接墊分別對應並連接該些直通矽穿孔;接合多個晶片至該半導體基材的該第二表面,該些晶片分別電性連接至所對應的該些第一接墊;形成一封裝膠體於該半導體基材的該第二表面上,該封裝膠體覆蓋該些晶片以及該些第一接墊;分離該半導體基材與該載具,之後,形成多個銲球於該半導體基材的該第一表面上,該些銲球分別電性連接至所對應的該些第二接墊;以及同時裁切該封裝膠體以及該半導體基材,以形成多個封裝單元。
- 如申請專利範圍第1項所述之封裝製程,更包括在每一第二接墊上形成一球底金屬層。
- 如申請專利範圍第1項所述之封裝製程,更包括在每一第一接墊上形成一球底金屬層。
- 如申請專利範圍第1項所述之封裝製程,其中接合該些晶片至該半導體基材的方法包括以覆晶倒裝接合技術將每一晶片經由多個導電凸塊接合至所對應的該些第一接墊。
- 如申請專利範圍第4項所述之封裝製程,更包括在接合該些晶片至該半導體基材之後並且在形成該封裝膠體之前,形成一底膠於每一晶片與該半導體基材之間,該底膠包覆該些導電凸塊。
- 一種封裝製程,包括:將一半導體基材配置於一載具上,其中該半導體基材具有面向該載具的一第一表面以及位於該第一表面上的多個接點,其中在將該半導體基材配置於該載具之前,形成一重佈線層於該半導體基材的該第一表面上,該重佈線層的表面具有多個接墊,該些接墊分別電性連接至該些接點,且該半導體基材內具有多個導電孔道,分別對應並連接至該些接點;由該半導體基材相對於該第一表面的背側來薄化該半導體基材,薄化後的該半導體基材具有相對於該第一表面的一第二表面,且每一導電孔道的一端凸出該第二表面而成為一直通矽穿孔; 接合多個晶片至該半導體基材的該第二表面,該些晶片分別電性連接至所對應的該些直通矽穿孔;形成一封裝膠體於該半導體基材的該第二表面上,該封裝膠體覆蓋該些晶片;分離該半導體基材與該載具,之後,形成多個銲球於該半導體基材的該第一表面上,該些銲球分別電性連接至所對應的該些第二接墊;以及同時裁切該封裝膠體以及該半導體基材,以形成多個封裝單元。
- 如申請專利範圍第6項所述之封裝製程,更包括在每一接墊上形成一球底金屬層。
- 如申請專利範圍第1項所述之封裝製程,其中接合該些晶片至該半導體基材的方法包括以覆晶倒裝接合技術將每一晶片經由多個導電凸塊接合至所對應的該些第一接墊。
- 如申請專利範圍第8項所述之封裝製程,更包括在接合該些晶片至該半導體基材之後並且在形成該封裝膠體之前,形成一底膠於每一晶片與該半導體基材之間,該底膠包覆該些導電凸塊。
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8687546B2 (en) | 2009-12-28 | 2014-04-01 | Intel Corporation | Efficient uplink SDMA operation |
KR20160075845A (ko) * | 2010-03-31 | 2016-06-29 | 에베 그룹 에. 탈너 게엠베하 | 양면에 칩이 장착되는 웨이퍼를 제작하기 위한 방법 |
US8932910B2 (en) * | 2010-05-20 | 2015-01-13 | Ev Group E. Thallner Gmbh | Method for producing chip stacks, and a carrier for carrying out the method |
TWI469312B (zh) | 2012-03-09 | 2015-01-11 | Ind Tech Res Inst | 晶片堆疊結構及其製作方法 |
TWI536468B (zh) * | 2012-09-10 | 2016-06-01 | 矽品精密工業股份有限公司 | 封裝件之製法 |
TWI492350B (zh) * | 2012-11-20 | 2015-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
TWI711095B (zh) * | 2019-08-21 | 2020-11-21 | 欣興電子股份有限公司 | 封裝結構及其製備方法 |
CN111128910B (zh) * | 2019-12-10 | 2022-04-15 | 深圳宏芯宇电子股份有限公司 | 芯片堆叠封装方法及芯片堆叠结构 |
CN111739840B (zh) * | 2020-07-24 | 2023-04-11 | 联合微电子中心有限责任公司 | 一种硅转接板的制备方法及硅转接板的封装结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US20060151870A1 (en) * | 2002-11-21 | 2006-07-13 | Nec Corporation | Semiconductor device, wiring substrate, and method for manufacturing wiring substrate |
US20070184583A1 (en) * | 2006-02-08 | 2007-08-09 | Oki Electric Industry Co., Ltd. | Method for fabricating semiconductor package |
US20080315372A1 (en) * | 2007-06-20 | 2008-12-25 | Stats Chippac, Ltd. | Wafer Level Integration Package |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
US6424034B1 (en) * | 1998-08-31 | 2002-07-23 | Micron Technology, Inc. | High performance packaging for microprocessors and DRAM chips which minimizes timing skews |
JP3788268B2 (ja) * | 2001-05-14 | 2006-06-21 | ソニー株式会社 | 半導体装置の製造方法 |
US7189595B2 (en) * | 2001-05-31 | 2007-03-13 | International Business Machines Corporation | Method of manufacture of silicon based package and devices manufactured thereby |
JP3834589B2 (ja) * | 2001-06-27 | 2006-10-18 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
CN101714516A (zh) * | 2001-08-24 | 2010-05-26 | 肖特股份公司 | 用于形成触点的方法及封装的集成电路组件 |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
US6995462B2 (en) * | 2003-09-17 | 2006-02-07 | Micron Technology, Inc. | Image sensor packages |
US7247517B2 (en) * | 2003-09-30 | 2007-07-24 | Intel Corporation | Method and apparatus for a dual substrate package |
US7919410B2 (en) * | 2007-03-14 | 2011-04-05 | Aptina Imaging Corporation | Packaging methods for imager devices |
KR100951284B1 (ko) * | 2007-06-01 | 2010-04-02 | 삼성전기주식회사 | 웨이퍼 레벨 패키지 제조방법 |
SG152086A1 (en) * | 2007-10-23 | 2009-05-29 | Micron Technology Inc | Packaged semiconductor assemblies and associated systems and methods |
US7750459B2 (en) * | 2008-02-01 | 2010-07-06 | International Business Machines Corporation | Integrated module for data processing system |
US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
US8067308B2 (en) * | 2009-06-08 | 2011-11-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support |
US7883991B1 (en) * | 2010-02-18 | 2011-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Temporary carrier bonding and detaching processes |
-
2010
- 2010-02-11 TW TW099104480A patent/TWI419302B/zh active
- 2010-04-23 US US12/766,549 patent/US8338235B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US20060151870A1 (en) * | 2002-11-21 | 2006-07-13 | Nec Corporation | Semiconductor device, wiring substrate, and method for manufacturing wiring substrate |
US20070184583A1 (en) * | 2006-02-08 | 2007-08-09 | Oki Electric Industry Co., Ltd. | Method for fabricating semiconductor package |
US20080315372A1 (en) * | 2007-06-20 | 2008-12-25 | Stats Chippac, Ltd. | Wafer Level Integration Package |
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