TWI419208B - 半導體裝置的製造方法 - Google Patents
半導體裝置的製造方法 Download PDFInfo
- Publication number
- TWI419208B TWI419208B TW099117139A TW99117139A TWI419208B TW I419208 B TWI419208 B TW I419208B TW 099117139 A TW099117139 A TW 099117139A TW 99117139 A TW99117139 A TW 99117139A TW I419208 B TWI419208 B TW I419208B
- Authority
- TW
- Taiwan
- Prior art keywords
- spacer
- gate
- trench
- layer
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 125000006850 spacer group Chemical group 0.000 claims description 68
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 32
- 229910052786 argon Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 238000004544 sputter deposition Methods 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 8
- 238000007517 polishing process Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 183
- 238000000034 method Methods 0.000 description 132
- 230000008569 process Effects 0.000 description 71
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 38
- 229920005591 polysilicon Polymers 0.000 description 38
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 22
- 229910052782 aluminium Inorganic materials 0.000 description 21
- 238000001039 wet etching Methods 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000005240 physical vapour deposition Methods 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 5
- 239000000908 ammonium hydroxide Substances 0.000 description 5
- 239000008367 deionised water Substances 0.000 description 5
- 229910021641 deionized water Inorganic materials 0.000 description 5
- 238000011049 filling Methods 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 238000000671 immersion lithography Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002164 ion-beam lithography Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000009736 wetting Methods 0.000 description 3
- RYHBNJHYFVUHQT-UHFFFAOYSA-N 1,4-Dioxane Chemical compound C1COCCO1 RYHBNJHYFVUHQT-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- -1 LaSiO Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910017121 AlSiO Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical compound [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本發明係有關於一種半導體製程,特別是有關於一種具有金屬閘極的半導體裝置的製造方法。
半導體積體電路(integrated circuit,IC)工業歷經了快速的成長。在IC材料與設計的技術進展造就了各個IC世代,每一世代的電路都比前世代來得更小更為複雜。然而,這些進展卻增加IC製造及加工的複雜度,而因應這些進展,IC製造及加工需要類似的演進。
在IC進展課題中,功能密度(即,單位晶片面積的內連裝置數量)普遍增加,而幾何尺寸(即,所使用的製程能形成的最小部件(或線))則下降。上述尺寸微縮製程因生產效率的增加及成本的降低而有所助益。而降低尺寸比例產生相對較高的功率消耗(power dissipation)值,其可藉由低功耗裝置的使用而獲得解決,例如互補式金氧半(complementary metal-oxide-semiconductor,CMOS)裝置。CMOS裝置通常具有閘極氧化層及多晶矽閘極電極。而當特徵尺寸(feature size)持續下降時,這些裝置的製造希望能以高介電常數(high-k)材料取代閘極氧化層,且以金屬材料取代多晶矽閘極電極,以改善裝置效能。然而,當整合高介電常數材料/金屬閘極特徵於CMOS製程時會因為於各種因素而引起一些問題,例如使用於多晶矽閘極取代(replaced polysilicon gate,RPG)(Lg~25.5nm)的閘極溝槽寬度變得非常窄(例如,NMOS小於10nm,而PMOS小於2nm)。上述窄溝槽具有一架橋跨越溝槽上半部。換句話說,用於潤濕(wetting)閘極金屬填充(例如,鋁金屬填充)的空間非常窄小。因此,架橋會造成閘極金屬填充在填入溝槽之後,使金屬具有孔洞。
因此,需要改進閘極金屬填充及其製造方法。
在一實施例中,一種半導體裝置的製造方法,包括提供一半導體基底及在半導體基底上方形成一閘極結構。閘極結構包括一第一間隙壁及與第一件隙壁隔開的一第二間隙壁。閘極結構亦包括位於第一間隙壁及第二間隙壁之間的一犧牲閘極。此方法亦包括自閘極結構局部去除犧牲閘極,以形成一未完整溝槽。另外,此方法亦包括局部去除鄰接於未完整溝槽的第一間隙壁及第二間隙壁,以形成未完整溝槽的一擴寬部。再者,此方法亦包括自閘極結構去除犧牲閘極的一剩餘部,以形成一完整溝槽。接著在完整溝槽內形成一高介電常數材料層以及一金屬閘極。
在另一實施例中,一種半導體裝置的製造方法,包括提供一半導體基底及在半導體基底上方形成一絕緣層。此方法亦包括在絕緣層上方形成一第一間隙壁、在絕緣層上方形成與第一間隙壁隔開的一第二間隙壁、及在第一間隙壁及第二間隙壁之間形成一犧牲閘極。此方法更包括局部去除第一間隙壁及第二間隙壁,以在第一間隙壁及第二間隙壁之間形成一擴寬區域。另外,此方法亦包括去除犧牲閘極,以形成一溝槽以及在溝槽內形成一金屬閘極。
又另一實施例中,提供一種半導體裝置的製造方法,包括提供一基底,具有一第一區及一第二區。此方法亦包括在第一區上方形成一第一閘極結構,且在第二區上方形成一第二閘極結構。第一閘極結構包括一第一間隙壁、一第二間隙壁、以及一第一犧牲閘極,且第二閘極結構包括一第三間隙壁、一第四間隙壁、以及一第二犧牲閘極。此方法更包括自第一閘極結構局部去除第一犧牲閘極,以形成一第一未完整溝槽。另外,此方法亦包括自第二閘極結構局部去除第二犧牲閘極,以形成一第二未完整溝槽。再者,此方法包括局部去除第一間隙壁及第二間隙壁,以形成第一未完整溝槽的一擴寬部,且局部去除該第三間隙壁及該第四間隙壁,以形成該第二未完整溝槽的一擴寬部。另外,此方法包括去除第一及第二犧牲閘極的剩餘部,以形成一第一完整溝槽及一第二完整溝槽。再者,此方法包括在第一及第二完整溝槽內分別形成一高介電常數材料層以及在第一及第二完整溝槽內分別形成一金屬閘極。
可瞭解的是以下的揭露內容提供許多不同的實施例或範例,用以實施各個實施例的不同特徵。而以下所揭露的內容是敘述各個構件及其排列方式的特定範例,以求簡化本發明的說明。當然,這些特定的範例並非用以限定本發明。再者,本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方,其表示包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例,亦包含了尚可將額外的特徵形成於第一特徵與第二特徵之間而使第一特徵與第二特徵並未直接接觸的實施例。為了達到簡化及清晰的目的,不同特徵可能以不同尺寸比例繪示。另外,本說明書以下的揭露內容係以”後閘極(gate last)”金屬閘極製程作為範例說明,然而所屬技術領域中具有通常知識者能夠理解本發明對於其他製程及/或其他材料使用的適用性。
請參照第1圖,其為根據本說明書各個型態所繪示出具有金屬閘極的半導體裝置製造方法100的流程圖。亦請參照第2A至2F圖,係根據第1圖的方法100所繪示出半導體裝置200在不同製造階段的剖面示意圖。需注意的是部分的半導體裝置200可利用CMOS製程來製造。因此,可以理解的是在第1圖的方法100進行之前、期間及之後可進行其他製程,且此處對於某些製程僅略作說明。半導體裝置200可製作於一後閘極製程(亦稱作多晶矽閘極取代製程(replacement poly gate process,RPG))中。在一後閘極製程中,可先形成犧牲(dummy)介電層及犧牲多晶矽閘極結構再接著進行正規CMOS製程直至形成內層介電(interlayer dielectric,ILD)層。接著去除犧牲介電層及犧牲多晶矽閘極結構,並以高介電常數(high-k)閘極介電層/金屬閘極結構取而代之。半導體裝置200類似於第4A至4G圖的半導體裝置400。因此,為了達到簡化及清晰的目的,第2及4圖中類似的特徵部件係使用相同的標號。
方法100開始於區塊102,提供一半導體基底。請參照第2A圖,半導體裝置200可包括一半導體基底202,例如一矽基底。基底202亦可包括鍺化矽、砷化鎵、或其他適當的半導體材料。基底202亦可進一步包括摻雜區,例如一P型井及/或N型井(未繪示)。基底202亦可進一步包括其他特徵部件,例如埋入層及/或磊晶層。再者,基底202可為一絕緣層上覆半導體結構,例如絕緣層上覆矽(silicon on insulator,SOI)。在其他實施例中,半導體基底202包括摻雜的磊晶矽、漸變半導體層、及/或進一步包括一半導體層,其位於不同種類的另一半導體層上,例如一矽層位於一鍺化矽層上。在其他範例中,一化合物半導體基底可包括一多層矽結構,或一矽基底可包括一多層化合物半導體結構。基底202可進一步包括摻雜區,例如一P型井及/或N型井(未繪示)。主動區可為NMOS裝置(例如,nFET)或是PMOS裝置(例如,pFET)。
方法100進行至區塊104,在基底202上方形成一閘極結構,閘極結構包括間隙壁(spacer) 227及犧牲多晶矽層/閘極218。閘極結構的製造包括形成各種不同的材料層及蝕刻/圖案化各個材料層以形成一閘極結構。半導體裝置200可包括形成於基底202上方的一犧牲絕緣層215。另外,基底202上方可形成一界面層、一高介電常數材料層、及/或一阻障層且留於最終裝置中。這些不同的材料層將詳述於第4A圖中。絕緣層215可為形成於基底202上的一犧牲介電層。犧牲介電層包括氧化層(例如,熱氧化層或化學氧化層)犧牲介電層的厚度在10至50埃()的範圍。
半導體裝置200亦包括藉由適當沉積製程而形成於絕緣層215上方的一犧牲多晶矽層218。舉例來說可在化學氣相沉積(chemical vapor deposition,CVD)製程中使用一化學氣體以形成多晶矽層218,例如矽烷(SiH4
)、二矽乙烷(Si2
H6
)或二氯矽烷(SiCl2
H4
)。多晶矽層218的厚度在400至2000埃()的範圍。另外,可選擇性地以非晶矽層取代多晶矽層。半導體裝置200可進一步包括在多晶矽層218上方形成一硬式罩幕層(未繪示)。硬式罩幕層可包括氧化矽、氮化矽、氮氧化矽、碳化矽及/或其他適當的介電材料,且可藉由CVD或是物理氣相沉積(physical vapor deposition,PVD)等方法來製作。硬式罩幕層的厚度在100至400埃()的範圍。另外,可使用一抗反射層或是底層抗反射(bottom antireflective coating,BARC)層來改善光阻層圖案化所進行的微影製程。舉例來說,在硬式罩幕層上方形成具有閘極圖案的一光阻圖案層(未繪示)。閘極圖案可藉由乾蝕刻或濕蝕刻而使用於圖案化硬式罩幕層。圖案化的硬式罩幕層可接著藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合而使用於閘極結構的製作。因此,閘極結構可包括絕緣層215、犧牲多晶矽閘極218及一硬式罩幕層(未繪示)。
在形成閘極結構(例如,閘極蝕刻或圖案化)之後,可以理解的是半導體裝置200可進行額外製程(例如,CMOS製程)以形成詳述於第4B圖中各個特徵部件。以化學機械研磨(chemical mechanical polidhing,CMP)製程對裝置200進行平坦化。
方法100進行至區塊106,自閘極結構局部去除犧牲閘極,以在閘極結構內形成未完整溝槽。請參照第2B圖,在裝置200上形成一光阻圖案層(未繪示),以保護局部的裝置200。可藉由光學微影(photolithography)、浸潤式微影(immersion lithography)、離子束微影(ion-beam writing)或其他適當的技術來形成光阻圖案層。舉例來說,光學微影包括旋轉塗佈、軟烤、曝光、後曝烤、顯影、清洗、乾燥及其他適當製程。可藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合去除閘極結構中部分的犧牲閘極218。舉例來說,濕蝕刻包括暴露於含氫氧化物溶液(例如,氫氧化銨(ammonium hydroxide))、去離子水及/或其他適當的蝕刻溶液。可在0℃至100℃下,使用HBr、CF4
、CL2
、O2
或HeO2
來進行多晶矽層218的蝕刻。可在進行一段時間之後停止蝕刻,以留下局部的犧牲多晶矽閘極218(例如,約400埃)。任何適當的製程可使用於終止蝕刻製程。因此,可去除局部的犧牲多晶矽閘極218,以在閘極結構內形成未完整溝槽234。而可藉由剝除法或其他適當至製程來去除任何所使用的光阻圖案層(未繪示)。
方法100進行至區塊108,去除局部的間隙壁227,以形成未完整溝槽的一擴寬部235。在一實施例中,使用乾式氬氣濺射(argon sputtering)局部去除間隙壁227,以形成漏斗型(funnel-shape)溝槽235。氬氣分子尺寸適合製作出漏斗型。然而,其他元素或其他蝕刻/形成方法也可產生可接受的結果。如第2C圖所示,氬氣濺射可在間隙壁227產生稍微傾斜的側邊,而使溝槽具有漏斗型輪廓。在一實施例中,此傾斜角度向下延伸約100埃且朝向溝槽235內部。在一實施例中,剩餘閘極的高度約400埃且閘極寬度約22至27奈米(nm)。然而,氬氣濺射期間間隙壁227內也可能形成其他外型及尺寸。可以理解的是這些方法可使用後高介電常數材料製程(high-k last process)而實施於具有多晶矽閘極取代(replaced polysilicon gate,RPG)的金屬閘極裝置。另外,此製程也可使用其他方法,例如濕蝕刻。在一實施例中,只有間隙壁227的上半部受到蝕刻,而使裝置200留下完整的下半部間隙壁。可使用化學機械研磨(CMP)去除間隙壁227的擴寬部,如以下所述。因此,擴寬的溝槽235能提供較佳的金屬閘極填入能力,例如鋁旋轉塗佈。
在一實施例中,此製程可於單一PVD蝕刻設備中進行。進行的氬氣濺射所使用氬氣壓力約在3mTorr至20mTorr的範圍且氬氣流量約在300sccm至600sccm的範圍。氬氣濺射的偏壓功率約在200W至500W的範圍。在一實施例中,氬氣濺射所進行的溫度約在0℃至100℃的範圍。氬氣濺射所進行的時間約在5秒至30秒的範圍。
方法100進行至區塊110,自閘極結構去除剩餘的犧牲閘極,以在閘極結構內形成完整溝槽。請參照第2D圖,在裝置200上方形成一光阻圖案層(未繪示),以保護局部的裝置200。可藉由光學微影、浸潤式微影、離子束微影或其他適當的技術來形成光阻圖案層。舉例來說,光學微影包括旋轉塗佈、軟烤、曝光、後曝烤、顯影、清洗、乾燥及其他適當製程。可藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合去除閘極結構中剩餘的犧牲閘極218而形成完整溝槽236。舉例來說,濕蝕刻包括暴露於含氫氧化物溶液(例如,氫氧化銨)、去離子水及/或其他適當的蝕刻溶液。可在0℃至100℃下,使用HBr、CF4
、CL2
、O2
或HeO2
來進行多晶矽層218的蝕刻。因此,可蝕刻除去剩餘的犧牲多晶矽閘極218至下方的絕緣層215,以在閘極結構內形成完整溝槽236。而可藉由剝除法或其他適當至製程來去除任何所使用的光阻圖案層(未繪示)。
可藉由單一蝕刻製程步驟或多步驟蝕刻製程來去除犧牲多晶矽閘極218及犧牲介電層215。舉例來說,可使用第一濕蝕刻製程以去除犧牲多晶矽閘極218。第一濕蝕刻製程包括暴露於含氫氧化物溶液(例如,氫氧化銨)、去離子水及/或其他適當的蝕刻溶液。可使用第二蝕刻製程以去除犧牲介電層215。第二濕蝕刻製程包括暴露於緩衝氫氟酸(HF)溶液或緩衝氧化蝕刻溶液(buffered oxide etchant,BOE)。第二濕蝕刻製程可選擇性去除犧牲介電層215且終止於基底202上,以在閘極結構內形成完整溝槽236。可以理解的是也可使用其他蝕刻化學來選擇性去除犧牲介電層及犧牲多晶矽閘極。
方法100進行至區塊112,形成高介電常數材料層及金屬閘極以大抵填入於溝槽中。請參照第2E圖,高介電常數材料層216(若尚未形成於基底202上)可形成於基底202上。高介電常數材料層可包括一界面層、一高介電常數材料層、及/或一阻障層。這些不同的材料層將詳述於第4A圖中。另外,可形成填洞金屬280以填入於溝槽236中。在本實施例中,可沉積一鈦層作為後續鋁填入的潤濕層(wetting layer)。可藉由PVD或其他適當的製程來形成鈦層。可形成鋁層280以填入溝槽236中。藉由CVD形成一第一鋁層,接著藉由PVD以形成一第二鋁層而構成鋁層280。另外,填洞金屬280可包括鎢(W)、銅(Cu)或其他適當的金屬材料。
方法100進行至區塊114,進行化學機械研磨製程。請參照第2F圖,對鋁層280進行化學機械研磨製程285以去除多餘的鋁(例如,溝槽236外側的鋁)。化學機械研磨製程285具有高選擇比,使閘極結構具有大抵平坦表面。因此,金屬閘極呈現適當的功函數(work function)。而不需太過繁複即可獲得FET裝置所需的起始電壓(threshold voltage)。需注意的是可藉由CMP及蝕刻製程去除溝槽外側的不同金屬層及旋轉塗佈玻璃(SOG)層。再者,由於高介電常數材料層形成於後閘極製程中時經歷較低的熱週期,因此可維持高介電常數材料層的品質及完整性(integrity)。可以理解的是半導體裝置200可進一步加工,以形成不同的特徵部件,例如接觸窗(contact)/介層洞(via)、內連金屬層、內層介電層、鈍化保護(passivation)層等等。需注意的是關於第1及2A至2F圖所述的技術及製程,例如微影製程、蝕刻製程及高介電常數材料/金屬閘極製作,也可實施於以下關於第3及4A至4G圖所述的各個實施例。
請參照第3圖,其為根據本說明書各個型態所繪示出具有多金屬閘極的半導體裝置製造方法300的流程圖。亦請參照第4A至4G圖,係根據第3圖的方法300所繪示出半導體裝置400在不同製造階段的剖面示意圖。需注意的是部分的半導體裝置400可利用CMOS製程來製造。因此,可以理解的是在第3圖的方法300進行之前、期間及之後可進行其他製程,且此處對於某些製程僅略作說明。半導體裝置400可製作於一後閘極製程中。半導體裝置400類似於第2圖的半導體裝置200。因此,為了達到簡化及清晰的目的,第2及4圖中類似的特徵部件係使用相同的標號。
方法300開始於區塊302,提供一半導體基底,該基底具有第一區及第二區。請參照第2A圖,半導體裝置400可包括一半導體基底202,例如一矽基底。基底202亦可進一步包括摻雜區,例如一P型井404及N型井406。基底202亦可進一步包括一隔離結構410,例如形成於基底202內的淺溝槽隔離(shallow trench isolation,STI)或局部矽氧化(local oxidation of silicon,LOCOS)特徵部件,以隔離基底202的主動區412及414。主動區412可為NMOS裝置(例如,nFET),且主動區414可為PMOS裝置(例如,pFET)。
方法300進行至區塊304,在第一區上方形成一第一閘極結構,且在第二區上方形成一第二閘極結構。第一閘極結構包括間隙壁227及犧牲多晶矽層/閘極218。第二閘極結構包括間隙壁227及犧牲多晶矽閘極218。閘極結構的製造包括形成各種不同的材料層及蝕刻/圖案化各個材料層以在nFET裝置412側成一閘極結構且在pFET裝置414側成一閘極結構,如以下所述。
半導體裝置400可包括形成於基底202上方的一介面層415。介面層415可包括氧化矽(SiO2
)層(例如,熱氧化層或化學氧化層),且厚度在5至20埃()的範圍。另外,介面層415可包括HfSiO或SiON且藉由原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化法、或其組合。在一些實施例中,Hf層可藉由ALD、CVD、或PVD形成於熱氧化層上,接著藉由熱氧(O2
)來氧化以形成HfSiO。在其他實施例中,可在活性氧氛圍,藉由ALD、CVD、或PVD形成Hf層。
半導體裝置400可進一步包括形成於界面層415上方的高介電常數介電層416。可藉由原子層沉積(ALD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(metalorganic CVD,MOCVD)、物理氣相沉積(PVD)、熱氧化法、及其組合或其他適當的製程來形成高介電常數介電層416。高介電常數介電層416的厚度在5至20埃()的範圍。高介電常數介電層416可包括二元或三元高介電常數層,例如HfOx
。另外,高介電常數介電層416可包括其他高介電常數材料,例如LaO、AlO、ZrO、TiO、Ta2
O5
、Y2
O3
、SrTiO3
(STO)、BaTiO3
(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr) TiO3
(BST)、Al2
O3
、Si3
N4
、氮氧化物或其他適當的材料。在一些實施例中可進行後高介電常數材料沉積退火。
半導體裝置400可進一步包括形成於高介電常數介電層416上方的一阻障層417。阻障層417可包括金屬層,例如TiN或TaN。另外,阻障層417可包括Si3
N4
。阻障層417可作為高介電常數介電層416與後續犧牲多晶矽閘極之間的阻障層。阻障層417有助於降低或排除後續製程期間多晶矽與高介電常數介電層416之間費米能階鎖定(Fermi level pinning)的風險。再者,阻障層417可做為去除多晶矽閘極期間的蝕刻終止層及保護層,如本為稍後所述。可藉由各種沉積技術形成阻障層417,例如ALD、PVD、CVD、或其他適當技術。需注意的是界面層415、高介電常數介電層416及阻障層417可形成於後閘極製程中,如第1及2圖所述。
半導體裝置400亦包括藉由適當沉積製程而形成於阻障層417上方的一犧牲多晶矽層218。舉例來說可在化學氣相沉積(CVD)製程中使用一化學氣體以形成多晶矽層218,例如矽烷(SiH4
)、二矽乙烷(Si2
H6
)或二氯矽烷(SiCl2
H4
)。多晶矽層218的厚度在400至2000埃的範圍。另外,可選擇性地以非晶矽層取代多晶矽層。半導體裝置400可進一步包括在多晶矽層218上方形成一硬式罩幕層(未繪示)。硬式罩幕層可包括氧化矽、氮化矽、氮氧化矽、碳化矽及/或其他適當的介電材料,且可藉由CVD或是PVD等方法來製作。硬式罩幕層的厚度在100至400埃的範圍。另外,可使用一抗反射層或是底層抗反射(BARC)層來改善光阻層圖案化所進行的微影製程。舉例來說,在硬式罩幕層上方形成具有閘極圖案位於nFET裝置412側及位於pFET裝置414側的一光阻圖案層(未繪示)。閘極圖案可藉由乾蝕刻或濕蝕刻而使用於圖案化硬式罩幕層。
圖案化的硬式罩幕層可接著藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合而使用於nFET裝置412側及於pFET裝置414側的閘極結構製作。因此,閘極結構420n及420p各包括界面層415、高介電常數介電層416、阻障層417、犧牲多晶矽閘極218及/或一硬式罩幕層。
在形成閘極結構420n及420p(例如,閘極蝕刻或圖案化)之後,可以理解的是半導體裝置400可進行額外CMOS製程,以形成nFET裝置412及於pFET裝置414中的各個不同特徵部件。因此,此處僅對這些特徵部件略作說明。請參照第4B圖,各個不同特徵部件包括位於nFET裝置412的SiC特徵部件422及位於pFET裝置414的SiGe特徵部件424、淺摻雜源極/汲極區(n型及p型LDD區)、側壁或閘極間隙壁227、源極/汲極區(n型及p型S/D區)、矽化物特徵部件、接觸蝕刻終止層(contact etch stop layer,CESL)及內層介電(interlayer dielectric,ILD)層430。需注意的是SiC特徵部件422及SiGe特徵部件424為非必需的部件,且nFET裝置412及/或pFET裝置414可具有一應變層,以提高裝置效能。內層介電(ILD)層430可包括氧化物,其藉由高深寬比製程(high aspect ratio process,HARP)及/或高密度電漿化學氣相沉積(high density CVD,HDPCVD)製作而成。內層介電層430填入於nFET裝置412側的閘極結構420n與相鄰的pFET裝置414側的閘極結構420p之間的間隙。之後,對內層介電層430進行化學機械研磨製程,以平坦化內層介電層430直至分別露出nFET裝置412側及pFET裝置414側的犧牲多晶矽閘極218。
方法300進行至區塊306,自這些閘極結構局部去除犧牲閘極,以在閘極結構內形成未完整溝槽。請參照第4C圖,在裝置400上形成一光阻圖案層(未繪示),以保護局部的裝置400,例如這些閘極結構其中之一。可藉由光學微影、浸潤式微影、離子束微影或其他適當的技術來形成光阻圖案層。舉例來說,光學微影包括旋轉塗佈、軟烤、曝光、後曝烤、顯影、清洗、乾燥及其他適當製程。可藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合去除這些閘極結構中部分的犧牲閘極218。舉例來說,濕蝕刻包括暴露於含氫氧化物溶液(例如,氫氧化銨)、去離子水及/或其他適當的蝕刻溶液。可在0℃至100℃下,使用HBr、CF4
、CL2
、O2
或HeO2
來進行多晶矽層218的蝕刻。可在進行一段時間之後停止蝕刻,以留下局部的犧牲多晶矽閘極218(例如,約400埃)。任何適當的製程可使用於終止蝕刻製程。因此,可去除局部的犧牲多晶矽閘極218,以在這些閘極結構內形成未完整溝槽234。而可藉由剝除法或其他適當至製程來去除任何所使用的光阻圖案層(未繪示)。
方法300進行至區塊308,去除局部的間隙壁227,以形成未完整溝槽的一擴寬部235。在一實施例中,使用乾式氬氣濺射,以局部去除間隙壁227,而形成漏斗型溝槽235。氬氣分子尺寸適合製作出漏斗型。然而,其他元素或其他蝕刻/形成方法也可產生可接受的結果。如第4D圖所示,氬氣濺射可在間隙壁227產生稍微傾斜的側邊,而使溝槽具有漏斗型輪廓。在一實施例中,此傾斜角度向下延伸約100埃且朝向溝槽235內部。在一實施例中,剩餘閘極的高度約400埃且閘極寬度約22至27奈米(nm)。然而,氬氣濺射期間間隙壁227內也可能形成其他外型及尺寸。可以理解的是這些方法可使用後高介電常數材料製程而實施於具有多晶矽閘極取代(RPG)的金屬閘極裝置。另外,此製程也可使用其他方法,例如濕蝕刻。在一實施例中,只有間隙壁227的最上部受到蝕刻,而使裝置400留下完整的下半部間隙壁。可使用化學機械研磨(CMP)去除間隙壁227的擴寬部,如以下所述。因此,擴寬的溝槽235能提供較佳的金屬閘極填入能力,例如鋁旋轉塗佈。
在一實施例中,此製程可於單一PVD蝕刻設備中進行。進行的氬氣濺射所使用氬氣壓力約在3mTorr至20mTorr的範圍且氬氣流量約在300sccm至600sccm的範圍。氬氣濺射的偏壓功率約在200W至500W的範圍。在一實施例中,氬氣濺射所進行的溫度約在0℃至100℃的範圍。氬氣濺射所進行的時間約在5秒至30秒的範圍。
方法300進行至區塊310,自這些閘極結構去除剩餘的犧牲閘極,以在這些閘極結構內形成完整溝槽。請參照第4E圖,在裝置400上方形成一光阻圖案層(未繪示),以保護局部的裝置400,例如這些閘極結構其中之一。可藉由光學微影、浸潤式微影、離子束微影或其他適當的技術來形成光阻圖案層。舉例來說,光學微影包括旋轉塗佈、軟烤、曝光、後曝烤、顯影、清洗、乾燥及其他適當製程。可藉由乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻的組合去除閘極結構中剩餘的犧牲閘極218而形成完整溝槽236。舉例來說,濕蝕刻包括暴露於含氫氧化物溶液(例如,氫氧化銨)、去離子水及/或其他適當的蝕刻溶液。可在0℃至100℃下,使用HBr、CF4
、CL2
、O2
或HeO2
來進行多晶矽層218的蝕刻。因此,可蝕刻除去剩餘的犧牲多晶矽閘極218至下方的界面層415,以在閘極結構內形成完整溝槽236。而可藉由剝除法或其他適當至製程來去除任何所使用的光阻圖案層(未繪示)。
方法300進行至區塊312,形成高介電常數材料層及金屬閘極以大抵填入於溝槽中。請參照第4F圖,高介電常數材料層216(若尚未形成於基底202上)可形成於基底202上。另外,可形成填洞金屬480以填入於溝槽236中。在本實施例中,可沉積一鈦層作為後續鋁填入的潤濕層。可藉由PVD或其他適當的製程來形成鈦層。可形成鋁層480以填入溝槽236中。藉由CVD形成一第一鋁層,接著藉由PVD以形成一第二鋁層而構成鋁層480。另外,填洞金屬480可包括鎢(W)、銅(Cu)或其他適當的金屬材料。
方法300進行至區塊314,進行化學機械研磨製程。請參照第4G圖,對鋁層480進行化學機械研磨製程485以去除多餘的鋁(例如,溝槽236外側的鋁)。化學機械研磨製程485具有高選擇比,使閘極結構420n及420p及內層介電層430具有大抵平坦表面。因此,nFET裝置412的金屬閘極(包括N-金屬層(未繪示)及鋁填洞層480)可呈現適當的N功函數,而pFET裝置414的金屬閘極(包括P-金屬層(未繪示)及鋁填洞層480)可呈現適當的P功函數。而不需太過繁複即可分別獲得nFET裝置412及pFET裝置414所需的起始電壓。
可以理解的是半導體裝置400可進一步加工,以形成不同的特徵部件,例如接觸窗/介層洞、內連金屬層、內層介電層、鈍化保護層等等。需注意的是關於第3及4A至4G圖所述的技術及製程也可實施於以下關於第1及2A至2F圖所述的各個實施例。
本發明在所述的各個不同實施例中獲得不同的益處。可以理解的是此處所述的各個不同實施例提供許多不同的益處,且所有實施例中無特定益處是必須的。舉例來說,本文所揭示的方法提供一種簡單且節省成本的方法,以在藉由使用犧牲介電層在後閘極製程中形成高介電常數的閘極介電層。在另一範例中,本文所揭示的方法提供一種具有較少孔隙的填洞金屬,此乃由於閘極填入於一較大的開口中。再者,本文所揭示的方法提供一種簡單且節省成本的方法,以在後閘極製程中形成對於nFET裝置及pFET裝置而言具有適當功函數的金屬閘極。再者,本文所揭示的方法及裝置可輕易地整合於現行的CMOS製程及半導體製程設備中。舉例來說,本文所揭示的方法中的材料及製程適用且相容於CMOS製程中,且整合至CMOS製程的成本並不昂貴。
以上敘述許多實施例的特徵,使所屬技術領域中具有通常知識者能夠清楚理解以下的說明。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容作為基礎,以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。舉例來說,第1及3圖所揭示的技術、方法及製程可實施及/或結合於第1或3圖的任何實施例,例如微影、蝕刻及高介電常數材料/金屬閘極的製作。
100、300...方法
102、104、106、108、110、112、114、302、304、306、308、310、312、314...區塊
200、400...半導體裝置
202...半導體基底
215...犧牲絕緣層
216、416...高介電常數材料層
218...犧牲多晶矽層/閘極
227...間隙壁
234...未完整溝槽
235...擴寬部/漏斗型溝槽
236...完整溝槽
280、480...填洞金屬/鋁層
285、485...化學機械研磨
404...P型井
406...N型井
410...隔離結構
412...主動區/nFET裝置
414...主動區/pFET裝置
415...界面層
417...阻障層
420n、420p...閘極結構
422...SiC特徵部件
424...SiGe特徵部件
430...內層介電層
第1圖係根據本說明書各個型態所繪示出具有金屬閘極的半導體裝置製造方法流程圖。
第2A至2F圖係根據第1圖的方法所繪示出半導體裝置不同製造階段的剖面示意圖。
第3圖係根據本說明書各個型態所繪示出具有多金屬閘極的半導體裝置製造方法流程圖。
第4A至4G圖係根據第3圖的方法所繪示出半導體裝置不同製造階段的剖面示意圖。
100...方法
102、104、106、108、110、112、114...區塊
Claims (12)
- 一種半導體裝置的製造方法,包括:提供一半導體基底;在該半導體基底上方形成一閘極結構,該閘極結構包括一第一間隙壁、與該第一件隙壁隔開的一第二間隙壁、以及位於該第一間隙壁及該第二間隙壁之間的一犧牲閘極;自該閘極結構局部去除該犧牲閘極,以形成一未完整溝槽;局部去除鄰接於該未完整溝槽的該第一間隙壁及該第二間隙壁,以形成該未完整溝槽的一擴寬部;自該閘極結構去除該犧牲閘極的一剩餘部,以形成一完整溝槽;在該完整溝槽內形成一高介電常數材料層;以及在該完整溝槽內形成一金屬閘極。
- 如申請專利範圍第1項所述之半導體裝置的製造方法,更包括在形成該金屬閘極之後進行化學機械研磨製程,以去除該未完整溝槽的該擴寬部。
- 如申請專利範圍第1項所述之半導體裝置的製造方法,其中藉由蝕刻該第一及該第二間隙壁,以局部去除該第一及該第二間隙壁。
- 如申請專利範圍第3項所述之半導體裝置的製造方法,其中該蝕刻為氬氣濺射。
- 如申請專利範圍第4項所述之半導體裝置的製造方法,其中該氬氣濺射中所進行的壓力在3mTorr至20mTorr的範圍、所進行的氬氣流量在300sccm至600sccm的範圍、所進行的偏壓功率在200W至500W的範圍、所進行的溫度在0℃至100℃的範圍、及所進行的時間在5秒至30秒的範圍。
- 一種半導體裝置的製造方法,包括:提供一半導體基底;在該半導體基底上方形成一絕緣層;在該絕緣層上方形成一第一間隙壁;在該絕緣層上方形成與該第一間隙壁隔開的一第二間隙壁;在該第一間隙壁及該第二間隙壁之間形成一犧牲閘極;局部去除該第一間隙壁及該第二間隙壁,以在該第一間隙壁及該第二間隙壁之間形成一擴寬區域;去除該犧牲閘極,以形成一溝槽;以及在該溝槽內形成一金屬閘極。
- 如申請專利範圍第6項所述之半導體裝置的製造方法,更包括進行化學機械研磨製程,以去除形成於該擴寬區域內局部的該金屬閘極。
- 如申請專利範圍第6項所述之半導體裝置的製造方法,其中藉由蝕刻該第一及該第二間隙壁,以局部去除該第一及該第二間隙壁。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中該蝕刻為氬氣濺射。
- 如申請專利範圍第9項所述之半導體裝置的製造方法,其中該氬氣濺射中所進行的壓力在3mTorr至20mTorr的範圍、所進行的氬氣流量在300sccm至600sccm的範圍、所進行的溫度在0℃至100℃的範圍、及所進行的時間在5秒至30秒的範圍。
- 一種半導體裝置的製造方法,包括:提供一基底,具有一第一區及一第二區;在該第一區上方形成一第一閘極結構,且在該第二區上方形成一第二閘極結構,該第一閘極結構包括一第一間隙壁、一第二間隙壁、以及一第一犧牲閘極,且第二閘極結構包括一第三間隙壁、一第四間隙壁、以及一第二犧牲閘極;自該第一閘極結構局部去除該第一犧牲閘極,以形成一第一未完整溝槽,且自該第二閘極結構局部去除該第二犧牲閘極,以形成一第二未完整溝槽;局部去除該第一間隙壁及該第二間隙壁,以形成該第一未完整溝槽的一擴寬部,且局部去除該第三間隙壁及該第四間隙壁,以形成該第二未完整溝槽的一擴寬部;去除該第一及該第二犧牲閘極的剩餘部,以形成一第一完整溝槽及一第二完整溝槽;在該第一及該第二完整溝槽內分別形成一高介電常數材料層;以及在該第一及該第二完整溝槽內分別形成一金屬閘極。
- 如申請專利範圍第11項所述之半導體裝置的製造方法,更包括對該第一、該第二、該第三、及該第四間隙壁進行化學機械研磨製程。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/641,560 US8357603B2 (en) | 2009-12-18 | 2009-12-18 | Metal gate fill and method of making |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201123276A TW201123276A (en) | 2011-07-01 |
TWI419208B true TWI419208B (zh) | 2013-12-11 |
Family
ID=44151701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099117139A TWI419208B (zh) | 2009-12-18 | 2010-05-28 | 半導體裝置的製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8357603B2 (zh) |
CN (1) | CN102104003B (zh) |
TW (1) | TWI419208B (zh) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US7682924B2 (en) * | 2007-08-13 | 2010-03-23 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8388851B2 (en) | 2008-01-08 | 2013-03-05 | Micron Technology, Inc. | Capacitor forming methods |
US8357603B2 (en) | 2009-12-18 | 2013-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate fill and method of making |
CN102110650A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
TWI570787B (zh) * | 2011-03-24 | 2017-02-11 | 聯華電子股份有限公司 | 金屬閘極cmos元件及其製作方法 |
US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
US8753968B2 (en) * | 2011-10-24 | 2014-06-17 | United Microelectronics Corp. | Metal gate process |
US8946043B2 (en) | 2011-12-21 | 2015-02-03 | Micron Technology, Inc. | Methods of forming capacitors |
US8652926B1 (en) | 2012-07-26 | 2014-02-18 | Micron Technology, Inc. | Methods of forming capacitors |
US9023708B2 (en) * | 2013-04-19 | 2015-05-05 | United Microelectronics Corp. | Method of forming semiconductor device |
US9425048B2 (en) * | 2013-11-06 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for semiconductor device structure |
CN104681488B (zh) * | 2013-11-26 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
KR102410146B1 (ko) * | 2015-06-26 | 2022-06-16 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US9570318B1 (en) * | 2015-07-22 | 2017-02-14 | International Business Machines Corporation | High-k and p-type work function metal first fabrication process having improved annealing process flows |
US10050147B2 (en) * | 2015-07-24 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20170053793A1 (en) * | 2015-08-17 | 2017-02-23 | Tokyo Electron Limited | Method and system for sculpting spacer sidewall mask |
US10147799B2 (en) * | 2016-01-15 | 2018-12-04 | Taiwan Semiconductor Manufacturing Company Limited | Method of fabricating tantalum nitride barrier layer and semiconductor device thereof |
US10312089B1 (en) * | 2017-11-29 | 2019-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for controlling an end-to-end distance in semiconductor device |
CN110571141B (zh) * | 2018-06-05 | 2022-01-28 | 中芯国际集成电路制造(上海)有限公司 | 金属栅极的制造方法和半导体器件的制造方法 |
US11107907B2 (en) * | 2018-10-30 | 2021-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10879373B2 (en) * | 2019-04-23 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with metal gate stack |
US11037833B2 (en) | 2019-06-28 | 2021-06-15 | United Microelectronics Corp. | Fabrication method of semiconductor device with spacer trimming process |
US11398384B2 (en) * | 2020-02-11 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacer |
DE102020122120A1 (de) | 2020-02-18 | 2021-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metall-gate-strukturen und verfahren zum herstellen derselben in feldeffekttransistoren |
US11476351B2 (en) * | 2020-02-18 | 2022-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structures and methods of fabricating the same in field-effect transistors |
CN112259504A (zh) * | 2020-10-19 | 2021-01-22 | 上海华力集成电路制造有限公司 | 金属栅的制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956573A (en) * | 1997-01-17 | 1999-09-21 | International Business Machines Corporation | Use of argon sputtering to modify surface properties by thin film deposition |
US20030107088A1 (en) * | 1997-06-30 | 2003-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872401A (en) * | 1996-02-29 | 1999-02-16 | Intel Corporation | Deposition of an inter layer dielectric formed on semiconductor wafer by sub atmospheric CVD |
US6110837A (en) * | 1999-04-28 | 2000-08-29 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a hard mask of half critical dimension |
TW417165B (en) * | 1999-06-23 | 2001-01-01 | Taiwan Semiconductor Mfg | Manufacturing method for reducing the critical dimension of the wire and gap |
TW525260B (en) * | 1999-08-02 | 2003-03-21 | Taiwan Semiconductor Mfg | Shallow trench isolation pull-back process |
TW442961B (en) * | 1999-10-08 | 2001-06-23 | Taiwan Semiconductor Mfg | Manufacturing method of double-recess crown capacitor of DRAM |
TW429533B (en) * | 1999-10-18 | 2001-04-11 | Taiwan Semiconductor Mfg | Planarization method for polysilicon plug |
US6218244B1 (en) * | 1999-12-10 | 2001-04-17 | Taiwan Semiconductor Mfg Co Ltd | Method of fabricating transistor |
TW475211B (en) * | 2000-04-17 | 2002-02-01 | Taiwan Semiconductor Mfg | Forming method of borderless via |
JP2002198521A (ja) | 2000-12-25 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
US6410424B1 (en) * | 2001-04-19 | 2002-06-25 | Taiwan Semiconductor Manufacturing Company | Process flow to optimize profile of ultra small size photo resist free contact |
US6440875B1 (en) * | 2001-05-02 | 2002-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd | Masking layer method for forming a spacer layer with enhanced linewidth control |
US6503848B1 (en) * | 2001-11-20 | 2003-01-07 | Taiwan Semiconductor Manufacturing Company | Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window |
US6656796B2 (en) * | 2002-01-14 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple etch method for fabricating split gate field effect transistor (FET) device |
US6706591B1 (en) * | 2002-01-22 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Method of forming a stacked capacitor structure with increased surface area for a DRAM device |
US6812044B2 (en) * | 2002-12-19 | 2004-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Advanced control for plasma process |
US20040214448A1 (en) * | 2003-04-22 | 2004-10-28 | Taiwan Semiconductor Manufacturing Co. | Method of ashing a photoresist |
US6764903B1 (en) * | 2003-04-30 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Dual hard mask layer patterning method |
US20040266115A1 (en) * | 2003-06-25 | 2004-12-30 | Bor-Wen Chan | Method of making a gate electrode on a semiconductor device |
US6828237B1 (en) * | 2003-09-11 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Sidewall polymer deposition method for forming a patterned microelectronic layer |
US7202172B2 (en) * | 2003-12-05 | 2007-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Microelectronic device having disposable spacer |
US7081413B2 (en) * | 2004-01-23 | 2006-07-25 | Taiwan Semiconductor Manufacturing Company | Method and structure for ultra narrow gate |
US7354847B2 (en) * | 2004-01-26 | 2008-04-08 | Taiwan Semiconductor Manufacturing Company | Method of trimming technology |
US7067391B2 (en) * | 2004-02-17 | 2006-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to form a metal silicide gate device |
US7122484B2 (en) * | 2004-04-28 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for removing organic materials during formation of a metal interconnect |
US7241674B2 (en) * | 2004-05-13 | 2007-07-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming silicided gate structure |
US20050269644A1 (en) * | 2004-06-08 | 2005-12-08 | Brask Justin K | Forming integrated circuits with replacement metal gate electrodes |
US7172933B2 (en) * | 2004-06-10 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed polysilicon gate structure for a strained silicon MOSFET device |
US20050282350A1 (en) * | 2004-06-22 | 2005-12-22 | You-Hua Chou | Atomic layer deposition for filling a gap between devices |
US20060040481A1 (en) * | 2004-08-17 | 2006-02-23 | Bor-Wen Chan | Methods and structures for preventing gate salicidation and for forming source and drain salicidation and for forming semiconductor device |
TWI304395B (en) * | 2004-11-26 | 2008-12-21 | Ind Tech Res Inst | A method for fabricating a high specific surface area mesoporous alumina |
US7195969B2 (en) * | 2004-12-31 | 2007-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained channel CMOS device with fully silicided gate electrode |
US20070296052A1 (en) * | 2006-06-26 | 2007-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming silicide regions and resulting MOS devices |
US7517746B2 (en) * | 2007-04-24 | 2009-04-14 | United Microelectronics Corp. | Metal oxide semiconductor transistor with Y shape metal gate and fabricating method thereof |
TWI346199B (en) * | 2007-11-30 | 2011-08-01 | Ind Tech Res Inst | Radiation apparatus with capability of preventing heat convection |
US8735235B2 (en) * | 2008-08-20 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit metal gate structure and method of fabrication |
US8299508B2 (en) * | 2009-08-07 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS structure with multiple spacers |
US8367563B2 (en) * | 2009-10-07 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for a gate replacement process |
US8193081B2 (en) * | 2009-10-20 | 2012-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for metal gate formation with wider metal gate fill margin |
US8334197B2 (en) * | 2009-12-16 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating high-k/metal gate device |
US8357603B2 (en) | 2009-12-18 | 2013-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate fill and method of making |
US8779530B2 (en) * | 2009-12-21 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a field effect transistor |
US8008143B2 (en) * | 2009-12-30 | 2011-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to form a semiconductor device having gate dielectric layers of varying thicknesses |
US8093117B2 (en) * | 2010-01-14 | 2012-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a metal gate |
US8513107B2 (en) * | 2010-01-26 | 2013-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement gate FinFET devices and methods for forming the same |
US8048810B2 (en) * | 2010-01-29 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for metal gate N/P patterning |
US8952462B2 (en) * | 2010-02-05 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
US8564072B2 (en) * | 2010-04-02 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a blocking structure and method of manufacturing the same |
US8580698B2 (en) * | 2010-04-14 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a gate dielectric layer |
US20110256682A1 (en) * | 2010-04-15 | 2011-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device |
US8278173B2 (en) * | 2010-06-30 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating gate structures |
US8329546B2 (en) * | 2010-08-31 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified profile gate structure for semiconductor device and methods of forming thereof |
US9105653B2 (en) * | 2010-10-18 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a metal gate electrode |
-
2009
- 2009-12-18 US US12/641,560 patent/US8357603B2/en active Active
-
2010
- 2010-05-28 TW TW099117139A patent/TWI419208B/zh active
- 2010-06-10 CN CN201010202875.1A patent/CN102104003B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956573A (en) * | 1997-01-17 | 1999-09-21 | International Business Machines Corporation | Use of argon sputtering to modify surface properties by thin film deposition |
US20030107088A1 (en) * | 1997-06-30 | 2003-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
Also Published As
Publication number | Publication date |
---|---|
TW201123276A (en) | 2011-07-01 |
US8357603B2 (en) | 2013-01-22 |
US20110151655A1 (en) | 2011-06-23 |
CN102104003B (zh) | 2015-04-22 |
CN102104003A (zh) | 2011-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI419208B (zh) | 半導體裝置的製造方法 | |
US11721746B2 (en) | Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features | |
TWI419264B (zh) | 製造半導體裝置的方法 | |
CN109427873B (zh) | 具有粗糙阻挡层的金属栅极的结构和方法 | |
TWI584472B (zh) | 半導體元件結構及其形成方法 | |
TWI535024B (zh) | 半導體結構及其製造方法 | |
CN104835838B (zh) | 具有不同宽度的栅极结构及其制造方法 | |
US8334197B2 (en) | Method of fabricating high-k/metal gate device | |
TWI393220B (zh) | 半導體元件之製法 | |
TWI416667B (zh) | 半導體元件及其製造方法 | |
US7939392B2 (en) | Method for gate height control in a gate last process | |
US7923321B2 (en) | Method for gap filling in a gate last process | |
CN106206688B (zh) | 半导体器件结构的结构和形成方法 | |
US8349680B2 (en) | High-k metal gate CMOS patterning method | |
US9196611B2 (en) | Reduced substrate coupling for inductors in semiconductor devices | |
US8969922B2 (en) | Field effect transistors and method of forming the same | |
US20150087144A1 (en) | Apparatus and method of manufacturing metal gate semiconductor device | |
TW201903858A (zh) | 半導體裝置的製造方法 | |
TWI478339B (zh) | 半導體元件及其製法 | |
US9941152B2 (en) | Mechanism for forming metal gate structure | |
TW201539759A (zh) | 半導體元件結構及製造方法 | |
KR101552007B1 (ko) | 전극을 갖는 반도체 디바이스 및 이의 제조 방법 |