TWI417720B - Flash memory managing methods and computing systems utilizing the same - Google Patents
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Description
本發明係關於一種記憶體裝置之管理方法，特別關於一種可優化快閃記憶體裝置之讀寫操作性能之方法。The present invention relates to a method of managing a memory device, and more particularly to a method for optimizing read and write performance of a flash memory device.
快閃記憶體(flash memory)為一種特殊種類的非揮發性(nonvolatile)記憶體，其可儲存資料以及被電性抹除。以快閃記憶體為基礎之儲存裝置具有低功率耗損，並且與以磁碟記憶體為基礎的儲存裝置相比，具有相對小的尺寸。因此，快閃記憶體裝置目前為一些手持電子計算裝置中經常被使用的記憶體裝置，例如數位相機、手機或個人數位助理(personal digital assistants，PDA)等。Flash memory is a special kind of nonvolatile memory that can store data and be erased electrically. Flash memory-based storage devices have low power consumption and are relatively small in size compared to disk memory based storage devices. Therefore, flash memory devices are currently memory devices that are often used in some handheld electronic computing devices, such as digital cameras, cell phones, or personal digital assistants (PDAs).
在磁碟記憶體裝置中，新的資料可覆寫舊的資料。然而，在快閃記憶體裝置中，若要更新先前儲存的資料，必須先將一區塊(block)範圍進行抹除，即，快閃記憶體裝置的讀取與寫入操作的單位可以是以頁(page)或區段(sector)為基礎，而抹除操作的最小單位為區塊。因此，抹除操作通常比寫入與讀取操作需要更多的時間。此外，由於區塊的大小遠大於頁與區段，即使區塊內不需被寫入的部分也要同時被抹除。In the disk memory device, new data can overwrite old data. However, in the flash memory device, in order to update the previously stored data, a block range must be erased first, that is, the unit of the read and write operations of the flash memory device can be It is based on a page or a sector, and the smallest unit of the erase operation is a block. Therefore, the erase operation usually takes more time than the write and read operations. In addition, since the size of the block is much larger than the page and the segment, even the portion of the block that does not need to be written is also erased at the same time.
傳統技術中改善讀寫操作性能的方法為透過介質管理層，使用映射的方式，當需要修改某一區塊內儲存的資料時，在系統內取得另一個可用區塊(通常稱此區塊為log區塊)，用以儲存該區塊之修改紀錄，如此一來，每當需要修改該區塊之資料時，僅需將修改資料儲存至該區塊對應的log區塊，即可避免必須抹除一整個區塊的寫入操作。然而，在讀取操作時，為了尋找到最近被更新的資料內容，必須自log區塊的末端倒序地遍曆(visit)log區塊內所儲存的資料，這樣一來，增加了許多不必要的資料讀取操作，更降低了讀取的速度。 In the conventional technology, the method for improving the performance of the read and write operations is to use the mapping management mode through the medium management layer. When it is necessary to modify the data stored in a certain block, another available block is obtained in the system (generally called this block is The log block) is used to store the modified record of the block, so that whenever the data of the block needs to be modified, only the modified data needs to be stored in the log block corresponding to the block, thereby avoiding the necessity Erase a whole block of write operations. However, in the read operation, in order to find the newly updated data content, it is necessary to traverse the data stored in the log block in reverse order from the end of the log block, thus adding a lot of unnecessary The data reading operation reduces the reading speed.
因此，需要一種新的快閃記憶體管理方法，可優化快閃記憶體裝置之讀寫操作性能，使得記憶體裝置之讀寫操作速度可大幅地被提升。 Therefore, there is a need for a new flash memory management method that optimizes the read and write operation performance of the flash memory device, so that the read and write operation speed of the memory device can be greatly improved.
根據本發明之一實施例，一種快閃記憶體管理方法，用以管理一快閃記憶體裝置，其中該快閃記憶體裝置配置至少一映射區塊、至少一修改區塊以及至少一快取區塊，包括：接收包含一寫入邏輯位址與一既定資料之一寫入指令，用以寫入該既定資料至該快閃記憶體裝置；以及判斷對應於該寫入邏輯位址之該映射區塊之一頁是否已經被使用。其中當對應於該寫入邏輯位址之該映射區塊之該頁已經被使用，則寫入該既定資料於該修改區塊之一空白頁，包括：根據該寫入邏輯位址由該快取區塊讀取對應於該修改區塊之一快取頁至一隨機存取記憶體裝置，於該隨機存取記憶體裝置內依序讀取該快取頁之資料欄位以獲得該空白頁於該修改區塊內之位置資訊，其中該快取區塊之各快取頁具有複數資料欄位用以依序儲存該修改區塊之各非空白頁所寫入之資料所對應之該位置資訊；以及依據該位置資訊寫入該既定資料於該修改區塊之該空白頁。 According to an embodiment of the present invention, a flash memory management method for managing a flash memory device, wherein the flash memory device is configured with at least one mapping block, at least one modified block, and at least one cache The block includes: receiving a write command including a write logic address and a predetermined data for writing the predetermined data to the flash memory device; and determining the corresponding to the write logical address Whether one of the mapped blocks has been used. When the page corresponding to the mapping block of the write logical address has been used, writing the predetermined data to a blank page of the modified block includes: according to the write logical address, the fast The fetch block reads a cache page corresponding to one of the modified blocks to a random access memory device, and sequentially reads the data field of the cache page in the random access memory device to obtain the blank Position information in the modified block, wherein each cache page of the cache block has a plurality of data fields for sequentially storing the data corresponding to each non-blank page of the modified block Location information; and writing the predetermined data to the blank page of the modified block according to the location information.
根據本發明之另一實施例，一種快閃記憶體管理方 法，用以管理一快閃記憶體裝置，其中該快閃記憶體裝置配置至少一映射區塊、至少一修改區塊以及至少一快取區塊，包括：接收包含一讀取邏輯位址之一讀取指令用以由該快閃記憶體裝置之一頁讀取一既定資料；以及判斷對應於該讀取邏輯位址之該映射區塊之一頁是否已經被使用。其中當對應於該讀取邏輯位址之該映射區塊之頁的資料已經被修改過，則於對應於該映射區塊之該修改區塊中讀取該既定資料，包括：根據該讀取邏輯位址由該快取區塊讀取對應於該修改區塊之一快取頁至一隨機存取記憶體裝置，於該隨機存取記憶體裝置內依序讀取該快取頁之資料欄位以獲得對應於該讀取邏輯位址之頁於該修改區塊內之一位置資訊，其中該快取區塊之各快取頁具有複數資料欄位用以依序儲存該修改區塊之各非空白頁所寫入之資料所對應之該位置資訊；以及依據該位置資訊於該修改區塊之該頁讀取該既定資料。 According to another embodiment of the present invention, a flash memory management party The method for managing a flash memory device, wherein the flash memory device is configured with at least one mapping block, at least one modified block, and at least one cache block, including: receiving a read logical address a read command for reading a predetermined data from a page of the flash memory device; and determining whether a page of the mapped block corresponding to the read logical address has been used. When the data corresponding to the page of the mapping block of the read logical address has been modified, reading the predetermined data in the modified block corresponding to the mapping block, including: according to the reading Reading, by the cache block, the cache page corresponding to one of the modified blocks to a random access memory device, and sequentially reading the data of the cache page in the random access memory device a field to obtain a location information corresponding to the page of the read logical address in the modified block, wherein each cache page of the cache block has a plurality of data fields for sequentially storing the modified block The location information corresponding to the data written by each non-blank page; and reading the predetermined data on the page of the modified block according to the location information.
根據本發明之另一實施例，一種計算機系統，包括一快閃記憶體、一隨機存取記憶體裝置以及一處理器。快閃記憶體配置至少一映射區塊、至少一修改區塊以及至少一快取區塊。處理器耦接至該快閃記憶體與該隨機存取記憶體裝置，接收包含一寫入邏輯位址與既定資料之一寫入指令，當對應於該寫入邏輯位址之該映射區塊之一頁已經被使用，則根據該寫入邏輯位址由該快取區塊讀取對應於該修改區塊之一快取頁至該隨機存取記憶體裝置，並於該隨機存取記憶體裝置內依序讀取該快取頁之內容以獲得該修改區塊內之一空白頁之位置資訊，以及依據該位置資訊 寫入該既定資料於該修改區塊之該空白頁，其中該快取區塊之各快取頁具有複數資料欄位用以依序儲存該修改區塊之各非空白頁所寫入之資料所對應之該位置資訊。 In accordance with another embodiment of the present invention, a computer system includes a flash memory, a random access memory device, and a processor. The flash memory is configured with at least one mapping block, at least one modified block, and at least one cache block. The processor is coupled to the flash memory and the random access memory device, and receives a write instruction including a write logic address and a predetermined data, and the mapping block corresponding to the write logical address One page has been used, and a cache page corresponding to the modified block is read from the cache block to the random access memory device according to the write logic address, and the random access memory is used in the random access memory. Reading the content of the cache page sequentially in the body device to obtain location information of a blank page in the modified block, and according to the location information Writing the predetermined data to the blank page of the modified block, wherein each cache page of the cache block has a plurality of data fields for sequentially storing data written by each non-blank page of the modified block The corresponding location information.
根據本發明之另一實施例，一種計算機系統，包括一快閃記憶體、一隨機存取記憶體裝置以及一處理器。快閃記憶體配置至少一映射區塊、至少一修改區塊以及至少一快取區塊。處理器耦接至該快閃記憶體與該隨機存取記憶體裝置，接收包含一讀取邏輯位址之一讀取指令，當對應於該讀取邏輯位址之該映射區塊之一頁的資料已經被修改過，則根據該讀取邏輯位址由該快取區塊讀取對應於該修改區塊之一快取頁至該隨機存取記憶體裝置，並於該隨機存取記憶體裝置內依序讀取該快取頁之內容以獲得對應於該讀取邏輯位址之該頁於該修改區塊內之一位置資訊，以及依據該位置資訊於該修改區塊之該頁讀取該既定資料，其中該快取區塊之各快取頁具有複數資料欄位用以依序儲存該修改區塊之各非空白頁所寫入之資料所對應之該位置資訊。 In accordance with another embodiment of the present invention, a computer system includes a flash memory, a random access memory device, and a processor. The flash memory is configured with at least one mapping block, at least one modified block, and at least one cache block. The processor is coupled to the flash memory and the random access memory device, and receives a read instruction including a read logical address, when one of the mapped blocks corresponding to the read logical address The data has been modified, and the cache page corresponding to the modified block is read from the cache block to the random access memory device according to the read logical address, and the random access memory is used in the random access memory. Reading the content of the cache page in sequence to obtain a location information of the page corresponding to the read logical address in the modified block, and the page according to the location information in the modified block The predetermined data is read, wherein each cache page of the cache block has a plurality of data fields for sequentially storing the location information corresponding to the data written by each non-blank page of the modified block.
根據本發明之另一實施例，一種快閃記憶體管理方法，用以管理一快閃記憶體裝置，其中該快閃記憶體裝置配置至少一映射區塊、至少一修改區塊以及至少一快取區塊。快閃記憶體管理方法包括：接收一包含一邏輯位址之存取指令，用以於該快閃記憶體裝置存取一既定資料；以及當對應於該邏輯位址之該映射區塊之一頁不適於存取該既定資料，則對與該映射區塊對應之該修改區塊進行存取操作，包括：由該快閃記憶體裝置之該快取區塊讀取對應 於該修改區塊之一快取頁至一隨機存取記憶體裝置，於該隨機存取記憶體裝置內依序讀取該快取頁之內容以獲得該既定資料於該修改區塊內之存取位置資訊，其中該快取區塊之各快取頁具有複數資料欄位用以依序儲存該修改區塊之各非空白頁所寫入之資料所對應之該位置資訊；以及依據該存取位置資訊與該快閃記憶體裝置之修改區塊內存取該既定資料。 According to another embodiment of the present invention, a flash memory management method for managing a flash memory device, wherein the flash memory device is configured with at least one mapping block, at least one modified block, and at least one fast Take the block. The flash memory management method includes: receiving an access instruction including a logical address for accessing a predetermined data to the flash memory device; and when the mapping block corresponding to the logical address If the page is not suitable for accessing the predetermined data, performing an access operation on the modified block corresponding to the mapping block, including: reading, by the cache block of the flash memory device Cache the page to the random access memory device, and sequentially read the content of the cache page in the random access memory device to obtain the predetermined data in the modified block. Accessing location information, wherein each cache page of the cache block has a plurality of data fields for sequentially storing the location information corresponding to the data written by each non-blank page of the modified block; Accessing the location information and accessing the predetermined data in the modified block of the flash memory device.
為使本發明之製造、操作方法、目標和優點能更明顯易懂，下文特舉幾個較佳實施例，並配合所附圖式，作詳細說明如下： In order to make the manufacturing, operating methods, objects and advantages of the present invention more apparent, the following detailed description of the preferred embodiments and the accompanying drawings
第1圖係顯示根據本發明之一實施例所述之計算機系統100，包括快閃記憶體101、處理器102以及隨機存取記憶體裝置103。處理器102根據接收到的指令以及藉由執行既定之程式碼管理快閃記憶體101。根據本發明之一實施例，快閃記憶體101可以是具有一次可抹除資料之最小單位大於一次可寫入資料之最小單位之特性之一種記憶體裝置，例如NAND型或NOR型快閃記憶體。快閃記憶體101可被配置至少一映射區塊、修改區塊以及快取區塊，其中對於NAND型快閃記憶體而言，映射區塊、修改區塊以及快取區塊可分別包括複數頁(page)，而對於NOR型快閃記憶體而言，映射區塊、修改區塊以及快取區塊可分別包括複數區段(sector)。為了簡潔起見，本說明書將統一使用「頁」進行相關的描述，然而值得注意的是，其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，用以將本發明之精神應用同時於各種快閃記憶體。1 shows a computer system 100, including a flash memory 101, a processor 102, and a random access memory device 103, in accordance with an embodiment of the present invention. The processor 102 manages the flash memory 101 in accordance with the received instructions and by executing the predetermined code. According to an embodiment of the present invention, the flash memory 101 may be a memory device having a characteristic that the minimum unit of erasable data is greater than the minimum unit of one writeable data, such as NAND type or NOR type flash memory. body. The flash memory 101 can be configured with at least one mapping block, a modified block, and a cache block, wherein for the NAND type flash memory, the mapping block, the modified block, and the cache block can respectively include the complex number A page, and for a NOR type flash memory, the mapping block, the modifying block, and the cache block may respectively include a plurality of sectors. For the sake of brevity, the description will use the "pages" in the description of the present invention, but it is not intended to limit the scope of the present invention, and those skilled in the art without departing from the spirit and scope of the present invention. In the meantime, a few changes and retouchings can be made to apply the spirit of the present invention to various flash memories.
根據本發明之一實施例，映射區塊之各頁用以儲存原始資料，並且映射區塊可具有至少一對應之修改區塊，用以當原始資料需被更改時，於該修改區塊之各頁儲存原始資料之更新內容，並且各修改區塊可對應於至少一快取區塊之一頁，用以儲存修改區塊所寫入之資料之位置資訊。第2圖係顯示根據本發明之一實施例所述之快閃記憶體之資料結構示意圖。如圖所示，快閃記憶體200可被配置複數個快取區塊201、複數個映射區塊202以及複數個修改區塊203。快取區塊201之各頁分別包括一資料區域與一冗餘區域，資料區域可包含複數資料欄位，用以依照對應之修改區塊之頁順序儲存修改區塊的各非空白頁之位置資訊。以256百萬位元組(MB)之快閃記憶體為例，可配置2048個區塊，各區塊大小為128KB，並且各區塊可包含256頁(或區段)，各頁之資料區域大小為512位元組(byte)，並具有對應之16byte之冗餘區域。因此，根據本發明之一實施例，若各資料欄位使用2byte紀錄位置資訊，則快取區塊201 之各頁之資料區域可分成256個資料欄位，足以完整紀錄一修改區塊之各頁之所有位置資訊，而快取區塊201的冗餘區域則可用以紀錄該快取區塊201之一快取區塊索引，以及該快取區塊201所對應之修改區塊之物理區塊編號(以下將作詳細介紹)。此外，如第2圖所示，映射區塊202與修改區塊203也可分別包括一資料區域與一冗餘區域，其中映射區塊202與修改區塊203之冗餘區域用以儲存該頁之資料區域所寫入之資料所對應之邏輯區塊編號與邏輯頁編號(以下將作詳細介紹)。According to an embodiment of the present invention, each page of the mapping block is used to store the original data, and the mapping block may have at least one corresponding modified block, when the original data needs to be changed, in the modified block. Each page stores the updated content of the original data, and each modified block may correspond to one of the at least one cached block for storing the location information of the data written by the modified block. 2 is a schematic diagram showing the structure of a flash memory according to an embodiment of the present invention. As shown, the flash memory 200 can be configured with a plurality of cache blocks 201, a plurality of mapping blocks 202, and a plurality of modified blocks 203. Each page of the cache block 201 includes a data area and a redundant area, and the data area may include a plurality of data fields for storing the positions of the non-blank pages of the modified block according to the page order of the corresponding modified block. News. Taking 256 megabytes (MB) of flash memory as an example, 2048 blocks can be configured, each block size is 128 KB, and each block can contain 256 pages (or segments). The area size is 512 bytes and has a corresponding 16 byte redundant area. Therefore, according to an embodiment of the present invention, if each data field uses 2 bytes of record location information, the data area of each page of the cache block 201 can be divided into 256 data fields, which is sufficient to completely record each of the modified blocks. All the location information of the page block, and the redundant area of the cache block 201 can be used to record the cache block index of the cache block 201 and the physical area of the modified block corresponding to the cache block 201. Block number (detailed below). In addition, as shown in FIG. 2, the mapping block 202 and the modifying block 203 may also include a data area and a redundant area, respectively, wherein the redundant area of the mapping block 202 and the modified block 203 is used to store the page. The logical block number and logical page number corresponding to the data written in the data area (described in detail below).
根據本發明之一實施例，當寫入快閃記憶體101時，處理器102接收包含一寫入邏輯位址與既定資料之一寫入指令，並根據該寫入邏輯位址取得對應之一邏輯區塊編號LBN以及一邏輯頁編號LSN。例如，假設寫入邏輯位址為90，其中快閃記憶體101之一區塊包含8頁，並且一頁大小為10byte，則可得到邏輯區塊編號LBN為90除以80之商數，而邏輯頁編號LSN為90除以80之餘數再除以頁大小所得到的數值，即在此範例中，LBN=1，LSN=1，因此處理器102將接收到的既定資料存入第1個邏輯區塊之第1頁。處理器102進一步根據邏輯區塊編號LBN取得對應之一映射區塊，其中此映射區塊為快閃記憶體101中實際被配置之一物理區塊，用以儲存此邏輯區塊的原始資料。當處理器102判斷映射區塊中對應於此邏輯頁編號LSN之一頁尚未被寫入時，處理器102將既定資料寫入至該頁，並且當該頁已被寫入時，處理器102進一步取得對應於此映射區塊之一修改區塊，以及對應於此修改區塊之一快取區塊，處理器102將既定資料寫入至此修改區塊之一空白頁，並且將既定資料之邏輯頁編號LSN寫入至此快取區塊之一空白頁。According to an embodiment of the present invention, when writing to the flash memory 101, the processor 102 receives a write command including a write logic address and a predetermined data, and obtains a correspondence according to the write logic address. The logical block number LBN and a logical page number LSN. For example, assuming that the write logical address is 90, where one block of the flash memory 101 contains 8 pages, and the page size is 10 bytes, the quotient of the logical block number LBN is divided by 90 by 80, and The logical page number LSN is a value obtained by dividing 90 by the remainder of 80 and dividing by the page size, that is, in this example, LBN=1, LSN=1, so the processor 102 stores the received data in the first one. Page 1 of the logical block. The processor 102 further obtains a corresponding one of the mapping blocks according to the logical block number LBN, where the mapping block is one of the physical blocks actually configured in the flash memory 101 for storing the original data of the logical block. When the processor 102 determines that one of the mapped blocks corresponding to the logical page number LSN has not been written, the processor 102 writes the predetermined material to the page, and when the page has been written, the processor 102 Further obtaining a modified block corresponding to one of the mapping blocks, and corresponding to one of the modified blocks, the processor 102 writes the predetermined data to a blank page of the modified block, and the predetermined data is The logical page number LSN is written to one of the blank pages of this cache block.
根據本發明之一實施例，處理器102更進一步在隨機存取記憶體裝置103內建立一邏輯至映射區塊對應表(第一資訊表)、一物理區塊資訊表(第二資訊表)以及一快取區塊索引表(第三資訊表)。第3圖係顯示根據本發明之一實施例所述之邏輯至映射區塊對應表300之資料結構示意圖。根據本發明之一實施例，邏輯至映射區塊對應表300依照邏輯區塊編號之順序依序儲存各邏輯區塊所對應之映射區塊之一物理區塊編號，例如，對應於邏輯區塊編號LBN=0之一邏輯區塊，其映射區塊之物理區塊編號為0x0002。第4圖係顯示根據本發明之一實施例所述之物理區塊資訊表400之資料結構示意圖。根據本發明之一實施例，物理區塊資訊表400依照物理區塊編號之順序依序儲存各物理區塊之狀態資訊與其連結資訊。例如，物理區塊編號為0之一物理區塊為一空閒區塊(FB)，即，尚未被使用之區塊，其連結資訊則儲存下一個空閒區塊之物理區塊編號。物理區塊編號為2之一物理區塊為一映射區塊(MpB)，其連結資訊則儲存對應之修改區塊之物理區塊編號(0x0003)。物理區塊編號為3之一物理區塊為一修改區塊(MoB)，其連結資訊則儲存對應之快取頁之一快取區塊索引，其中快取區塊索引可用以指示出對應於此修改區塊之快取區塊的位置以及頁資訊。例如，對於同樣包含8頁之快取區塊，快取區塊索引0x0011可指示出快取頁位於系統配置的第1個快取區塊(11除以8之商數)的第3頁(11除以8之餘數)。而物理區塊編號為6之一物理區塊為一快取區塊(CB)，其連結資訊則儲存此快取區塊之快取區塊編號。第5a圖係顯示根據本發明之一實施例所述之快取區塊索引表500之資料結構示意圖。快取區塊索引表500根據快取區塊編號依序紀錄該快取區塊之物理區塊編號與第一個空閒的快取頁(即，快取區塊的第一個空白頁)的頁編號。如圖所示，假設系統最大可配置4個快取區塊，並且各快取區塊可包含8頁，則快取區塊索引表500依序紀錄這4個快取區塊的物理區塊編號與第一個空白頁的編號。根據本發明之一實施例，當一個快取區塊的各頁都被使用過後，才會配置下一個快取區塊。如第5a圖所示，編號0的快取區塊已被存滿資料，因此目前使用中的快取區塊為編號1的快取區塊。According to an embodiment of the present invention, the processor 102 further establishes a logic-to-map block correspondence table (first information table) and a physical block information table (second information table) in the random access memory device 103. And a cache block index table (third information table). FIG. 3 is a block diagram showing the structure of a logical-to-map block correspondence table 300 according to an embodiment of the present invention. According to an embodiment of the present invention, the logical-to-map block correspondence table 300 sequentially stores the physical block number of one of the mapping blocks corresponding to each logical block according to the logical block number, for example, corresponding to the logical block. The logical block numbered LBN=0, and the physical block number of the mapped block is 0x0002. FIG. 4 is a block diagram showing the structure of a physical block information table 400 according to an embodiment of the present invention. According to an embodiment of the present invention, the physical block information table 400 sequentially stores the status information of each physical block and its connection information in the order of the physical block number. For example, if the physical block number is 0, one physical block is a free block (FB), that is, a block that has not been used, and the link information stores the physical block number of the next free block. One physical block numbered as 2 is a mapping block (MpB), and the link information stores the physical block number (0x0003) of the corresponding modified block. One physical block number is one modified block (MoB), and the link information stores one cache block index corresponding to the cache page, wherein the cache block index can be used to indicate that the corresponding block corresponds to The location of the cache block and the page information of this modified block. For example, for a cache block that also contains 8 pages, the cache block index 0x0011 may indicate that the cache page is located on page 3 of the first cache block of the system configuration (11 divided by the quotient of 8) ( 11 divided by the remainder of 8). The physical block number 6 is a cache block (CB), and the link information stores the cache block number of the cache block. Figure 5a is a diagram showing the data structure of the cache block index table 500 according to an embodiment of the present invention. The cache block index table 500 sequentially records the physical block number of the cache block and the first free cache page (ie, the first blank page of the cache block) according to the cache block number. Page number. As shown in the figure, assuming that the system can configure up to four cache blocks, and each cache block can contain eight pages, the cache block index table 500 sequentially records the physical blocks of the four cache blocks. Number the number with the first blank page. According to an embodiment of the present invention, the next cache block is configured when each page of a cache block has been used. As shown in Figure 5a, the cache block numbered 0 has been filled with data, so the cache block currently in use is the cache block number 1.
第6圖係顯示根據本發明之一實施例所述之快閃記憶體管理方法流程圖。如圖所示，處理器102首先接收包含一寫入邏輯位址與一既定資料之一寫入指令，用以寫入該既定資料至一快閃記憶體裝置之一頁(步驟S601)。接著，當該頁已寫入資料時，處理器102取得對應於包含該頁之一映射區塊之一修改區塊，以及配置對應於該修改區塊之一快取區塊(步驟S602)。最後，處理器102寫入該既定資料於該修改區塊之一空白頁，並且寫入包含該修改區塊之該頁之位置資訊於該快取區塊之一空白頁(步驟S603)。Figure 6 is a flow chart showing a method of managing a flash memory according to an embodiment of the present invention. As shown, the processor 102 first receives a write command including a write logical address and a predetermined data for writing the predetermined data to a page of a flash memory device (step S601). Next, when the page has been written, the processor 102 obtains a modified block corresponding to one of the mapped blocks including the page, and configures one of the cache blocks corresponding to the modified block (step S602). Finally, the processor 102 writes the predetermined data to a blank page of the modified block, and writes location information of the page including the modified block to a blank page of the cache block (step S603).
第7a-7b圖係顯示根據本發明之一實施例所述之快閃記憶體之寫入操作之詳細流程圖。首先，處理器102根據接收到的寫入指令取得寫入邏輯位址所對應之邏輯區塊編號LBN與邏輯頁編號LSN(步驟S701)。接著，處理器102查詢邏輯至映射區塊對應表以取得映射區塊的物理區塊編號(步驟S702)。接著，處理器102檢查此映射區塊中對應於此邏輯頁編號LSN之一頁是否為空白頁(步驟S703)。若此頁為一空白頁，則處理器102將既定資料寫入此頁(步驟S704)。若此頁已存有資料，則處理器102依據物理區塊資訊表查詢映射區塊是否有對應的修改區塊(步驟S705)。若此映射區塊沒有對應的修改區塊，則處理器102為此映射區塊分配一修改區塊(步驟S706)。接著，處理器102將既定資料寫入此修改區塊的第一頁(步驟S707)，並且分配快取區塊之一頁給此修改區塊(步驟S708)，用以紀錄此既定資料之位置資訊(例如，邏輯頁編號LSN)，並且最後更新物理區塊資訊表(參考第4圖)與快取區塊索引表(參考第5a、5b圖)中映射區塊、修改區塊以及快取區塊的相關資訊(步驟S709)。7a-7b are detailed flowcharts showing the write operation of the flash memory according to an embodiment of the present invention. First, the processor 102 acquires the logical block number LBN and the logical page number LSN corresponding to the write logical address according to the received write command (step S701). Next, the processor 102 queries the logical-to-map block correspondence table to obtain the physical block number of the mapped block (step S702). Next, the processor 102 checks whether a page corresponding to this logical page number LSN in the mapping block is a blank page (step S703). If the page is a blank page, the processor 102 writes the predetermined material to the page (step S704). If the page has stored data, the processor 102 queries whether the mapping block has a corresponding modified block according to the physical block information table (step S705). If the mapping block does not have a corresponding modified block, the processor 102 allocates a modified block for this mapping block (step S706). Next, the processor 102 writes the predetermined data to the first page of the modified block (step S707), and allocates one page of the cache block to the modified block (step S708) for recording the location of the predetermined data. Information (for example, logical page number LSN), and finally update the physical block information table (refer to Figure 4) and the cache block index table (refer to Figure 5a, 5b) map blocks, modify blocks and cache Information about the block (step S709).
另一方面，若此映射區塊已有對應的修改區塊，則處理器102依據物理區塊資訊表中映射區塊的連結資訊取得修改區塊所對應的快取頁的快取區塊索引(步驟S710)。接著，處理器102再根據快取區塊索引查詢快取區塊索引表，以取得此快取頁所對應的快取區塊的物理區塊編號(步驟S711)。接著，處理器102將此快取頁的內容載入隨機存取記憶體裝置103(步驟S712)。接著，處理器102操作於隨機存取記憶體裝置103中，自快取頁之資料尾端倒序遍曆(visit)快取頁所儲存的資料，找出此快取頁的資料區域中，第一個未被使用的空白資料欄位的索引，以取得此快取頁所對應之修改區塊的第一個可使用之空白頁的位置(步驟S713)，並根據此位置資訊將既定資料寫入修改區塊所對應的空白頁(步驟S714)。接著，處理器102將此既定資料的位置資訊(例如，邏輯頁編號LSN)寫入至被載入隨機存取記憶體裝置103之快取頁的下一個空白欄位，並且將此被更新過的快取頁資料更新至快閃記憶體101內之快取區塊的下一個空白頁(步驟S715)。最後，處理器102更新物理區塊資訊表(參考第4圖)與快取區塊索引表(參考第5a、5b圖)中映射區塊、修改區塊以及快取區塊的相關資訊(步驟S716)。On the other hand, if the mapping block already has a corresponding modified block, the processor 102 obtains the cached block index of the cached page corresponding to the modified block according to the link information of the mapped block in the physical block information table. (Step S710). Then, the processor 102 queries the cache block index table according to the cache block index to obtain the physical block number of the cache block corresponding to the cache page (step S711). Next, the processor 102 loads the contents of the cache page into the random access memory device 103 (step S712). Next, the processor 102 operates in the random access memory device 103, and sequentially stores the data stored in the cache page from the end of the data page of the cache page to find out the data area of the cache page. An index of an unused blank data field to obtain the position of the first usable blank page of the modified block corresponding to the cache page (step S713), and writing the predetermined data according to the location information The blank page corresponding to the modified block is entered (step S714). Next, the processor 102 writes the location information (for example, the logical page number LSN) of the predetermined material to the next blank field of the cache page loaded into the random access memory device 103, and updates this. The cache page data is updated to the next blank page of the cache block in the flash memory 101 (step S715). Finally, the processor 102 updates the physical block information table (refer to FIG. 4) and the information of the mapping block, the modified block, and the cache block in the cache block index table (refer to FIG. 5a, 5b) (steps) S716).
第8a-8e圖係顯示根據本發明之一實施例所述之快閃記憶體之寫入操作之示意圖。值得注意的是，圖式中的虛線用以區隔分別位於快閃記憶體101與隨機存取記憶體裝置103之資料，其中虛線的右側用以顯示快閃記憶體101內的資料結構。如上述，假設處理器102接收到的寫入邏輯位址為90，其中寫入快閃記憶體101之一區塊包含8頁，並且一頁大小為10byte，則可得到邏輯區塊編號LBN為90除以80之商數，而邏輯頁編號LSN為90除以80之餘數再除以頁大小所得到的數值，即在此範例中，LBN=1，LSN=1，因此處理器102必須將接收到的既定資料存入第1個邏輯區塊之第1頁。接著，如第8a圖所示，處理器102根據邏輯區塊編號(LBN=1)查找邏輯至映射區塊對應表801中索引1的資料欄位內容，得到對應之映射區塊之物理區塊編號。其中，根據本發明之一實施例，若該資料欄位為空，代表此邏輯區塊尚未分配對應之映射區塊，處理器102可分配映射區塊給此邏輯區塊。若該資料欄位不為空，代表此邏輯區塊已分配有對應之映射區塊，例如，在此實施例中，對應之映射區塊之物理區塊編號為3，代表此映射區塊實際配置為第3個物理區塊。處理器102接著根據邏輯頁編號(LSN=1)存取映射區塊803(物理區塊3)之第1頁，並且判斷此頁是否已被使用。根據本發明之一實施例，處理器102可根據此頁之冗餘區域中所儲存的LBN與LSN判斷此頁是否已被使用，若無紀錄LBN與LSN，則處理器102可直接將資料寫入該頁。另一方面，若此頁之冗餘區域已紀錄LBN與LSN，代表此頁之資料區域已被使用，如圖所示之映射區塊803之第1頁，其中被填滿的欄位代表該欄位已被使用。因此，處理器102接著根據得到的物理區塊編號查找物理區塊資訊表802中索引3的資料欄位內容，其中物理區塊資訊表802如上述包含狀態與連結資訊兩欄位，狀態欄位用以紀錄此物理區塊為一空閒區塊(FB)、快取區塊(CB)、映射區塊(MpB)或修改區塊(MoB)，而連結資訊如上述分別用以儲存此物理區塊之連結資訊。根據本發明之一實施例，若連結資訊為空，代表此映射區塊內所儲存的資料尚未被修改過，處理器102可配置一修改區塊以及一快取區塊，利用此修改區塊之一空白頁儲存在本次寫入操作要被儲存的既定資料，並且於快取區塊之一空白頁儲存此既定資料所對應之邏輯頁編號(LSN=1)。另一方面，當連結資訊不為空，例如第8a圖所示，處理器102由物理區塊資訊表802中得知映射區塊對應之修改區塊之物理區塊編號為4。8a-8e are diagrams showing a write operation of a flash memory according to an embodiment of the present invention. It should be noted that the dotted line in the drawing is used to separate the data located in the flash memory 101 and the random access memory device 103, respectively, wherein the right side of the dotted line is used to display the data structure in the flash memory 101. As described above, it is assumed that the write logical address received by the processor 102 is 90, wherein one block of the write flash memory 101 contains 8 pages, and the page size is 10 bytes, then the logical block number LBN is obtained. 90 is divided by the quotient of 80, and the logical page number LSN is the value obtained by dividing 90 by the remainder of 80 and dividing by the page size, that is, in this example, LBN=1, LSN=1, so the processor 102 must The received data received is stored in the first page of the first logical block. Next, as shown in FIG. 8a, the processor 102 searches the logical field to the index field of the index 1 in the mapping block correspondence table 801 according to the logical block number (LBN=1) to obtain the physical block of the corresponding mapping block. Numbering. According to an embodiment of the present invention, if the data field is empty, indicating that the logical block has not been allocated a corresponding mapping block, the processor 102 may allocate the mapping block to the logical block. If the data field is not empty, it means that the logical block has been assigned a corresponding mapping block. For example, in this embodiment, the physical block number of the corresponding mapping block is 3, which represents the actual mapping block. Configured as the third physical block. The processor 102 then accesses the first page of the mapping block 803 (physical block 3) according to the logical page number (LSN=1) and determines whether the page has been used. According to an embodiment of the present invention, the processor 102 can determine whether the page has been used according to the LBN and the LSN stored in the redundant area of the page. If there is no record LBN and LSN, the processor 102 can directly write the data. Go to this page. On the other hand, if the redundant area of the page has recorded LBN and LSN, the data area representing the page has been used, as shown in the first page of the mapping block 803, wherein the filled field represents the The field has been used. Therefore, the processor 102 then searches the data field content of the index 3 in the physical block information table 802 according to the obtained physical block number, wherein the physical block information table 802 includes two fields of status and link information, and the status field. The physical block is used to record a free block (FB), a cache block (CB), a map block (MpB), or a modified block (MoB), and the link information is used to store the physical area as described above. Link information of the block. According to an embodiment of the present invention, if the link information is empty, the data stored in the map block has not been modified, and the processor 102 can configure a modified block and a cache block to modify the block. One blank page stores the predetermined data to be stored in this write operation, and stores the logical page number (LSN=1) corresponding to the predetermined data in one blank page of the cache block. On the other hand, when the link information is not empty, for example, as shown in FIG. 8a, the processor 102 knows from the physical block information table 802 that the physical block number of the modified block corresponding to the mapped block is 4.
接著，處理器102根據修改區塊之物理區塊編號查找物理區塊資訊表802內對應的欄位，得到修改區塊之連結資訊。如上述，修改區塊之連結資訊儲存對應之快取頁之一快取區塊索引。處理器102接著根據快取區塊索引得到快取區塊之位置資訊，如上述，在此實施例中，快取區塊索引為11，處理器102因此得知對應於此修改區塊之快取頁位於系統配置的第1個快取區塊(11除以8之商數)的第3頁(11除以8之餘數)。請參考第8b圖，處理器102可進一步根據快取區塊索引表809取得此快取頁所對應的快取區塊的物理區塊編號，得知系統配置的第1個快取區塊(快取區塊編號為1)所對應的物理區塊編號為2。處理器102接著可存取系統配置的第1個快取區塊805的第3頁。Next, the processor 102 searches for a corresponding field in the physical block information table 802 according to the physical block number of the modified block, and obtains the link information of the modified block. As described above, the link information of the modified block stores one cache block index corresponding to the cache page. The processor 102 then obtains the location information of the cache block according to the cache block index. As described above, in this embodiment, the cache block index is 11, and the processor 102 thus knows that the modified block corresponds to the fast. The page fetch is located on page 3 of the first cache block of the system configuration (11 divided by the quotient of 8) (11 divided by the remainder of 8). Referring to FIG. 8b, the processor 102 may further obtain the physical block number of the cache block corresponding to the cache page according to the cache block index table 809, and learn the first cache block configured by the system ( The physical block number corresponding to the cache block number is 1) is 2. Processor 102 can then access page 3 of the first cache block 805 of the system configuration.
值得注意的是，如上述，快取區塊的冗餘區域同樣會紀錄對應之修改區塊之物理區塊編號，例如快取區塊804與805的冗餘區域(右側欄位)可儲存對應之修改區塊之物理區塊編號，用以顯示出各頁之資料區域所儲存之位置資訊屬於哪個修改區塊。根據本發明之一實施例，當處理器102根據快取區塊索引找到對應之快取頁806時，處理器102將快取頁806之內容載入隨機存取記憶體裝置103。It should be noted that, as described above, the redundant area of the cache block also records the physical block number of the corresponding modified block. For example, the redundant area of the cache block 804 and 805 (the right field) can be stored correspondingly. The physical block number of the modified block is used to indicate which modified block the location information stored in the data area of each page belongs to. In accordance with an embodiment of the present invention, processor 102 loads the contents of cache page 806 into random access memory device 103 when processor 102 finds a corresponding cache page 806 based on the cache block index.
在此實施例中，由於是要將資料寫入快閃記憶體，因此處理器102自快取頁806之資料尾端倒序遍曆(visit)快取頁806之內容，如第8c圖所示，處理器102發現最後一筆被儲存之邏輯頁編號LSN位於快取頁806的第5個欄位。因此，處理器102得知修改區塊內下一個可使用之空白頁為第6頁。In this embodiment, since the data is to be written to the flash memory, the processor 102 sequentially traverses the contents of the cache page 806 from the data end of the cache page 806, as shown in FIG. 8c. The processor 102 finds that the last stored logical page number LSN is located in the fifth field of the cache page 806. Therefore, the processor 102 knows that the next available blank page in the modified block is page 6.
值得注意的是，在本發明之實施例中，由於快取頁806之內容已被載入隨機存取記憶體裝置103，因此處理器102可快速得知修改區塊內下一個可使用之空白頁，因此，與傳統技術中必須在快閃記憶體中倒序遍曆修改區塊的內容以找出下一個空白頁等的技術相比，本發明所提出之快閃記憶體管理方法實際上僅需存取快取區塊之一頁(即，上述之快取頁)，以及修改區塊之一頁，顯然地可大幅度地提升快閃記憶體之寫入速度。It should be noted that in the embodiment of the present invention, since the content of the cache page 806 has been loaded into the random access memory device 103, the processor 102 can quickly know the next available blank in the modified block. The page, therefore, the flash memory management method proposed by the present invention is actually only compared with the technique in the prior art that the content of the modified block must be traversed in the flash memory to find the next blank page or the like. Accessing one page of the cache block (ie, the cache page described above), and modifying one of the pages of the block, can obviously greatly improve the write speed of the flash memory.
請參考至第8d圖，由於處理器102已得知修改區塊807(物理區塊4)內下一個可使用之空白頁為第6頁，因此處理器102接著將既定資料寫入該頁，並且在該頁的冗餘區域寫入這筆既定資料的邏輯頁編號LSN(以及邏輯區塊編號LBN，圖未示)。此外，請參考回第8c圖，由於處理器102已在遍曆過程中得知快取頁806下一個可被使用之欄位為第6個欄位，如第8c圖中繪出的箭頭所指，處理器102接著將這筆既定資料的邏輯頁編號LSN=1寫入至被載入隨機存取記憶體裝置103之快取頁806第6個欄位。Referring to FIG. 8d, since the processor 102 has learned that the next available blank page in the modified block 807 (physical block 4) is the sixth page, the processor 102 then writes the predetermined data to the page. And the logical page number LSN (and the logical block number LBN, not shown) of the predetermined material is written in the redundant area of the page. In addition, please refer back to Figure 8c, since the processor 102 has learned during the traversal that the next available field of the cache page 806 is the sixth field, as shown by the arrow in Figure 8c. The processor 102 then writes the logical page number LSN=1 of the given material to the sixth field of the cache page 806 that is loaded into the random access memory device 103.
值得注意的是，由於實際上快取區塊805是被儲存於快閃記憶體內，因此處理器102接著將隨機存取記憶體裝置103內被更新之快取頁806資料寫入至快取區塊805(物理區塊2)的下一個空白頁。根據本發明之一實施例，處理器102根據快取區塊索引表809得知快取區塊805的下一個空白頁為第4頁，因此處理器102如第8e圖所示將被更新之快取頁806資料寫入至快取區塊805(物理區塊2)的第4頁，並且將快取區塊索引表809中此快取區塊的第一空白頁資訊更新為5。此外，修改區塊所對應之快取區塊索引變成12，因此處理器102最後於物理區塊資訊表802內將修改區塊807所對應之快取區塊索引更新成12。It should be noted that since the cache block 805 is actually stored in the flash memory, the processor 102 then writes the updated cache page 806 data in the random access memory device 103 to the cache area. The next blank page of block 805 (physical block 2). According to an embodiment of the present invention, the processor 102 knows that the next blank page of the cache block 805 is the fourth page according to the cache block index table 809, so the processor 102 will be updated as shown in FIG. 8e. The cache page 806 data is written to page 4 of the cache block 805 (physical block 2), and the first blank page information of the cache block in the cache block index table 809 is updated to 5. In addition, the cache block index corresponding to the modified block becomes 12, so the processor 102 finally updates the cache block index corresponding to the modified block 807 to 12 in the physical block information table 802.
第9圖係顯示根據本發明之另一實施例所述之快閃記憶體管理方法流程圖。首先，處理器102接收包含一讀取邏輯位址之一讀取指令，並根據讀取邏輯位址取得一快取區塊之一快取區塊索引(步驟S901)。接著，處理器102根據快取區塊索引載入快取區塊之複數資料欄位所儲存之位置資訊至一隨機存取記憶體裝置(步驟S902)。接著，處理器102於隨機存取記憶體裝置內自快取區塊之資料欄位尾端倒序尋找讀取邏輯位址所對應之一位置資訊，以取得讀取邏輯位址最近儲存之位置資訊(步驟S903)。最後，處理器102根據取得之位置資訊存取讀取邏輯位址所對應之修改區塊內所儲存之對應於讀取邏輯位址之資料(步驟S904)。Figure 9 is a flow chart showing a method of managing a flash memory according to another embodiment of the present invention. First, the processor 102 receives a read instruction including a read logical address, and obtains a cache block index of a cache block according to the read logical address (step S901). Next, the processor 102 loads the location information stored in the complex data field of the cache block into a random access memory device according to the cache block index (step S902). Then, the processor 102 searches for the location information corresponding to the read logical address in the random access memory device from the end of the data field of the cache block to obtain the location information of the most recently stored logical address. (Step S903). Finally, the processor 102 accesses the data corresponding to the read logical address stored in the modified block corresponding to the read logical address according to the obtained location information (step S904).
第10圖係顯示根據本發明之一實施例所述之快閃記憶體之讀取操作之詳細流程圖。首先，處理器102根據讀取指令之讀取邏輯位址取得邏輯區塊編號LBN與邏輯頁編號LSN(步驟S1001)。接著，處理器102查詢邏輯至映射區塊對應表以取得映射區塊的物理區塊編號(步驟S1002)。接著，處理器102檢查此映射區塊中對應於此邏輯頁編號LSN之一頁是否為空白頁(步驟S1003)。若是，處理器102返回空白資料(步驟S1004)。若否，處理器102依據物理區塊資訊表查詢映射區塊是否有對應的修改區塊(步驟S1005)。若此映射區塊沒有對應的修改區塊，則處理器102直接返回此頁所儲存之資料(步驟S1006)。若此映射區塊有對應的修改區塊，則處理器102依據物理區塊資訊表中映射區塊的連結資訊取得修改區塊所對應的快取頁的快取區塊索引(步驟S1007)。接著，處理器102再根據快取區塊索引查詢快取區塊索引表，以取得此快取頁所對應的快取區塊的物理區塊編號(步驟S1008)。接著，處理器102將此快取頁的內容載入隨機存取記憶體裝置103(步驟S1009)。接著，處理器102操作於隨機存取記憶體裝置103中，自快取頁之資料尾端倒序遍曆(visit)快取頁所儲存的資料，尋找出最新一筆對應於此邏輯頁編號LSN之紀錄，並取得儲存此邏輯頁編號LSN之欄位之索引(步驟S1010)。最後，處理器102根據此索引讀取修改區塊中對應於此邏輯頁編號LSN之最新一筆資料並返回(步驟S1011)。Figure 10 is a detailed flow chart showing the reading operation of the flash memory according to an embodiment of the present invention. First, the processor 102 obtains the logical block number LBN and the logical page number LSN according to the read logical address of the read command (step S1001). Next, the processor 102 queries the logical-to-map block correspondence table to obtain the physical block number of the mapped block (step S1002). Next, the processor 102 checks whether a page corresponding to this logical page number LSN in the mapping block is a blank page (step S1003). If so, the processor 102 returns blank data (step S1004). If not, the processor 102 queries whether the mapping block has a corresponding modified block according to the physical block information table (step S1005). If the mapping block does not have a corresponding modified block, the processor 102 directly returns the data stored on the page (step S1006). If the mapping block has a corresponding modified block, the processor 102 obtains the cached block index of the cached page corresponding to the modified block according to the link information of the mapped block in the physical block information table (step S1007). Then, the processor 102 queries the cache block index table according to the cache block index to obtain the physical block number of the cache block corresponding to the cache page (step S1008). Next, the processor 102 loads the contents of the cache page into the random access memory device 103 (step S1009). Next, the processor 102 operates in the random access memory device 103, and sequentially stores the data stored in the cache page from the end of the data page of the cache page to find the latest one corresponding to the logical page number LSN. Record and obtain an index for storing the field of this logical page number LSN (step S1010). Finally, the processor 102 reads the latest piece of data corresponding to the logical page number LSN in the modified block according to the index and returns (step S1011).
第11a-11d圖係顯示根據本發明之一實施例所述之快閃記憶體之讀取操作之示意圖。假設處理器102接收到的讀取邏輯位址為90，則處理器102可得到邏輯區塊編號LBN=1，邏輯頁編號LSN=1。接著，如第11a圖所示，處理器102根據邏輯區塊編號(LBN=1)查找邏輯至映射區塊對應表801中索引1的資料欄位內容，得到對應之映射區塊之物理區塊編號。其中，根據本發明之一實施例，若該資料欄位為空，代表此邏輯區塊尚未分配對應之映射區塊，處理器102無法找到有效之資料，便可直接返回此結果。若該資料欄位不為空，代表此邏輯區塊已分配有對應之映射區塊，例如，在此實施例中，對應之映射區塊之物理區塊編號為3，代表此映射區塊實際配置為第3個物理區塊。處理器102接著根據邏輯頁編號(LSN=1)存取映射區塊803(物理區塊3)之第1頁，並且判斷此頁是否已被使用。根據本發明之一實施例，處理器102可根據此頁之冗餘區域中所儲存的LBN與LSN判斷此頁是否已被使用，若無紀錄LBN與LSN，代表此頁尚未被使用，處理器102可返回空資料。另一方面，若此頁之冗餘區域已記錄LBN與LSN，代表此頁之資料區域已被使用，如圖所示之映射區塊803之第1頁，其中被填滿的欄位代表該欄位已被使用。因此，處理器102接著根據得到的物理區塊編號查找物理區塊資訊表802中索引3的資料欄位內容。根據本發明之一實施例，若映射區塊之連結資訊為空，代表此映射區塊內所儲存的資料尚未被修改過，即，映射區塊內所儲存的資料為有效的，處理器102可直接讀取並返回映射區塊內所儲存的資料。另一方面，當連結資訊不為空，代表此映射區塊內所儲存的資料已被修改過，即，映射區塊內所儲存的資料為無效的。因此，處理器102進一步透過物理區塊資訊表802中得知映射區塊所對應之修改區塊之物理區塊編號為4。11a-11d are diagrams showing a read operation of a flash memory according to an embodiment of the present invention. Assuming that the read logical address received by the processor 102 is 90, the processor 102 can obtain the logical block number LBN=1 and the logical page number LSN=1. Next, as shown in FIG. 11a, the processor 102 searches the logical field to the index field of the index 1 in the mapping block correspondence table 801 according to the logical block number (LBN=1) to obtain the physical block of the corresponding mapping block. Numbering. According to an embodiment of the present invention, if the data field is empty, indicating that the logical block has not been assigned a corresponding mapping block, and the processor 102 cannot find valid data, the result can be directly returned. If the data field is not empty, it means that the logical block has been assigned a corresponding mapping block. For example, in this embodiment, the physical block number of the corresponding mapping block is 3, which represents the actual mapping block. Configured as the third physical block. The processor 102 then accesses the first page of the mapping block 803 (physical block 3) according to the logical page number (LSN=1) and determines whether the page has been used. According to an embodiment of the present invention, the processor 102 can determine whether the page has been used according to the LBN and the LSN stored in the redundant area of the page. If there is no record LBN and LSN, the processor is not used, the processor is not used. 102 can return empty data. On the other hand, if the LBN and LSN have been recorded in the redundant area of the page, the data area representing the page has been used, as shown in the first page of the mapping block 803, wherein the filled field represents the The field has been used. Therefore, the processor 102 then searches the data field contents of the index 3 in the physical block information table 802 according to the obtained physical block number. According to an embodiment of the present invention, if the link information of the mapping block is empty, the data stored in the mapping block has not been modified, that is, the data stored in the mapping block is valid, and the processor 102 is The data stored in the mapping block can be directly read and returned. On the other hand, when the link information is not empty, the data stored in the map block has been modified, that is, the data stored in the map block is invalid. Therefore, the processor 102 further knows through the physical block information table 802 that the physical block number of the modified block corresponding to the mapping block is 4.
接著，處理器102根據修改區塊之物理區塊編號查找物理區塊資訊表802內對應的欄位，得到修改區塊之連結資訊。如上述，修改區塊之連結資訊儲存對應之快取頁之一快取區塊索引，例如在此實施例中，快取區塊索引為12。接著，處理器102根據快取區塊索引得知對應於此修改區塊之快取頁位於系統配置的第1個快取區塊(12除以8之商數)的第4頁(12除以8之餘數)。請參考第11b圖，處理器102可進一步根據快取區塊索引表809取得此快取頁所對應的快取區塊的物理區塊編號，得知系統配置的第1個快取區塊(快取區塊編號為1)所對應的物理區塊編號為2。處理器102接著可存取系統配置的第1個快取區塊805的第4頁，並且將此快取頁808之內容載入隨機存取記憶體裝置103。Next, the processor 102 searches for a corresponding field in the physical block information table 802 according to the physical block number of the modified block, and obtains the link information of the modified block. As described above, the link information of the modified block stores one cache page index corresponding to the cache page. For example, in this embodiment, the cache block index is 12. Next, the processor 102 learns, according to the cache block index, that the cache page corresponding to the modified block is located on the fourth page of the first cache block (12 divided by the quotient of 8) of the system configuration (12 Take the remainder of 8). Referring to FIG. 11b, the processor 102 may further obtain the physical block number of the cache block corresponding to the cache page according to the cache block index table 809, and learn the first cache block configured by the system ( The physical block number corresponding to the cache block number is 1) is 2. The processor 102 can then access page 4 of the first cache block 805 of the system configuration and load the contents of the cache page 808 into the random access memory device 103.
接著，處理器102自快取頁808之資料尾端倒序遍曆快取頁808之內容，以尋找出最後一筆存有LSN=1的資料的索引。如上述，由於快取頁808之內容已被載入隨機存取記憶體裝置103，因此處理器102不需遍曆配置於快閃記憶體101內之修改區塊，僅需透過遍曆儲存於隨機存取記憶體裝置103之快取頁，即可得知修改區塊內最新存有LSN=1的資料的位置。因此，與傳統技術相比，本發明所提出之快閃記憶體管理方法顯然地可大幅度地提升快閃記憶體之讀取速度。再者，雖然本實施例中，處理器102是從尾端開始倒序遍曆隨機存取記憶體裝置103中快取頁的資料欄位元，但是顯然也可以從頭端開始順序遍曆該快取頁的資料欄位元來獲得需要存取的頁在該修改區塊中的位置資訊。Next, the processor 102 traverses the contents of the cache page 808 in reverse order from the data end of the cache page 808 to find the index of the last data with the LSN=1. As described above, since the content of the cache page 808 has been loaded into the random access memory device 103, the processor 102 does not need to traverse the modified block disposed in the flash memory 101, and only needs to be stored by traversing. The cache page of the random access memory device 103 can know the location of the latest data with the LSN=1 in the modified block. Therefore, compared with the conventional technology, the flash memory management method proposed by the present invention can significantly improve the reading speed of the flash memory. Furthermore, in the embodiment, the processor 102 sequentially traverses the data field of the cache page in the random access memory device 103 from the tail end, but obviously it is also possible to sequentially traverse the cache from the head end. The data field of the page is used to obtain the location information of the page to be accessed in the modified block.
如第11c圖所示，處理器102發現最後一筆存有LSN=1的資料位於快取頁808的第6個欄位。因此，處理器102可得知修改區塊的第6頁儲存著對應於邏輯位址為90的最新資料。最後，如第11d圖所示，處理器102存取修改區塊807(物理區塊4)的第6頁之資料區域，並返回讀取的資料。As shown in FIG. 11c, the processor 102 finds that the last data with LSN=1 is located in the sixth field of the cache page 808. Therefore, the processor 102 can know that the sixth page of the modified block stores the latest data corresponding to the logical address of 90. Finally, as shown in Fig. 11d, the processor 102 accesses the data area of the sixth page of the modified block 807 (physical block 4) and returns the read data.
根據本發明之一實施例，快取區塊的數量可根據計算機系統的需求而決定。例如，對於一快閃記憶體裝置，可配置四個快取區塊，並依序分配快取區塊編號(例如，0~3)，並且處理器102於快取區塊初始化時，可藉由遍曆修改區塊之冗餘區域所儲存之位置資訊建立出快取區塊。處理器102接著根據映射區塊、修改區塊以及快取區塊之冗餘區域所儲存之資料(包含邏輯塊編號與邏輯頁編號)建立出如第3圖所示之邏輯至映射區塊對應表300、如第4圖所示之物理區塊資訊表400以及如第5圖所示之快取區塊索引表500。根據本發明之一實施例，為了避免不正常關機導致快取區塊所儲存的資料產生錯誤，於計算機系統初始化時，處理器102也可先檢查各快取區塊所儲存的內容是否正確，例如，根據各快取頁之資料欄位所儲存的位置資訊(即，邏輯頁編號)以及各快取頁之冗餘區域所儲存的修改區塊之物理區塊編號，比對該快取頁之各位置資訊是否與此修改區塊之各頁的冗餘區域所儲存的邏輯頁編號相符。若符合則保留此快取區塊，若不符合，則捨棄此快取區塊，直接抹除。此外，當一個快取區塊存滿資料時，處理器102可取出下一個預留的空閒快取區塊使用(如第5a圖與第5b圖所示)，並且當所有已被使用的快取區塊達到系統規定的最大可用快取區塊數量時，例如，若第5b圖所示之快取區塊索引表501中4個快取區塊的第一個空白頁皆紀錄為系統最大頁數8時，處理器102直接抹除所有快取區塊，以釋放出有效的空間。According to an embodiment of the invention, the number of cache blocks can be determined according to the needs of the computer system. For example, for a flash memory device, four cache blocks can be configured, and cache block numbers (eg, 0~3) are sequentially allocated, and the processor 102 can borrow when the cache block is initialized. A cache block is created by traversing the location information stored in the redundant area of the modified block. The processor 102 then establishes a logical-to-map block corresponding to the mapping block, the modified block, and the data stored in the redundant area of the cache block (including the logical block number and the logical page number) as shown in FIG. The table 300, the physical block information table 400 as shown in FIG. 4, and the cache block index table 500 as shown in FIG. According to an embodiment of the present invention, in order to avoid an abnormal shutdown, the data stored in the cache block is generated incorrectly. When the computer system is initialized, the processor 102 may first check whether the content stored in each cache block is correct. For example, the location information stored in the data field of each cache page (ie, the logical page number) and the physical block number of the modified block stored in the redundant area of each cache page are compared to the cache page. Whether each location information matches the logical page number stored in the redundant area of each page of the modified block. If it is met, the cache block is reserved. If it is not, the cache block is discarded and directly erased. In addition, when a cache block is full of data, the processor 102 can retrieve the next reserved free cache block (as shown in Figures 5a and 5b), and when all have been used fast When the block reaches the maximum number of available cache blocks specified by the system, for example, if the first blank page of the four cache blocks in the cache block index table 501 shown in FIG. 5b is recorded as the largest system. At page 8, processor 102 directly erases all cache blocks to free up valid space.
本領域一般技術人員可以瞭解，雖然於之前描述中是將讀取操作與寫入操作分開說明的，但是本發明讀取與寫入操作的實質特徵是相同的。當邏輯位元址所對應之映射區塊之資料不能直接進行存取時，即在進行寫入操作時映射區塊的該頁已存儲有資料或是在進行讀取操作時映射區塊的該頁資料並不是最新的，處理器需要通過映射區塊的資訊來獲取與映射區塊相對應之修改區塊的第一個空白頁的位置資訊或是與該邏輯位址相對應的最新的頁的位置資訊，進而才能夠高效而準確地完成既定資料的寫入或讀取操作。One of ordinary skill in the art will appreciate that although the read operation has been described separately from the write operation in the previous description, the essential features of the read and write operations of the present invention are the same. When the data of the mapping block corresponding to the logical bit address cannot be directly accessed, that is, the page of the mapping block has stored data when the writing operation is performed or the mapping block is performed when the reading operation is performed. The page information is not up-to-date. The processor needs to obtain the location information of the first blank page of the modified block corresponding to the mapped block or the latest page corresponding to the logical address by mapping the information of the block. The location information, in order to efficiently and accurately complete the writing or reading of the given data.
此外，當系統對快閃記憶體執行合併(merge)操作時，處理器102可根據各修改區塊之冗餘區域所儲存之邏輯區塊編號LBN與邏輯頁編號LSN判斷修改區塊之資料區域是否依照映射區塊之資料順序被寫入資料。當映射區塊之各頁的更新資料依序被寫入修改區塊時，處理器102可直接抹除映射區塊，並且改為配置修改區塊作為映射區塊。另一方面，當映射區塊之各頁的更新資料依序未被寫入修改區塊時，處理器102可取得一空閒區塊，將修改區塊與映射區塊之有效資料合併至空閒區塊，抹除映射區塊與修改區塊，並且配置此空閒區塊作為新的映射區塊。In addition, when the system performs a merge operation on the flash memory, the processor 102 can determine the data area of the modified block according to the logical block number LBN and the logical page number LSN stored in the redundant area of each modified block. Whether data is written in the order of the data of the mapping block. When the update data of each page of the mapping block is sequentially written into the modified block, the processor 102 can directly erase the mapped block and configure the modified block as the mapped block instead. On the other hand, when the updated data of each page of the mapping block is not sequentially written into the modified block, the processor 102 may obtain a free block, and merge the valid data of the modified block and the mapped block into the free area. Block, erase the mapped block and modify the block, and configure this free block as the new mapped block.
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．計算機系統100. . . computer system
101．．．快閃記憶體101. . . Flash memory
102．．．處理器102. . . processor
103．．．隨機存取記憶體裝置103. . . Random access memory device
200．．．快閃記憶體200. . . Flash memory
201．．．快取區塊201. . . Cache block
202．．．映射區塊202. . . Map block
203．．．修改區塊203. . . Modify block
300、801‧‧‧邏輯至映射區塊對應表 300, 801‧‧‧Logic to mapping block correspondence table
400、802‧‧‧物理區塊資訊表 400, 802‧‧‧ physical block information sheet
500、501、809‧‧‧快取區塊索引表 500, 501, 809‧‧‧ cache block index table
803‧‧‧映射區塊 803‧‧‧ mapping block
804、805‧‧‧快取區塊 804, 805‧‧‧ cache block
806、808‧‧‧快取頁 806, 808‧‧‧ cache page
807‧‧‧修改區塊 807‧‧‧Modified blocks
LBN‧‧‧邏輯區塊編號 LBN‧‧‧ logical block number
LSN‧‧‧邏輯頁編號LSN‧‧‧ logical page number
第1圖係顯示根據本發明之一實施例所述之計算機系統。Figure 1 is a diagram showing a computer system in accordance with an embodiment of the present invention.
第2圖係顯示根據本發明之一實施例所述之快閃記憶體之資料結構示意圖。2 is a schematic diagram showing the structure of a flash memory according to an embodiment of the present invention.
第3圖係顯示根據本發明之一實施例所述之邏輯至映射區塊對應表之資料結構示意圖。FIG. 3 is a schematic diagram showing the structure of a logical-to-map block correspondence table according to an embodiment of the present invention.
第4圖係顯示根據本發明之一實施例所述之物理區塊資訊表之資料結構。Figure 4 is a diagram showing the data structure of a physical block information table according to an embodiment of the present invention.
第5a-5b圖係顯示根據本發明之一實施例所述之快取區塊索引表之資料結構示意圖。5a-5b are diagrams showing the structure of a data of a cache block index table according to an embodiment of the present invention.
第6圖係顯示根據本發明之一實施例所述之快閃記憶體管理方法流程圖。Figure 6 is a flow chart showing a method of managing a flash memory according to an embodiment of the present invention.
第7a-7b圖係顯示根據本發明之一實施例所述之快閃記憶體之寫入操作之詳細流程圖。7a-7b are detailed flowcharts showing the write operation of the flash memory according to an embodiment of the present invention.
第8a-8e圖係顯示根據本發明之一實施例所述之快閃記憶體之寫入操作之示意圖。8a-8e are diagrams showing a write operation of a flash memory according to an embodiment of the present invention.
第9圖係顯示根據本發明之另一實施例所述之快閃記憶體管理方法流程圖。Figure 9 is a flow chart showing a method of managing a flash memory according to another embodiment of the present invention.
第10圖係顯示根據本發明之一實施例所述之快閃記憶體之讀取操作之詳細流程圖。Figure 10 is a detailed flow chart showing the reading operation of the flash memory according to an embodiment of the present invention.
第11a-11d圖係顯示根據本發明之一實施例所述之快閃記憶體之讀取操作之示意圖。11a-11d are diagrams showing a read operation of a flash memory according to an embodiment of the present invention.
100．．．計算機系統100. . . computer system
101．．．快閃記憶體101. . . Flash memory
102．．．處理器102. . . processor
103．．．隨機存取記憶體裝置103. . . Random access memory device
Claims (29)
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| US10565115B2 (en) | 2017-03-30 | 2020-02-18 | Western Digital Technologies, Inc. | Calculating the optimal number of LBNS to prefetch per CPU |
| CN109117383B (en) * | 2017-06-25 | 2022-09-20 | 慧荣科技股份有限公司 | Method for managing flash memory module and flash memory controller |
| TWI707234B (en) * | 2019-05-20 | 2020-10-11 | 慧榮科技股份有限公司 | A data storage device and a data processing method |
| TWI695264B (en) * | 2019-05-20 | 2020-06-01 | 慧榮科技股份有限公司 | A data storage device and a data processing method |
| TWI744752B (en) * | 2019-12-24 | 2021-11-01 | 大陸商合肥沛睿微電子股份有限公司 | Redundant method applied to flash memory storage device and flash memory storage device |
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