TWI414926B - Controlling device and related controlling method - Google Patents
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本發明係關於一控制裝置與其相關控制方法,尤指一單埠先進先出記憶體的控制裝置與其相關控制方法。The present invention relates to a control device and related control method thereof, and more particularly to a control device for a first-in first-out memory and a related control method thereof.
在一存取系統中,一儲存裝置,例如一單埠先進先出(One-port FIFO)記憶體,通常會被指派給具有不同時脈特性(例如不同時脈頻率或工作週期)的控制電路來進行存取的動作。以該單埠先進先出記憶體為例,該單埠先進先出記憶體的一輸出入埠就必須常常在不同的控制電路之間進行切換。然而,在切換的過程中,為了避免時脈突發訊號(Glitch)的產生,傳統的存取系統的韌體(firmware)會執行一保護機制來確保不會產生突發訊號。更進一步來說,當具有一第一時脈的一第一控制電路正在存取該單埠先進先出記憶體時,該韌體欲切換存取(使用)該單埠先進先出記憶體的電路,將存取(使用)該單埠先進先出記憶體的電路從第一控制電路切換至一第二控制電路。其中該第一控制電路具有一第一控制時脈以及該第二控制電路具有一第二控制時脈,此時傳統存取系統的韌體會將輸入該單埠先進先出記憶體的該第一控制時脈切換為該第二控制時脈。接著,該韌體會計數一特定延遲時間後,才控制該第二控制電路得以開始存取該單埠先進先出記憶體。換句話說,該特定延遲時間必須夠長才能保證該單埠先進先出記憶體所接收到的該第一控制時脈成功切換為該第二控制時脈之後,該第二控制電路才開始存取該單埠先進先出記憶體以避免產生時脈突發訊號。然而,當該第一控制時脈以及該第二控制時脈的時脈頻率為高頻率時,則其週期時間係相對的減少了,因此該第一控制時脈切換為該第二控制時脈所需的時間亦減少了。但是,若此時該特定延遲時間仍維持不變的話,則該特定延遲時間就顯得過長而產生不必要的時間浪費,進而拖慢了一控制電路存取一單埠先進先出記憶體的速度。因此,要如何可適性地調整該特定延遲時間以提高一控制電路存取一單埠先進先出記憶體的速度已成為一存取系統所亟需解決的問題。In an access system, a storage device, such as a One-port FIFO memory, is typically assigned to control circuits having different clock characteristics (eg, different clock frequencies or duty cycles). The action to access. Taking the 單埠 first-in first-out memory as an example, an input/output port of the 單埠 first-in first-out memory must often switch between different control circuits. However, in the process of switching, in order to avoid the generation of the clock burst signal (Glitch), the firmware of the conventional access system performs a protection mechanism to ensure that no burst signal is generated. Further, when a first control circuit having a first clock is accessing the first-in first-out memory, the firmware is to be switched to access (use) the first-in first-out memory. The circuit switches the circuit for accessing (using) the first-in first-out memory from the first control circuit to a second control circuit. The first control circuit has a first control clock and the second control circuit has a second control clock. At this time, the firmware of the conventional access system inputs the first input of the first-in first-out memory. The control clock is switched to the second control clock. Then, the firmware will count the specific delay time before controlling the second control circuit to start accessing the first-in first-out memory. In other words, the specific delay time must be long enough to ensure that the first control clock received by the first-in first-out memory successfully switches to the second control clock, and the second control circuit begins to save. Take the 單埠 first-in first-out memory to avoid clock burst signals. However, when the clock frequency of the first control clock and the second control clock is a high frequency, the cycle time thereof is relatively reduced, so the first control clock is switched to the second control clock. The time required is also reduced. However, if the specific delay time remains unchanged at this time, the specific delay time is too long to waste unnecessary time, thereby slowing down a control circuit to access a first-in first-out memory. speed. Therefore, how to adjust the specific delay time to improve the speed of accessing a first-in first-out memory by a control circuit has become an urgent problem to be solved by an access system.
因此,本發明之一實施例在於提供一單埠先進先出記憶體的控制裝置與其相關控制方法以解決習知技術所面臨的問題。Accordingly, an embodiment of the present invention provides a control device for a first-in first-out memory and associated control method thereof to solve the problems faced by the prior art.
依據本發明之一第一實施例,其係提供一種控制裝置。該控制裝置包含有一第一延遲電路、一第二延遲電路、一第一控制電路、一第三延遲電路以及一第二控制電路。該第一延遲電路具有一第一延遲量,並用來依據一選擇訊號來選擇性地延遲一第一輸入時脈以及一第二輸入時脈中之一以產生一輸出時脈至一儲存裝置。該第二延遲電路係耦接於該第一延遲電路,並用來對該選擇訊號延遲一第二延遲量以產生一第二延遲選擇訊號。該第一控制電路係操作於該第一輸入時脈並耦接於該第二延遲電路,並用來依據該第二延遲選擇訊號來選擇性地存取該儲存裝置。該第三延遲電路係耦接於該第一延遲電路,並用來對該選擇訊號延遲一第三延遲量以產生一第三延遲選擇訊號。該第二控制電路係操作於該第二輸入時脈並耦接於該第三延遲電路,並用來依據該第三延遲選擇訊號來選擇性地存取該儲存裝置。According to a first embodiment of the invention, a control device is provided. The control device includes a first delay circuit, a second delay circuit, a first control circuit, a third delay circuit, and a second control circuit. The first delay circuit has a first delay amount and is configured to selectively delay one of a first input clock and a second input clock to generate an output clock to a storage device according to a selection signal. The second delay circuit is coupled to the first delay circuit and configured to delay the selection signal by a second delay amount to generate a second delay selection signal. The first control circuit is coupled to the first input clock and coupled to the second delay circuit, and is configured to selectively access the storage device according to the second delay selection signal. The third delay circuit is coupled to the first delay circuit and configured to delay the selection signal by a third delay amount to generate a third delay selection signal. The second control circuit is coupled to the second input clock and coupled to the third delay circuit, and is configured to selectively access the storage device according to the third delay selection signal.
依據本發明之一第二實施例,其係提供一種控制方法。該控制方法包含有下列步驟:依據一選擇訊號來選擇性地延遲一第一輸入時脈以及一第二輸入時脈中之一以產生一輸出時脈至一儲存裝置;對該選擇訊號延遲一第二延遲量以產生一第二延遲選擇訊號;依據該第二延遲選擇訊號來指示一第一控制電路選擇性地存取該儲存裝置;對該選擇訊號延遲一第三延遲量以產生一第三延遲選擇訊號;以及依據該第三延遲選擇訊號來指示一第二控制電路選擇性地存取該儲存裝置。According to a second embodiment of the present invention, a control method is provided. The control method includes the steps of: selectively delaying one of a first input clock and a second input clock to generate an output clock to a storage device according to a selection signal; delaying the selection signal by one a second delay amount to generate a second delay selection signal; instructing a first control circuit to selectively access the storage device according to the second delay selection signal; delaying the selection signal by a third delay amount to generate a And delaying the selection signal; and instructing a second control circuit to selectively access the storage device according to the third delay selection signal.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。此外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段,因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或者透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.
請參考第1圖。第1圖所示係依據本發明一種控制裝置100之一實施例示意圖。控制裝置100包含有一第一延遲電路101、一第二延遲電路102、一第一控制電路103、一第三延遲電路104、一第二控制電路105以及一選擇電路106。Please refer to Figure 1. Figure 1 is a schematic illustration of one embodiment of a control device 100 in accordance with the present invention. The control device 100 includes a first delay circuit 101, a second delay circuit 102, a first control circuit 103, a third delay circuit 104, a second control circuit 105, and a selection circuit 106.
第一延遲電路101具有一第一延遲量D1,用來依據一選擇訊號Ss來選擇性地延遲一第一輸入時脈C1以及一第二輸入時脈C2中之一以產生一輸出時脈Cout至一儲存裝置107。The first delay circuit 101 has a first delay amount D1 for selectively delaying one of the first input clock C1 and the second input clock C2 according to a selection signal Ss to generate an output clock Cout. To a storage device 107.
第二延遲電路102係耦接於第一延遲電路101,用來對選擇訊號Ss延遲一第二延遲量D2以產生一第二延遲選擇訊號Ssd2。第一控制電路102操作於第一輸入時脈C1並耦接於第二延遲電路102,用來依據第二延遲選擇訊號Ssd2來選擇性地存取儲存裝置107。The second delay circuit 102 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a second delay amount D2 to generate a second delay selection signal Ssd2. The first control circuit 102 operates on the first input clock C1 and is coupled to the second delay circuit 102 for selectively accessing the storage device 107 according to the second delay selection signal Ssd2.
第三延遲電路104係耦接於第一延遲電路101,用來對選擇訊號Ss延遲一第三延遲量D3以產生一第三延遲選擇訊號Ssd3。第二控制電路105係操作於第二輸入時脈C2並耦接於第三延遲電路104,用來依據第三延遲選擇訊號Ssd3來選擇性地存取儲存裝置107。The third delay circuit 104 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a third delay amount D3 to generate a third delay selection signal Ssd3. The second control circuit 105 is operative to the second input clock C2 and coupled to the third delay circuit 104 for selectively accessing the storage device 107 according to the third delay selection signal Ssd3.
選擇電路106係耦接於第一延遲電路101、第二延遲電路102、第三延遲電路104、第一控制電路103以及第二控制電路105,用來依據由第一控制電路103所產生一第一控制訊號Sc1以及第二控制電路105所產生的一第二控制訊號Sc2來產生選擇訊號Ss至第一延遲電路101、第二延遲電路102以及第三延遲電路104。在本實施例中,儲存裝置107係以一單埠先進先出(One-port FIFO)記憶體來加以實作,然其並不作為本發明之限制所在。The selection circuit 106 is coupled to the first delay circuit 101, the second delay circuit 102, the third delay circuit 104, the first control circuit 103, and the second control circuit 105 for generating a number according to the first control circuit 103. A control signal Sc1 and a second control signal Sc2 generated by the second control circuit 105 generate the selection signal Ss to the first delay circuit 101, the second delay circuit 102, and the third delay circuit 104. In the present embodiment, the storage device 107 is implemented in a first-in-first-out (FIFO) memory, which is not a limitation of the present invention.
第一延遲電路101包含有及閘(And Gate)101a、101b、101c、101d、D型正反器(D Flip-Flop)101e、101f、101g、101h、一或閘(Or Gate)101i以及一反相器101j。D型正反器101e、101f係互相串接,用來依據第一輸入時脈C1來提供一延遲量1.5Ta,其中Ta係第一輸入時脈C1的週期。D型正反器101g、101h係互相串接,用來依據第二輸入時脈C2來提供一延遲量1.5Tb,其中Tb係第二輸入時脈C2的週期。及閘101a的一輸入端N1用來接收選擇訊號Ss,一輸出端N2耦接於D型正反器101e的一輸入端。D型正反器101f的一正相輸出端N3耦接於及閘101c的一輸入端。及閘101c另一輸入端N4接收第一輸入時脈C1。此外,反相器101j耦接於輸入端N1與及閘101b的一輸入端N5之間。及閘101b的另一輸入端N6耦接於D型正反器101f的一反相輸出端,及閘101b的一輸出端N7耦接於D型正反器101g的一輸入端。D型正反器101h的一正相輸出端N8係耦接於及閘101d的一輸入端。及閘101d的另一輸入端N9接收第二輸入時脈C2。及閘101c和及閘101d個別的輸出端N10、N11係分別耦接於或閘(Or Gate)101i的二輸入端。或閘101i的輸出端N12用來輸出輸出時脈Cout。請注意,第一延遲電路101的細部連接關係請參照本發明第1圖,在此不另贅述。The first delay circuit 101 includes an AND gate 101a, 101b, 101c, 101d, a D-Flip-Flop 101e, 101f, 101g, 101h, an OR Gate 101i, and a Inverter 101j. The D-type flip-flops 101e, 101f are connected in series with each other for providing a delay amount 1.5Ta according to the first input clock C1, wherein Ta is the period of the first input clock C1. The D-type flip-flops 101g, 101h are connected in series to provide a delay amount of 1.5 Tb according to the second input clock C2, wherein Tb is the period of the second input clock C2. An input terminal N1 of the gate 101a is used to receive the selection signal Ss, and an output terminal N2 is coupled to an input terminal of the D-type flip-flop 101e. A positive phase output terminal N3 of the D-type flip-flop 101f is coupled to an input terminal of the AND gate 101c. The other input terminal N4 of the gate 101c receives the first input clock C1. In addition, the inverter 101j is coupled between the input terminal N1 and an input terminal N5 of the AND gate 101b. The other input terminal N6 of the gate 101b is coupled to an inverting output terminal of the D-type flip-flop 101f, and an output terminal N7 of the gate 101b is coupled to an input terminal of the D-type flip-flop 101g. A positive phase output terminal N8 of the D-type flip-flop 101h is coupled to an input terminal of the AND gate 101d. The other input terminal N9 of the AND gate 101d receives the second input clock C2. The respective output terminals N10 and N11 of the gate 101c and the gate 101d are respectively coupled to the two input ends of the OR gate 101i. The output terminal N12 of the OR gate 101i is used to output the output clock Cout. Please note that the detailed connection relationship of the first delay circuit 101 is referred to in FIG. 1 of the present invention, and will not be further described herein.
由於第一延遲電路101的結構,故自第一控制電路103/第二控制電路105產生第一控制訊號Sc1/第二控制訊號Sc2以表示欲存取(使用)儲存裝置107起,直到儲存裝置107收到改變後的輸出時脈Cout為止,共將需要1.5Ta+1.5Tb的延遲時間。由於在切換時脈時常常會產生時脈突發訊號(Glitch),為了避免儲存裝置107收到具有時脈突發訊號的時脈訊號而誤動作,故利用第一延遲電路101延遲一段時間(例如1.5Ta+1.5Tb),待頻率改變後的時脈信號穩定後再輸入儲存裝置107。第1圖所示之第一延遲電路101僅為一示範性實施例,而非本發明之限制,熟悉此項技藝者當得在本發明之教導之下,改變第一延遲電路101中的D型正反器數目,而以各種變化例實現第一延遲電路101,例如可產生2.5Ta+1.5Tb的第一延遲電路101或可產生2.5Ta+2.5Tb第一延遲電路101等。Due to the structure of the first delay circuit 101, the first control signal Sc / the second control signal Sc2 is generated from the first control circuit 103 / the second control circuit 105 to indicate that the storage device 107 is to be accessed (used) until the storage device 107 After receiving the changed output clock Cout, a total delay of 1.5 Ta + 1.5 Tb will be required. Since the clock burst signal (Glitch) is often generated when switching the clock, in order to prevent the storage device 107 from receiving the clock signal with the clock burst signal, the first delay circuit 101 is delayed for a period of time (for example, 1.5Ta+1.5Tb), the clock signal after the frequency change is stabilized and then input to the storage device 107. The first delay circuit 101 shown in FIG. 1 is merely an exemplary embodiment, and is not a limitation of the present invention. Those skilled in the art will be able to change the D in the first delay circuit 101 under the teaching of the present invention. The number of flip-flops is implemented, and the first delay circuit 101 is implemented in various variations, for example, a first delay circuit 101 of 2.5 Ta + 1.5 Tb can be generated or a 2.5 Ta + 2.5 Tb first delay circuit 101 can be generated.
第二延遲電路102包含有複數個第一特定延遲單元,其係前後串接以分別提供一延遲量。在本實施例中,該複數個第一特定延遲單元包含有一第一延遲單元1022以及一第二延遲單元1024,其中第一延遲單元1022操作於第二輸入時脈C2之下,以及第二延遲單元1024操作於第一輸入時脈C1之下。第一延遲單元1022包含有D型正反器1022a、1022b,其係前後串接以提供一延遲量2Tb。第二延遲單元1024包含有D型正反器1024a、1024b,其係前後串接以提供一延遲量2Ta。請注意到,在本實施例中D型正反器1022a、1022b、1024a、1024b之串接順序僅為說明之用,而非本發明之限制,D型正反器1022a、1022b、1024a、1024b之串接順序得任意調整。在本實施例中,第一延遲單元1022與第二延遲單元1024之延遲量總和係大致上等於第二延遲量D2,亦即2Ta+2Tb=D2。換句話說,第二延遲電路102係用來提供延遲量2Ta+2Tb於選擇訊號Ss,並延遲後所產生的第二延遲選擇訊號Ssd2輸出於D型正反器1024b的一輸出端N13。The second delay circuit 102 includes a plurality of first specific delay units that are connected in series to provide a delay amount. In this embodiment, the plurality of first specific delay units include a first delay unit 1022 and a second delay unit 1024, wherein the first delay unit 1022 operates under the second input clock C2, and the second delay Unit 1024 operates below the first input clock C1. The first delay unit 1022 includes D-type flip-flops 1022a, 1022b that are connected in series to provide a delay amount 2Tb. The second delay unit 1024 includes D-type flip-flops 1024a, 1024b which are connected in series to provide a delay amount 2Ta. Please note that the serial sequence of the D-type flip-flops 1022a, 1022b, 1024a, 1024b in this embodiment is for illustrative purposes only, and is not a limitation of the present invention. The D-type flip-flops 1022a, 1022b, 1024a, 1024b The concatenation sequence can be adjusted arbitrarily. In the present embodiment, the sum of the delay amounts of the first delay unit 1022 and the second delay unit 1024 is substantially equal to the second delay amount D2, that is, 2Ta+2Tb=D2. In other words, the second delay circuit 102 is configured to provide the delay amount 2Ta+2Tb to the selection signal Ss, and the second delay selection signal Ssd2 generated after the delay is outputted to an output terminal N13 of the D-type flip-flop 1024b.
另一方面,第三延遲電路104包含有複數個第二特定延遲單元,其係前後串接以分別提供一延遲量。在本實施例中,該複數個第二特定延遲單元包含有一第三延遲單元1042以及一第四延遲單元1044,其中第三延遲單元1042操作於第一輸入時脈C1之下,以及第四延遲單元1044操作於第二輸入時脈C2之下。第三延遲單元1042包含有D型正反器1042a、1042b,其係前後串接以提供一延遲量2Ta。第四延遲單元1044包含有D型正反器1044a、1044b,其係前後串接以提供一延遲量2Tb。請注意到,在本實施例中D型正反器1042a、1042b、1044a、1044b之串接順序僅為說明之用,而非本發明之限制,D型正反器1042a、1042b、1044a、1044b之串接順序得任意調整。此外,本發明的第三延遲電路104另包含有一反相器1046耦接於輸入端N1與D型正反器1042a的一輸入端N14之間以依據選擇訊號Ss來產生一反相選擇訊號Ssb。在本實施例中,第三延遲單元1042與第四延遲單元1044之延遲量總和係大致上等於第三延遲量D3,亦即2Ta+2Tb=D3。換句話說,第三延遲電路104係用來提供延遲量2Ta+2Tb於反相選擇訊號Ssb,並將延遲後所產生的第三延遲選擇訊號Ssd3輸出於D型正反器1044b的一輸出端N15。請注意,本發明並未限制反相器1046的耦接方式,換句話說,只要是串接於第三延遲單元1042與第四延遲單元1044均為本發明之範疇所在。舉例來說,反相器1046亦可以耦接於第四延遲單元1044與第二控制電路105之間。On the other hand, the third delay circuit 104 includes a plurality of second specific delay units which are connected in series to provide a delay amount. In this embodiment, the plurality of second specific delay units include a third delay unit 1042 and a fourth delay unit 1044, wherein the third delay unit 1042 operates under the first input clock C1, and the fourth delay Unit 1044 operates below the second input clock C2. The third delay unit 1042 includes D-type flip-flops 1042a, 1042b that are connected in series to provide a delay amount 2Ta. The fourth delay unit 1044 includes D-type flip-flops 1044a, 1044b that are connected in series to provide a delay amount 2Tb. Please note that the serial sequence of the D-type flip-flops 1042a, 1042b, 1044a, 1044b in this embodiment is for illustrative purposes only, and is not a limitation of the present invention. The D-type flip-flops 1042a, 1042b, 1044a, 1044b The concatenation sequence can be adjusted arbitrarily. In addition, the third delay circuit 104 of the present invention further includes an inverter 1046 coupled between the input terminal N1 and an input terminal N14 of the D-type flip-flop 1042a to generate an inverted selection signal Ssb according to the selection signal Ss. . In the present embodiment, the sum of the delay amounts of the third delay unit 1042 and the fourth delay unit 1044 is substantially equal to the third delay amount D3, that is, 2Ta+2Tb=D3. In other words, the third delay circuit 104 is configured to provide the delay amount 2Ta+2Tb to the inverted selection signal Ssb, and output the third delay selection signal Ssd3 generated after the delay to an output terminal of the D-type flip-flop 1044b. N15. It should be noted that the present invention does not limit the coupling manner of the inverter 1046. In other words, as long as it is serially connected to the third delay unit 1042 and the fourth delay unit 1044, it is within the scope of the present invention. For example, the inverter 1046 can also be coupled between the fourth delay unit 1044 and the second control circuit 105.
此外,本實施例的選擇電路106包含有一第一觸變(toggle)電路1062、一第二觸變電路1064以及一邏輯閘1066。第一觸變電路1062係操作於第一輸入時脈C1之下,用來依據第一控制訊號Sc1來觸變一第一觸變輸出訊號St1。第二觸變電路1064係操作於第二輸入時脈Sc2之下,用來依據第二控制訊號Sc2來觸變一第二觸變輸出訊號St2。邏輯閘1066係耦接於第一觸變電路1062以及第二觸變電路1064,用來依據第一觸變輸出訊號St1以及第二觸變輸出訊號St2來產生選擇訊號Ss。在本實施例中,邏輯閘1066係以一互斥或(Exclusive OR)閘加以實作。In addition, the selection circuit 106 of the embodiment includes a first toggle circuit 1062, a second touch circuit 1064, and a logic gate 1066. The first thixotropic circuit 1062 is operated under the first input clock C1 for thixo-switching a first thixotropic output signal St1 according to the first control signal Sc1. The second thixotropic circuit 1064 is operated under the second input clock Sc2 for thiking a second thixotropic output signal St2 according to the second control signal Sc2. The logic gate 1066 is coupled to the first thixotropic circuit 1062 and the second thixotropic circuit 1064 for generating the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. In the present embodiment, the logic gate 1066 is implemented as an exclusive OR gate.
請參考第2圖。第2圖係本發明實施例第一延遲電路101的選擇訊號Ss、第一輸入時脈C1、第二輸入時脈C2、訊號S1、訊號S2、訊號S3、訊號S4、訊號S5、訊號S6、訊號S7、訊號S8、訊號S9之時序圖,其中訊號S1係及閘101a的輸出端N2的訊號,訊號S2係D型正反器101e的一輸出端N16的訊號,訊號S3係D型正反器101f的輸出端N3的訊號、訊號S4係D型正反器101f的反相輸出端N17的訊號,訊號S5係及閘101b的輸出端N7的訊號,訊號S6係D型正反器101g的一輸出端N18的訊號,訊號S7係D型正反器101h的輸出端N8的訊號、訊號S8係D型正反器101h的反相輸出端N19的訊號、訊號S9係反相器101j的輸出端N5的訊號。Please refer to Figure 2. 2 is a selection signal Ss, a first input clock C1, a second input clock C2, a signal S1, a signal S2, a signal S3, a signal S4, a signal S5, a signal S6, and a first input clock S1 of the first delay circuit 101 of the embodiment of the present invention. The timing diagram of the signal S7, the signal S8, and the signal S9, wherein the signal S1 is the signal of the output terminal N2 of the gate 101a, the signal S2 is the signal of the output terminal N16 of the D-type flip-flop 101e, and the signal S3 is the D-type positive and negative. The signal of the output terminal N3 of the device 101f, the signal S4 is the signal of the inverted output terminal N17 of the D-type flip-flop 101f, the signal of the signal S5 and the output terminal N7 of the gate 101b, and the signal S6 is the D-type flip-flop 101g. The signal of the output terminal N18, the signal S7 is the signal of the output terminal N8 of the D-type flip-flop 101h, the signal S8 is the signal of the inverted output terminal N19 of the D-type flip-flop 101h, and the output of the signal S9-series inverter 101j The signal of the end N5.
為了方更敘述本發明的精神所在,本實施例係假設第一輸入時脈C1係同步於第二輸入時脈C2。當選擇訊號Ss於時間T1從一低電壓準位切換至一高電壓準位時,訊號S9以及訊號S5亦會從該高電壓準位切換至該低電壓準位。由於D型正反器101g係一上升邊緣觸發的D型正反器,因此第二輸入時脈C2會於時間T2觸發D型正反器101g以使得訊號S6從該高電壓準位切換至該低電壓準位。接著,由於D型正反器101h係一下降邊緣觸發的D型正反器,因此第二輸入時脈C2會於時間T3觸發D型正反器101h以使得訊號S7從該高電壓準位切換至該低電壓準位。同時,D型正反器101h的訊號S8會從該低電壓準位切換至該高電壓準位,進而使得訊號S1從該低電壓準位切換至該高電壓準位。同理,第一輸入時脈C1會於時間T4觸發D型正反器101e(D型正反器101e係一上升邊緣觸發的D型正反器)以使得訊號S2從該低電壓準位切換至該高電壓準位。接著,第一輸入時脈C1會於時間T5觸發D型正反器101f(D型正反器101f係一下降邊緣觸發的D型正反器)以使得訊號S3從該低電壓準位切換至該高電壓準位。因此,在時間T5以後,及閘101d的輸出訊號就會係該低電壓準位,而及閘101c的輸出訊號就會係第一輸入時脈C1。換句話說,在時間T5以後,輸出時脈Cout(亦即或閘101i的輸出端)就會從第二輸入時脈C2切換為第一輸入時脈C1。To further illustrate the spirit of the present invention, this embodiment assumes that the first input clock C1 is synchronized to the second input clock C2. When the selection signal Ss is switched from a low voltage level to a high voltage level at time T1, the signal S9 and the signal S5 are also switched from the high voltage level to the low voltage level. Since the D-type flip-flop 101g is a rising-edge triggered D-type flip-flop, the second input clock C2 triggers the D-type flip-flop 101g at time T2 to cause the signal S6 to switch from the high-voltage level to the Low voltage level. Then, since the D-type flip-flop 101h is a D-type flip-flop triggered by a falling edge, the second input clock C2 triggers the D-type flip-flop 101h at time T3 to switch the signal S7 from the high-voltage level. To this low voltage level. At the same time, the signal S8 of the D-type flip-flop 101h is switched from the low voltage level to the high voltage level, so that the signal S1 is switched from the low voltage level to the high voltage level. Similarly, the first input clock C1 triggers the D-type flip-flop 101e (the D-type flip-flop 101e is a D-type flip-flop triggered by a rising edge) at time T4 to switch the signal S2 from the low voltage level. To this high voltage level. Then, the first input clock C1 triggers the D-type flip-flop 101f at time T5 (the D-type flip-flop 101f is a D-type flip-flop triggered by a falling edge) to switch the signal S3 from the low voltage level to The high voltage level. Therefore, after time T5, the output signal of the gate 101d is at the low voltage level, and the output signal of the gate 101c is the first input clock C1. In other words, after time T5, the output clock Cout (i.e., the output of the OR gate 101i) is switched from the second input clock C2 to the first input clock C1.
另一方面,請再次參考第2圖,當選擇訊號Ss於時間T6從該高電壓準位切換至該低電壓準位時(即,欲將輸出時脈Cout從第一輸入時脈C1切換為第二輸入時脈C2),訊號S1亦會從該高電壓準位切換至該低電壓準位。由於D型正反器101e係一上升邊緣觸發的D型正反器,因此第一輸入時脈C1會於時間T7觸發D型正反器101e以使得訊號S2從該高電壓準位切換至該低電壓準位。接著,由於D型正反器101f係一下降邊緣觸發的D型正反器,因此第一輸入時脈C1會於時間T8觸發D型正反器101f以使得訊號S3從該高電壓準位切換至該低電壓準位。同時,D型正反器101f的訊號S4會從該低電壓準位切換至該高電壓準位,進而使得訊號S5從該低電壓準位切換至該高電壓準位。同理,第二輸入時脈C2會於時間T9觸發D型正反器101g以使得訊號S6從該低電壓準位切換至該高電壓準位。接著,第二輸入時脈C2會於時間T10觸發D型正反器101h以使得訊號S7從該低電壓準位切換至該高電壓準位。因此,在時間T10以後,及閘101c的輸出訊號就會係該低電壓準位,而及閘101d的輸出訊號就會係第二輸入時脈C2。換句話說,在時間T10以後,輸出時脈Cout(亦即或閘101i的輸出端)就會從第一輸入時脈C1切換為第二輸入時脈C2。On the other hand, please refer to FIG. 2 again, when the selection signal Ss is switched from the high voltage level to the low voltage level at time T6 (ie, the output clock Cout is to be switched from the first input clock C1 to The second input clock C2), the signal S1 also switches from the high voltage level to the low voltage level. Since the D-type flip-flop 101e is a rising-edge triggered D-type flip-flop, the first input clock C1 triggers the D-type flip-flop 101e at time T7 to switch the signal S2 from the high-voltage level to the Low voltage level. Then, since the D-type flip-flop 101f is a D-type flip-flop triggered by a falling edge, the first input clock C1 triggers the D-type flip-flop 101f at time T8 to switch the signal S3 from the high-voltage level. To this low voltage level. At the same time, the signal S4 of the D-type flip-flop 101f is switched from the low voltage level to the high voltage level, so that the signal S5 is switched from the low voltage level to the high voltage level. Similarly, the second input clock C2 triggers the D-type flip-flop 101g at time T9 to switch the signal S6 from the low voltage level to the high voltage level. Then, the second input clock C2 triggers the D-type flip-flop 101h at time T10 to switch the signal S7 from the low voltage level to the high voltage level. Therefore, after time T10, the output signal of the gate 101c is at the low voltage level, and the output signal of the gate 101d is the second input clock C2. In other words, after time T10, the output clock Cout (i.e., the output of the gate 101i) is switched from the first input clock C1 to the second input clock C2.
更進一步來說,D型正反器101g以及101h所構成的延遲單元最長可對訊號S5延遲1.5Tb,而D型正反器101e以及101f所構成的延遲單元最長可對訊號S1延遲1.5Ta,因此第一延遲電路101的第一延遲量D1最長可具有1.5Ta+1.5Tb的延遲時間。換句話說,當選擇訊號Ss從該低電壓準位切換至該高電壓準位時,輸出時脈Cout最久不會超過1.5Ta+1.5Tb的延遲時間就會從第二輸入時脈C2切換為第一輸入時脈C1。反之,當選擇訊號Ss從該高電壓準位切換至該低電壓準位時,輸出時脈Cout最久不會超過1.5Ta+1.5Tb的延遲時間就會從第一輸入時脈C1切換為第二輸入時脈C2。因此,當選擇訊號Ss從該低電壓準位切換至該高電壓準位時,只要第一控制電路103能夠在超過第一延遲電路101的延遲時間(1.5Ta+1.5Tb)後才對儲存裝置107進行存取的話,則儲存裝置107(亦即輸出端N12)就可以避免因時脈突發訊號(Glitch)的產生而造成的誤動作。請注意到,熟悉此項技藝者,在本發明之教導之下,當得改變第一延遲電路101中正反器的數目、類型(D型正反器或其他類型之正反器)及觸發態樣(上升邊緣觸發或下降邊緣觸發)以改變第一延遲電路101的延遲時間。Furthermore, the delay unit formed by the D-type flip-flops 101g and 101h can be delayed by 1.5Tb for the signal S5, and the delay unit formed by the D-type flip-flops 101e and 101f can be delayed by 1.5Ta for the signal S1. Therefore, the first delay amount D1 of the first delay circuit 101 can have a delay time of 1.5 Ta + 1.5 Tb at the longest. In other words, when the selection signal Ss is switched from the low voltage level to the high voltage level, the delay time of the output clock Cout not exceeding 1.5Ta+1.5Tb for the longest time is switched from the second input clock C2. Enter the clock C1 for the first time. Conversely, when the selection signal Ss is switched from the high voltage level to the low voltage level, the delay time of the output clock Cout not exceeding 1.5 Ta+1.5 Tb for the longest time is switched from the first input clock C1 to the first Two input clocks C2. Therefore, when the selection signal Ss is switched from the low voltage level to the high voltage level, the first control circuit 103 can only access the storage device after the delay time (1.5Ta+1.5Tb) of the first delay circuit 101 is exceeded. When access is made 107, the storage device 107 (i.e., the output terminal N12) can avoid malfunction caused by the generation of the clock burst signal (Glitch). Please note that those skilled in the art, under the teachings of the present invention, may change the number and type of flip-flops (D-type flip-flops or other types of flip-flops) and triggers in the first delay circuit 101. The aspect (rising edge trigger or falling edge trigger) changes the delay time of the first delay circuit 101.
因此,針對於選擇訊號Ss,本實施例的第二延遲電路102就提供了2Ta+2Tb的延遲時間,來產生第二延遲選擇訊號Ssd2。而第一控制電路103就會依據第二延遲選擇訊號Ssd2來存取儲存裝置107。從第1圖可以得知,第二延遲電路102中的D型正反器1022a、1022b係提供了2Tb的延遲時間,而D型正反器1024a、1024b係提供了2Ta的延遲時間,故第二延遲電路102總共提供了2Ta+2Tb的延遲時間。Therefore, for the selection signal Ss, the second delay circuit 102 of the present embodiment provides a delay time of 2Ta+2Tb to generate the second delay selection signal Ssd2. The first control circuit 103 accesses the storage device 107 according to the second delay selection signal Ssd2. As can be seen from FIG. 1, the D-type flip-flops 1022a, 1022b in the second delay circuit 102 provide a delay time of 2Tb, and the D-type flip-flops 1024a, 1024b provide a delay time of 2Ta, so The two delay circuits 102 provide a total delay time of 2Ta + 2Tb.
另一方面,針對於選擇訊號Ss,第三延遲電路104亦提供了2Ta+2Tb的延遲時間,來產生第三延遲選擇訊號Ssd3,其原因如同第二延遲電路102,故不另贅述。請注意,本發明並不受限於上述的實施方式,只要係第二延遲電路102以及第三延遲電路104所提供的延遲時間比第一延遲電路101所提供的延遲時間來得長的電路組合均為本發明之範疇所在,亦即,熟悉此項技藝者,在本發明之教導之下,當得改變第二延遲電路102或第三延遲電路104中正反器的數目、類型及觸發態樣以改變第一延遲電路101的延遲時間。因此,經過了第一延遲量D1(亦即2Ta+2Tb),第二延遲選擇訊號Ssd2就會從該低電壓準位切換至該高電壓準位以允許第一控制電路103存取儲存裝置107。請注意,此領域具有通常知識者在閱讀完上述所揭露的技術內容後,應可瞭解控制裝置100對應的運作,亦即當選擇訊號Ss從一高電壓準位切換至一低電壓準位時的運作,其亦具有上述所描述的優點,故在此不另贅述。On the other hand, for the selection signal Ss, the third delay circuit 104 also provides a delay time of 2Ta+2Tb to generate the third delay selection signal Ssd3, which is caused by the second delay circuit 102, and therefore will not be further described. It should be noted that the present invention is not limited to the above embodiments, as long as the delay time provided by the second delay circuit 102 and the third delay circuit 104 is longer than the delay time provided by the first delay circuit 101. It is the scope of the present invention, that is, those skilled in the art, under the teachings of the present invention, when changing the number, type, and triggering pattern of the flip-flops in the second delay circuit 102 or the third delay circuit 104 To change the delay time of the first delay circuit 101. Therefore, after the first delay amount D1 (ie, 2Ta+2Tb), the second delay selection signal Ssd2 is switched from the low voltage level to the high voltage level to allow the first control circuit 103 to access the storage device 107. . Please note that after reading the above-mentioned technical contents, the general knowledge in this field should be able to understand the corresponding operation of the control device 100, that is, when the selection signal Ss is switched from a high voltage level to a low voltage level. The operation also has the advantages described above, and therefore will not be further described herein.
請注意,本實施例控制裝置100的第二延遲電路102、第三延遲電路104以及選擇電路106係為純硬體電路。換句話說,在一實施例中,控制裝置100可不透過韌體(Firmware)的方式來控制第一控制電路103或第二控制電路105以存取儲存裝置107。因此,當第一控制電路103需要存取儲存裝置107時,第一控制電路103就會產生第一控制訊號Sc1至選擇電路106來產生選擇訊號Ss。同理,當第二控制電路105需要存取儲存裝置107時,第二控制電路105就會產生第二控制訊號Sc2至選擇電路106來產生選擇訊號Ss。舉例來說,假設當第二控制電路105正在存取儲存裝置107,而第一控制電路103欲存取儲存裝置107時,第一控制電路103就會先產生第一控制訊號Sc1至第一觸變電路1062,其中第一控制訊號Sc1係一脈波訊號,如第3圖所示。Please note that the second delay circuit 102, the third delay circuit 104, and the selection circuit 106 of the control device 100 of the present embodiment are pure hardware circuits. In other words, in an embodiment, the control device 100 can control the first control circuit 103 or the second control circuit 105 to access the storage device 107 without being through a firmware. Therefore, when the first control circuit 103 needs to access the storage device 107, the first control circuit 103 generates the first control signal Sc1 to the selection circuit 106 to generate the selection signal Ss. Similarly, when the second control circuit 105 needs to access the storage device 107, the second control circuit 105 generates the second control signal Sc2 to the selection circuit 106 to generate the selection signal Ss. For example, if the second control circuit 105 is accessing the storage device 107 and the first control circuit 103 is to access the storage device 107, the first control circuit 103 first generates the first control signal Sc1 to the first touch. The variable circuit 1062, wherein the first control signal Sc1 is a pulse signal, as shown in FIG.
第3圖係本發明實施例控制裝置100的第一控制訊號Sc1、第二控制訊號Sc2、第一觸變輸出訊號St1、第二觸變輸出訊號St2以及選擇訊號Ss的一波形時序圖。當第一控制電路103於時間To產生第一控制訊號Sc1時,第一觸變電路1062就會被第一控制訊號Sc1所觸發而於時間Tx將第一觸變輸出訊號St1從一低電壓準位切換至一高電壓準位。接著,邏輯閘1066(亦即該互斥或閘)就會依據第一觸變輸出訊號St1以及第二觸變輸出訊號St2來產生選擇訊號Ss。由於此時第二觸變輸出訊號St2的電壓準位為該低電壓準位,因此邏輯閘1066就會於時間Tb將選擇訊號Ss從該低電壓準位切換至該高電壓準位。接者,第一延遲電路101就會執行如第2圖所示的運作來將輸出時脈Cout從第二輸入時脈C2切換為第一輸入時脈C1。接者,經過了第一延遲量D1(亦即2Ta+2Tb)後,第一控制電路103就被允許存取儲存裝置107了。FIG. 3 is a waveform timing diagram of the first control signal Sc, the second control signal Sc2, the first thixotropic output signal St1, the second thixotropic output signal St2, and the selection signal Ss of the control device 100 according to the embodiment of the present invention. When the first control circuit 103 generates the first control signal Sc1 at time To, the first thixotropic circuit 1062 is triggered by the first control signal Sc1 and the first thixotropic output signal St1 is from a low voltage at time Tx. The level is switched to a high voltage level. Then, the logic gate 1066 (that is, the mutex or gate) generates the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. Since the voltage level of the second thixotropic output signal St2 is the low voltage level at this time, the logic gate 1066 switches the selection signal Ss from the low voltage level to the high voltage level at time Tb. Then, the first delay circuit 101 performs the operation as shown in FIG. 2 to switch the output clock Cout from the second input clock C2 to the first input clock C1. After receiving the first delay amount D1 (that is, 2Ta+2Tb), the first control circuit 103 is allowed to access the storage device 107.
反之,當第一控制電路103正在存取儲存裝置107,而第二控制電路105欲存取儲存裝置107時,第二控制電路105就會先產生第二控制訊號Sc2至第二觸變電路1064,其中第二控制訊號Sc2亦係一脈波訊號,如第3圖所示。當第二控制電路105於時間To’產生第二控制訊號Sc2時,第二觸變電路1064就會被第二控制訊號Sc2所觸發而於時間Ty將第二觸變輸出訊號St2從一低電壓準位切換至一高電壓準位。由於此時第一觸變輸出訊號St1以及第二觸變輸出訊號St2的電壓準位為該高電壓準位,因此邏輯閘1066就會於時間Ty將選擇訊號Ss從該高電壓準位切換至該低電壓準位。同理,第一延遲電路101就會執行如第2圖所示的運作來將輸出時脈Cout從第一輸入時脈C1切換為第二輸入時脈C2。接者,經過了第一延遲量D1(亦即2Ta+2Tb)後,第二控制電路105就被允許存取儲存裝置107了。因此,透過選擇電路106內第一觸變電路1062、第二觸變電路1064以及邏輯閘1066互相搭配的運作,第一控制電路103以及第二控制電路105就可以不需依據韌體的控制來選擇性地存取儲存裝置107。因此,相較於傳統的儲存裝置存取系統,本發明的控制裝置100不僅具有較快的反應時間(亦即時脈切換時間),亦同時克服了時脈突發訊號的問題。On the contrary, when the first control circuit 103 is accessing the storage device 107 and the second control circuit 105 is to access the storage device 107, the second control circuit 105 first generates the second control signal Sc2 to the second touch circuit. 1064, wherein the second control signal Sc2 is also a pulse signal, as shown in FIG. When the second control circuit 105 generates the second control signal Sc2 at time To', the second thixotropic circuit 1064 is triggered by the second control signal Sc2 and the second thixotropic output signal St2 is low from the time Ty. The voltage level is switched to a high voltage level. Since the voltage levels of the first thixotropic output signal St1 and the second thixotropic output signal St2 are at the high voltage level, the logic gate 1066 switches the selection signal Ss from the high voltage level to the time Ty. The low voltage level. Similarly, the first delay circuit 101 performs the operation as shown in FIG. 2 to switch the output clock Cout from the first input clock C1 to the second input clock C2. After receiving the first delay amount D1 (ie, 2Ta+2Tb), the second control circuit 105 is allowed to access the storage device 107. Therefore, the first control circuit 103 and the second control circuit 105 can be operated without the firmware according to the operation of the first thixotropic circuit 1062, the second thixotropic circuit 1064 and the logic gate 1066 in the selection circuit 106. Control to selectively access the storage device 107. Therefore, compared with the conventional storage device access system, the control device 100 of the present invention not only has a faster response time (also immediate pulse switching time), but also overcomes the problem of the clock burst signal.
請參考第4圖。第4圖所示係本發明控制裝置100之第一延遲電路101之另一實施例示意圖,該另一實施例以標號201來標示。第一延遲電路201包含有及閘201a、201b、201c、201d、D型正反器201e、201f、一或閘201g以及一反相器201h。D型正反器101e依據一第一輸入時脈C1’來提供一延遲量0.5Ta’,其中Ta’係第一輸入時脈C1’的週期。D型正反器201f用來依據一第二輸入時脈C2’來提供一延遲量0.5Tb’,其中Tb’係第二輸入時脈C2’的週期。及閘201a的一輸入端N1’用來接收一選擇訊號Ss’,一輸出端N2’耦接於D型正反器201e的一輸入端。D型正反器201e的一正相輸出端N3’耦接於及閘201c的一輸入端,及閘201c另一輸入端N4’接收第一輸入時脈C1’。此外,反相器201h耦接於輸入端N1’與及閘201b的一輸入端N5’之間。及閘201b的另一輸入端N6’耦接於D型正反器201e的一反相輸出端,及閘201b的一輸出端N7’耦接於D型正反器201f的一輸入端。D型正反器201f的一正相輸出端N8’係耦接於及閘201d的一輸入端。及閘201d的另一輸入端N9’接收第二輸入時脈C2’。及閘201c和及閘201d分別輸出端N10’、N11’係分別耦接於或閘201g的二輸入端。或閘201g的輸出端N12’用來輸出輸出時脈Cout’。參照關於第一延遲電路101的運作,此領域具有通常知識者應可瞭解第一延遲電路201最長可具有0.5Ta’+0.5Tb’的延遲時間。換句話說,當選擇訊號Ss’從該低電壓準位切換至該高電壓準位時,輸出時脈Cout’最久不會超過0.5Ta’+0.5Tb’的延遲時間就會從第二輸入時脈C2’切換為第一輸入時脈C1’。反之,當選擇訊號Ss’從該高電壓準位切換至該低電壓準位時,輸出時脈Cout’最久不會超過0.5Ta’+0.5Tb’的延遲時間就會從第一輸入時脈C1’切換為第二輸入時脈C2’。因此,以利用第一延遲電路201來構成控制裝置100的實施例來說,當選擇訊號Ss’從該低電壓準位切換至該高電壓準位時,只要第一控制電路103能夠在超過0.5Ta’+0.5Tb’的延遲時間後才對儲存裝置107進行存取的話,則儲存裝置107(亦即輸出端N12)就可以避免時脈突發訊號(Glitch)所造成的問題。換句話說,在此一實施例中,只要將第二延遲電路102的第二延遲量D2以及第三延遲電路103的第三延遲量D3設定為比0.5Ta’+0.5Tb’來得長(例如1Ta’+1Tb’)的話就可以避免時脈突發訊號的產生了。Please refer to Figure 4. 4 is a schematic diagram of another embodiment of a first delay circuit 101 of the control device 100 of the present invention, the other embodiment being designated by reference numeral 201. The first delay circuit 201 includes gates 201a, 201b, 201c, 201d, D-type flip-flops 201e, 201f, a gate 201g, and an inverter 201h. The D-type flip-flop 101e provides a delay amount 0.5Ta' according to a first input clock C1', wherein Ta' is the period of the first input clock C1'. The D-type flip-flop 201f is for providing a delay amount of 0.5 Tb' according to a second input clock C2', wherein Tb' is the period of the second input clock C2'. An input terminal N1' of the gate 201a is for receiving a selection signal Ss', and an output terminal N2' is coupled to an input terminal of the D-type flip-flop 201e. A positive phase output terminal N3' of the D-type flip-flop 201e is coupled to an input of the AND gate 201c, and another input terminal N4' of the gate 201c receives the first input clock C1'. In addition, the inverter 201h is coupled between the input terminal N1' and an input terminal N5' of the AND gate 201b. The other input terminal N6' of the gate 201b is coupled to an inverting output terminal of the D-type flip-flop 201e, and an output terminal N7' of the gate 201b is coupled to an input terminal of the D-type flip-flop 201f. A positive phase output terminal N8' of the D-type flip-flop 201f is coupled to an input terminal of the AND gate 201d. The other input terminal N9' of the AND gate 201d receives the second input clock C2'. The output terminals N10' and N11' of the gate 201c and the gate 201d are respectively coupled to the two input terminals of the OR gate 201g. The output terminal N12' of the OR gate 201g is used to output the output clock Cout'. Referring to the operation of the first delay circuit 101, those skilled in the art should understand that the first delay circuit 201 can have a delay time of up to 0.5 Ta' + 0.5 Tb'. In other words, when the selection signal Ss' is switched from the low voltage level to the high voltage level, the output clock Cout' will not exceed 0.5 Ta'+0.5Tb' for the longest delay time from the second input. The clock C2' is switched to the first input clock C1'. Conversely, when the selection signal Ss' is switched from the high voltage level to the low voltage level, the output clock Cout' will not exceed 0.5 Ta' + 0.5 Tb' for the longest delay time from the first input clock. C1' switches to the second input clock C2'. Therefore, in the embodiment in which the first delay circuit 201 is used to construct the control device 100, when the selection signal Ss' is switched from the low voltage level to the high voltage level, as long as the first control circuit 103 can exceed 0.5. If the storage device 107 is accessed after the delay time of Ta'+0.5Tb', the storage device 107 (i.e., the output terminal N12) can avoid the problem caused by the clock burst signal (Glitch). In other words, in this embodiment, the second delay amount D2 of the second delay circuit 102 and the third delay amount D3 of the third delay circuit 103 are set to be longer than 0.5Ta'+0.5Tb' (for example, 1Ta'+1Tb') can avoid the generation of clock burst signals.
請參考第5圖。第5圖所示係依據本發明一種控制方法500之一實施例流程圖。為了更清楚說明本發明之精神所在,控制方法500係以第1圖之實施例控制裝置100來加以實作,但所提供之實施例並不用以限制本發明所涵蓋的範圍。此外,倘若大體上可達到相同的結果,並不需要一定照第5圖所示之流程中的步驟順序來進行,且第5圖所示之步驟不一定要連續進行,亦即其他步驟亦可***其中。控制方法500包含有下列的步驟:步驟501:產生第一控制訊號Sc1以及第二控制訊號Sc2至少其中之一;步驟502:依據第一控制訊號Sc1或第二控制訊號Sc2來分別觸變第一觸變輸出訊號St1以及第二觸變輸出訊號St2;步驟503:依據第一觸變輸出訊號St1以及第二觸變輸出訊號St2來產生選擇訊號Ss,跳至步驟504;步驟504:依據選擇訊號Ss對第一輸入時脈C1以及第二輸入時脈C2中之一延遲一第一延遲量D1以產生輸出時脈Cout至儲存裝置107;步驟505:對選擇訊號Ss延遲第二延遲量D2以產生第二延遲選擇訊號Ssd2;步驟506:依據第二延遲選擇訊號Ssd2來選擇性地存取儲存裝置107;步驟507:對選擇訊號Ss延遲第三延遲量D3以產生第三延遲選擇訊號Ssd3;步驟508:依據第三延遲選擇訊號Ssd3來選擇性地存取儲存裝置107。Please refer to Figure 5. Figure 5 is a flow chart showing an embodiment of a control method 500 in accordance with the present invention. In order to clarify the spirit of the present invention, the control method 500 is implemented by the control device 100 of the embodiment of FIG. 1, but the embodiments provided are not intended to limit the scope of the present invention. In addition, if the same result can be substantially achieved, it is not necessary to perform the sequence of steps in the flow shown in FIG. 5, and the steps shown in FIG. 5 do not have to be performed continuously, that is, other steps may also be performed. Insert it. The control method 500 includes the following steps: Step 501: generate at least one of the first control signal Sc1 and the second control signal Sc2; Step 502: respectively change the first according to the first control signal Sc1 or the second control signal Sc2 Step 503: generating a selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2, and skipping to step 504; step 504: selecting the signal according to the selection signal Ss delays one of the first input clock C1 and the second input clock C2 by a first delay amount D1 to generate an output clock Cout to the storage device 107; Step 505: delays the selection signal Ss by a second delay amount D2 Generating a second delay selection signal Ssd2; step 506: selectively accessing the storage device 107 according to the second delay selection signal Ssd2; step 507: delaying the selection signal Ss by a third delay amount D3 to generate a third delay selection signal Ssd3; Step 508: Selectively access the storage device 107 according to the third delay selection signal Ssd3.
在步驟501中,當第一控制電路103和第二控制電路105中一控制電路欲對儲存裝置107進行存取時,該控制電路就會產生一控制訊號至第一觸變電路1062或第二觸變電路1064。例如,當第一控制電路103欲對儲存裝置107進行存取時,第一控制電路103就會產生一控制訊號Sc1至第一觸變電路1062。當第二控制電路105欲對儲存裝置107進行存取時,第二控制電路105就會產生一控制訊號Sc2至第二觸變電路1064。接著,受到該控制訊號所觸變的觸變電路就會將其輸出訊號(第一觸變輸出訊號St1或第二觸變輸出訊號St2)的電壓準位進行切換(步驟502)。接著,在步驟503中,邏輯閘1066就會依據第一觸變輸出訊號St1以及第二觸變輸出訊號St2來產生選擇訊號Ss。相應地,選擇訊號Ss可表示出第一控制電路103或第二控制電路105中哪一個電路欲對儲存裝置107進行存取。參照關於控制裝置100的操作敘述,選擇訊號Ss會經過三個延遲電路(亦即第一延遲電路101(步驟504)、第二延遲電路102(步驟505)以及第三延遲電路104(步驟507))來分別產生三個輸出訊號(亦即輸出時脈Cout、第二延遲選擇訊號Ssd2以及第三延遲選擇訊號Ssd3),其中第二延遲電路102以及第三延遲電路104的延遲時間(D2、D3)係大於第一延遲電路101的延遲時間(D1)。接著,若輸出時脈Cout係第一輸入時脈C1,則第一控制電路103就會依據第二延遲選擇訊號Ssd2的指示,開始存取儲存裝置107(步驟506)。反之,若輸出時脈Cout係第二輸入時脈C2,則第二控制電路105就會依據第三延遲選擇訊號Ssd3的指示,開始存取儲存裝置107(步驟508)。請注意到,控制裝置100係依據選擇訊號Ss產生三個輸出訊號(亦即輸出時脈Cout、第二延遲選擇訊號Ssd2以及第三延遲選擇訊號Ssd3),其中第二延遲選擇訊號Ssd2係用來指示第一控制電路103何時開始存取儲存裝置107,第三延遲選擇訊號Ssd3係用來指示第二控制電路105何時開始存取儲存裝置107。在正常運作下,當第二延遲選擇訊號Ssd2指示第一控制電路103存取儲存裝置107時,第三延遲選擇訊號Ssd3則指示第二控制電路105不對儲存裝置107進行存取,反之亦然。由於當第一控制電路103或第二控制電路105開始存取儲存裝置107時,對應的輸入時脈已於較早被傳送至儲存裝置107,因此儲存裝置107就可以避免時脈突發訊號所造成的問題。In step 501, when a control circuit of the first control circuit 103 and the second control circuit 105 wants to access the storage device 107, the control circuit generates a control signal to the first thixotropic circuit 1062 or the first Two thixotropic circuit 1064. For example, when the first control circuit 103 wants to access the storage device 107, the first control circuit 103 generates a control signal Sc1 to the first thixotropic circuit 1062. When the second control circuit 105 wants to access the storage device 107, the second control circuit 105 generates a control signal Sc2 to the second touch circuit 1064. Then, the thixotropic circuit that is touched by the control signal switches the voltage level of the output signal (the first thixotropic output signal St1 or the second thixotropic output signal St2) (step 502). Next, in step 503, the logic gate 1066 generates the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. Correspondingly, the selection signal Ss can indicate which of the first control circuit 103 or the second control circuit 105 is to access the storage device 107. Referring to the operation description of the control device 100, the selection signal Ss passes through three delay circuits (i.e., the first delay circuit 101 (step 504), the second delay circuit 102 (step 505), and the third delay circuit 104 (step 507). ) respectively generating three output signals (ie, output clock Cout, second delay selection signal Ssd2, and third delay selection signal Ssd3), wherein the delay times of the second delay circuit 102 and the third delay circuit 104 (D2, D3) It is greater than the delay time (D1) of the first delay circuit 101. Next, if the output clock Cout is the first input clock C1, the first control circuit 103 starts to access the storage device 107 according to the instruction of the second delay selection signal Ssd2 (step 506). On the other hand, if the output clock Cout is the second input clock C2, the second control circuit 105 starts to access the storage device 107 according to the instruction of the third delay selection signal Ssd3 (step 508). Please note that the control device 100 generates three output signals (ie, the output clock Cout, the second delay selection signal Ssd2, and the third delay selection signal Ssd3) according to the selection signal Ss, wherein the second delay selection signal Ssd2 is used. When the first control circuit 103 is instructed to start accessing the storage device 107, the third delay selection signal Ssd3 is used to indicate when the second control circuit 105 begins to access the storage device 107. Under normal operation, when the second delay selection signal Ssd2 instructs the first control circuit 103 to access the storage device 107, the third delay selection signal Ssd3 instructs the second control circuit 105 not to access the storage device 107, and vice versa. Since the corresponding input clock has been transmitted to the storage device 107 earlier when the first control circuit 103 or the second control circuit 105 starts accessing the storage device 107, the storage device 107 can avoid the clock burst signal. The problem caused.
綜上所述,相較於傳統的儲存裝置存取系統,本發明的控制裝置100以及其控制方法500可以純硬體電路而不需透過韌體的方式來加以實作,此舉不僅具有較快的反應時間(亦即時脈切換時間),亦同時克服了時脈突發訊號的問題。In summary, the control device 100 of the present invention and the control method 500 thereof can be implemented in a pure hardware circuit without using a firmware, compared to the conventional storage device access system. The fast response time (also the instant pulse switching time) also overcomes the problem of the burst signal.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100...控制裝置100. . . Control device
101、201...第一延遲電路101, 201. . . First delay circuit
102...第二延遲電路102. . . Second delay circuit
103...第一控制電路103. . . First control circuit
104...第三延遲電路104. . . Third delay circuit
105...第二控制電路105. . . Second control circuit
106...選擇電路106. . . Selection circuit
107‧‧‧儲存裝置107‧‧‧Storage device
101a、101b、101c、101d、201a、201b、201c、201d‧‧‧及閘101a, 101b, 101c, 101d, 201a, 201b, 201c, 201d‧‧‧ and gate
101e、101f、101g、101h、201e、201f、1022a、1022b、1024a、1024b、1042a、1042b、1044a、1044b‧‧‧D型正反器101e, 101f, 101g, 101h, 201e, 201f, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b‧‧‧D type flip-flop
101i、201g‧‧‧或閘101i, 201g‧‧‧ or gate
101j‧‧‧反相器101j‧‧‧Inverter
1022‧‧‧第一延遲單元1022‧‧‧First delay unit
1024‧‧‧第二延遲單元1024‧‧‧second delay unit
1042‧‧‧第三延遲單元1042‧‧‧3rd delay unit
1044‧‧‧第四延遲單元1044‧‧‧4th delay unit
1062‧‧‧第一觸變電路1062‧‧‧First thixotropic circuit
1064‧‧‧第二觸變電路1064‧‧‧Second touch circuit
1066‧‧‧邏輯閘1066‧‧‧Logic gate
第1圖係本發明一種控制裝置之一實施例示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of one embodiment of a control device of the present invention.
第2圖係本發明一第一延遲電路的一選擇訊號、一第一輸入時脈、一第二輸入時脈以及其係複數個訊號之時序圖。2 is a timing diagram of a selection signal, a first input clock, a second input clock, and a plurality of signals thereof in a first delay circuit of the present invention.
第3圖係本發明該控制裝置的一第一控制訊號、一第二控制訊號、一第一觸變輸出訊號、一第二觸變輸出訊號以及該選擇訊號的一波形時序圖。FIG. 3 is a waveform timing diagram of a first control signal, a second control signal, a first thixotropic output signal, a second thixotropic output signal, and the selection signal of the control device of the present invention.
第4圖係本發明該控制裝置之一第一延遲電路之另一實施例示意圖。Figure 4 is a schematic view showing another embodiment of the first delay circuit of one of the control devices of the present invention.
第5圖係依據本發明一種控制方法之一實施例流程圖。Figure 5 is a flow diagram of an embodiment of a control method in accordance with the present invention.
100...控制裝置100. . . Control device
101...第一延遲電路101. . . First delay circuit
102...第二延遲電路102. . . Second delay circuit
103...第一控制電路103. . . First control circuit
104...第三延遲電路104. . . Third delay circuit
105...第二控制電路105. . . Second control circuit
106...選擇電路106. . . Selection circuit
107...儲存裝置107. . . Storage device
101a、101b、101c、101d...及閘101a, 101b, 101c, 101d. . . Gate
101e、101f、101g、101h、1022a、1022b、1024a、1024b、1042a、1042b、1044a、1044b...D型正反器101e, 101f, 101g, 101h, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b. . . D-type flip-flop
101i...或閘101i. . . Gate
101j...反相器101j. . . inverter
1022...第一延遲單元1022. . . First delay unit
1024...第二延遲單元1024. . . Second delay unit
1042...第三延遲單元1042. . . Third delay unit
1044...第四延遲單元1044. . . Fourth delay unit
1062...第一觸變電路1062. . . First thixotropic circuit
1064...第二觸變電路1064. . . Second thixotropic circuit
1066...邏輯閘1066. . . Logic gate
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