TWI414025B - Power gold - oxygen half - effect transistor structure and its manufacturing method - Google Patents
Power gold - oxygen half - effect transistor structure and its manufacturing method Download PDFInfo
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本發明係關於一種功率金氧半場效電晶體(Power MOSFET)結構及其製程方法，尤指具有雪崩能量改進及可達淺接面(shallow junction)者。The invention relates to a power MOSFET structure and a manufacturing method thereof, in particular to an avalanche energy improvement and a shallow junction.
功率金氧半場效電晶體(Power MOSFET)已被廣泛使用在許多的應用上，例如分離元件、光電子元件、電源控制元件、直流對直流轉換器、馬達驅動...等。這些應用需要一個特殊的崩潰電壓、低導通電阻、高開關切換速度、和廣大的安全操作區域。除此之外，對大部分的應用來說，功率金氧半場效電晶體需要能夠在有電感性負載的情形發生時被導通與截止。當功率金氧半場效電晶體從導通被切換至截止時，此感應負載會在源極與汲極之間感應出一電磁力，並加快雪崩崩潰電流的增加速度；而當寄生的雙極性電晶體被導通時，元件便會毀損。Power MOSFETs have been widely used in many applications, such as discrete components, optoelectronic components, power control components, DC-to-DC converters, motor drives, and more. These applications require a special breakdown voltage, low on-resistance, high switching speed, and a wide range of safe operating areas. In addition, for most applications, the power MOS field effect transistor needs to be able to be turned on and off when an inductive load occurs. When the power MOS half-effect transistor is switched from on to off, the inductive load induces an electromagnetic force between the source and the drain, and accelerates the increase rate of the avalanche breakdown current; and when parasitic bipolar electricity When the crystal is turned on, the component will be damaged.
因此，在這種情形之下，功率金氧半場效電晶體必須保持大量的壓力來避免破壞性失敗的發生，此種能力即被稱為元件的「強健性(ruggedness)」。一般而言，功率金氧半場效電晶體的強健性是被定義在一個單一脈波電感性負載切換(Unclamped Inductive load Switching,UIS)的測試下，還能保持雪崩崩潰電流之雪崩崩潰能量的電流值。Therefore, under this circumstance, the power MOS half-effect transistor must maintain a large amount of pressure to avoid the occurrence of destructive failure, which is called the "ruggedness" of the component. In general, the robustness of a power MOS field-effect transistor is defined by a single pulse inductive load switching (UIS) test, which also maintains the avalanche collapse energy of the avalanche collapse current. value.
然而，由於目前的功率金氧半場效電晶體產品不斷的在追求低導通電阻(turn-on resistance)，採用的手段係不斷的以微縮元件的記憶單元間距(cell pitch)，以使記憶單元密度(cell density)增加。然而，在縮小記憶單元間距的設計下，雖然達到導通電阻下降的目的，但確也增加了整體電容值(Capacitance)及降低了元件的雪崩崩潰能量(Avalanche Energy)。However, since current power MOS field-effect transistor products are continually pursuing low turn-on resistance, the means used is to constantly narrow the memory cell pitch of the components to make the cell density. (cell density) increases. However, in the design of reducing the memory cell pitch, although the purpose of reducing the on-resistance is achieved, it also increases the overall capacitance value and reduces the avalanche energy of the component.
因此，如何發展出一種功率金氧半場效電晶體之結構及其製程方法，使其具有低導通電阻外更具有較佳的雪崩能量，將是本發明所欲積極揭露之處。Therefore, how to develop a structure of a power MOS field-effect transistor and a process method thereof to have a better avalanche energy in addition to low on-resistance will be actively disclosed in the present invention.
有鑑於上述習知功率金氧半場效電晶體產品之缺憾，發明人有感其未臻於完善，遂竭其心智悉心研究克服，憑其從事該項產業多年之累積經驗，進而研發出一種具有一溝渠式電場屏護(Field Plate Trench)設計之功率金氧半場效電晶體結構及其製程方法，其係在元件單一記憶單元(Single cell)的源極接點區加入一電場屏護設計，以期達到淺接面(shallow junction)低導通電阻及較佳的雪崩崩潰能量提升的目的。In view of the shortcomings of the above-mentioned conventional power MOS half-field effect transistor products, the inventor felt that he had not perfected it, exhausted his mental and careful research and overcoming, and based on his accumulated experience in the industry for many years, he developed a A power gold-oxygen half-field effect transistor structure designed by a Field Plate Trench and a process method thereof are added to an electric field screen protection design in a source contact region of a single memory cell (Single cell). In order to achieve the shallow junction low on-resistance and better avalanche collapse energy enhancement.
為達上述目的，本發明之一較佳實施態樣係提供一種功率金氧半場效電晶體結構之製程方法，其包含下列步驟：(a)提供一基板作為汲極，其上具有一磊晶層；(b)於該磊晶層上蝕刻出一閘極淺溝渠結構及一源極淺溝渠結構；(c)於該些淺溝渠之側壁及底部形成氧化物層，並於該些溝渠內沉積多晶矽結構；(d)進行一第一次離子佈植製程，以於該磊晶層中形成一淺基體井區；(e)進行一第二次離子佈植製程，以於該磊晶層中形成一淺源極接面；(f)沉積一介電質層，利用光罩微影蝕刻製程於該磊晶層中蝕刻該源極淺溝渠結構以形成一源極接點區；(g)進行一傾角離子佈植製程，以於該源極淺溝渠結構兩側的該磊晶層中各形成一重摻雜區；及(h)沉積一金屬導線以與該源極接點區接觸而形成一源極金屬導線。In order to achieve the above object, a preferred embodiment of the present invention provides a method for fabricating a power MOS field-effect transistor structure, comprising the steps of: (a) providing a substrate as a drain having an epitaxial layer thereon; a layer; (b) etching a gate shallow trench structure and a source shallow trench structure on the epitaxial layer; (c) forming an oxide layer on the sidewalls and the bottom of the shallow trenches, and forming the oxide layer in the trenches Depositing a polycrystalline germanium structure; (d) performing a first ion implantation process to form a shallow matrix well region in the epitaxial layer; (e) performing a second ion implantation process to the epitaxial layer Forming a shallow source junction; (f) depositing a dielectric layer, etching the source shallow trench structure in the epitaxial layer by a photomask lithography process to form a source contact region; Performing an oblique ion implantation process to form a heavily doped region in each of the epitaxial layers on both sides of the source shallow trench structure; and (h) depositing a metal wire to contact the source contact region A source metal wire is formed.
為達上述目的，本發明之另一較佳實施態樣係提供一種功率金氧半場效電晶體結構之製程方法，其包含下列步驟：提供一基板作為汲極，其上具有一磊晶層；(a)進行一第一次離子佈植製程，以於該磊晶層中形成一淺基體井區；(b)進行一第二次離子佈植製程，以於該磊晶層中形成一淺源極接面；(c)於該磊晶層上蝕刻出一閘極淺溝渠結構及一源極淺溝渠結構；(d)於該些淺溝渠之側壁及底部形成氧化物層，並於該些溝渠內沉積多晶矽結構；(e)沉積一介電質層，利用光罩微影蝕刻製程於該磊晶層中蝕刻該源極淺溝渠結構以形成一源極接點區；(f)進行一傾角離子佈植製程，以於該源極淺溝渠結構兩側的該磊晶層中各形成一重摻雜區；及(g)沉積一金屬導線以與該源極接點區接觸而形成一源極金屬導線。In order to achieve the above object, another preferred embodiment of the present invention provides a method for fabricating a power MOS field-effect transistor structure, comprising the steps of: providing a substrate as a drain having an epitaxial layer thereon; (a) performing a first ion implantation process to form a shallow substrate well region in the epitaxial layer; (b) performing a second ion implantation process to form a shallow layer in the epitaxial layer a source junction; (c) etching a gate shallow trench structure and a source shallow trench structure on the epitaxial layer; (d) forming an oxide layer on sidewalls and bottom portions of the shallow trenches, and Depositing a polycrystalline germanium structure in the trenches; (e) depositing a dielectric layer, etching the source shallow trench structure in the epitaxial layer to form a source contact region by using a mask lithography process; (f) performing An oblique ion implantation process for forming a heavily doped region in the epitaxial layer on both sides of the source shallow trench structure; and (g) depositing a metal wire to contact the source contact region to form a Source metal wire.
於本發明的一實施例中，該基板為N+ 型紅磷基板，於該基板下具有一導電金屬層，該磊晶層為N- 型磊晶層，該N+ 型紅磷基板具有0～0.0015Ω-cm的電阻值。In an embodiment of the invention, the substrate is an N + -type red phosphor substrate, and has a conductive metal layer under the substrate, the epitaxial layer is an N − -type epitaxial layer, and the N + -type red phosphor substrate has 0 A resistance value of -0.0015 Ω-cm.
於本發明的一實施例中，該閘極淺溝渠結構及該源極淺溝渠結構之縱橫比約為1：6，該些淺溝渠結構於該磊晶層中之蝕刻深度約為0.5～1.5μm。In an embodiment of the invention, the gate shallow trench structure and the source shallow trench structure have an aspect ratio of about 1:6, and the shallow trench structures have an etching depth of about 0.5 to 1.5 in the epitaxial layer. Mm.
於本發明的一實施例中，該淺基體井區為一P- 淺基體井區，該淺源極接面為一N+ 淺源極接面，該些重摻雜區為一P+ 重摻雜區。In an embodiment of the invention, the shallow base well region is a P - light base well region, the shallow source junction is an N + shallow source junction, and the heavily doped regions are a P + weight Doped area.
於本發明的一實施例中，該第一及第二次離子佈植製程為全面性植入製程。In an embodiment of the invention, the first and second ion implantation processes are comprehensive implantation processes.
於本發明的一實施例中，該源極接點區於該磊晶層中之蝕刻深度約為0.1～0.7μm。In an embodiment of the invention, the source contact region has an etch depth of about 0.1 to 0.7 μm in the epitaxial layer.
於本發明的一實施例中，該傾角離子佈植製程包含兩次旋轉傾角離子佈植製程，其傾角約為正負7度。In an embodiment of the invention, the tilt ion implantation process comprises two rotation tilt ion implantation processes, and the tilt angle is about plus or minus 7 degrees.
為達上述目的，本發明之再一較佳實施態樣係提供一種功率金氧半場效電晶體結構，其包含：一基板，於該基板之下表面具有一汲極金屬導線以作為汲極接點；一磊晶層，係成長於該基板上，其中該磊晶層更具有一閘極淺溝渠結構及一源極淺溝渠結構，於該些淺溝渠結構之側壁及底部形成有氧化物層並沉積有多晶矽結構以填滿該些淺溝渠結構；一淺基體井區，位於該磊晶層中，係藉由一第一次離子佈植製程所形成；一淺源極接面，位於該淺基體井區之上，係藉由一第二次離子佈植製程所形成；一介電質層，形成於該閘極淺溝渠結構上；一源極接點區，係藉由蝕刻該磊晶層及該源極淺溝渠結構所形成；二重摻雜區，位於該源極淺溝渠結構兩側的該磊晶層中，係藉由一傾角離子佈植製程所形成；及一源極金屬導線，沉積於該介電質層及該源極接點區上以與該源極接點區接觸。In order to achieve the above object, a preferred embodiment of the present invention provides a power MOS field effect transistor structure, comprising: a substrate having a drain metal wire on the lower surface of the substrate for use as a drain An epitaxial layer is grown on the substrate, wherein the epitaxial layer has a gate shallow trench structure and a source shallow trench structure, and an oxide layer is formed on the sidewall and the bottom of the shallow trench structure. And depositing a polycrystalline germanium structure to fill the shallow trench structures; a shallow base well region located in the epitaxial layer is formed by a first ion implantation process; a shallow source junction is located at the The shallow base body region is formed by a second ion implantation process; a dielectric layer is formed on the gate shallow trench structure; and a source contact region is formed by etching the Lei a crystal layer and the source shallow trench structure are formed; a double doped region is formed in the epitaxial layer on both sides of the shallow trench structure, and is formed by an oblique ion implantation process; and a source a metal wire deposited on the dielectric layer and the source contact region In contact with the source contact region.
於本發明的一實施例中，該基板為N+ 型紅磷基板，該磊晶層為N- 型磊晶層，該N+ 型紅磷基板具有0～0.0015Ω-cm的電阻值。In an embodiment of the invention, the substrate is an N + -type red phosphor substrate, the epitaxial layer is an N − -type epitaxial layer, and the N + -type red phosphor substrate has a resistance value of 0 to 0.0015 Ω-cm.
於本發明的一實施例中，該閘極淺溝渠結構及該源極淺溝渠結構之縱橫比約為1：6，該些淺溝渠結構於該磊晶層中之蝕刻深度約為0.5～1.5μm。In an embodiment of the invention, the gate shallow trench structure and the source shallow trench structure have an aspect ratio of about 1:6, and the shallow trench structures have an etching depth of about 0.5 to 1.5 in the epitaxial layer. Mm.
於本發明的一實施例中，該淺基體井區為一P- 淺基體井區，該淺源極接面為一N+ 淺源極接面，該些重摻雜區為一P+ 重摻雜區。In an embodiment of the invention, the shallow base well region is a P - light base well region, the shallow source junction is an N + shallow source junction, and the heavily doped regions are a P + weight Doped area.
於本發明的一實施例中，該第一及第二次離子佈植製程為全面性植入製程。In an embodiment of the invention, the first and second ion implantation processes are comprehensive implantation processes.
於本發明的一實施例中，該源極接點區於該磊晶層中之蝕刻深度約為0.1～0.7μm。In an embodiment of the invention, the source contact region has an etch depth of about 0.1 to 0.7 μm in the epitaxial layer.
於本發明的一實施例中，該傾角離子佈植製程包含兩次旋轉傾角離子佈植製程，其傾角約為正負7度。In an embodiment of the invention, the tilt ion implantation process comprises two rotation tilt ion implantation processes, and the tilt angle is about plus or minus 7 degrees.
為充分瞭解本發明之目的、特徵及功效，茲藉由下述具體之實施例，並配合所附之圖式，對本發明做一詳細說明，說明如後：請參見第一至五圖，係本發明較佳具體實施例之功率金氧半場效電晶體結構的製造流程示意圖，其中將以N通道型為示例予以說明。如圖所示，本發明之功率金氧半場效電晶體結構之製法包含下列步驟：首先，提供一基板21，於該基板21上具有一磊晶層23，然後於該磊晶層23上成長一氧化層25。於本實施例中，該基板21可為高濃度掺雜的N+ 型紅磷基板(Red phosphorous Substrate)，該磊晶層23可為N- 型磊晶層(N- type Epitaxy layer)，而該氧化層25可為氧化矽層(SiO2 )並可利用一熱氧化製程來形成，其結構如第一圖所示。其中，該基板21可作為該功率金氧半場效電晶體結構之汲極，其下方表面可鍍上一導電金屬層以作為汲極接點(請見第五圖之汲極金屬導線47)；該基板21亦可為一矽基板；該氧化層25係做為罩幕層用；而該N+ 型紅磷基板之電阻值較佳為具有0～0.0015Ω-cm的電阻值。In order to fully understand the objects, features and effects of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings, which are illustrated as follows: A schematic diagram of a manufacturing process of a power metal oxide half field effect transistor structure according to a preferred embodiment of the present invention, wherein an N channel type will be described as an example. As shown in the figure, the method for fabricating the power metal oxide half field effect transistor structure of the present invention comprises the steps of: firstly, providing a substrate 21 having an epitaxial layer 23 on the substrate 21 and then growing on the epitaxial layer 23; An oxide layer 25. In the present embodiment, the substrate 21 may be doped to a high concentration of red phosphorus N + type substrate (Red phosphorous Substrate), the epitaxial layer 23 may be an N - type epitaxial layer (N - type Epitaxy layer), and The oxide layer 25 may be a hafnium oxide layer (SiO 2 ) and may be formed by a thermal oxidation process, the structure of which is as shown in the first figure. Wherein, the substrate 21 can serve as a drain of the power MOS field-effect transistor structure, and a lower conductive surface can be plated with a conductive metal layer as a drain contact (see the drain metal wire 47 of FIG. 5); The substrate 21 may also be a germanium substrate; the oxide layer 25 is used as a mask layer; and the resistance value of the N + -type red phosphor substrate is preferably a resistance value of 0 to 0.0015 Ω-cm.
請參見第二圖，接著在該氧化層25上透過光罩微影蝕刻製程(Mask photolithograph)的方式形成圖案化的一光阻層27(Photo Resist)，並以該光阻層27為蝕刻罩幕來蝕刻該氧化層25，之後再蝕刻該磊晶層23，進而形成一源極淺溝渠結構28及二閘極淺溝渠結構29a、29b。該些淺溝渠結構28、29a及29b於該磊晶層23中之蝕刻深度可為0.5～1.5μm，於本實施例中約為0.7～0.9μm，且較佳為具有約H：W=1：6的高縱橫比(high aspect ratio,H/W)。接著進行移除步驟，留下該基板21、該磊晶層23及該些淺溝渠結構28、29a及29b。Referring to the second figure, a patterned photoresist layer 27 (Photo Resist) is formed on the oxide layer 25 by a mask photolithography process, and the photoresist layer 27 is used as an etching mask. The oxide layer 25 is etched by the curtain, and then the epitaxial layer 23 is etched to form a source shallow trench structure 28 and two gate shallow trench structures 29a, 29b. The etch depths of the shallow trench structures 28, 29a and 29b in the epitaxial layer 23 may be 0.5 to 1.5 μm, in the present embodiment, about 0.7 to 0.9 μm, and preferably have about H: W=1. : 6 high aspect ratio (H/W). A removal step is then performed to leave the substrate 21, the epitaxial layer 23, and the shallow trench structures 28, 29a, and 29b.
請參見第三圖，接著以熱氧化製程形成一氧化矽層31於該磊晶層23之表面及該些淺溝渠結構28、29a及29b之側壁及底部，之後進行一多晶矽層(Poly Silicon)之沉積並填滿該些淺溝渠結構28、29a及29b，最後再蝕刻部分的該多晶矽層及該磊晶層23表面之該氧化矽層31，而留下該些淺溝渠結構28、29a及29b內之氧化矽層31及多晶矽結構33。接著，進行第一次離子佈植製程以於該磊晶層23中形成一P- 淺基體井區35(shallow P-body junction)，再進行第二次離子佈植製程以於該磊晶層23中形成一N+ 淺源極接面37(shallow source junction)，其結構如第三圖所示。於本實施例中，該第一次及第二次離子佈植可用全面性(blanket implantation)植入製程以節省光罩微影製程的次數及成本，然亦可採用光罩的方式來形成基體井區或源極植入。第一次離子佈植製程之濃度可為3E12~7E13，能量可為40keV~200keV，使該P-淺基體井區35於該磊晶層23之佈植深度可為0.45～1.45μm；而第二次離子佈植製程之濃度約為1E15~2E16，能量可為40~100keV，使該N+ 淺源極接面37於該磊晶層23之深度約為0.1~0.4μm。Referring to the third figure, a ruthenium oxide layer 31 is formed on the surface of the epitaxial layer 23 and the sidewalls and bottom portions of the shallow trench structures 28, 29a and 29b by a thermal oxidation process, followed by a polysilicon layer (Poly Silicon). Depositing and filling the shallow trench structures 28, 29a and 29b, and finally etching a portion of the polysilicon layer and the germanium oxide layer 31 on the surface of the epitaxial layer 23, leaving the shallow trench structures 28, 29a and The yttrium oxide layer 31 and the polysilicon structure 33 in 29b. Then, a first ion implantation process is performed to form a P - shallow P-body junction in the epitaxial layer 23, and a second ion implantation process is performed on the epitaxial layer. An N + shallow source junction is formed in 23, and its structure is as shown in the third figure. In this embodiment, the first and second ion implantation can be performed by a blanket implantation implantation process to save the number and cost of the photomask lithography process, or a photomask can be used to form the substrate. Well or source implanted. The concentration of the first ion implantation process may be 3E12~7E13, and the energy may be 40 keV~200 keV, so that the implantation depth of the P-light base well region 35 in the epitaxial layer 23 may be 0.45 to 1.45 μm; The concentration of the secondary ion implantation process is about 1E15~2E16, and the energy can be 40~100keV, so that the depth of the N + shallow source junction 37 is about 0.1~0.4μm in the epitaxial layer 23.
前述實施例中係先進行該些淺溝渠結構28、29a及29b的製作，接著才進行該P- 淺基體井區35及該N+ 淺源極接面37的佈植；而於另一實施例中，其程序可互相調換，即先進行該P- 淺基體井區35及該N+ 淺源極接面37的佈植，再進行該些淺溝渠結構28、29a及29b的製作。其佈植與製作方式皆相同，僅順序不同。In the foregoing embodiment, the preparation of the shallow trench structures 28, 29a and 29b is performed first, and then the implantation of the P - light base well region 35 and the N + shallow source junction 37 is performed; In the example, the procedures can be interchanged, that is, the P - light base well region 35 and the N + shallow source junction 37 are implanted first, and then the shallow trench structures 28, 29a and 29b are fabricated. It is planted and produced in the same way, only in different order.
請參見第四圖，隨後沉積一介電質層39，再透過光罩微影蝕刻製程(Mask photolithograph)的方式形成一圖案化的光阻層(圖未示)，以對該介電質層39進行部分蝕刻。接著，去除掉上述光阻層後，以剩餘下來的該介電質層39當做罩幕層，向下蝕刻該磊晶層23(Si etch)。於本實施例中，該介電質層39可為硼磷矽酸鹽玻璃(Boron-Phosphosilicate glass,BPSG)介電質層。Referring to the fourth figure, a dielectric layer 39 is deposited, and a patterned photoresist layer (not shown) is formed through a mask photolithography process to the dielectric layer. 39 is partially etched. Next, after removing the photoresist layer, the remaining dielectric layer 39 is used as a mask layer, and the epitaxial layer 23 (Si etch) is etched downward. In this embodiment, the dielectric layer 39 can be a Boron-Phosphosilicate glass (BPSG) dielectric layer.
上述該磊晶層23的蝕刻深度可做適當的調整(Si etch depth adjustment)，其蝕刻深度可為0.1～0.7μm，而於本實施例中約為0.3～0.5μm。該磊晶層23經過黃光顯影及蝕刻後所形成的開口即為一源極接點區41(Source contact)。其中，由於蝕刻選擇比的關係，蝕刻製程對於該磊晶層23及該多晶矽結構33之蝕刻速度不一，對於該多晶矽結構33之蝕刻速度會較為快速而造成高度差(Si/Poly Si step height,poly recess)，如第五圖所示之該多晶矽結構33表面低於該源極接點區41之表面的情形，此種結構將影響後續重摻雜的接面外觀。The etching depth of the epitaxial layer 23 can be appropriately adjusted (Si etch depth adjustment), and the etching depth can be 0.1 to 0.7 μm, and is about 0.3 to 0.5 μm in this embodiment. The opening formed by the development and etching of the epitaxial layer 23 by yellow light is a source contact region 41 (Source contact). The etching process has different etching speeds for the epitaxial layer 23 and the polysilicon structure 33 due to the etching selectivity ratio, and the etching speed of the polycrystalline germanium structure 33 is relatively fast and causes a height difference (Si/Poly Si step height). , poly recess), as shown in the fifth figure, the surface of the polysilicon structure 33 is lower than the surface of the source contact region 41, such a structure will affect the appearance of the subsequently heavily doped junction.
請繼續參見第四圖，接著進行一傾角離子佈植製程以於該源極淺溝渠結構28兩側的該磊晶層23中各形成一P+ 重摻雜區43，其中該些P+ 重摻雜區43、該多晶矽結構33、該氧化矽層31、該源極淺溝渠結構28構成一溝渠式電場屏護(Field Plate)結構。於本實施例中，該傾角離子佈植製程可為兩次的旋轉傾角離子佈植製程，傾角約為正負7度，而於該源極淺溝渠結構28兩側的該磊晶層23中形成互相對稱的該P+ 重摻雜區43，其中旋轉離子佈植製程之佈植濃度可為5E14~5E15，能量約為20keV~120keV。Please continue to refer to the fourth figure, and then perform an oblique ion implantation process to form a P + heavily doped region 43 in the epitaxial layer 23 on both sides of the source shallow trench structure 28, wherein the P + heavy The doped region 43, the polysilicon structure 33, the yttria layer 31, and the source shallow trench structure 28 form a trench-type field plate structure. In this embodiment, the tilting ion implantation process can be two rotating tilt ion implantation processes, and the tilt angle is about plus or minus 7 degrees, and is formed in the epitaxial layer 23 on both sides of the source shallow trench structure 28. The P + heavily doped region 43 is symmetric with each other, wherein the rotary ion implantation process can be implanted at a concentration of 5E14 to 5E15 and an energy of about 20 keV to 120 keV.
如前所述，由於該多晶矽結構33表面與該源極接點區41表面之高度差，該P+ 重摻雜區43的接面外觀(junction profile)係呈階梯狀，如第四圖所示。此種接面外觀增加了在N+ 源極區下P+ 摻雜區的面積，因而大幅降低在該P- 淺基體井區35、該源極金屬導線45與該源極接點區41間之寄生雙極性電晶體被導通的機會，也因此大幅加強了雪崩崩潰能量的耐受度。As described above, due to the difference in height between the surface of the polysilicon structure 33 and the surface of the source contact region 41, the junction profile of the P + heavily doped region 43 is stepped, as shown in the fourth figure. Show. The appearance of such junction increases the area of the P + doped region under the N + source region, thereby greatly reducing the P - shallow substrate well region 35, the source metal conductor 45 and the source contact region 41 The opportunity for the parasitic bipolar transistor to be turned on greatly enhances the tolerance of the avalanche collapse energy.
接著請參見第五圖，再以金屬沉積(Metalization)及光罩微影蝕刻製程來形成金屬連接導線，以及產生較佳的歐姆接觸(ohmic contact)。前述金屬連接導線為一源極金屬導線45，加上先前的一汲極金屬導線47，如此，具有一溝渠式電場屏護結構功率電晶體的三端子，閘極(Gate)、源極(Source)及汲極(Drain)便得以製作完成，而可達到淺接面低導通電阻及提升雪崩能量的目的。Next, please refer to the fifth figure, and then metallization and lithography process to form metal connection wires, and to produce a better ohmic contact. The metal connecting wire is a source metal wire 45, plus a previous one of the drain metal wires 47. Thus, the three terminals of the power transistor having a trench type electric field screen protection structure, the gate and the source (Source) ) and Drain can be completed, which can achieve the low on-resistance of the shallow junction and the avalanche energy.
本發明可實際應用於一功率金氧半場效電晶體之結構內。根據前述方法，本發明同時揭示一種功率金氧半場效電晶體之結構，請參閱第五圖，其結構包含：一基板21，於該基板21之下表面具有一汲極金屬導線47以作為汲極接點；一磊晶層23，係成長於該基板21上，其中該磊晶層23更具有一閘極淺溝渠結構29a、29b及一源極淺溝渠結構28，於該些淺溝渠結構之側壁及底部形成有氧化物層31並沉積有多晶矽結構33以填滿該些淺溝渠結構；一淺基體井區，位於該磊晶層23中，係藉由一第一次離子佈植製程所形成；一淺源極接面，位於該淺基體井區35之上，係藉由一第二次離子佈植製程所形成；一介電質層39，形成於該閘極淺溝渠結構29a、29b上；一源極接點區41，係藉由蝕刻該磊晶層23及該源極淺溝渠結構28所形成；二重摻雜區，位於該源極淺溝渠結構28兩側的該磊晶層23中，係藉由一傾角離子佈植製程所形成；及一源極金屬導線45，沉積於該介電質層39及該源極接點區41上以與該源極接點區41接觸。The invention can be practically applied to the structure of a power MOS field effect transistor. According to the foregoing method, the present invention simultaneously discloses a structure of a power MOS field effect transistor. Referring to FIG. 5, the structure includes: a substrate 21 having a drain metal wire 47 on the lower surface of the substrate 21 as a 汲An epitaxial layer 23 is grown on the substrate 21, wherein the epitaxial layer 23 further has a gate shallow trench structure 29a, 29b and a source shallow trench structure 28, and the shallow trench structure An oxide layer 31 is formed on the sidewalls and the bottom portion and a polycrystalline germanium structure 33 is deposited to fill the shallow trench structures; a shallow base well region is located in the epitaxial layer 23 by a first ion implantation process Formed; a shallow source junction, located above the shallow base well region 35, formed by a second ion implantation process; a dielectric layer 39 formed in the gate shallow trench structure 29a And a source contact region 41 formed by etching the epitaxial layer 23 and the source shallow trench structure 28; the double doped region is located on both sides of the source shallow trench structure 28 The epitaxial layer 23 is formed by an oblique ion implantation process; and a source metal A wire 45 is deposited on the dielectric layer 39 and the source contact region 41 to be in contact with the source contact region 41.
在實際應用時，該基板21可為N+ 型紅磷基板，該磊晶層23可為N- 型磊晶層，其中該N+ 型紅磷基板具有低於0.0015Ω-cm的阻值。該閘極淺溝渠結構29a、29b及該源極淺溝渠結構28之縱橫比約為1：6，該些淺溝渠結構於該磊晶層23中之蝕刻深度可為0.5～1.5μm，於本實施例中約為0.7～0.9μm。該淺基體井區為一P- 淺基體井區35，該淺源極接面為一N+ 淺源極接面37，該些重摻雜區為一P+ 重摻雜區43。該源極接點區41於該磊晶層23中之蝕刻深度可為0.1～0.7μm，而於本實施例中約為0.3～0.5μm。In practical applications, the substrate 21 may be an N + -type red phosphor substrate, and the epitaxial layer 23 may be an N − -type epitaxial layer, wherein the N + -type red phosphor substrate has a resistance lower than 0.0015 Ω-cm. The gate shallow trench structure 29a, 29b and the source shallow trench structure 28 have an aspect ratio of about 1:6, and the shallow trench structure may have an etching depth of 0.5 to 1.5 μm in the epitaxial layer 23, In the examples, it is about 0.7 to 0.9 μm. The shallow base well region is a P - light base well region 35, the shallow source junction is an N + shallow source junction 37, and the heavily doped regions are a P + heavily doped region 43. The source contact region 41 may have an etch depth of 0.1 to 0.7 μm in the epitaxial layer 23, and is about 0.3 to 0.5 μm in this embodiment.
如上所述，本發明完全符合專利三要件：新穎性、進步性和產業上的可利用性。以新穎性和進步性而言，本發明係提供一種新的元件結構，可實現淺接面來達成低導通電阻，並又能達到高雪崩能量及較低的電容值；就產業上的可利用性而言，利用本發明所衍生的產品，當可充分滿足目前市場的需求。As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. In terms of novelty and advancement, the present invention provides a new component structure that can achieve a shallow junction to achieve low on-resistance, and can achieve high avalanche energy and low capacitance; industrially available Sexually, the products derived from the present invention can fully satisfy the needs of the current market.
本發明在上文中已以較佳實施例揭露，然上述說明係以磊晶層為N- 通道的功率金氧半場效電晶體來做說明，但本發明亦可適用於磊晶層為P- 通道的功率金氧半場效電晶體，其中僅需將原本的P改為N，原本的N改為P即可實施本發明。此外，上述說明中，該些淺溝渠結構之數量僅為一種示例，熟習本項技術者應理解的是，該實施例僅用於描繪本發明，而不應解讀為限制本發明之範圍。應注意的是，舉凡與該實施例等效之變化與置換，均應設為涵蓋於本發明之範疇內。因此，本發明之保護範圍當以下文之申請專利範圍所界定者為準。In the present invention, the above embodiment has been disclosed in terms of preferred embodiments, then to the above description based epitaxial layer N - power metal oxide semiconductor field effect transistor channel to do, but the present invention is also applicable to the epitaxial layer is a P - The power MOS half-field effect transistor of the channel, wherein only the original P is changed to N, and the original N is changed to P to implement the present invention. In addition, in the above description, the number of the shallow trench structures is only an example, and it should be understood by those skilled in the art that the present invention is only used to describe the present invention and should not be construed as limiting the scope of the present invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.
21．．．基板twenty one. . . Substrate
23．．．磊晶層twenty three. . . Epitaxial layer
25．．．氧化層25. . . Oxide layer
27．．．光阻層27. . . Photoresist layer
28．．．源極淺溝渠結構28. . . Source shallow trench structure
29a．．．閘極淺溝渠結構29a. . . Gate shallow ditches
29b．．．閘極淺溝渠結構29b. . . Gate shallow ditches
31．．．氧化矽層31. . . Cerium oxide layer
33．．．多晶矽結構33. . . Polycrystalline germanium structure
35．．．P-淺基體井區35. . . P-shallow base well area
37．．．N+淺源極接面37. . . N+ shallow source junction
39．．．介電質層39. . . Dielectric layer
41．．．源極接點區41. . . Source contact area
43．．．P+重摻雜區43. . . P+ heavily doped area
45．．．源極金屬導線45. . . Source metal wire
47．．．汲極金屬導線47. . . Bungee metal wire
第一圖至第五圖為本發明較佳具體實施例之功率金氧半場效電晶體結構的製造流程示意圖。The first to fifth figures are schematic diagrams showing the manufacturing process of the power metal oxide half field effect transistor structure according to a preferred embodiment of the present invention.
21．．．基板twenty one. . . Substrate
23．．．磊晶層twenty three. . . Epitaxial layer
28．．．源極淺溝渠結構28. . . Source shallow trench structure
29a．．．閘極淺溝渠結構29a. . . Gate shallow ditches
29b．．．閘極淺溝渠結構29b. . . Gate shallow ditches
31．．．氧化矽層31. . . Cerium oxide layer
33．．．多晶矽結構33. . . Polycrystalline germanium structure
35．．．P-淺基體井區35. . . P-shallow base well area
37．．．N+淺源極接面37. . . N+ shallow source junction
39．．．介電質層39. . . Dielectric layer
41．．．源極接點區41. . . Source contact area
43．．．P+重摻雜區43. . . P+ heavily doped area
45．．．源極金屬導線45. . . Source metal wire
47．．．汲極金屬導線47. . . Bungee metal wire
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| TW97147523A TWI414025B (en) | 2008-12-05 | 2008-12-05 | Power gold - oxygen half - effect transistor structure and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI746007B (en) * | 2020-06-12 | 2021-11-11 | 新唐科技股份有限公司 | Power device |
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| TWI455287B (en) * | 2010-11-04 | 2014-10-01 | Sinopower Semiconductor Inc | Termination structure of power semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6770539B2 (en) * | 2002-04-30 | 2004-08-03 | Nec Electronics Corporation | Vertical type MOSFET and manufacturing method thereof |
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| US6770539B2 (en) * | 2002-04-30 | 2004-08-03 | Nec Electronics Corporation | Vertical type MOSFET and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI746007B (en) * | 2020-06-12 | 2021-11-11 | 新唐科技股份有限公司 | Power device |
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