TWI413971B - Adjusting circuit for setup time and hold time of chip - Google Patents
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本發明涉及一種驅動晶片的調整電路，特別涉及一種液晶監視器內驅動晶片的建立時間和保持時間的調整電路。 The present invention relates to an adjustment circuit for driving a wafer, and more particularly to an adjustment circuit for establishing a setup time and a retention time of a wafer in a liquid crystal monitor.
液晶監視器中驅動晶片(Source IC)在接收資料之前具有一段建立時間(setup time)，它的定義為低擺幅差分訊號(RSDS，Reduced swing differential signal)開始傳送到驅動晶片起到第一個低擺幅差分訊號開始的時間，這段時間為低擺幅差分訊號從零到有即低擺幅差分訊號由零升高到高電位所需要的準備時間。當低擺幅差分訊號準備好之後，即在第一個低擺幅差分訊號開始時，驅動晶片開始抓取低擺幅差分訊號，保持時間(hold time)即是為了能夠讓驅動晶片抓取到正確的低擺幅差分訊號。 The source chip in the LCD monitor has a settling time before receiving the data. It is defined as the reduced swing differential signal (RSDS) that starts to be transmitted to the driver chip. The start time of the low-swing differential signal, which is the preparation time required for the low-swing differential signal to go from zero to the low-swing differential signal from zero to high. When the low swing differential signal is ready, that is, at the beginning of the first low swing differential signal, the driver chip begins to capture the low swing differential signal. The hold time is to enable the driver chip to be captured. Correct low swing differential signal.
由於習知所使用的液晶監視器的刷新頻率基本上皆為60HZ或者75HZ，故將建立時間和保持時間設定為一固定值即可。然，隨著對液晶監視器的品質要求的不斷增加，需要透過增加監視器的刷新頻率來彌補液晶監視器的動態模糊(Motion blur)等不足，如此則需要將建立時間和保持時間縮短。且，當用戶自定義刷新頻率時，無法做到建立時間和保持時間自動更新。 Since the refresh rate of the liquid crystal monitor used in the prior art is basically 60 Hz or 75 Hz, the settling time and the holding time can be set to a fixed value. However, as the quality requirements for liquid crystal monitors continue to increase, it is necessary to compensate for the lack of motion blur of the liquid crystal monitor by increasing the refresh rate of the monitor, and thus it is necessary to shorten the setup time and the hold time. Moreover, when the user customizes the refresh frequency, the setup time and the hold time cannot be automatically updated.
鑒於以上內容，有必要提供一種能根據液晶監視器的刷新頻率自動調整驅動晶片的建立時間和保持時間的電路。 In view of the above, it is necessary to provide a circuit capable of automatically adjusting the setup time and the hold time of the drive wafer in accordance with the refresh rate of the liquid crystal monitor.
一種驅動晶片的建立時間和保持時間調整電路，包括：一控制器，用於接收一刷新頻率訊號；一記憶體，用於存儲複數不同刷新頻率訊號及其所對應的最佳建立時間和保持時間；一偵測器，用於對輸入控制器的刷新頻率訊號進行偵測，以得到刷新頻率訊號的時鐘頻率，該控制器還用於將得到的時鐘頻率與記憶體中刷新頻率及其最佳建立時間和保持時間進行比對，以得到該刷新頻率所對應的最佳建立時間和保持時間，並根據該最佳建立時間和保持時間產生對應的控制訊號；以及一控制電路，用於接收控制器輸出的控制訊號，並產生對應的偏斜值，該驅動晶片根據偏斜值完成對建立時間及保持時間的設定。 A setup time and hold time adjustment circuit for driving a chip, comprising: a controller for receiving a refresh frequency signal; a memory for storing a plurality of different refresh frequency signals and corresponding optimum setup time and hold time a detector for detecting a refresh frequency signal of the input controller to obtain a clock frequency for refreshing the frequency signal, and the controller is further configured to use the obtained clock frequency and the refresh frequency in the memory and the best Establishing time and holding time for comparison to obtain an optimal setup time and hold time corresponding to the refresh frequency, and generating corresponding control signals according to the optimal setup time and hold time; and a control circuit for receiving control The controller outputs a control signal and generates a corresponding skew value. The driver wafer completes the setting of the setup time and the hold time according to the skew value.
一種驅動晶片的建立時間和保持時間調整電路，包括：一時序控制器，用於接收一刷新頻率訊號；一記憶體，用於存儲複數不同刷新頻率訊號及其所對應的最佳建立時間和保持時間；以及一偵測器，用於對輸入時序控制器的刷新頻率訊號進 行偵測，以得到刷新頻率訊號的時鐘頻率，並將得到的時鐘頻率輸出給該時序控制器；其中，該時序控制器還用於將得到的時鐘頻率與記憶體中刷新頻率及其最佳建立時間和保持時間進行比對，以得到該刷新頻率所對應的最佳建立時間和保持時間，並根據該最佳建立時間和保持時間產生對應的時序控制訊號以輸出給驅動晶片。 A setup time and hold time adjustment circuit for driving a chip, comprising: a timing controller for receiving a refresh frequency signal; a memory for storing a plurality of different refresh frequency signals and corresponding optimum setup time and retention Time; and a detector for refreshing the frequency of the input timing controller Line detection to obtain the clock frequency of the refresh frequency signal, and output the obtained clock frequency to the timing controller; wherein the timing controller is further used to obtain the obtained clock frequency and the refresh frequency in the memory and the best The setup time and the hold time are compared to obtain an optimal setup time and a hold time corresponding to the refresh frequency, and corresponding timing control signals are generated according to the optimal setup time and the hold time for output to the drive wafer.
一種驅動晶片的建立時間和保持時間調整電路，包括：一時序控制器，用於接收一刷新頻率訊號；一記憶體，用於存儲複數驅動晶片在複數不同刷新頻率訊號下所對應的最佳建立時間和保持時間；以及一偵測器，用於對輸入時序控制器的刷新頻率訊號進行偵測，以得到刷新頻率訊號的時鐘頻率，並將得到的時鐘頻率輸出給該時序控制器；其中，該時序控制器還用於將得到的時鐘頻率與記憶體中每一驅動晶片在不同刷新頻率訊號下所對應的最佳建立時間和保持時間進行比對，以得到該驅動晶片在該刷新頻率下所對應的最佳建立時間和保持時間，並根據該最佳建立時間和保持時間產生對應的時序控制訊號以輸出給對應的驅動晶片。 A setup time and hold time adjustment circuit for driving a chip, comprising: a timing controller for receiving a refresh frequency signal; and a memory for storing the optimal setup of the complex drive chip under a plurality of different refresh frequency signals And a time detector; and a detector for detecting a refresh frequency signal of the input timing controller to obtain a clock frequency for refreshing the frequency signal, and outputting the obtained clock frequency to the timing controller; wherein The timing controller is further configured to compare the obtained clock frequency with an optimal setup time and a hold time corresponding to each driver chip in the memory under different refresh frequency signals, to obtain the driving chip at the refresh frequency. Corresponding optimal setup time and hold time, and corresponding timing control signals are generated according to the optimal setup time and hold time for output to the corresponding drive chip.
前述驅動晶片的建立時間和保持時間調整電路透過控制器或時序控制器偵測液晶監視器的刷新頻率，並將其與存儲於記憶體內部的最佳建立時間和保持時間進行比對，然後據此輸出對應的控制訊號或者直接輸出時序訊號至驅 動晶片，從而可使得驅動晶片根據不同的刷新頻率具有不同的最佳建立時間和保持時間。 The setup time and hold time adjustment circuit of the driving chip detects the refresh frequency of the liquid crystal monitor through the controller or the timing controller, and compares it with the optimal setup time and the hold time stored in the memory, and then This output corresponds to the control signal or directly outputs the timing signal to the drive The wafer is driven so that the driver wafers have different optimum settling times and hold times depending on the refresh rate.
請參閱圖1，本發明驅動晶片的建立時間和保持時間調整電路用於根據液晶監視器的刷新頻率自動調整驅動晶片的建立時間和保持時間，其第一較佳實施方式包括一控制器10、一記憶體12、一偵測器15以及一控制電路16。 Referring to FIG. 1 , the setup time and hold time adjustment circuit of the drive wafer of the present invention is used to automatically adjust the setup time and the hold time of the drive wafer according to the refresh frequency of the liquid crystal monitor. The first preferred embodiment includes a controller 10 . A memory 12, a detector 15 and a control circuit 16.
該控制器10與記憶體12、偵測器15以及控制電路16均相連，還用於接收液晶監視器的刷新頻率訊號。 The controller 10 is connected to the memory 12, the detector 15 and the control circuit 16, and is also configured to receive a refresh frequency signal of the liquid crystal monitor.
該記憶體12中存儲有複數不同刷新頻率及其所對應的最佳建立時間和保持時間。用戶可事先將複數不同刷新頻率下驅動晶片所對應的最佳建立時間和保持時間透過測量的方法得出，並將其存儲於該記憶體12中。本實施方式中，該記憶體12為一電可讀寫可編程唯讀記憶體(EEPROM)。 The memory 12 stores a plurality of different refresh frequencies and their corresponding optimal setup and hold times. The user can obtain the optimal setup time and hold time corresponding to the driving of the wafer at different refresh frequencies in advance through measurement, and store it in the memory 12. In this embodiment, the memory 12 is an electrically readable and writable programmable read only memory (EEPROM).
該偵測器15用於對輸入控制器10的刷新頻率進行偵測，以得知此時所輸入的訊號的時鐘頻率，並將偵測得到的時鐘頻率傳送至控制器10，該時鐘頻率即為液晶監視器的刷新頻率。該控制器10將得到的時鐘頻率與存儲在記憶體12中的刷新頻率及其最佳建立時間和保持時間進行比對，以得到該刷新頻率所對應的最佳建立時間和保持時間，並根據該最佳建立時間和保持時間產生對應的控制訊 號。 The detector 15 is configured to detect the refresh frequency of the input controller 10 to know the clock frequency of the signal input at this time, and transmit the detected clock frequency to the controller 10, and the clock frequency is Is the refresh rate of the LCD monitor. The controller 10 compares the obtained clock frequency with the refresh frequency stored in the memory 12 and its optimal setup time and hold time to obtain the optimal setup time and hold time corresponding to the refresh frequency, and according to The optimal setup time and hold time generate corresponding control signals number.
該控制電路16包括四個場效應電晶體Q1-Q4以及四個電阻R1-R4，該場效應電晶體Q1-Q4的閘極對應與該控制器10的四個輸出端相連。該場效應電晶體Q1的汲極與數位電源DVDD相連，源極依次透過電阻R1及R2與場效應電晶體Q2的汲極相連，該場效應電晶體Q2的源極接地。該場效應電晶體Q3的汲極與數位電源DVDD相連，源極依次透過電阻R3與R4與場效應電晶體Q4的汲極相連，該場效應電晶體Q4的源極接地。本實施方式中，電阻R1-R4的阻值均為1K歐姆。其中，電阻R1和R2之間的電平值即為第一偏斜(Skew)值，電阻R3和R4之間的電平值即為第二偏斜值。該第一偏斜值及第二偏斜值均用於輸出給驅動晶片，該驅動晶片可根據接收的第一及第二偏斜值設定對應的建立時間及保持時間。其中，第一及第二偏斜值與建立時間及保持時間的對應關係如下表：
上表中T代表一個完整的低擺幅差分訊號週期(RSDS clock cycle)。當場效應電晶體Q1及Q3均不導通、場效應電晶體Q2及Q4導通時，該第一及第二偏斜值均為0，此時驅動晶片的建立時間為T/16-T/2、保持時間為T/16；當場效應電晶體Q1不導通、場效應電晶體Q2導通、場效應電晶體Q3導通、場效應電晶體Q4不導通時，該第一偏斜值為0、第二偏斜值為1，此時驅動晶片的建立時間為2T/16-T/2、保持時間為2T/16；當場效應電晶體Q1及Q4導通、場效應電晶體Q2及Q3均不導通時，該第一偏斜值為1、第二偏斜值為0，此時驅動晶片的建立時間為3T/16-T/2、保持時間為3T/16。其他情形依此類推。 In the above table, T represents a complete low-swing RSDS clock cycle. When the field effect transistors Q1 and Q3 are not turned on, and the field effect transistors Q2 and Q4 are turned on, the first and second skew values are all 0, and the setup time of the driving wafer is T/16-T/2. The hold time is T/16; when the field effect transistor Q1 is not turned on, the field effect transistor Q2 is turned on, the field effect transistor Q3 is turned on, and the field effect transistor Q4 is not turned on, the first skew value is 0, and the second bias is The skew value is 1, when the setup time of the driving chip is 2T/16-T/2, and the holding time is 2T/16; when the field effect transistors Q1 and Q4 are turned on, and the field effect transistors Q2 and Q3 are not turned on, The first skew value is 1, and the second skew value is 0. At this time, the setup time of the driving wafer is 3T/16-T/2, and the holding time is 3T/16. Other situations and so on.
第一較佳實施方式中，透過控制器10輸出對應的控制訊號控制四個場效應電晶體Q1-Q4的導通與截止，以得到對應的第一偏斜值及第二偏斜值，從而可實現對驅動晶片的最佳建立時間和保持時間的選擇。比如，當偵測器15偵測到輸入的訊號的時鐘頻率為60HZ時，該控制器10從記憶體12中得知此刷新頻率下最佳建立時間與保持時間分別為4T/16-T/2、4T/16，則該控制器10產生對應的控制訊 號(1，1，0，0)，並輸出該控制訊號至控制電路16，使得場效應電晶體Q1及Q3導通、場效應電晶體Q2及Q4不導通，從而使得第一及第二偏斜值均為“1”，此時，該驅動晶片接收到第一及第二偏斜值均為“1”，則其建立時間將被設定為4T/16-T/2，保持時間為4T/16。 In the first preferred embodiment, the controller 10 outputs a corresponding control signal to control the on and off of the four field effect transistors Q1-Q4 to obtain a corresponding first skew value and a second skew value. Achieve the choice of optimal setup and hold times for driving the wafer. For example, when the detector 15 detects that the clock frequency of the input signal is 60 Hz, the controller 10 knows from the memory 12 that the optimal setup time and the hold time at the refresh frequency are 4T/16-T/, respectively. 2, 4T/16, the controller 10 generates a corresponding control signal No. (1, 1, 0, 0), and outputting the control signal to the control circuit 16, so that the field effect transistors Q1 and Q3 are turned on, and the field effect transistors Q2 and Q4 are not turned on, thereby making the first and second skews The value is "1". At this time, the driver chip receives the first and second skew values of "1", and the setup time will be set to 4T/16-T/2, and the hold time is 4T/ 16.
請參閱圖2，本發明驅動晶片的建立時間和保持時間調整電路的第二較佳實施方式包括一時序控制器20、一記憶體22以及一偵測器25。 Referring to FIG. 2, a second preferred embodiment of the setup time and hold time adjustment circuit for driving a wafer of the present invention includes a timing controller 20, a memory 22, and a detector 25.
該時序控制器20與記憶體22、偵測器25以及一驅動晶片26均相連，還用於接收液晶監視器的刷新頻率訊號。 The timing controller 20 is connected to the memory 22, the detector 25, and a driving chip 26, and is also configured to receive a refresh frequency signal of the liquid crystal monitor.
該記憶體22中存儲有複數不同刷新頻率及其所對應的最佳建立時間和保持時間。用戶可事先將複數不同頻率下驅動晶片的最佳建立時間和保持時間透過測量的方法得出，並將其存儲於該記憶體22中。本實施方式中，該記憶體22為一電可讀寫可編程唯讀記憶體。 The memory 22 stores a plurality of different refresh frequencies and their corresponding optimal setup and hold times. The user can previously obtain the optimum settling time and holding time of the driving chip at different frequencies by measurement and store it in the memory 22. In this embodiment, the memory 22 is an electrically readable and writable programmable read only memory.
該偵測器25用於對輸入時序控制器20的刷新頻率進行偵測，以得知此時所輸入的訊號的時鐘頻率，並將偵測得到的時鐘頻率傳送至時序控制器20，該時鐘頻率即為液晶監視器的刷新頻率。該時序控制器20將得到的時鐘頻率與存儲在記憶體22中的刷新頻率及其所對應的最佳建立時間和保持時間進行比對，以得到該刷新頻率所對應的最佳建立時間和保持時間，並根據得到的最佳建立時間和保 持時間輸出對應的時序訊號至驅動晶片26，即可實現最佳的建立時間和保持時間。 The detector 25 is configured to detect the refresh frequency of the input timing controller 20 to know the clock frequency of the signal input at this time, and transmit the detected clock frequency to the timing controller 20, the clock. The frequency is the refresh rate of the LCD monitor. The timing controller 20 compares the obtained clock frequency with the refresh frequency stored in the memory 22 and the corresponding optimal setup time and hold time to obtain the optimal setup time and hold corresponding to the refresh frequency. Time and according to the best settling time and guarantee The optimal setup time and hold time can be achieved by time-sending the corresponding timing signal to the driver chip 26.
第二較佳實施方式中，該時序控制器20根據得到的最佳建立時間和保持時間直接輸出時序訊號給驅動晶片26，從而可實現對最佳建立時間和保持時間的選擇。 In the second preferred embodiment, the timing controller 20 directly outputs timing signals to the driver wafer 26 according to the obtained optimal setup time and hold time, so that the selection of the optimal setup time and the hold time can be achieved.
請參閱圖3，本發明驅動晶片的建立時間和保持時間調整電路的第三較佳實施方式包括一時序控制器30、一記憶體32以及一偵測器35。 Referring to FIG. 3, a third preferred embodiment of the setup time and hold time adjustment circuit for driving a wafer of the present invention includes a timing controller 30, a memory 32, and a detector 35.
該時序控制器30與記憶體32、偵測器35以及複數驅動晶片36均相連，還用於接收液晶監視器的刷新頻率訊號。 The timing controller 30 is connected to the memory 32, the detector 35, and the complex driving chip 36, and is also configured to receive a refresh frequency signal of the liquid crystal monitor.
該記憶體32中存儲有每一驅動晶片36在複數不同刷新頻率下所對應的最佳建立時間和保持時間。用戶可事先將每一驅動晶片36在複數不同頻率下所對應的最佳建立時間和保持時間透過測量的方法得出，並將其存儲於該記憶體32中。本實施方式中，該記憶體32為一電可讀寫可編程唯讀記憶體。 The memory 32 stores the optimum settling time and hold time for each of the drive wafers 36 at a plurality of different refresh frequencies. The user can previously obtain the optimal setup time and hold time corresponding to each of the drive chips 36 at a plurality of different frequencies through measurement, and store them in the memory 32. In the embodiment, the memory 32 is an electrically readable and writable programmable read only memory.
該偵測器35用於對輸入時序控制器30的刷新頻率進行偵測，以得知此時所輸入的訊號的時鐘頻率，並將偵測得到的時鐘頻率傳送至時序控制器30，該時鐘頻率即為液晶監視器的刷新頻率。該時序控制器30將得到的時鐘頻率與存儲在記憶體32中的每一驅動晶片36的刷新頻率及其 對應的最佳建立時間和保持時間進行比對，以得到該刷新頻率下每一驅動晶片36所對應的最佳建立時間和保持時間，並根據得到的最佳建立時間和保持時間輸出對應的時序訊號至對應的驅動晶片36，即可實現每一驅動晶片36均擁有最佳的建立時間和保持時間。 The detector 35 is configured to detect the refresh frequency of the input timing controller 30 to know the clock frequency of the signal input at this time, and transmit the detected clock frequency to the timing controller 30, the clock. The frequency is the refresh rate of the LCD monitor. The timing controller 30 compares the obtained clock frequency with the refresh frequency of each of the drive chips 36 stored in the memory 32 and Corresponding optimal setup time and hold time are compared to obtain an optimal setup time and hold time corresponding to each drive chip 36 at the refresh frequency, and the corresponding timing is output according to the obtained optimal setup time and hold time. Signaling to the corresponding driver die 36 allows for optimal setup and hold times for each driver die 36.
第三較佳實施方式中，該時序控制器30根據得到的每一驅動晶片36的最佳建立時間和保持時間直接輸出對應的時序訊號給不同的驅動晶片36，從而可實現對最佳建立時間和保持時間的選擇。 In the third preferred embodiment, the timing controller 30 directly outputs the corresponding timing signals to the different driving chips 36 according to the obtained optimal setup time and the holding time of each of the driving chips 36, thereby achieving optimal setup time. And keep the choice of time.
前述驅動晶片的建立時間和保持時間調整電路透過控制器或時序控制器偵測液晶監視器的刷新頻率，並將其與存儲於記憶體內部的最佳建立時間和保持時間進行比對，然後據此輸出對應的控制訊號或者直接輸出時序訊號至驅動晶片，從而可使得驅動晶片根據不同的刷新頻率具有不同的最佳建立時間和保持時間。 The setup time and hold time adjustment circuit of the driving chip detects the refresh frequency of the liquid crystal monitor through the controller or the timing controller, and compares it with the optimal setup time and the hold time stored in the memory, and then The output corresponding to the control signal or the direct output timing signal to the driving chip, so that the driving wafer has different optimal setup time and holding time according to different refresh frequencies.
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。 In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.
10‧‧‧控制器 10‧‧‧ Controller
12、22、32‧‧‧記憶體 12, 22, 32‧‧‧ memory
15、25、35‧‧‧偵測器 15, 25, 35‧‧‧Detector
16‧‧‧控制電路 16‧‧‧Control circuit
DVDD‧‧‧數位電源 DVDD‧‧‧Digital power supply
Q1-Q4‧‧‧場效應電晶體 Q1-Q4‧‧‧ Field Effect Transistor
R1-R4‧‧‧電阻 R1-R4‧‧‧ resistance
20、30‧‧‧時序控制器 20, 30‧‧‧ timing controller
26、36‧‧‧驅動晶片 26, 36‧‧‧ drive chip
圖1是本發明驅動晶片的建立時間和保持時間調整電路的第一較佳實施方式的示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a first preferred embodiment of a setup time and hold time adjustment circuit for a drive wafer of the present invention.
圖2是本發明驅動晶片的建立時間和保持時間調整電路的第二較佳實施方式的示意圖。 2 is a schematic diagram of a second preferred embodiment of the setup time and hold time adjustment circuit of the drive wafer of the present invention.
圖3是本發明驅動晶片的建立時間和保持時間調整電路的第三較佳實施方式的示意圖。 3 is a schematic diagram of a third preferred embodiment of the setup time and hold time adjustment circuit of the drive wafer of the present invention.
10‧‧‧控制器 10‧‧‧ Controller
12‧‧‧記憶體 12‧‧‧ memory
15‧‧‧偵測器 15‧‧‧Detector
16‧‧‧控制電路 16‧‧‧Control circuit
DVDD‧‧‧數位電源 DVDD‧‧‧Digital power supply
Q1-Q4‧‧‧場效應電晶體 Q1-Q4‧‧‧ Field Effect Transistor
R1-R4‧‧‧電阻 R1-R4‧‧‧ resistance
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| TW98144038A TWI413971B (en) | 2009-12-22 | 2009-12-22 | Adjusting circuit for setup time and hold time of chip |
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| TWI413971B true TWI413971B (en) | 2013-11-01 |
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| TW201123153A (en) | 2011-07-01 |
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