TWI412108B - Bond pad structure and integrated circuit chip - Google Patents
Bond pad structure and integrated circuit chip Download PDFInfo
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- TWI412108B TWI412108B TW100100051A TW100100051A TWI412108B TW I412108 B TWI412108 B TW I412108B TW 100100051 A TW100100051 A TW 100100051A TW 100100051 A TW100100051 A TW 100100051A TW I412108 B TWI412108 B TW I412108B
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Abstract
Description
本發明係有關於一種用於積體電路之接合墊結構，特別是有關於一種用於接合墊結構之介層孔圖案。The present invention relates to a bond pad structure for an integrated circuit, and more particularly to a via pattern for a bond pad structure.
在半導體晶片中，接合墊(bond pad)係為積體電路和晶片封裝之間的界面。在晶片元件中，會使用大量的接合墊來傳遞電源/接地信號與輸入/輸出信號。因此，需要足夠的可靠度來確保高良率的接合墊是相當重要的。一般而言，接合墊包括被金屬層間介電層(inter metal dielectric，IMD)所分隔的金屬層以及穿過金屬層間介電層並電性連接至金屬層的金屬介層孔。In a semiconductor wafer, a bond pad is an interface between an integrated circuit and a chip package. In wafer components, a large number of bond pads are used to transfer power/ground signals and input/output signals. Therefore, it is important to have sufficient reliability to ensure a high yield bond pad. In general, the bond pad includes a metal layer separated by an inter-metal dielectric layer (IMD) and a metal via hole that passes through the inter-metal dielectric layer and is electrically connected to the metal layer.
在封裝過程中，當接合線(wire bond)要接合到接合墊時，接合墊會承受到較大的接合力(bonding force)，其容易造成金屬層間介電層產生碎裂。對半導體晶片而言，金屬層間介電層碎裂是很嚴重的失效類型。一旦小裂縫開始沿著金屬層間介電層延伸，接合墊在後續的製程期間中所承受的應力將大幅增長。During the packaging process, when a wire bond is to be bonded to the bonding pad, the bonding pad is subjected to a large bonding force, which is liable to cause chipping of the inter-metal dielectric layer. For semiconductor wafers, metal interlayer dielectric layer fragmentation is a very serious type of failure. Once the small crack begins to extend along the inter-metal dielectric layer, the stress experienced by the bond pad during subsequent processing will increase substantially.
此外，對可減少晶粒面積的接合墊下電路(circuit under pad，CUP)結構而言，打線時接合力所產生的應力不僅會造成頂層金屬層間介電層產生碎裂，更會往下層的金屬層繼續擠壓而造成電路結構中的金屬層產生短路現象，而影響良率。In addition, for a circuit under pad (CUP) structure that can reduce the grain area, the stress generated by the bonding force during wire bonding not only causes the dielectric layer between the top metal layers to be broken, but also goes to the lower layer. The metal layer continues to be squeezed to cause a short circuit in the metal layer in the circuit structure, which affects the yield.
因此，需要一種接合墊結構來分散打線時的接合力，以降低對金屬層間介電層及其下方之電路結構的破壞，進而提高量產良率。Therefore, there is a need for a bond pad structure to disperse the bonding force during wire bonding to reduce damage to the inter-metal interlayer dielectric layer and the circuit structure thereunder, thereby improving mass production yield.
本發明提供一種接合墊結構以及一種積體電路晶片。本發明提供之一種接合墊結構包括：一第一金屬層；一第二金屬層，位於上述第一金屬層上方；一介電層，位於上述第一金屬層以及上述第二金屬層之間；以及一介層孔圖案。上述介層孔圖案設置於上述介電層中且電性連接於上述第一金屬層以及上述第二金屬層，包括至少一第一介層孔組以及與其相鄰的至少一第二介層孔組。上述第一介層孔組具有一H型之輪廓，且上述第二介層孔組也具有一H型之輪廓，其方向異於上述第一介層孔組之上述H型之輪廓。The present invention provides a bond pad structure and an integrated circuit chip. The present invention provides a bonding pad structure comprising: a first metal layer; a second metal layer above the first metal layer; a dielectric layer between the first metal layer and the second metal layer; And a layer of hole pattern. The via pattern is disposed in the dielectric layer and electrically connected to the first metal layer and the second metal layer, and includes at least one first via hole group and at least one second via hole adjacent thereto group. The first via hole group has an H-shaped profile, and the second via hole group also has an H-shaped profile which is different from the H-shaped profile of the first via hole group.
再者，本發明提供一種積體電路晶片。上述積體電路晶片包括：一半導體基底；以及一接合墊結構。上述接合墊結構包括：一第一金屬層，位於上述半導體基底上方；一第二金屬層，位於上述第一金屬層上方；一介電層，位於上述第一金屬層以及上述第二金屬層之間；以及一介層孔圖案。上述介層孔圖案設置於上述介電層中且電性連接於上述第一金屬層以及上述第二金屬層，包括依一矩陣陣列排列之複數第一介層孔組以及複數第二介層孔組。上述第一介層孔組具有一H型之輪廓，且上述H型之輪廓具有一中心點。上述第二介層孔組具有相同於上述第一介層孔組並以上述中心點旋轉一特定角度之輪廓。Furthermore, the present invention provides an integrated circuit chip. The integrated circuit chip includes: a semiconductor substrate; and a bond pad structure. The bonding pad structure includes: a first metal layer over the semiconductor substrate; a second metal layer over the first metal layer; and a dielectric layer located in the first metal layer and the second metal layer And a layer of hole pattern. The via hole pattern is disposed in the dielectric layer and electrically connected to the first metal layer and the second metal layer, and includes a plurality of first via hole groups and a plurality of second via holes arranged in a matrix array group. The first via hole group has an H-shaped profile, and the H-shaped profile has a center point. The second via hole group has the same contour as the first interlayer hole group and is rotated by a specific angle with the center point.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;
實施例：Example:
第1圖係顯示根據本發明一實施例所述之頂部介層孔圖案100之平面示意圖，而第2圖係顯示沿第1圖中A-A線之具有頂部介層孔圖案之接合墊結構200之剖面示意圖。同時參考第1圖及第2圖，接合墊結構200包括積體電路基底10、金屬層20、金屬層間介電層30與金屬層40。在一實施例中，積體電路基底10為一半導體積體電路製程之半導體基底。此外，在另一實施例中，積體電路基底10可包括半導體基底14以及積體電路12(即接合墊下電路CUP)，其中積體電路12的功能係對應於接合墊結構200並可設置於積體電路基底10的內部及/或表面。舉例來說，積體電路12可以係接合墊結構200的靜電放電(Electrostatic Discharge，ESD)防護電路。此外，金屬層間介電層30位於積體電路基底10的上方，並設置於金屬層20與金屬層40之間，其中金屬層間介電層30中的複數介層孔會形成第1圖的介層孔圖案100。此外，介層孔圖案100內的介層孔會電性連接於金屬層20與金屬層40。1 is a plan view showing a top via hole pattern 100 according to an embodiment of the present invention, and FIG. 2 is a view showing a bond pad structure 200 having a top via pattern along the AA line in FIG. Schematic diagram of the section. Referring also to FIGS. 1 and 2, the bond pad structure 200 includes an integrated circuit substrate 10, a metal layer 20, an inter-metal dielectric layer 30, and a metal layer 40. In one embodiment, the integrated circuit substrate 10 is a semiconductor substrate of a semiconductor integrated circuit process. In addition, in another embodiment, the integrated circuit substrate 10 may include a semiconductor substrate 14 and an integrated circuit 12 (ie, a bond pad circuit CUP), wherein the function of the integrated circuit 12 corresponds to the bond pad structure 200 and may be set The inside and/or the surface of the integrated circuit substrate 10. For example, the integrated circuit 12 can be coupled to an Electrostatic Discharge (ESD) protection circuit of the pad structure 200. In addition, the inter-metal dielectric layer 30 is disposed above the integrated circuit substrate 10 and disposed between the metal layer 20 and the metal layer 40, wherein the plurality of via holes in the inter-metal dielectric layer 30 form the interface of FIG. Layer hole pattern 100. In addition, the via holes in the via pattern 100 are electrically connected to the metal layer 20 and the metal layer 40.
在第1圖中，介層孔圖案100包括由複數第一介層孔組110以及複數第二介層孔組120所形成之矩陣陣列。在矩陣陣列中，第一介層孔組110以及第二介層孔組120為交互排列。第一介層孔組110包括複數個彼此隔開的介層孔130，其排列成一H型之輪廓，並具有中心點C。相似地，第二介層孔組120亦包括排列成H型之輪廓的複數個介層孔130。然而，值得注意的是，相較於第一介層孔組110，第二介層孔組120的H型輪廓係根據中心點C旋轉了90度。換言之，第一介層孔組110與第二介層孔組120之H型輪廓的開口方向互為正交。如第1圖所顯示，介層孔圖案100具有足夠的介層孔數量可支撐打線時的接合力。此外，介層孔圖案100中兩相鄰的介層孔組之間具有足夠的空間可減少接合力往下層擠壓，並可避免兩鄰近的介層孔組之間存在一直線狀開放的路徑，因此可增加金屬層間介電層的韌性和抑制碎裂於金屬層間介電層中傳遞的可能性，進而改善可靠度、接合度及良率。In FIG. 1, the via pattern 100 includes a matrix array formed by a plurality of first via groups 110 and a plurality of second via groups 120. In the matrix array, the first via hole group 110 and the second via hole group 120 are alternately arranged. The first via hole group 110 includes a plurality of via holes 130 spaced apart from each other, arranged in an H-shaped profile, and having a center point C. Similarly, the second via set 120 also includes a plurality of vias 130 arranged in an H-shaped profile. However, it is worth noting that the H-profile of the second via set 120 is rotated 90 degrees from the center point C compared to the first via set 110. In other words, the opening directions of the H-shaped profiles of the first via hole group 110 and the second via hole group 120 are orthogonal to each other. As shown in Fig. 1, the via pattern 100 has a sufficient number of via holes to support the bonding force when wiring. In addition, there is sufficient space between two adjacent via hole groups in the via hole pattern 100 to reduce the bonding force to the lower layer, and to avoid a linear open path between the two adjacent via hole groups. Therefore, the toughness of the dielectric layer between the metal layers can be increased and the possibility of chipping in the dielectric layer between the metal layers can be suppressed, thereby improving the reliability, the bonding degree and the yield.
第3圖係顯示根據本發明另一實施例所述之頂部介層孔圖案300之平面示意圖。相似地，介層孔圖案300包括由複數第一介層孔組310以及複數第二介層孔組320所形成之矩陣陣列。然而，相較於第1圖的第一介層孔組110以及第二介層孔組120，第一介層孔組310以及第二介層孔組320各包括三個彼此隔開的線型介層孔，其亦排列成H型之輪廓。如先前所描述，第一介層孔組310與第二介層孔組320之H型輪廓的開口方向互為正交。3 is a plan view showing a top via hole pattern 300 according to another embodiment of the present invention. Similarly, the via pattern 300 includes a matrix array formed by a plurality of first via groups 310 and a plurality of second via groups 320. However, compared to the first via hole group 110 and the second via hole group 120 of FIG. 1, the first via hole group 310 and the second via hole group 320 each include three line types separated from each other. Layer holes, which are also arranged in an H-shaped profile. As previously described, the opening directions of the H-shaped profiles of the first via hole set 310 and the second via hole set 320 are orthogonal to each other.
第4圖係顯示根據本發明另一實施例所述之頂部介層孔圖案400之平面示意圖。相似地，介層孔圖案400包括由複數第一介層孔組410以及複數第二介層孔組420所形成之矩陣陣列。然而，相較於第1圖的第一介層孔組110以及第二介層孔組120，第一介層孔組410以及第二介層孔組420分別係由一個H型介層孔所形成。如先前所描述，第一介層孔組410與第二介層孔組420之H型介層孔的開口方向互為正交。4 is a plan view showing a top via hole pattern 400 according to another embodiment of the present invention. Similarly, the via pattern 400 includes a matrix array formed by a plurality of first via groups 410 and a plurality of second via groups 420. However, compared to the first via hole group 110 and the second via hole group 120 of FIG. 1, the first via hole group 410 and the second via hole group 420 are respectively formed by an H-type via hole. form. As previously described, the opening directions of the H-type via holes of the first via hole group 410 and the second via hole group 420 are orthogonal to each other.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10．．．積體電路基底10. . . Integrated circuit substrate
14．．．半導體基底14. . . Semiconductor substrate
12．．．積體電路12. . . Integrated circuit
100、300、400．．．介層孔圖案100, 300, 400. . . Interlayer hole pattern
110、310、410．．．第一介層孔組110, 310, 410. . . First layer hole group
120、320、420．．．第二介層孔組120, 320, 420. . . Second layer hole group
130．．．介層孔130. . . Interlayer hole
20、40．．．金屬層20, 40. . . Metal layer
200．．．接合墊結構200. . . Mat structure
以及as well as
30．．．金屬層間介電層30. . . Metal interlayer dielectric layer
第1圖係顯示根據本發明一實施例所述之頂部介層孔圖案之平面示意圖；1 is a schematic plan view showing a top via hole pattern according to an embodiment of the invention;
第2圖係顯示沿第1圖中A-A線之具有頂部介層孔圖案之接合墊結構之剖面示意圖；Figure 2 is a schematic cross-sectional view showing the structure of the bonding pad having the pattern of the top via holes along the line A-A in Figure 1;
第3圖係顯示根據本發明另一實施例所述之頂部介層孔圖案之平面示意圖；以及3 is a plan view showing a top via hole pattern according to another embodiment of the present invention;
第4圖係顯示根據本發明另一實施例所述之頂部介層孔圖案之平面示意圖。Figure 4 is a plan view showing the pattern of the top via holes according to another embodiment of the present invention.
100．．．介層孔圖案100. . . Interlayer hole pattern
110．．．第一介層孔組110. . . First layer hole group
120．．．第二介層孔組120. . . Second layer hole group
以及as well as
130．．．介層孔130. . . Interlayer hole
Claims (14)
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| TW100100051A TWI412108B (en) | 2011-01-03 | 2011-01-03 | Bond pad structure and integrated circuit chip |
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| TW100100051A TWI412108B (en) | 2011-01-03 | 2011-01-03 | Bond pad structure and integrated circuit chip |
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| TW201230267A TW201230267A (en) | 2012-07-16 |
| TWI412108B true TWI412108B (en) | 2013-10-11 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247803A (en) * | 1997-03-05 | 1998-09-14 | Murata Mfg Co Ltd | Passive element |
| US20010009802A1 (en) * | 1997-06-24 | 2001-07-26 | Lee Hyae-Ryoung | Method of forming integrated bonding pads including closed vias and closed conductive patterns |
| TW200634961A (en) * | 2005-03-17 | 2006-10-01 | Taiwan Semiconductor Mfg Co Ltd | Bond pad structure amd method for forming the same |
| TW200802753A (en) * | 2006-06-19 | 2008-01-01 | Taiwan Semiconductor Mfg | Structure and bond pad structure |
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2011
- 2011-01-03 TW TW100100051A patent/TWI412108B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247803A (en) * | 1997-03-05 | 1998-09-14 | Murata Mfg Co Ltd | Passive element |
| US20010009802A1 (en) * | 1997-06-24 | 2001-07-26 | Lee Hyae-Ryoung | Method of forming integrated bonding pads including closed vias and closed conductive patterns |
| TW200634961A (en) * | 2005-03-17 | 2006-10-01 | Taiwan Semiconductor Mfg Co Ltd | Bond pad structure amd method for forming the same |
| TW200802753A (en) * | 2006-06-19 | 2008-01-01 | Taiwan Semiconductor Mfg | Structure and bond pad structure |
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