TWI411111B - Thin-film transistor structure and manufacturing method of the same - Google Patents
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本發明係關於一薄膜電晶體結構及其製作方法,特別是關於一種可降低汲極端電場之薄膜電晶體結構及其製作方法。The present invention relates to a thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure capable of reducing a 汲 extreme electric field and a method of fabricating the same.
近年來,多晶矽薄膜電晶體由於比非晶矽薄膜電晶體有較高的載子移動率,因此應用在主動式液晶顯示器和電路整合在玻璃基板上面,可提供良好之效能,而已被應用在液晶顯示器、手機面板、薄膜太陽能電池、三維積體電路,當成畫素的開關元件。然而,由於汲極端的高電場會導致強大的漏電流與扭結效應(kink effect)使元件產生不穩定性,因此阻礙了多晶矽薄膜電晶體在高效能電路上的應用。漏電流主要的機制是汲極端空乏區的強大電場誘使載子經由晶粒邊界的缺陷而形成漏電流。因此,為了減少強大的漏電流,如何降低汲極端的高電場乃係亟欲克服之技術瓶頸。In recent years, polycrystalline germanium thin film transistors have higher carrier mobility than amorphous germanium thin film transistors, so they are applied to liquid crystal displays and circuits integrated on glass substrates to provide good performance, and have been applied to liquid crystals. Display, mobile phone panel, thin film solar cell, three-dimensional integrated circuit, as a switching element of pixels. However, due to the extremely high electric field of the crucible, strong leakage current and kink effect cause instability of the element, thus hindering the application of the polycrystalline silicon transistor to the high-performance circuit. The main mechanism of leakage current is that the strong electric field in the extremely depleted region induces the carrier to form a leakage current through defects in the grain boundary. Therefore, in order to reduce the strong leakage current, how to reduce the high electric field of the 汲 extreme is a technical bottleneck that is to be overcome.
在目前的研究中,已經有學者提出改善的方法,如偏移(offset)、輕摻雜汲極(Lightly doped drain;LDD)(例如美國專利US 6,468,839揭露LDD薄膜電晶體結構)、閘極覆蓋輕摻雜汲極(Gate overlapped lightly doped drain;GOLDD)等結構,都是用來減輕汲極端的高電場,不過由於其中有的方法需要額外的離子佈植(ion-implantation)條件,而且摻雜的能量藥劑都不好控制,而有其侷限。另外一些方法則需 要額外的光罩,因此會增加整體的花費。In the current research, some scholars have proposed methods for improvement, such as offset, Lightly doped drain (LDD) (for example, US Patent No. 6,468,839 discloses LDD thin film transistor structure), gate coverage Structures such as light overlapped lightly doped drain (GOLDD) are used to alleviate the high electric field of the 汲 extreme, but some methods require additional ion-implantation conditions and doping. The energy agents are not well controlled, but have their limitations. Other methods need Additional masks are required, thus increasing overall cost.
近年來,也有相關研究提出厚源汲極(Raised Source/Drain;RSD)之薄膜電晶體結構來降低汲極端高電場,例如:In recent years, related research has also proposed a thin film transistor structure of Raised Source/Drain (RSD) to reduce the extremely high electric field of germanium, for example:
Kow Ming Chang等人於2007年提出論文"A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process"(IEEE ELECTRON DEVICE LETTERS,VOL.28,NO.9,SEPTEMBER 2007)中揭露一種厚源汲極架構10,如圖1A所示。厚源汲極架構10包含載板11、源極12、汲極13、通道區14、閘極介電層15及閘極層16。該載板11可為氧化層,通道區14則由多晶矽組成。形成該厚源汲極架構10需進行化學機械研磨(chemical mechanical polishing;CMP)及離子佈植等製程。Kow Ming Chang et al. presented the paper "A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process" (IEEE ELECTRON DEVICE LETTERS, VOL.28, NO. 9, SEPTEMBER 2007) discloses a thick source drain structure 10, as shown in Figure 1A. The thick source drain structure 10 includes a carrier 11, a source 12, a drain 13, a channel region 14, a gate dielectric layer 15, and a gate layer 16. The carrier 11 can be an oxide layer and the channel region 14 is composed of polysilicon. The formation of the thick source drain structure 10 requires chemical mechanical polishing (CMP) and ion implantation.
II-Suk Kang等人於2008年提出論文"Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain"(IEEE ELECTRON DEVICE LETTERS,VOL.29,NO.3,MARCH 2008)中揭露一種下部閘極之厚源汲極架構20,厚源汲極架構20包含載板21、源極22、汲極23、氮化矽層24、閘極介電層25、通道區26及閘極層27。該載板21係玻璃,通道區26則由多晶矽組成。本論文之閘極層27係直接設置於載板21上,而與一般傳統結構略有不同。形成該厚源汲極架構20需進行背向曝光(back surface exposure)及離子佈植(ion-implanting)製程 ,整體製程較為複雜。II-Suk Kang et al., 2008, presented "Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain" (IEEE ELECTRON DEVICE LETTERS, VOL.29, NO.3, MARCH In 2008), a thick gate drain structure 20 of a lower gate is disclosed. The thick source drain structure 20 includes a carrier 21, a source 22, a drain 23, a tantalum nitride layer 24, a gate dielectric layer 25, and a channel region. 26 and gate layer 27. The carrier 21 is glass and the channel region 26 is composed of polycrystalline germanium. The gate layer 27 of this paper is directly disposed on the carrier 21, which is slightly different from the conventional structure. Forming the thick source drain structure 20 requires back surface exposure and ion-implanting processes. The overall process is more complicated.
縱然目前學界或業界已提出厚源汲極架構以解決漏電流的問題,然而該等技術製作厚源汲極結構時需要化學機械研磨技術或者額外的離子佈植,因此製程較複雜且有增加整體花費的疑慮。Even though academics or the industry have proposed thick-source bungee architectures to solve the problem of leakage current, these technologies require chemical mechanical polishing or additional ion implantation when making thick-source bungee structures, so the process is complicated and increases overall. The doubts spent.
本發明提出一種下部閘極薄膜電晶體結構,伴隨著一簡單的半導體邊襯製程。經由模擬結果顯示,有半導體邊襯之下部閘極薄膜電晶體結構比起沒有半導體邊襯者,可有效降低汲極端的電場。再者,擁有半導體邊襯的結構可以有效地改善衝擊解離,因此扭結效應得以改善。半導體邊襯提供了一個有效的方式來擴開汲極端的高電場,藉此改善元件的電性,而且由於形成的半導體邊襯在通道內,所以導通電流不會因此而下降太多。The present invention provides a lower gate thin film transistor structure with a simple semiconductor edge liner process. The simulation results show that the gate thin film transistor structure under the semiconductor edge liner can effectively reduce the electric field of the 汲 extreme than the semiconductor lining. Furthermore, the structure with the semiconductor backing can effectively improve the impact dissociation, so the kink effect is improved. The semiconductor lining provides an effective way to expand the high electric field of the 汲 extreme, thereby improving the electrical properties of the component, and since the formed semiconductor lining is in the channel, the conduction current does not drop too much.
根據本發明之一實施例之一種薄膜電晶體結構,其包含一載板、一閘極層、一閘極介電層、一第一半導體層、一第二半導體層以及二半導體邊襯。閘極層係形成於該載板表面。閘極介電層係覆蓋該載板及該閘極層。第一半導體層形成於該閘極介電層表面,且包含一通道區。第二半導體層形成於該第一半導體層之上,包含一源極區域及一汲極區域,該源極區域及該汲極區域間形成一凹部,該凹部鄰接該源極區域及汲極區域處形成二內側壁。二半導體邊襯分別鄰接該二內側壁及該通道區表面。A thin film transistor structure according to an embodiment of the invention includes a carrier, a gate layer, a gate dielectric layer, a first semiconductor layer, a second semiconductor layer, and two semiconductor edge liners. A gate layer is formed on the surface of the carrier. A gate dielectric layer covers the carrier and the gate layer. A first semiconductor layer is formed on the surface of the gate dielectric layer and includes a channel region. a second semiconductor layer is formed on the first semiconductor layer, and includes a source region and a drain region. A recess is formed between the source region and the drain region, and the recess is adjacent to the source region and the drain region. Two inner side walls are formed. Two semiconductor backings respectively adjoin the two inner sidewalls and the surface of the channel region.
根據本發明之一實施例之一種薄膜電晶體結構之製作方 法,包含以下步驟:提供一載板;形成一閘極層於該載板上方;形成一閘極介電層於該閘極層及載板上方;形成一第一半導體層於該閘極介電層上方,其中該第一半導體層包含一通道區;形成一第二半導體層於該第一半導體層上方;蝕刻該第二半導體層形成一凹部以暴露出該通道區,凹部兩側之第二半導體層分別為源極區域及汲極區域,且凹部鄰接該源極區域及汲極區域處形成二內側壁;以及形成二半導體邊襯,分別鄰接該二內側壁及該通道區表面。A method for fabricating a thin film transistor structure according to an embodiment of the present invention The method includes the steps of: providing a carrier; forming a gate layer over the carrier; forming a gate dielectric layer over the gate layer and the carrier; forming a first semiconductor layer on the gate Above the electrical layer, wherein the first semiconductor layer comprises a channel region; forming a second semiconductor layer over the first semiconductor layer; etching the second semiconductor layer to form a recess to expose the channel region, the two sides of the recess The two semiconductor layers are respectively a source region and a drain region, and the recesses form two inner sidewalls adjacent to the source region and the drain region; and two semiconductor edge liners are formed adjacent to the two inner sidewalls and the surface of the channel region.
以下詳細討論本發明於目前較佳實施例的製作和使用。不過應當理解,本發明提供許多可應用的發明概念,其可在各種各樣的具體情況下實施。該討論的具體實施例僅說明了製作和使用該發明的具體方式,並沒有限制本發明的範圍。The making and using of the present invention in the presently preferred embodiments are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts which can be embodied in various specific embodiments. The specific embodiments of the present invention are merely illustrative of specific ways of making and using the invention and are not intended to limit the scope of the invention.
為降低汲極端的高電場,本發明提出一個具有半導體邊襯之薄膜電晶體,而且不需使用額外的離子佈植或化學機械研磨步驟。與傳統型結構比較之下,本發明之薄膜電晶體降低了汲極端的高電場,並且改善了扭結效應,及降低漏電流。In order to reduce the high electric field of the crucible extreme, the present invention proposes a thin film transistor with a semiconductor backing without the need for additional ion implantation or chemical mechanical polishing steps. Compared with the conventional structure, the thin film transistor of the present invention lowers the high electric field of the 汲 extreme, and improves the kinking effect and reduces the leakage current.
圖2A至圖2G繪示本發明一實施例之薄膜電晶體結構之製作方法。參照圖2A,提供一基板31,其可為矽基板,並在基板31上面形成一載板32。載板32可為氧化矽層,例如緩衝氧化層(buffer oxide),以模擬薄膜電晶體用之玻璃基板。一實施例中,利用水平爐管於1050℃形成厚度約4000 至5000埃之緩衝氧化層作為後續製作薄膜電晶體之載板32。2A to 2G illustrate a method of fabricating a thin film transistor structure according to an embodiment of the present invention. Referring to FIG. 2A, a substrate 31 is provided which may be a germanium substrate and a carrier 32 is formed on the substrate 31. The carrier 32 may be a ruthenium oxide layer, such as a buffer oxide, to simulate a glass substrate for a thin film transistor. In one embodiment, the thickness is about 4000 at 1050 ° C using a horizontal furnace tube. A buffer oxide layer of up to 5000 angstroms is used as a carrier plate 32 for subsequently forming a thin film transistor.
參照圖2B,接著形成閘極層33於載板32上方。一實施例中,閘極層33係利用垂直爐管現地(in-situ)沉積摻雜多晶矽層,且以微影蝕刻技術定義出閘極層33。所謂in-situ摻雜多晶矽技術係於例如利用化學氣相沉積(CVD)形成多晶矽層的同時,加入摻雜氣體例如磷化氫(phosphine)或硼化氫(diborane)。藉此直接沉積摻雜多晶矽層(doped polysilicon),而無需額外之摻雜或植入之製程。Referring to FIG. 2B, a gate layer 33 is then formed over the carrier 32. In one embodiment, the gate layer 33 is in-situ deposited with a doped polysilicon layer using a vertical furnace tube and the gate layer 33 is defined by photolithographic etching techniques. The so-called in-situ doped polysilicon technique is based on, for example, the formation of a polycrystalline germanium layer by chemical vapor deposition (CVD), with the addition of a dopant gas such as phosphine or diborane. Thereby, doped polysilicon is deposited directly without additional doping or implantation processes.
參照圖2C,依序沉積閘極介電層34於閘極層33及載板32上方,以及形成第一半導體層35於閘極層介電層34上方。一實施例中,利用水平爐管沉積四乙氧基矽烷(Tetraethoxysilane;TEOS)氧化物層作為閘極介電層34。且沉積非晶矽層(amorphous silicon)並以600℃進行24小時之固態氣相結晶(或稱回火),以形成多晶矽作為第一半導體層35。其中閘極介電層34及第一半導體層35覆蓋該閘極層33之部分順應閘極層33之形狀而成凸出結構52。位於凸出結構52上之第一半導體層35包含通道區36。Referring to FIG. 2C, a gate dielectric layer 34 is sequentially deposited over the gate layer 33 and the carrier 32, and a first semiconductor layer 35 is formed over the gate dielectric layer 34. In one embodiment, a layer of tetraethoxy silane (TEOS) oxide is deposited as a gate dielectric layer 34 using a horizontal furnace tube. And an amorphous silicon layer was deposited and solid-state vapor phase crystallization (or tempering) was performed at 600 ° C for 24 hours to form polycrystalline germanium as the first semiconductor layer 35. The gate dielectric layer 34 and the portion of the first semiconductor layer 35 covering the gate layer 33 conform to the shape of the gate layer 33 to form a protruding structure 52. The first semiconductor layer 35 on the protruding structure 52 includes a channel region 36.
參照圖2D,形成第二半導體層37於第一半導體層35上方。一實施例中,利用垂直爐管in-situ沉積摻雜多晶矽層,作為第二半導體層37。Referring to FIG. 2D, a second semiconductor layer 37 is formed over the first semiconductor layer 35. In one embodiment, a doped polysilicon layer is deposited as a second semiconductor layer 37 using a vertical furnace tube in-situ.
參照圖2E,利用微影及蝕刻技術,例如乾蝕刻閘極層33上方之第二半導體層37,形成一凹部38,藉此暴露出該通道區36。凹部38兩側之第二半導體層37分別定義為源極區 域41及汲極區域43。凹部38鄰接該源極區域42及汲極區域43處形成二內側壁39。Referring to FIG. 2E, a recess 38 is formed by lithography and etching techniques, such as dry etching the second semiconductor layer 37 over the gate layer 33, thereby exposing the channel region 36. The second semiconductor layer 37 on both sides of the recess 38 is defined as a source region Field 41 and drain region 43. The recess 38 forms two inner side walls 39 adjacent to the source region 42 and the drain region 43.
參照圖2F,沉積第三半導體層40於第二半導體層37及通道區36上方。一實施例中,第三半導體層40係以水平爐管沉積之多晶矽層。Referring to FIG. 2F, a third semiconductor layer 40 is deposited over the second semiconductor layer 37 and the channel region 36. In one embodiment, the third semiconductor layer 40 is a polysilicon layer deposited in a horizontal furnace tube.
參照圖2G,蝕刻第三半導體層40,於凹部38內之該第三半導體層40係形成二半導體邊襯41。蝕刻第三半導體層40可利用乾蝕刻之非等向性蝕刻,完全去除位於第二半導體層37上之第三半導體層40。因為凹部38中央部份之第三半導體層40較薄,因此蝕刻後將完全去除而暴露出通道區36。鄰接開口38內二內側壁39之第三半導體層40較厚,因此蝕刻後即形成半導體邊襯41。二側之半導體邊襯41之間形成一開口50,其暴露出通道區36。本實施例中,半導體邊襯41之材料係多晶矽。此外,介電常數大於等於3.9之高介電常數材料如氧化矽、氮化矽或氧化鉿亦可使用作為半導體邊襯41之材料。Referring to FIG. 2G, the third semiconductor layer 40 is etched, and the third semiconductor layer 40 in the recess 38 forms two semiconductor backings 41. Etching the third semiconductor layer 40 may completely remove the third semiconductor layer 40 on the second semiconductor layer 37 by dry etching anisotropic etching. Since the third semiconductor layer 40 in the central portion of the recess 38 is thin, it will be completely removed after etching to expose the channel region 36. The third semiconductor layer 40 adjacent the two inner sidewalls 39 in the opening 38 is thicker, so that the semiconductor backing 41 is formed after etching. An opening 50 is formed between the semiconductor backings 41 on the two sides which exposes the channel region 36. In this embodiment, the material of the semiconductor backing 41 is polysilicon. Further, a high dielectric constant material having a dielectric constant of 3.9 or more, such as hafnium oxide, tantalum nitride or hafnium oxide, can also be used as the material of the semiconductor backing 41.
至此,即形成本發明一實施例之薄膜電晶體結構30,就結構關係而言,薄膜電晶體結構30包含載板32、閘極層33、閘極介電層34、第一半導體層35、第二半導體層37及二半導體邊襯41。閘極層33形成於載板32表面。閘極介電層34覆蓋該載板32及閘極層33。第一半導體層35形成於閘極介電層34表面,且包含一通道區36。第二半導體層37形成於第一半導體層35之表面,包含源極區域42及汲極區域43,該源極區域42及該汲極區域43間形成一凹部38,凹部38 鄰接源極區域41及汲極區域43處形成二內側壁39。二半導體邊襯41分別鄰接該二內側壁39及該通道區36表面,二半導體邊襯41之間形成一暴露出該通道區36之開口50。Thus, the thin film transistor structure 30 of the embodiment of the present invention is formed. In terms of structural relationship, the thin film transistor structure 30 includes a carrier 32, a gate layer 33, a gate dielectric layer 34, a first semiconductor layer 35, The second semiconductor layer 37 and the two semiconductor backings 41. The gate layer 33 is formed on the surface of the carrier 32. The gate dielectric layer 34 covers the carrier 32 and the gate layer 33. The first semiconductor layer 35 is formed on the surface of the gate dielectric layer 34 and includes a channel region 36. The second semiconductor layer 37 is formed on the surface of the first semiconductor layer 35, and includes a source region 42 and a drain region 43. A recess 38 is formed between the source region 42 and the drain region 43. The recess 38 is formed. Two inner side walls 39 are formed adjacent to the source region 41 and the drain region 43. Two semiconductor backings 41 respectively adjoin the two inner sidewalls 39 and the surface of the channel region 36. An opening 50 is formed between the two semiconductor edge liners 41 to expose the channel region 36.
特而言之,該半導體邊襯41包含第一連接面61及第二連接面62,其中第一連接面61鄰接該源極區域42或汲極區域43之一端部;第二連接面62鄰接該通道區36之至少一部分。In particular, the semiconductor backing 41 includes a first connecting surface 61 and a second connecting surface 62, wherein the first connecting surface 61 abuts one end of the source region 42 or the drain region 43; the second connecting surface 62 is adjacent At least a portion of the channel region 36.
一實施例中,除了採用摻雜多晶矽外,閘極層33亦可使用碳化矽或矽化鍺。In one embodiment, in addition to the doped polysilicon, the gate layer 33 may also use tantalum carbide or tantalum.
在本發明中,採用in-situ摻雜的方法來形成汲極區域43和源極區域42,此法較離子佈植成本較低,相似於非晶矽薄膜電晶體的製程。且利用源極區域42及汲極區域43與通道36形成的高度落差,對此來製作多晶矽邊襯41的結構,讓通道區36在靠近汲極區域43的區域變厚,對電子流有一個緩衝紓解的效果,就像增加一個阻值較高的offset區,故可降低汲極端的高電場。In the present invention, the in-situ doping method is used to form the drain region 43 and the source region 42, which is less expensive than the ion implantation and is similar to the process of the amorphous germanium thin film transistor. And by using the height difference formed by the source region 42 and the drain region 43 and the channel 36, the structure of the polysilicon lining 41 is made, and the channel region 36 is thickened in the region near the drain region 43, and there is a flow of electrons. The effect of buffering mitigation is like adding an offset region with a higher resistance value, thus reducing the high electric field of the 汲 extreme.
一般的offset結構、LDD結構或GOLDD結構,都需要增加額外的光罩,而本發明在源極和汲極被定義出來後,僅僅使用沉積再蝕刻的製程製作出多晶矽邊襯,不需要額外的光罩或複雜的製程就可以降低了汲極端的高電場,而且對於多晶矽的不理想效應,如漏電流及扭結效應,可獲得有效改善。A general offset structure, an LDD structure, or a GOLDD structure requires an additional mask. However, after the source and drain electrodes are defined, the process of depositing and etching is used to fabricate the polysilicon liner, without requiring additional A mask or a complicated process can reduce the high electric field of the crucible, and the effect of the undesirable effects of polysilicon, such as leakage current and kink effect, can be effectively improved.
在扭結效應方面,由模擬衝擊解離圖可以發現擁有半導體邊襯之薄膜電晶體結構,較沒有半導體邊襯者,有明顯 的削弱減少。按載子的碰撞,也就是衝擊解離,是影響扭結效應的主要因素之一,載子由通道區在靠近汲極區域時,受到空乏區的高電場影響,加速碰撞而解離,而擁有半導體邊襯的薄膜電晶體結構明顯地降低電場,因此改善了衝擊解離的現象,也就改善了扭結效應。In terms of the kink effect, a thin film transistor structure with a semiconductor edge liner can be found from the simulated impact dissociation pattern, which is more obvious than the semiconductor edge liner. The weakening is reduced. Collision by carrier, that is, impact dissociation, is one of the main factors affecting the kink effect. When the channel is near the bungee region, the carrier is affected by the high electric field in the depletion zone, accelerates the collision and dissociates, and has the semiconductor edge. The lining of the thin film transistor structure significantly reduces the electric field, thus improving the phenomenon of impact dissociation and improving the kink effect.
對導通電流方面,由於形成半導體邊襯的區域是在通道區內,不會因為電阻值太高而造成導通電流下降,一般offset結構或是LDD結構,其降低了汲極端的高電場,但也讓導通電流下降許多,因為它們的電阻值較高了而影響開啟(turn on)電流。因此,半導體邊襯降低了汲極端的高電場,改善了漏電流,但不會犧牲了導通電流。In terms of on-current, since the region where the semiconductor lining is formed is in the channel region, the on-current is not lowered due to the resistance value being too high, and the general offset structure or the LDD structure reduces the high electric field of the 汲 extreme, but also Let the on currents drop a lot because their resistance values are higher and affect the turn on current. Therefore, the semiconductor lining reduces the high electric field of the 汲 extreme and improves the leakage current without sacrificing the on current.
圖3顯示薄膜電晶體結構之與源極之距離和電場間之關係,其中模擬不具半導體邊襯及不同厚度(寬度)的半導體邊襯大小對元件電性的影響,顯然地,沒有半導體邊襯的薄膜電晶體結構之電場峰值最大,即其電性結果最差。相對地,擁有較厚(200nm)的半導體邊襯,其電場峰值較小,即其有較好的對抗扭結效應。這是因為較厚的半導體邊襯在通道靠近汲極端有更大的阻值,對於電場及衝擊解離方面都有更顯著的改善。Figure 3 shows the relationship between the distance from the source and the electric field of the thin-film transistor structure, in which the influence of the size of the semiconductor backing without semiconductor backing and different thickness (width) on the electrical properties of the device is simulated. Obviously, there is no semiconductor edge. The thin film transistor structure has the largest electric field peak, that is, its electrical result is the worst. In contrast, having a thicker (200 nm) semiconductor lining has a smaller electric field peak, that is, it has a better anti-kink effect. This is because thicker semiconductor linings have greater resistance at the channel near the 汲 extreme and have a significant improvement in both electric field and shock dissociation.
圖4顯示薄膜電晶體結構之汲極-源極電壓Vds與汲極-源極電流Ids間之關係,其中模擬不具半導體邊襯及不同厚度(寬度)的半導體邊襯大小對元件電性的影響。由圖4可知,當Vds大於約7V時,不具半導體邊襯之薄膜電晶體結構較具有半導體邊襯者,其Ids明顯快速升高。亦即不具半導體 邊襯之薄膜電晶體結構具有較大之漏電流。此外,半導體邊襯厚度為100nm者較半導體邊襯厚度為200nm者,其Ids亦較高。因此,具較厚之半導體邊襯之薄膜電晶體結構可進一步減少漏電流。4 shows the relationship between the drain-source voltage Vds of the thin film transistor structure and the drain-source current Ids, in which the influence of the size of the semiconductor edge liner without semiconductor edge liner and different thickness (width) on the electrical properties of the device is simulated. . As can be seen from FIG. 4, when the Vds is greater than about 7 V, the thin film transistor structure without the semiconductor edge liner has a semiconductor edge lining, and the Ids is significantly increased rapidly. That is, without semiconductor The edge-lined thin film transistor structure has a large leakage current. In addition, the thickness of the semiconductor lining of 100 nm is higher than that of the semiconductor lining of 200 nm. Therefore, a thin film transistor structure with a thick semiconductor edge can further reduce leakage current.
綜上,本發明之具有半導體邊襯之薄膜電晶體結構具有以下特點:(1)降低汲極端高電場的現象:本發明在汲極端有多晶矽邊襯的結構,藉此擴散強烈的電場,而得以降低汲極端高電場。(2)降低漏電流:本發明藉由多晶矽邊襯的結構,提升了汲極端通道的阻值,降低高電場,因此也改善了漏電流問題。(3)改善扭結效應(kink effect):本發明藉由多晶矽邊襯的結構,降低了汲極端的高電場,也讓衝擊解離的現象獲得舒緩,因而改善了扭結效應。(4)導通電流的維持:由於多晶矽邊襯所形成的高阻值區是在通道內,故此構造將不會對導通電流有太大的影響,因此導通電流得以維持。In summary, the thin film transistor structure with semiconductor edge liner of the present invention has the following characteristics: (1) the phenomenon of reducing the extremely high electric field of the germanium: the present invention has a polycrystalline germanium edged structure at the end of the crucible, thereby diffusing a strong electric field, and It is possible to reduce the extremely high electric field. (2) Reducing leakage current: The present invention improves the leakage current by the structure of the polysilicon crucible lining, which improves the resistance of the crucible extreme channel and lowers the high electric field. (3) Improving the kink effect: The present invention reduces the high electric field of the 汲 extreme by the structure of the polycrystalline lining, and also relieves the phenomenon of impact dissociation, thereby improving the kinking effect. (4) Maintaining the on-current: Since the high-resistance region formed by the polysilicon lining is in the channel, the structure will not have a large influence on the on-current, and thus the on-current is maintained.
另外,本發明的製程簡單,不需要額外的光罩製程,僅利用沉積再蝕刻來製作半導體邊襯,即可降低汲極端的電場,而且不增加額外的通道串聯電阻,維持住導通電流。In addition, the process of the invention is simple, no additional mask process is required, and only the deposition and re-etching is used to fabricate the semiconductor lining, thereby reducing the electric field of the 汲 extreme, and maintaining the conduction current without adding additional series series resistance.
發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。The technical content and technical features of the invention have been disclosed as above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims
10‧‧‧厚源汲極架構10‧‧‧Thick source bungee architecture
11‧‧‧載板11‧‧‧ Carrier Board
12‧‧‧源極12‧‧‧ source
13‧‧‧汲極13‧‧‧汲polar
14‧‧‧通道區14‧‧‧Channel area
15‧‧‧閘極介電層15‧‧‧ gate dielectric layer
16‧‧‧閘極層16‧‧ ‧ gate layer
20‧‧‧厚源汲極架構20‧‧‧ Thick source bungee architecture
21‧‧‧載板21‧‧‧ Carrier Board
22‧‧‧源極22‧‧‧ source
23‧‧‧汲極23‧‧‧汲polar
24‧‧‧氮化矽層24‧‧‧ layer of tantalum nitride
25‧‧‧閘極介電層25‧‧‧ gate dielectric layer
26‧‧‧通道區26‧‧‧Channel area
27‧‧‧閘極層27‧‧‧ gate layer
30‧‧‧薄膜電晶體結構30‧‧‧Thin-film crystal structure
31‧‧‧基板31‧‧‧Substrate
32‧‧‧載板32‧‧‧ Carrier Board
33‧‧‧閘極層33‧‧‧ gate layer
34‧‧‧閘極介電層34‧‧‧ gate dielectric layer
35‧‧‧第一半導體層35‧‧‧First semiconductor layer
36‧‧‧通道區36‧‧‧Channel area
37‧‧‧第二半導體層37‧‧‧Second semiconductor layer
38‧‧‧凹部38‧‧‧ recess
40‧‧‧第三半導體層40‧‧‧ third semiconductor layer
41‧‧‧半導體邊襯41‧‧‧Semiconductor lining
42‧‧‧源極區域42‧‧‧ source area
43‧‧‧汲極區域43‧‧‧Bungee area
50‧‧‧開口50‧‧‧ openings
52‧‧‧凸出結構52‧‧‧ protruding structure
61‧‧‧第一連接面61‧‧‧First connection surface
62‧‧‧第二連接面62‧‧‧second connection surface
圖1A及1B顯示習知之薄膜電晶體結構;圖2A至2G顯示根據本發明一實施例之薄膜電晶體結構之製作方法;圖3顯示根據本發明一實施例之薄膜電晶體之電場曲線圖;以及圖4顯示根據本發明一實施例之薄膜電晶體之電流及電壓之關係曲線圖。1A and 1B show a conventional thin film transistor structure; FIGS. 2A to 2G show a method of fabricating a thin film transistor structure according to an embodiment of the present invention; and FIG. 3 shows an electric field curve of a thin film transistor according to an embodiment of the present invention; And Figure 4 is a graph showing the relationship between current and voltage of a thin film transistor according to an embodiment of the present invention.
30‧‧‧薄膜電晶體結構30‧‧‧Thin-film crystal structure
31‧‧‧基板31‧‧‧Substrate
32‧‧‧載板32‧‧‧ Carrier Board
33‧‧‧閘極層33‧‧‧ gate layer
34‧‧‧閘極介電層34‧‧‧ gate dielectric layer
35‧‧‧第一半導體層35‧‧‧First semiconductor layer
36‧‧‧通道區36‧‧‧Channel area
37‧‧‧第二半導體層37‧‧‧Second semiconductor layer
41‧‧‧半導體邊襯41‧‧‧Semiconductor lining
42‧‧‧源極區域42‧‧‧ source area
43‧‧‧汲極區域43‧‧‧Bungee area
50‧‧‧開口50‧‧‧ openings
52‧‧‧凸出結構52‧‧‧ protruding structure
61‧‧‧第一連接面61‧‧‧First connection surface
62‧‧‧第二連接面62‧‧‧second connection surface
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US5663578A (en) * | 1995-11-17 | 1997-09-02 | International Business Machines Corporation | Thin film transistor with self-aligned bottom gate |
US6077732A (en) * | 1996-03-25 | 2000-06-20 | Micron Technology, Inc. | Method of forming a thin film transistor |
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US5663578A (en) * | 1995-11-17 | 1997-09-02 | International Business Machines Corporation | Thin film transistor with self-aligned bottom gate |
US6077732A (en) * | 1996-03-25 | 2000-06-20 | Micron Technology, Inc. | Method of forming a thin film transistor |
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