TWI410949B - Method for determining an optimum skew of a data driver and the data driver utilizing the same - Google Patents

Method for determining an optimum skew of a data driver and the data driver utilizing the same Download PDF

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TWI410949B
TWI410949B TW98134598A TW98134598A TWI410949B TW I410949 B TWI410949 B TW I410949B TW 98134598 A TW98134598 A TW 98134598A TW 98134598 A TW98134598 A TW 98134598A TW I410949 B TWI410949 B TW I410949B
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offset
test pattern
pixel clock
clock signal
data
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TW98134598A
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TW201113856A (en
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Pen Hsin Chen
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Himax Tech Ltd
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Abstract

A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking periods. The skew adjusting circuit receives a pixel clock signal and adjusts a clock phase of the pixel clock signal by delaying the pixel clock signal with a controllable skew according to a feedback control signal so as to generate the processed pixel clock signal. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, determines an optimum skew by comparing the sampled test patterns with the predetermined test pattern, and generates the feedback control signal including information indicating the optimum skew.

Description

資料驅動器與用以決定資料驅動器之最佳偏移之方法Data driver and method for determining the optimal offset of the data driver

本發明係關於一種顯示裝置之資料驅動器，特別關於一種可自動決定最佳時脈偏移(clock skew)並調整時脈相位之資料驅動器。The present invention relates to a data driver for a display device, and more particularly to a data driver that automatically determines an optimal clock skew and adjusts the clock phase.

液晶顯示器，或稱LCD(Liquid Crystal Display)，由於其具有反應速度快、輕薄、明亮度高、消耗功率低以及可高度擴展之顯示尺寸等的特性，因而近年來被廣泛地使用。隨著液晶面板的解析度提高，資料驅動器(或稱源極驅動器)的數量因此隨之增加，並且時序控制器與各資料驅動器之間的傳輸速度也跟著提升。為了在有效期間內正確存取資料，需要準確地調整系統時脈(例如，像素時脈)的偏移。通常此期間稱為「資料有效期間(Data Valid Window，DVW)」，而系統時脈相對於此期間起始點的時間延遲則定義為所謂的偏移(skew)。A liquid crystal display, or LCD (Liquid Crystal Display), has been widely used in recent years because of its characteristics of high reaction speed, light weight, high brightness, low power consumption, and a highly expandable display size. As the resolution of the liquid crystal panel increases, the number of data drivers (or source drivers) increases accordingly, and the transfer speed between the timing controller and each data driver also increases. In order to properly access data during the active period, it is necessary to accurately adjust the offset of the system clock (eg, pixel clock). Usually this period is called "Data Valid Window (DVW)", and the time delay of the system clock relative to the starting point of this period is defined as the so-called skew.

傳統技術中，時脈偏移係在製造液晶顯示器時被手動地調整到一個固定的數值，並且此數值在離開工廠後就不會再被改變。然而，由於時序控制器與各資料驅動器之間的傳輸距離並不相同，導致固定的偏移數值無法全然適用於各資料驅動器，因而限制了液晶顯示器的操作容限。此外，資料驅動器的製程、電壓與溫度(Process,Voltage and Temperature，PVT)變化也可能使得固定的偏移數值變得不適當。因此，需要一種可自動決定最佳時脈偏移並調整時脈相位之資料驅動器。In the conventional art, the clock offset is manually adjusted to a fixed value when manufacturing the liquid crystal display, and this value is not changed after leaving the factory. However, since the transmission distance between the timing controller and each data driver is not the same, the fixed offset value cannot be fully applied to each data driver, thus limiting the operational tolerance of the liquid crystal display. In addition, changes in the process, voltage, and temperature (PVT) of the data driver may also make the fixed offset value inappropriate. Therefore, there is a need for a data driver that automatically determines the optimal clock offset and adjusts the clock phase.

根據本發明之一實施例，一種資料驅動器，用以驅動影像資料被顯示於顯示裝置之面板上，包括接收機、偏移調整電路與處理裝置。接收機根據一處理過的像素時脈於一資料匯流排上取樣該影像資料，其中該影像資料包括傳送於複數活化期間(active period)之像素資料以及反覆***於該影像資料之複數空白期間(blanking period)之一測試圖樣。偏移調整電路接收一像素時脈信號並藉由根據一回授控制信號使用一可控制之偏移數值延遲該像素時脈信號，用以調整該像素時脈信號之一時脈相位，以產生該處理過的像素時脈。處理裝置儲存與被***之該測試圖樣同步之一既定測試圖樣，藉由比較測試圖樣之該取樣結果與該既定測試圖樣決定一最佳偏移，並且產生包括用以指示該最佳偏移之資訊之該回授控制信號。According to an embodiment of the invention, a data driver for driving image data is displayed on a panel of a display device, including a receiver, an offset adjustment circuit, and a processing device. The receiver samples the image data on a data bus according to a processed pixel clock, wherein the image data includes pixel data transmitted in a plurality of active periods and a plurality of blanks repeatedly inserted into the image data ( Blanking period) One of the test patterns. The offset adjustment circuit receives a pixel clock signal and delays the pixel clock signal by using a controllable offset value according to a feedback control signal to adjust a clock phase of the pixel clock signal to generate the The processed pixel clock. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, and determines an optimal offset by comparing the sampled result of the test pattern with the predetermined test pattern, and generates an indication to indicate the optimal offset The feedback control signal of the information.

根據本發明之另一實施例，一種用以決定一顯示裝置之一資料驅動器之一最佳偏移之方法，包括：於影像資料之一空白期間傳送一測試圖樣至一資料匯流排，其中該資料匯流排也負責於該影像資料之複數活化期間傳送該影像資料之複數訊框之像素資料；接收一像素時脈信號；根據該像素時脈信號取樣該測試圖樣以取得測試圖樣之一取樣結果；以及藉由比較測試圖樣之該取樣結果與一預先儲存之測試圖樣決定該最佳偏移。According to another embodiment of the present invention, a method for determining an optimum offset of a data driver of a display device includes: transmitting a test pattern to a data bus during a blank of the image data, wherein The data bus is also responsible for transmitting pixel data of the plurality of frames of the image data during the plural activation of the image data; receiving a pixel clock signal; sampling the test pattern according to the pixel clock signal to obtain a sampling result of the test pattern And determining the optimal offset by comparing the sampled result of the test pattern with a pre-stored test pattern.

為使本發明之製造、操作方法、目標和優點能更明顯易懂，下文特舉幾個較佳實施例，並配合所附圖式，作詳細說明如下：實施例：第1圖係顯示根據本發明之一實施例所述之資料驅動器之部分方塊圖。根據本發明之一實施例，顯示裝置100包括一時序控制器101與一資料驅動器102(也稱為源極驅動器)。顯示裝置可以是，例如，液晶顯示器(LCD)。時序控制器101自一外部的影像資料供應源(圖未示)接收一影像資料信號SIM ，並且負責傳送要被顯示於顯示裝置100之一面板(圖未示)之影像資料。時序控制器101更產生時序控制信號用以控制影像資料之傳輸。時序控制信號可根據自影像資料供應源所接收之一個或多個時序信號而產生。例如，影像資料供應源可提供一個垂直同步信號SVsync 用以指示一訊框傳輸之開端(或指示訊框間的變化)、一水平同步信號SHref 用以指示乘載於資料匯流排上之影像資料信號SIM 為某一訊框線(frame line)之活化的(active)像素資料，以及一像素同步信號SPixel_Clk 用以同步像素資料之傳輸，等等。時序控制器101傳送影像資料之像素資料於匯流排之資料信號DATA中，用以傳送至資料驅動器102，並且產生多個時序控制信號，例如包括用以指示資料匯流排上的各訊框線之活化像素資料或活化期間之開端之一第一時序控制信號STH、用以指示資料匯流排上的各訊框線之活化像素資料或活化期間之結束之一第二時序控制信號TP，以及用以指示資料匯流排上之像素資料傳輸頻率之像素時脈信號CLOCK。各時序控制信號所對應之時序圖可參考至第3圖。In order to make the manufacturing, the operation, the objects, the advantages and the advantages of the present invention more obvious, the following detailed description of the preferred embodiments and the accompanying drawings are described in detail as follows: Example: Figure 1 shows A block diagram of a portion of a data driver in accordance with an embodiment of the present invention. According to an embodiment of the invention, display device 100 includes a timing controller 101 and a data driver 102 (also referred to as a source driver). The display device can be, for example, a liquid crystal display (LCD). The timing controller 101 receives an image data signal S IM from an external image data supply source (not shown) and is responsible for transmitting image data to be displayed on a panel (not shown) of the display device 100. The timing controller 101 further generates timing control signals for controlling the transmission of the image data. The timing control signal can be generated based on one or more timing signals received from the image data supply. For example, the image data supply source may provide a vertical synchronization signal S Vsync for indicating the beginning of a frame transmission (or a change between the indication frames), and a horizontal synchronization signal S Href for indicating the loading on the data bus. The image data signal S IM is an active pixel data of a frame line, and a pixel sync signal S Pixel_Clk is used to synchronize the transmission of pixel data, and the like. The timing controller 101 transmits the pixel data of the image data in the data signal DATA of the bus bar for transmission to the data driver 102, and generates a plurality of timing control signals, for example, including the frame lines for indicating the data bus. Activating the pixel data or one of the beginnings of the activation period, the first timing control signal STH, the activated pixel data of each frame line on the data bus or the second timing control signal TP of the end of the activation period, and The pixel clock signal CLOCK indicating the transmission frequency of the pixel data on the data bus. The timing chart corresponding to each timing control signal can be referred to FIG.

根據本發明之一實施例，時序控制器101在一些既定的時間區間將一既定之測試圖樣***於被乘載於資料匯流排上的資料信號DATA，用以在既定的時間區間內傳送該等測試圖樣。根據本發明之一實施例，既定的時間區間可為無活化像素資料需要被傳送之空白期間。例如，該空白期間可以是各訊框線中無活化像素資料出現之水平空白期間(horizontal blanking period，或簡稱H-blanking)，或者可以是各訊框內無活化像素資料出現之垂直空白期間(vertical blanking period，或簡稱V-blanking)。According to an embodiment of the present invention, the timing controller 101 inserts a predetermined test pattern into the data signal DATA carried on the data bus in some predetermined time intervals for transmitting the data within a predetermined time interval. Test the pattern. According to an embodiment of the invention, the predetermined time interval may be a blank period during which the non-activated pixel data needs to be transmitted. For example, the blank period may be a horizontal blanking period (or H-blanking) in which no activated pixel data appears in each frame line, or may be a vertical blank period in which no activated pixel data appears in each frame ( Vertical blanking period, or V-blanking for short).

資料驅動器102包括接收機201、偏移調整電路202與處理裝置203。接收機201用以根據一處理過的像素時脈CLOCK’於資料匯流排上取樣該影像資料，其中該影像資料包括傳送於複數活化期間(active period)之像素資料以及反覆由時序控制器101***於該影像資料之複數空白期間(blanking period)之測試圖樣。偏移調整電路202耦接至接收機201與時序控制器101，用以自時序控制器101接收像素時脈信號CLOCK，並且藉由根據一回授控制信號CTRL使用一可控制之偏移數值延遲該像素時脈信號，用以調整該像素時脈信號之一時脈相位，以產生該處理過的像素時脈CLOCK’。處理裝置203耦接至接收機201與偏移調整電路202，並且產生回授控制信號CTRL。根據本發明之一實施例，在各既定時間區間內，處理裝置203產生回授控制信號CTRL用以指示偏移調整電路202藉由使用數個不同的偏移數值延遲像素時脈信號，用以調整像素時脈信號之時脈相位。舉例而言，在各訊框線之既定時間區間內，例如在各訊框線之水平空白期間，偏移調整電路202藉由使用數個不同的偏移數值延遲像素時脈信號，用以調整像素時脈信號之時脈相位。使用數個不同的偏移數值調整像素時脈信號之時脈相位，並藉此於既定時間區間內根據各延遲過的像素時脈信號取樣測試圖樣的目的係為了取得適當的偏移容線，使得接收機201可正確地解碼資料。The data driver 102 includes a receiver 201, an offset adjustment circuit 202, and a processing device 203. The receiver 201 is configured to sample the image data on the data bus according to a processed pixel clock CLOCK', wherein the image data includes pixel data transmitted in a complex active period and is repeatedly inserted by the timing controller 101. A test pattern for the blanking period of the image data. The offset adjustment circuit 202 is coupled to the receiver 201 and the timing controller 101 for receiving the pixel clock signal CLOCK from the timing controller 101, and using a controllable offset value delay according to a feedback control signal CTRL The pixel clock signal is used to adjust a clock phase of the pixel clock signal to generate the processed pixel clock CLOCK'. The processing device 203 is coupled to the receiver 201 and the offset adjustment circuit 202, and generates a feedback control signal CTRL. According to an embodiment of the present invention, the processing device 203 generates a feedback control signal CTRL for instructing the offset adjustment circuit 202 to delay the pixel clock signal by using a plurality of different offset values for each predetermined time interval. Adjust the clock phase of the pixel clock signal. For example, during a predetermined time interval of each frame line, for example, during a horizontal blank of each frame line, the offset adjustment circuit 202 delays the pixel clock signal by using a plurality of different offset values for adjustment. The clock phase of the pixel clock signal. Adjusting the clock phase of the pixel clock signal by using a plurality of different offset values, and thereby sampling the test pattern according to each delayed pixel clock signal in a predetermined time interval in order to obtain an appropriate offset capacity line, The receiver 201 is enabled to correctly decode the data.

處理裝置203儲存與被時序控制器101***之該測試圖樣同步之一既定測試圖樣，以及用以指示對應之可控制的偏移數值之相關資訊，用以提供接收機201在不同的期間於資料匯流排上取樣測試圖樣。處理裝置203自接收機201接收測試圖樣之取樣結果，並且比較測試圖樣之該取樣結果與預先儲存之既定測試圖樣。根據本發明之一實施例，處理裝置203取得由一最小偏移與一最大偏移所定義之一容限，其中該最小偏移與該最大偏移為可使得測試圖樣之該取樣結果相等於該既定測試圖樣的最小偏移數值與最大偏移數值，並且根據該容限決定該最佳偏移。根據本發明之一實施例，最佳偏移係由處理裝置203根據分佈於該容限內之複數偏移數值之一平均值而決定。根據本發明之另一實施例，最佳偏移係由處理裝置203根據定義出該容限之該最大偏移與該最小偏移之一中位數而決定。The processing device 203 stores one of the predetermined test patterns synchronized with the test pattern inserted by the timing controller 101, and information related to the corresponding controllable offset value for providing the receiver 201 with data at different periods. The bus line is sampled and tested. The processing device 203 receives the sampling result of the test pattern from the receiver 201, and compares the sampling result of the test pattern with the predetermined test pattern stored in advance. According to an embodiment of the invention, the processing device 203 obtains a tolerance defined by a minimum offset and a maximum offset, wherein the minimum offset and the maximum offset are such that the sampling result of the test pattern is equal to The minimum offset value and the maximum offset value of the predetermined test pattern, and the optimal offset is determined according to the tolerance. In accordance with an embodiment of the present invention, the optimal offset is determined by processing device 203 based on an average of one of the complex offset values distributed within the tolerance. In accordance with another embodiment of the present invention, the optimal offset is determined by processing device 203 based on the maximum offset defining the tolerance and the median of the minimum offset.

處理裝置203可更產生包括用以指示該最佳偏移之資訊之該回授控制信號CTRL，用以彈性地控制接收機201透過偏移調整電路202根據最佳偏移取樣像素資料。如此一來，當顯示裝置內包含大量的資料驅動器時，各資料驅動器的偏移可分別地被控制，因此可大幅改善顯示裝置之操作容限。The processing device 203 can further generate the feedback control signal CTRL including information indicating the optimal offset for elastically controlling the receiver 201 to sample the pixel data according to the optimal offset through the offset adjustment circuit 202. In this way, when a large number of data drivers are included in the display device, the offsets of the data drivers can be separately controlled, thereby greatly improving the operational tolerance of the display device.

第3圖係顯示根據本發明之一實施例所述之時序控制信號與資料訊號DATA之波形圖。根據本發明之一實施例，接收機201可根據第一時序信號STH取得測試圖樣(如圖所示之Test Pattern)。例如，可定義出在測試圖樣被***的起始點之前，自STH脈衝發生後像素時脈信號CLOCK產生了多少個脈衝。如此一來，在接收到STH脈衝後，接收機201可計算既定數量個像素時脈信號之脈衝，爾後接收測試圖樣。測試圖樣的資料長度可是先被定義，並且事先為接收機201所知。根據本發明之其它實施例，接收機接收機201也可根據第二時序信號TP取樣測試圖樣。例如，可定義出在測試圖樣被***的起始點之前，自TP脈衝發生後像素時脈信號CLOCK產生了多少個脈衝，或定義自TP脈衝發生後的一既定之時間延遲後，測試圖樣開始被***。因此，在接收到TP脈衝後，接收機201可計算既定數量個像素時脈信號之脈衝或等待該既定之時間延遲，並且接著接收測試圖樣。更具體的來說，例如，可於最後一個時序信號TP具有高位準之時脈週期內定義出如第3圖所示之時間參數Ta，用以指示被***之測試圖樣的起始時間點，並且可定義另一個時間參數Tb，用以指示出***之測試圖樣的長度，其單位可以是時脈週期。3 is a waveform diagram showing a timing control signal and a data signal DATA according to an embodiment of the present invention. According to an embodiment of the present invention, the receiver 201 can obtain a test pattern (Test Pattern as shown) according to the first timing signal STH. For example, it is possible to define how many pulses are generated by the pixel clock signal CLOCK since the STH pulse occurred before the starting point at which the test pattern was inserted. In this way, after receiving the STH pulse, the receiver 201 can calculate the pulse of the clock signal of a predetermined number of pixels, and then receive the test pattern. The data length of the test pattern can be defined first and known to the receiver 201 in advance. According to other embodiments of the present invention, the receiver receiver 201 may also sample the test pattern based on the second timing signal TP. For example, it is possible to define how many pulses are generated by the pixel clock signal CLOCK since the TP pulse occurs before the start point of the test pattern is inserted, or after a predetermined time delay after the TP pulse occurs, the test pattern begins. Was inserted. Thus, upon receipt of the TP pulse, receiver 201 can calculate a pulse of a predetermined number of pixel clock signals or wait for the predetermined time delay and then receive the test pattern. More specifically, for example, a time parameter Ta as shown in FIG. 3 may be defined in a clock cycle in which the last timing signal TP has a high level to indicate the start time point of the inserted test pattern. And another time parameter Tb can be defined to indicate the length of the inserted test pattern, and the unit can be a clock cycle.

根據本發明之一實施例，可針對每個訊框決定出最佳偏移。因此，處理裝置203可根據在影像資料的一個訊框內所產生的複數不同的偏移數值決定出最小偏移與最大偏移，並且偏移調整電路202可於每個訊框內根據得到的最佳偏移調整時脈信號之時脈相位。根據本發明之另一實施例，最佳偏移也可週期性地在一既定時間區間內被決定。因此，處理裝置203可根據在既定時間區間內所產生的複數不同的偏移數值決定出最小偏移與最大偏移，並且偏移調整電路202可對應地於此既定時間區間內根據得到的最佳偏移調整時脈信號之時脈相位。According to an embodiment of the invention, an optimum offset can be determined for each frame. Therefore, the processing device 203 can determine the minimum offset and the maximum offset according to the complex offset values generated in a frame of the image data, and the offset adjustment circuit 202 can be obtained according to each frame. The optimum offset adjusts the clock phase of the clock signal. According to another embodiment of the invention, the optimal offset can also be determined periodically over a predetermined time interval. Therefore, the processing device 203 can determine the minimum offset and the maximum offset according to different complex offset values generated within a predetermined time interval, and the offset adjustment circuit 202 can correspondingly obtain the most according to the obtained time interval. Good offset adjusts the clock phase of the clock signal.

第2圖係顯示根據本發明之一實施例所述之偏移調整電路之方塊圖。偏移調整電路202包括一延遲鏈211與一多工器212。延遲鏈211用以接收像素時脈信號CLOCK，並且包括複數延遲單元用以延遲像素時脈信號CLOCK。多工器212用以接收回授控制信號CTRL以及於各延遲單元之一輸出端所對應輸出之延遲過之像素時脈信號，並且根據回授控制信號CTRL選擇該等延遲過之像素時脈信號之一者，用以產生處理過的像素時脈信號CLOCK’。2 is a block diagram showing an offset adjustment circuit according to an embodiment of the present invention. The offset adjustment circuit 202 includes a delay chain 211 and a multiplexer 212. The delay chain 211 is configured to receive the pixel clock signal CLOCK and includes a complex delay unit for delaying the pixel clock signal CLOCK. The multiplexer 212 is configured to receive the feedback control signal CTRL and the delayed pixel clock signal corresponding to the output of one of the delay units, and select the delayed pixel clock signals according to the feedback control signal CTRL One of them is used to generate a processed pixel clock signal CLOCK'.

第4圖係顯示根據本發明之一實施例所述之用以決定資料驅動器之最佳偏移之方法流程圖。首先，於影像資料之一空白期間***一測試圖樣至傳送於資料匯流排上的資料信號(步驟S401)。接著，接收一像素時脈信號(步驟S402)。接著，根據像素時脈信號取樣該測試圖樣以取得測試圖樣之一取樣結果(步驟S403)。值得注意的是，步驟S401、S402與S403可重複執行於數個空白期間，並且在步驟S402中，可於數個空白期間分別接收複數個根據不同偏移數值延遲過的像素時脈信號。最後，比較測試圖樣之該取樣結果與一預先儲存之測試圖樣以決定最佳偏移(步驟S404)。在步驟S404中，測試圖樣之取樣結果可與該預先儲存之測試圖樣進行比較，其中該預先儲存之測試圖樣係與被傳送之測試圖樣同步，並且可取得由一最小偏移與一最大偏移所定義之一容限，用以決定出最佳偏移，其中該最小偏移與該最大偏移為可使得測試圖樣之該取樣結果相等於該預先儲存之測試圖樣的最小偏移數值與最大偏移數值。根據本發明之一實施例，最佳偏移可根據分佈於該容限內之複數偏移數值之一平均值而決定，或根據定義出該容限之該最大偏移與該最小偏移之一中位數而決定。4 is a flow chart showing a method for determining an optimum offset of a data driver in accordance with an embodiment of the present invention. First, a test pattern is inserted during a blank of the image data to the data signal transmitted on the data bus (step S401). Next, a one-pixel clock signal is received (step S402). Next, the test pattern is sampled according to the pixel clock signal to obtain a sampling result of the test pattern (step S403). It should be noted that steps S401, S402, and S403 may be repeatedly performed in a plurality of blank periods, and in step S402, a plurality of pixel clock signals delayed according to different offset values may be respectively received during a plurality of blank periods. Finally, the sampled result of the test pattern is compared with a pre-stored test pattern to determine the optimal offset (step S404). In step S404, the sampling result of the test pattern can be compared with the pre-stored test pattern, wherein the pre-stored test pattern is synchronized with the transmitted test pattern, and can be obtained by a minimum offset and a maximum offset. One of the tolerances defined to determine an optimal offset, wherein the minimum offset and the maximum offset are such that the sampling result of the test pattern is equal to the minimum offset value and maximum of the pre-stored test pattern Offset value. According to an embodiment of the invention, the optimal offset may be determined according to an average value of one of the complex offset values distributed within the tolerance, or according to the maximum offset and the minimum offset defining the tolerance Determined by a median.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100．．．顯示裝置100. . . Display device

101．．．時序控制器101. . . Timing controller

102．．．資料驅動器102. . . Data driver

201．．．接收機201. . . Receiver

22

02、202A．．．偏移調整電路02, 202A. . . Offset adjustment circuit

203．．．處理裝置203. . . Processing device

211．．．延遲鏈211. . . Delay chain

212．．．多工器212. . . Multiplexer

Active Data．．．活化資料Active Data. . . Activation data

CLOCK、CLOCK’、CTRL、DATA、SHref 、SIM 、SPixel_Clk 、CLOCK, CLOCK ', CTRL, DATA , S Href, S IM, S Pixel_Clk,

STH、SVsync 、TP．．．信號STH, S Vsync , TP. . . signal

H-blanking．．．水平空白期間H-blanking. . . Horizontal blank period

S401、S402、S403、S404．．．步驟S401, S402, S403, S404. . . step

Ta、Tb．．．時間參數Ta, Tb. . . Time parameter

Test Pattern．．．測試圖樣Test Pattern. . . Test pattern

第1圖係顯示根據本發明之一實施例所述之資料驅動器之部分方塊圖。1 is a block diagram showing a portion of a data drive in accordance with an embodiment of the present invention.

第2圖係顯示根據本發明之一實施例所述之偏移調整電路之方塊圖。2 is a block diagram showing an offset adjustment circuit according to an embodiment of the present invention.

第3圖係顯示根據本發明之一實施例所述之時序控制信號與資料訊號DATA之波形圖。3 is a waveform diagram showing a timing control signal and a data signal DATA according to an embodiment of the present invention.

第4圖係顯示根據本發明之一實施例所述之用以決定資料驅動器之最佳偏移之方法流程圖。4 is a flow chart showing a method for determining an optimum offset of a data driver in accordance with an embodiment of the present invention.

100．．．顯示裝置100. . . Display device

101．．．時序控制器101. . . Timing controller

102．．．資料驅動器102. . . Data driver

201．．．接收機201. . . Receiver

202．．．偏移調整電路202. . . Offset adjustment circuit

203．．．處理裝置203. . . Processing device

CLOCK、CLOCK’、CTRL、DATA、SHref 、SIM 、SPixel_Clk 、STH、SVsync 、TP．．．信號CLOCK, CLOCK ', CTRL, DATA , S Href, S IM, S Pixel_Clk, STH, S Vsync, TP. . . signal

Claims (20)

一種資料驅動器，用以驅動影像資料被顯示於一顯示裝置之一面板上，包括：一接收機，根據一處理過的像素時脈於一資料匯流排上取樣該影像資料，其中該影像資料包括傳送於複數活化期間(active period)之像素資料以及反覆***於該影像資料之複數空白期間(blanking period)之一測試圖樣；一偏移調整電路，接收一像素時脈信號並藉由根據一回授控制信號使用一可控制之偏移數值延遲該像素時脈信號，用以調整該像素時脈信號之一時脈相位，以產生該處理過的像素時脈；以及一處理裝置，儲存與被***之該測試圖樣同步之一既定測試圖樣，藉由比較該測試圖樣之該取樣結果與該既定測試圖樣決定一最佳偏移，並且產生包括用以指示該最佳偏移之資訊之該回授控制信號。 A data driver for driving image data to be displayed on a panel of a display device, comprising: a receiver for sampling the image data on a data bus according to a processed pixel clock, wherein the image data includes a pixel data transmitted in a complex active period and a test pattern repeatedly inserted into the blanking period of the image data; an offset adjusting circuit that receives a pixel clock signal and according to a The control signal delays the pixel clock signal with a controllable offset value for adjusting a clock phase of the pixel clock signal to generate the processed pixel clock; and a processing device for storing and being inserted The test pattern is synchronized with one of the predetermined test patterns, and the optimal result is determined by comparing the sampled result of the test pattern with the predetermined test pattern, and generating the feedback including the information indicating the optimal offset. control signal. 如申請專利範圍第1項所述之資料驅動器，其中該等空白期間為水平空白期間(horizontal blanking period)。 The data driver of claim 1, wherein the blank period is a horizontal blanking period. 如申請專利範圍第1項所述之資料驅動器，其中該等空白期間為垂直空白期間(vertical blanking period)。 The data driver of claim 1, wherein the blank period is a vertical blanking period. 如申請專利範圍第1項所述之資料驅動器，其中該處理裝置更比較該測試圖樣之該取樣結果與該既定測試圖樣，取得由一最小偏移與一最大偏移所定義之一容限，其中該最小偏移與該最大偏移為可使得該測試圖樣之該取樣結果相等於該既定測試圖樣的最小偏移數值與最大偏移數 值，並且根據該容限決定該最佳偏移。 The data driver of claim 1, wherein the processing device compares the sampling result of the test pattern with the predetermined test pattern to obtain a tolerance defined by a minimum offset and a maximum offset. The minimum offset and the maximum offset are such that the sampling result of the test pattern is equal to the minimum offset value and the maximum offset number of the predetermined test pattern. Value, and the optimal offset is determined based on the tolerance. 如申請專利範圍第1項所述之資料驅動器，其中該接收機更接收包含用以指示該等活化期間之一開始或一結束之資訊之一時序信號，並且根據該時序信號取樣該測試圖樣。 The data driver of claim 1, wherein the receiver further receives a timing signal including information indicating one of the start or end of the activation period, and sampling the test pattern according to the timing signal. 如申請專利範圍第1項所述之資料驅動器，其中該處理裝置更產生該回授控制信號，用以指示該偏移調整電路藉由使用複數不同之偏移數值於每一複數訊框線之該等空白期間內延遲該像素時脈信號以調整該像素時脈信號之該時脈相位。 The data driver of claim 1, wherein the processing device further generates the feedback control signal for indicating that the offset adjustment circuit uses a plurality of different offset values for each complex frame line. The pixel clock signal is delayed during the blank period to adjust the clock phase of the pixel clock signal. 如申請專利範圍第4項所述之資料驅動器，其中該最小偏移與該最大偏移係根據於該影像資料之一訊框內所產生之複數偏移數值而取得，並且該時脈相位係在每個訊框被調整。 The data driver of claim 4, wherein the minimum offset and the maximum offset are obtained according to a complex offset value generated in a frame of the image data, and the clock phase system is obtained. The frame is adjusted in each frame. 如申請專利範圍第4項所述之資料驅動器，其中該最小偏移與該最大偏移係根據於一既定時間區間內所產生之複數偏移數值而取得，並且該時脈相位係根據該既定時間區間被調整。 The data driver of claim 4, wherein the minimum offset and the maximum offset are obtained based on a complex offset value generated within a predetermined time interval, and the clock phase is determined according to the predetermined The time interval is adjusted. 如申請專利範圍第4項所述之資料驅動器，其中該最佳偏移係根據分佈於該容限內之複數偏移數值之一平均值而決定。 The data driver of claim 4, wherein the optimal offset is determined based on an average of one of a plurality of offset values distributed within the tolerance. 如申請專利範圍第4項所述之資料驅動器，其中該最佳偏移係根據定義出該容限之該最大偏移與該最小偏移之一中位數而決定。 The data driver of claim 4, wherein the optimal offset is determined based on the maximum offset defining the tolerance and a median of the minimum offset. 如申請專利範圍第1項所述之資料驅動器，其中 該偏移調整電路包括：一延遲鏈，用以接收該像素時脈信號，並且包括複數延遲單元用以延遲該像素時脈信號；以及一多工器，用以接收該回授控制信號以及於各延遲單元之一輸出端所對應輸出之該延遲過之像素時脈信號，並且根據該回授控制信號選擇該等延遲過之像素時脈信號之一者用以產生該處理過的像素時脈信號。 For example, the data driver described in claim 1 of the patent scope, wherein The offset adjustment circuit includes: a delay chain for receiving the pixel clock signal, and a complex delay unit for delaying the pixel clock signal; and a multiplexer for receiving the feedback control signal and And outputting the delayed pixel clock signal corresponding to one of the output terminals of each delay unit, and selecting one of the delayed pixel clock signals according to the feedback control signal to generate the processed pixel clock signal. 一種用以決定一顯示裝置之一資料驅動器之一最佳偏移之方法，包括：於影像資料之一空白期間傳送一測試圖樣至一資料匯流排，其中該資料匯流排也負責於該影像資料之複數活化期間傳送該影像資料之複數訊框之像素資料；接收一像素時脈信號；根據該像素時脈信號取樣該測試圖樣以取得該測試圖樣之一取樣結果；以及藉由比較該測試圖樣之該取樣結果與一預先儲存之測試圖樣決定該最佳偏移。 A method for determining an optimal offset of a data driver of a display device, comprising: transmitting a test pattern to a data bus during a blank of the image data, wherein the data bus is also responsible for the image data Transmitting pixel data of the plurality of frames of the image data during the activation; receiving a pixel clock signal; sampling the test pattern according to the pixel clock signal to obtain a sampling result of the test pattern; and comparing the test pattern by comparing The sampling result and the pre-stored test pattern determine the optimal offset. 如申請專利範圍第12項所述之方法，其中該空白期間為水平空白期間(horizontal blanking period)。 The method of claim 12, wherein the blank period is a horizontal blanking period. 如申請專利範圍第12項所述之方法，其中傳送該測試圖樣之步驟、接收該像素時脈信號之步驟與取樣該測試圖樣之步驟係重複執行於一數量之空白期間，並且於該接收步驟分別在該等空白期間根據複數不同之偏移數值接收該像素時脈信號。 The method of claim 12, wherein the step of transmitting the test pattern, the step of receiving the pixel clock signal, and the step of sampling the test pattern are repeated for a number of blank periods, and the receiving step The pixel clock signal is received according to a plurality of different offset values during the blank periods. 如申請專利範圍第12項所述之方法，其中該測試 圖樣根據該像素時脈信號使用複數不同的偏移數值反覆地於一數量之空白期間被取樣，並且決定該最佳偏移之步驟更包括：比較該測試圖樣之該取樣結果與該預先儲存之測試圖樣，其中該預先儲存之測試圖樣係與被傳送之該測試圖樣同步；取得由一最小偏移與一最大偏移所定義之一容限，其中該最小偏移與該最大偏移為可使得該測試圖樣之該取樣結果相等於該預先儲存之測試圖樣的最小偏移數值與最大偏移數值；以及根據該容限決定該最佳偏移。 The method of claim 12, wherein the test The pattern is sampled repeatedly according to the pixel clock signal using a plurality of different offset values over a blank period, and the step of determining the optimal offset further comprises: comparing the sampled result of the test pattern with the pre-stored a test pattern, wherein the pre-stored test pattern is synchronized with the transmitted test pattern; obtaining a tolerance defined by a minimum offset and a maximum offset, wherein the minimum offset and the maximum offset are The sampling result of the test pattern is made equal to the minimum offset value and the maximum offset value of the pre-stored test pattern; and the optimal offset is determined according to the tolerance. 如申請專利範圍第12項所述之方法，更包括：接收包含用以指示傳送於該資料匯流排上的每一複數訊框線之活化像素資料之開始或結束之資訊之一時序信號；以及根據該時序信號使用複數不同之偏移於每一複數訊框線取樣該測試圖樣。 The method of claim 12, further comprising: receiving a timing signal including information indicating the start or end of the activated pixel data of each of the plurality of frame lines transmitted on the data bus; The test pattern is sampled on each of the complex frame lines using a plurality of different offsets based on the timing signal. 如申請專利範圍第12項所述之方法，更包括：根據該最佳偏移調整該接收到的像素時脈信號之一時脈相位；以及根據該調整過之像素時脈信號取樣該像素資料。 The method of claim 12, further comprising: adjusting a clock phase of the received pixel clock signal according to the optimal offset; and sampling the pixel data according to the adjusted pixel clock signal. 如申請專利範圍第15項所述之方法，其中該最佳偏移係根據分佈於該容限內之複數偏移數值之一平均值而決定。 The method of claim 15, wherein the optimal offset is determined based on an average of one of a plurality of offset values distributed within the tolerance. 如申請專利範圍第15項所述之方法，其中該最佳 偏移係根據定義出該容限之該最大偏移與該最小偏移之一中位數而決定。 The method of claim 15, wherein the best The offset is determined by the maximum offset defining the tolerance and the median of the minimum offset. 如申請專利範圍第16項所述之方法，其中該測試圖樣、該像素時脈信號以及該時序信號係由一時序控制器所傳送，並且其中該資料驅動器事先儲存該預先儲存之測試圖樣並且比較該預先儲存之測試圖樣與該測試圖樣之該取樣結果。 The method of claim 16, wherein the test pattern, the pixel clock signal, and the timing signal are transmitted by a timing controller, and wherein the data driver stores the pre-stored test pattern in advance and compares The pre-stored test pattern and the sampled result of the test pattern.
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