TWI410948B - Liquid crystal display device and method for driving the same - Google Patents

Liquid crystal display device and method for driving the same Download PDF

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TWI410948B
TWI410948B TW98132103A TW98132103A TWI410948B TW I410948 B TWI410948 B TW I410948B TW 98132103 A TW98132103 A TW 98132103A TW 98132103 A TW98132103 A TW 98132103A TW I410948 B TWI410948 B TW I410948B
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driving circuit
display area
liquid crystal
gate
driving
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TW201112211A (en
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Sheng Chao Liu
Kuang Hsiang Liu
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Au Optronics Corp
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Abstract

A liquid crystal display device periodically switches two gate drivers so that only one of the two gate drivers is turned on when displaying a frame. The two gate drivers can be disposed on the same side of the gate lines, or on the two opposite sides of the gate lines. The gate drivers can be alternatively switched on after displaying one frame or several frames.

Description

液晶顯示裝置及相關驅動方法Liquid crystal display device and related driving method

本發明相關於一種液晶顯示裝置及相關驅動方法，尤指一種利用多組電路來分時驅動之液晶顯示裝置及相關驅動方法。The present invention relates to a liquid crystal display device and related driving method, and more particularly to a liquid crystal display device and a related driving method which are driven by time-sharing using a plurality of sets of circuits.

液晶顯示器(liquid crystal display,LCD)具有低輻射、體積小及低耗能等優點，已逐漸取代傳統的陰極射線管(cathode ray tube display,CRT)顯示器，因而被廣泛地應用在筆記型電腦、個人數位助理(personal digital assistant,PDA)、平面電視，或行動電話等資訊產品上。傳統液晶顯示器之方式是利用外部驅動晶片來驅動面板上的畫素以顯示影像，但為了減少元件數目並降低製造成本，近年來逐漸發展成將驅動電路之結構直接製作於顯示面板上，例如應用將閘極驅動電路(gate driver)整合於液晶面板(gate on array,GOA)之技術。Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption. It has gradually replaced the traditional cathode ray tube display (CRT) display, so it is widely used in notebook computers. Personal digital assistant (PDA), flat-screen TV, or mobile phone and other information products. The conventional liquid crystal display adopts an external driving chip to drive pixels on the panel to display images, but in order to reduce the number of components and reduce the manufacturing cost, in recent years, the structure of the driving circuit is directly developed on the display panel, for example, application. A technology that integrates a gate driver into a gate on array (GOA).

請參考第1圖，第1圖為先前技術中一液晶顯示裝置700之簡化方塊示意圖。第1圖僅顯示了液晶顯示裝置700之部分結構，包含複數條閘極線GL(1)～GL(N)、一閘極驅動電路10和一時序控制器(timing controller)20。閘極線GL(1)～GL(N)設於液晶顯示裝置700之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10設於液晶顯示裝置700之非顯示區域40內，其包含複數級移位暫存單元SR(1)～SR(N)，可依據時序控制器20所產生之起始脈衝訊號VST(1)和時脈訊號CK、XCK來輸出閘極驅動訊號GS(1)～GS(N)至相對應之閘極線GL(1)～GL(N)，其中N為正整數。液晶顯示裝置700採用單邊佈局單端驅動之架構，亦即閘極驅動電路10係設置於閘極線GL(1)～GL(N)之一側，並從同一側來驅動閘極線GL(1)～GL(N)。Please refer to FIG. 1. FIG. 1 is a simplified block diagram of a liquid crystal display device 700 in the prior art. 1 shows only a part of the structure of the liquid crystal display device 700, and includes a plurality of gate lines GL(1) to GL(N), a gate driving circuit 10, and a timing controller 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 700, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10 is disposed in the non-display area 40 of the liquid crystal display device 700, and includes a plurality of stages of shift register units SR(1) to SR(N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST (1) and the clock signals CK and XCK output the gate drive signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N), where N is a positive integer. The liquid crystal display device 700 adopts a single-sided layout single-ended driving structure, that is, the gate driving circuit 10 is disposed on one side of the gate lines GL(1) to GL(N), and drives the gate lines GL from the same side. (1) ~ GL (N).

請參考第2圖，第2圖為先前技術之液晶顯示裝置700在運作時之時序圖。在驅動液晶顯示裝置700時，第一級移位暫存單元SR(1)依據時序控制器20所產生之起始脈衝訊號VST(1)來輸出第一級閘極驅動訊號GS(1)，而第二級至第N級移位暫存單元SR(2)～SR(N)則分別依據前一級移位暫存單元SR(1)～SR(N-1)所產生之起始脈衝訊號VST(2)～VST(N)來輸出第二級至第N級閘極驅動訊號GS(2)～GS(N)。第2圖說明了液晶顯示裝置700在顯示複數個畫面中兩相鄰畫面F(N)和F(N+1)時，起始脈衝訊號VST(1)～VST(N)之時序圖。Please refer to FIG. 2, which is a timing diagram of the prior art liquid crystal display device 700 in operation. When the liquid crystal display device 700 is driven, the first stage shift register unit SR(1) outputs the first level gate drive signal GS(1) according to the start pulse signal VST(1) generated by the timing controller 20. The second stage to the Nth stage shift register units SR(2) to SR(N) are respectively based on the start pulse signals generated by the previous stage shift register units SR(1) to SR(N-1). VST(2) to VST(N) output second to Nth gate drive signals GS(2) to GS(N). Fig. 2 is a timing chart showing the start pulse signals VST(1) to VST(N) when the liquid crystal display device 700 displays two adjacent pictures F(N) and F(N+1) in a plurality of pictures.

液晶顯示器一般使用非晶矽(amorphous silicon,a-Si)製程來製作各個移位暫存單元內之薄膜電晶體(thin film transistor,TFT)。薄膜電晶體之電特性相關於其閘極電壓之應力，施加閘極電壓的時間越長，薄膜電晶體之電特性劣化情形越嚴重，如此會降低液晶顯示器的使用期限與可靠度。Liquid crystal displays generally use an amorphous silicon (a-Si) process to fabricate thin film transistors (TFTs) in each of the shift register units. The electrical characteristics of the thin film transistor are related to the stress of the gate voltage. The longer the application of the gate voltage, the more serious the deterioration of the electrical characteristics of the thin film transistor, which reduces the lifetime and reliability of the liquid crystal display.

本發明提供一種液晶顯示裝置，包含一顯示區域，其上設有N條互相平行之閘極線，其中N為正整數；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，其依據一第一組控制訊號來運作，該第一驅動電路設於該第一非顯示區域內且包含N級串接之第一移位暫存單元，其中該N級第一移位暫存單元中一第n級第一移位暫存單元係用來驅動該N條閘極線中一相對應之第n條閘極線以顯示複數個畫面中之一第一畫面，且n為不大於N之正整數；及一第二驅動電路，其依據一第二組控制訊號來運作且包含N級串接之第二移位暫存單元，其中該N級第二移位暫存單元中一第n級第二移位暫存單元係用來驅動該第n條閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面。The present invention provides a liquid crystal display device comprising a display area having N parallel gate lines, wherein N is a positive integer; a first non-display area and a second non-display area are respectively located on the display Two opposite sides of the area; a first driving circuit, which operates according to a first group of control signals, the first driving circuit is disposed in the first non-display area and includes a first shift of the N-level series connection a memory cell, wherein an nth stage first shift register unit of the Nth stage first shift register unit is configured to drive a corresponding nth gate line of the N gate lines to display a plurality of One of the first pictures of the picture, and n is a positive integer not greater than N; and a second driving circuit that operates according to a second set of control signals and includes a second shift register unit of N stages The nth stage second shift register unit of the Nth stage second shift register unit is configured to drive the nth gate line to display the plurality of pictures connected to the first picture. A second picture.

本發明另提供一種液晶顯示裝置，包含一顯示區域，其上設有複數條互相平行之閘極線；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，設於該第一非顯示區域內並依據一第一組控制訊號來運作，該第一驅動電路包含複數級串接之第一移位暫存單元，分別用來驅動該複數條閘極線中相對應之奇數條閘極線以顯示複數個畫面中之一第一畫面；一第二驅動電路，設於該第二非顯示區域內並依據一第二組控制訊號來運作，該第二驅動電路包含複數級串接之第二移位暫存單元，分別用來驅動該複數條閘極線中相對應之偶數條閘極線以顯示該第一畫面；一第三驅動電路，其依據一第三組控制訊號來運作且包含複數級串接之第三移位暫存單元，分別用來驅動該相對應之奇數條閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面；及一第四驅動電路，其依據一第四組控制訊號來運作且包含複數級串接之第四移位暫存單元，分別用來驅動該相對應之偶數條閘極線以顯示該第二畫面。The present invention further provides a liquid crystal display device comprising a display area on which a plurality of gate lines parallel to each other are disposed; a first non-display area and a second non-display area respectively located in opposite directions of the display area a first driving circuit is disposed in the first non-display area and operates according to a first group of control signals, wherein the first driving circuit comprises a plurality of serially connected first shifting temporary storage units, respectively Driving a corresponding odd gate line of the plurality of gate lines to display a first picture of the plurality of pictures; a second driving circuit disposed in the second non-display area and controlled according to a second group The second driving circuit includes a plurality of serially connected second shift temporary storage units for respectively driving the corresponding even number of gate lines of the plurality of gate lines to display the first picture; a third driving circuit, which is operated according to a third group of control signals and includes a plurality of serially connected third shift register units for respectively driving the corresponding odd gate lines to display the plurality of pictures Continued from the first a second picture after the picture; and a fourth driving circuit, which operates according to a fourth group of control signals and includes a plurality of serially connected fourth shift register units for respectively driving the corresponding even number of lines The gate line to display the second picture.

本發明另提供一種液晶顯示裝置，包含一顯示區域，其上設有N條互相平行之閘極線，其中N為正整數；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，設於該第一非顯示區域內並依據一第一組控制訊號來運作，該第一驅動電路包含N級串接之第一移位暫存單元，分別用來驅動該N條閘極線中相對應之閘極線以顯示複數個畫面中之一第一畫面；一第二驅動電路，其依據一第二組控制訊號來運作，該第二驅動電路包含N級串接之第二移位暫存單元，分別用來驅動相對應之該N條閘極線以顯示該第一畫面；一第三驅動電路，設於該第一非顯示區域內並依據一第三組控制訊號來運作，該第三驅動電路包含N級串接之第三移位暫存單元，分別用來驅動相對應之該N條閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面；及一第四驅動電路，設於該第二非顯示區域內並依據一第四組控制訊號來運作，該第四驅動電路包含N級串接之第四移位暫存單元，分別用來驅動相對應之該N條閘極線以顯示該第二畫面。The present invention further provides a liquid crystal display device comprising a display area having N parallel gate lines, wherein N is a positive integer; a first non-display area and a second non-display area are respectively located Two opposite sides of the display area; a first driving circuit is disposed in the first non-display area and operates according to a first group of control signals, the first driving circuit includes a first shift of the N-level series connection a memory unit for driving a corresponding one of the N gate lines to display a first picture of the plurality of pictures; and a second driving circuit for operating according to a second group of control signals, The second driving circuit includes a second shift register unit of N stages connected to respectively drive the corresponding N gate lines to display the first picture; a third driving circuit is disposed at the first non- The third driving circuit comprises a third-stage serially connected third shift register unit for driving the corresponding N gate lines to display the complex number. One of the screens continues after the first screen And a fourth driving circuit, disposed in the second non-display area and operating according to a fourth group of control signals, wherein the fourth driving circuit comprises a fourth stage of the N-stage serial storage unit, respectively The corresponding N gate lines are driven to display the second picture.

本發明另提供一種液晶顯示裝置，包含一顯示區域，其上設有複數條互相平行之閘極線；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，設於該第一非顯示區域內並依據一第一組控制訊號來運作，該第一驅動電路包含複數級串接之第一移位暫存單元，分別用來驅動該複數條閘極線中相對應之奇數條閘極線以顯示複數個畫面中之一第一畫面；一第二驅動電路，設於該第一非顯示區域內並依據一第二組控制訊號來運作，該第二驅動電路包含複數級串接之第二移位暫存單元，分別用來驅動該複數條閘極線中相對應之偶數條閘極線以顯示該第一畫面；一第三驅動電路，設於該第二非顯示區域內並依據一第三組控制訊號來運作，該第三驅動電路包含複數級串接之第三移位暫存單元，分別用來驅動該相對應之奇數條閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面；及一第四驅動電路，設於該第二非顯示區域內並依據一第四組控制訊號來運作，該第四驅動電路包含複數級串接之第四移位暫存單元，分別用來驅動該相對應之偶數條閘極線以顯示該第二畫面。The present invention further provides a liquid crystal display device comprising a display area on which a plurality of gate lines parallel to each other are disposed; a first non-display area and a second non-display area respectively located in opposite directions of the display area a first driving circuit is disposed in the first non-display area and operates according to a first group of control signals, wherein the first driving circuit comprises a plurality of serially connected first shifting temporary storage units, respectively Driving a corresponding odd gate line of the plurality of gate lines to display a first picture of the plurality of pictures; a second driving circuit disposed in the first non-display area and controlled according to a second group The second driving circuit includes a plurality of serially connected second shift temporary storage units for respectively driving the corresponding even number of gate lines of the plurality of gate lines to display the first picture; The third driving circuit is disposed in the second non-display area and operates according to a third group of control signals, wherein the third driving circuit comprises a plurality of serially connected third shift temporary storage units for respectively driving the phase Corresponding odd number The polar line is configured to display a second picture subsequent to the first picture in the plurality of pictures; and a fourth driving circuit is disposed in the second non-display area and operates according to a fourth group of control signals, The fourth driving circuit includes a fourth shift register unit of a plurality of stages connected to respectively drive the corresponding even number of gate lines to display the second picture.

本發明另提供一種液晶顯示裝置之驅動方法，包含以一第一驅動電路來驅動一閘極線以顯示複數個畫面中之一第一畫面；及關閉該第一驅動電路並以一第二驅動電路來驅動該閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面。The present invention further provides a driving method of a liquid crystal display device, comprising: driving a gate line with a first driving circuit to display one of the plurality of pictures; and turning off the first driving circuit and driving the second driving The circuit drives the gate line to display a second picture subsequent to the first picture in the plurality of pictures.

請參考第3圖，第3圖為本發明第一實施例中一液晶顯示裝置100之簡化方塊示意圖。第3圖僅顯示了液晶顯示裝置100之部分結構，包含複數條閘極線GL(1)～GL(N)、兩閘極驅動電路10和11，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置100之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10設於液晶顯示裝置100之非顯示區域40L內，其包含複數級移位暫存單元SR(1)～SR(N)，可依據時序控制器20所產生之起始脈衝訊號VST(1)和時脈訊號CK、XCK來分別輸出閘極驅動訊號GS(1)～GS(N)至相對應之閘極線GL(1)～GL(N)；閘極驅動電路11設於液晶顯示裝置100之非顯示區域40R內，其包含複數級移位暫存單元SR’(1)～SR’(N)，可依據時序控制器20所產生之起始脈衝訊號VST’(1)和時脈訊號CK’、XCK’來分別輸出閘極驅動訊號GS(1)～GS(N)至相對應之閘極線GL(1)～GL(N)。其中，非顯示區域40L和40R分別位於顯示區域30之兩對向側，且N為正整數。在第3圖中，顯示區域30和非顯示區域40L、40R之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置100中各元件之實際大小比例。Please refer to FIG. 3. FIG. 3 is a simplified block diagram of a liquid crystal display device 100 according to the first embodiment of the present invention. 3 shows only a part of the structure of the liquid crystal display device 100, and includes a plurality of gate lines GL(1) to GL(N), two gate driving circuits 10 and 11, and a timing controller 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 100, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10 is disposed in the non-display area 40L of the liquid crystal display device 100, and includes a plurality of stages of shift register units SR(1) to SR(N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST (1) and the clock signals CK and XCK respectively output the gate driving signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N); the gate driving circuit 11 is provided In the non-display area 40R of the liquid crystal display device 100, the plurality of shift register units SR'(1) to SR'(N) are included, and the start pulse signal VST' generated by the timing controller 20 can be used. And the clock signals CK', XCK' respectively output the gate drive signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, and N is a positive integer. In Fig. 3, the indication ranges of the display area 30 and the non-display areas 40L, 40R are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 100 of the present invention.

本發明第一實施例之液晶顯示裝置100採用雙邊佈局單端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10和11係分別設置於閘極線GL(1)～GL(N)之兩對向側，在顯示複數個畫面中一畫面F(N)時，閘極驅動訊號GS(1)～GS(N)由第3圖左側之閘極驅動電路10來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動訊號GS(1)～GS(N)由第3圖右側之閘極驅動電路11來提供(由虛線箭頭來表示)。The liquid crystal display device 100 of the first embodiment of the present invention adopts a double-sided layout single-ended driving architecture and is driven in a time-division manner. In other words, the gate driving circuits 10 and 11 are respectively disposed on the opposite sides of the gate lines GL(1) to GL(N), and when a screen F(N) is displayed in a plurality of pictures, the gate is The drive signals GS(1) to GS(N) are provided by the gate drive circuit 10 on the left side of FIG. 3 (indicated by solid arrows); the picture F(N+1) after the display of the subsequent screen F(N) At this time, the gate drive signals GS(1) to GS(N) are supplied from the gate drive circuit 11 on the right side of FIG. 3 (indicated by a broken line arrow).

請參考第4圖，第4圖為本發明第二實施例中一液晶顯示裝置200之簡化方塊示意圖。第4圖僅顯示了液晶顯示裝置200之部分結構，包含複數條閘極線GL(1)～GL(N)、兩閘極驅動電路10和11，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置200之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10設於液晶顯示裝置200之非顯示區域40內，其包含複數級移位暫存單元SR(1)～SR(N)，可依據時序控制器20所產生之起始脈衝訊號VST(1)和時脈訊號CK、XCK來分別輸出閘極驅動訊號GS(1)～GS(N)至相對應之閘極線GL(1)～GL(N)；閘極驅動電路11亦設於液晶顯示裝置200之非顯示區域40內，其包含複數級移位暫存單元SR’(1)～SR’(N)，可依據時序控制器20所產生之起始脈衝訊號VST’(1)和時脈訊號CK’、XCK’來分別輸出閘極驅動訊號GS(1)～GS(N)至相對應之閘極線GL(1)～GL(N)，其中N為正整數。在第4圖中，顯示區域30和非顯示區域40之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置200中各元件之實際大小比例。Please refer to FIG. 4, which is a simplified block diagram of a liquid crystal display device 200 according to a second embodiment of the present invention. 4 shows only a part of the structure of the liquid crystal display device 200, and includes a plurality of gate lines GL(1) to GL(N), two gate driving circuits 10 and 11, and a timing controller 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 200, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10 is disposed in the non-display area 40 of the liquid crystal display device 200, and includes a plurality of shift register units SR(1) to SR(N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST (1) and the clock signals CK and XCK respectively output the gate driving signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N); the gate driving circuit 11 also The non-display area 40 of the liquid crystal display device 200 includes a plurality of shift register units SR'(1) to SR'(N), which can be generated according to the start pulse signal VST' generated by the timing controller 20. 1) and the clock signals CK' and XCK' respectively output the gate drive signals GS(1) to GS(N) to the corresponding gate lines GL(1) to GL(N), where N is a positive integer. In Fig. 4, the indication ranges of the display area 30 and the non-display area 40 are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 200 of the present invention.

本發明第二實施例之液晶顯示裝置200採用單邊佈局單端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10和11皆設置於閘極線GL(1)～GL(N)之一側，並從同一側來驅動閘極線GL(1)～GL(N)。在顯示複數個畫面中一畫面F(N)時，閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動訊號GS(1)～GS(N)由閘極驅動電路11來提供(由虛線箭頭來表示)。The liquid crystal display device 200 of the second embodiment of the present invention adopts a single-sided layout single-ended driving architecture and is driven in a time-division manner. In other words, the gate drive circuits 10 and 11 are disposed on one side of the gate lines GL(1) to GL(N), and drive the gate lines GL(1) to GL(N) from the same side. When a picture F(N) is displayed in a plurality of pictures, the gate drive signals GS(1) to GS(N) are provided by the gate drive circuit 10 (indicated by solid arrows); on the display connection screen F ( When the picture F(N+1) after N), the gate drive signals GS(1) to GS(N) are supplied from the gate drive circuit 11 (indicated by a broken line arrow).

請參考第5圖，第5圖為本發明第一實施例之液晶顯示裝置100和本發明第二實施例之液晶顯示裝置200在運作時之時序圖。在閘極驅動電路10中，第一級移位暫存單元SR(1)依據時序控制器20所產生之起始脈衝訊號VST(1)來輸出第一級閘極驅動訊號GS(1)，而第二級至第N級移位暫存單元SR(2)～SR(N)則分別依據前一級移位暫存單元SR(1)～SR(N-1)所產生之起始脈衝訊號VST(2)～VST(N)來分別輸出第二級至第N級閘極驅動訊號GS(2)～GS(N)；在閘極驅動電路11中，第一級移位暫存單元SR’(1)依據時序控制器20所產生之起始脈衝訊號VST’(1)來輸出第一級閘極驅動訊號GS(1)，而第二級至第N級移位暫存單元SR’(2)～SR’(N)則分別依據前一級移位暫存單元SR’(1)～SR’(N-1)所產生之起始脈衝訊號VST’(2)～VST’(N)來輸出第二級至第N級閘極驅動訊號GS(2)～GS(N)。在本發明中之液晶顯示裝置100和200中，兩組閘極驅動電路10和11可依據不同畫面而交替地開啟和關閉，交替開關之週期可為一個或多個畫面。假設複數個畫面中兩相鄰畫面F(N)和F(N+1)之間為切換閘極驅動電路10和11之時間點，此時起始脈衝訊號VST(1)～VST(N)和VST’(1)～VST’(N)之時序圖如第5圖所示。Referring to FIG. 5, FIG. 5 is a timing chart showing the operation of the liquid crystal display device 100 of the first embodiment of the present invention and the liquid crystal display device 200 of the second embodiment of the present invention. In the gate driving circuit 10, the first stage shift register unit SR(1) outputs the first stage gate driving signal GS(1) according to the start pulse signal VST(1) generated by the timing controller 20. The second stage to the Nth stage shift register units SR(2) to SR(N) are respectively based on the start pulse signals generated by the previous stage shift register units SR(1) to SR(N-1). VST(2) to VST(N) respectively output second to Nth gate drive signals GS(2) to GS(N); in the gate drive circuit 11, the first stage shift register unit SR '(1) outputs the first-stage gate drive signal GS(1) according to the start pulse signal VST'(1) generated by the timing controller 20, and the second-stage to N-th stage shift register unit SR' (2)~SR'(N) are based on the initial pulse signals VST'(2)~VST'(N) generated by the previous stage shift register units SR'(1) to SR'(N-1) The second to Nth gate drive signals GS(2) to GS(N) are output. In the liquid crystal display devices 100 and 200 of the present invention, the two sets of gate drive circuits 10 and 11 can be alternately turned on and off according to different screens, and the period of the alternate switch can be one or more pictures. Assume that between two adjacent pictures F(N) and F(N+1) in a plurality of pictures is the time point for switching the gate drive circuits 10 and 11, and the start pulse signals VST(1) to VST(N) at this time. The timing diagrams of VST'(1) to VST'(N) are shown in Figure 5.

請參考第6圖，第6圖為本發明第三實施例中一液晶顯示裝置300之簡化方塊示意圖。第6圖僅顯示了液晶顯示裝置300之部分結構，包含複數條閘極線GL(1)～GL(N)、四閘極驅動電路10A、10B、10A’和10B’，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置300之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10A設於液晶顯示裝置300之非顯示區域40L內，其包含複數級移位暫存單元SR_A(1)～SR_A(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A(1)和時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B設於液晶顯示裝置300之非顯示區域40L內，其包含複數級移位暫存單元SR_B(1)～SR_B(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B(1)和時脈訊號CKB、XCKB來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。閘極驅動電路10A’設於液晶顯示裝置300之非顯示區域40R內，其包含複數級移位暫存單元SR_A’(1)～SR_A’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A’(1)和時脈訊號CKA’、XCKA’來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B’設於液晶顯示裝置300之非顯示區域40R內，其包含複數級移位暫存單元SR_B’(1)～SR_B’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B’(1)和時脈訊號CKB’、XCKB’來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。其中，非顯示區域40L和40R分別位於顯示區域30之兩對向側，N和n為正整數，且N之值為2n。在第6圖中，顯示區域30和非顯示區域40L、40R之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置300中各元件之實際大小比例。Please refer to FIG. 6. FIG. 6 is a simplified block diagram of a liquid crystal display device 300 according to a third embodiment of the present invention. 6 shows only a part of the structure of the liquid crystal display device 300, and includes a plurality of gate lines GL(1) to GL(N), four gate driving circuits 10A, 10B, 10A', and 10B', and a timing controller. 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 300, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 300, and includes a plurality of shift register units SR_A(1) to SR_A(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_A(1) and clock signals CKA and XCKA respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding odd gate lines GL (1), GL(3), ..., GL(N-1). The gate driving circuit 10B is disposed in the non-display area 40L of the liquid crystal display device 300, and includes a plurality of shift register units SR_B(1) to SR_B(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_B(1) and clock signals CKB and XCKB respectively output even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to corresponding even-numbered gate lines GL(2) ), GL(4), ..., GL(N). The gate driving circuit 10A' is disposed in the non-display area 40R of the liquid crystal display device 300, and includes a plurality of stages of shift register units SR_A'(1) to SR_A'(n), which can be generated according to the timing controller 20. The start pulse signal VST_A'(1) and the clock signals CKA', XCKA' respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding ones Odd gate lines GL(1), GL(3), ..., GL(N-1). The gate driving circuit 10B' is disposed in the non-display area 40R of the liquid crystal display device 300, and includes a plurality of stages of shift register units SR_B'(1) to SR_B'(n), which can be generated according to the timing controller 20. The start pulse signal VST_B' (1) and the clock signals CKB', XCKB' respectively output the even-numbered gate drive signals GS (2), GS (4), ..., GS (N) to the corresponding even number Gate lines GL(2), GL(4), ..., GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, N and n are positive integers, and the value of N is 2n. In Fig. 6, the display range of the display area 30 and the non-display areas 40L, 40R is only for explaining the position of each element, and does not limit the actual size ratio of each element in the liquid crystal display device 300 of the present invention.

本發明第三實施例之液晶顯示裝置300採用雙邊佈局單端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10A和10B設置於閘極線GL(1)～GL(N)之一側，閘極驅動電路10A’和10B’設置於閘極線GL(1)～GL(N)之另一側，但顯示畫面時僅會開啟設置於閘極線GL(1)～GL(N)其中一側之閘極驅動電路。舉例來說，在顯示複數個畫面中一畫面F(N)時，閘極驅動電路10A和10B為開啟，而閘極驅動電路10A’和10B’為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A和10B來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動電路10A’和10B’為開啟，而閘極驅動電路10A和10B為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A’和10B’來提供(由虛線箭頭來表示)。The liquid crystal display device 300 of the third embodiment of the present invention adopts a double-sided layout single-ended driving architecture and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10B are disposed on one side of the gate lines GL(1) to GL(N), and the gate driving circuits 10A' and 10B' are disposed on the gate lines GL(1) to GL. On the other side of (N), only the gate driving circuit provided on one side of the gate lines GL(1) to GL(N) is turned on when the screen is displayed. For example, when one screen F(N) is displayed in a plurality of pictures, the gate driving circuits 10A and 10B are turned on, and the gate driving circuits 10A' and 10B' are turned off, and the gate driving signal GS (1) ) GS (N) is provided by the gate drive circuits 10A and 10B (indicated by solid arrows); when the screen F (N+1) after the subsequent picture F (N) is displayed, the gate drive circuit 10A' And 10B' are turned on, and the gate driving circuits 10A and 10B are turned off, at which time the gate driving signals GS(1) to GS(N) are provided by the gate driving circuits 10A' and 10B' (indicated by dotted arrows) ).

請參考第7圖，第7圖為本發明第四實施例中一液晶顯示裝置400之簡化方塊示意圖。第7圖僅顯示了液晶顯示裝置400之部分結構，包含複數條閘極線GL(1)～GL(N)、四閘極驅動電路10A、10B、10A’和10B’，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置400之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10A設於液晶顯示裝置400之非顯示區域40L內，其包含複數級移位暫存單元SR_A(1)～SR_A(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A(1)和時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B設於液晶顯示裝置400之非顯示區域40R內，其包含複數級移位暫存單元SR_B(1)～SR_B(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B(1)和時脈訊號CKB、XCKB來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。閘極驅動電路10A’設於液晶顯示裝置400之非顯示區域40R內，其包含複數級移位暫存單元SR_A’(1)～SR_A’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A’(1)和時脈訊號CKA’、XCKA’來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B’設於液晶顯示裝置400之非顯示區域40L內，其包含複數級移位暫存單元SR_B’(1)～SR_B’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B’(1)和時脈訊號CKB’、XCKB’來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。其中，非顯示區域40L和40R分別位於顯示區域30之兩對向側，N和n為正整數，且N之值為2n。在第7圖中，顯示區域30和非顯示區域40L、40R之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置400中各元件之實際大小比例。Please refer to FIG. 7. FIG. 7 is a simplified block diagram of a liquid crystal display device 400 according to a fourth embodiment of the present invention. FIG. 7 shows only a part of the structure of the liquid crystal display device 400, including a plurality of gate lines GL(1) to GL(N), four gate driving circuits 10A, 10B, 10A', and 10B', and a timing controller. 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 400, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 400, and includes a plurality of stages of shift register units SR_A(1) to SR_A(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_A(1) and clock signals CKA and XCKA respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding odd gate lines GL (1), GL(3), ..., GL(N-1). The gate driving circuit 10B is disposed in the non-display area 40R of the liquid crystal display device 400, and includes a plurality of shift register units SR_B(1) to SR_B(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_B(1) and clock signals CKB and XCKB respectively output even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to corresponding even-numbered gate lines GL(2) ), GL(4), ..., GL(N). The gate driving circuit 10A' is disposed in the non-display area 40R of the liquid crystal display device 400, and includes a plurality of stages of shift register units SR_A'(1) to SR_A'(n), which can be generated according to the timing controller 20. The start pulse signal VST_A'(1) and the clock signals CKA', XCKA' respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding ones Odd gate lines GL(1), GL(3), ..., GL(N-1). The gate driving circuit 10B' is disposed in the non-display area 40L of the liquid crystal display device 400, and includes a plurality of stages of shift register units SR_B'(1) to SR_B'(n), which can be generated according to the timing controller 20. The start pulse signal VST_B' (1) and the clock signals CKB', XCKB' respectively output the even-numbered gate drive signals GS (2), GS (4), ..., GS (N) to the corresponding even number Gate lines GL(2), GL(4), ..., GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, N and n are positive integers, and the value of N is 2n. In Fig. 7, the indication ranges of the display area 30 and the non-display areas 40L, 40R are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 400 of the present invention.

本發明第四實施例之液晶顯示裝置400採用雙邊佈局雙端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10A和10A’分別設置於閘極線GL(1)～GL(N)之兩對向側，而閘極驅動電路10B和10B’分別設置於閘極線GL(1)～GL(N)之兩對向側，但顯示畫面時僅會在閘極線GL(1)～GL(N)之兩側各開啟一閘極驅動電路。舉例來說，在顯示複數個畫面中一畫面F(N)時，閘極驅動電路10A和10B為開啟，而閘極驅動電路10A’和10B’為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A和10B來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動電路10A’和10B’為開啟，而閘極驅動電路10A和10B為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A’和10B’來提供(由虛線箭頭來表示)。The liquid crystal display device 400 of the fourth embodiment of the present invention adopts a double-sided layout structure of bilateral layout, and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10A' are respectively disposed on the opposite sides of the gate lines GL(1) to GL(N), and the gate driving circuits 10B and 10B' are respectively disposed on the gate lines GL. (1) ~ GL (N) on the opposite side, but when the screen is displayed, only one gate drive circuit is turned on on both sides of the gate lines GL(1) to GL(N). For example, when one screen F(N) is displayed in a plurality of pictures, the gate driving circuits 10A and 10B are turned on, and the gate driving circuits 10A' and 10B' are turned off, and the gate driving signal GS (1) ) GS (N) is provided by the gate drive circuits 10A and 10B (indicated by solid arrows); when the screen F (N+1) after the subsequent picture F (N) is displayed, the gate drive circuit 10A' And 10B' are turned on, and the gate driving circuits 10A and 10B are turned off, at which time the gate driving signals GS(1) to GS(N) are provided by the gate driving circuits 10A' and 10B' (indicated by dotted arrows) ).

請參考第8圖，第8圖為本發明第五實施例中一液晶顯示裝置500之簡化方塊示意圖。第8圖僅顯示了液晶顯示裝置500之部分結構，包含複數條閘極線GL(1)～GL(N)、四閘極驅動電路10A、10B、10A’和10B’，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置500之顯示區域30內，可分別依據閘極驅動訊號GS(1)～GS(N)來驅動畫素。閘極驅動電路10A設於液晶顯示裝置500之非顯示區域40L內，其包含複數級移位暫存單元SR_A(1)～SR_A(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A(1)和時脈訊號CKA、XCKA來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B設於液晶顯示裝置500之非顯示區域40R內，其包含複數級移位暫存單元SR_B(1)～SR_B(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B(1)和時脈訊號CKB、XCKB來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。閘極驅動電路10A’設於液晶顯示裝置500之非顯示區域40L內，其包含複數級移位暫存單元SR_A’(1)～SR_A’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_A’(1)和時脈訊號CKA’、XCKA’來分別輸出奇數級閘極驅動訊號GS(1)、GS(3)、...、GS(N-1)至相對應之奇數條閘極線GL(1)、GL(3)、...、GL(N-1)。閘極驅動電路10B’設於液晶顯示裝置500之非顯示區域40R內，其包含複數級移位暫存單元SR_B’(1)～SR_B’(n)，可依據時序控制器20所產生之起始脈衝訊號VST_B’(1)和時脈訊號CKB’、XCKB’來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)至相對應之偶數條閘極線GL(2)、GL(4)、...、GL(N)。其中，非顯示區域40L和40R分別位於顯示區域30之兩對向側，N和n為正整數，且N之值為2n。在第8圖中，顯示區域30和非顯示區域40L、40R之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置500中各元件之實際大小比例。Please refer to FIG. 8. FIG. 8 is a simplified block diagram of a liquid crystal display device 500 according to a fifth embodiment of the present invention. 8 shows only a part of the structure of the liquid crystal display device 500, and includes a plurality of gate lines GL(1) to GL(N), four gate driving circuits 10A, 10B, 10A', and 10B', and a timing controller. 20. The gate lines GL(1) to GL(N) are provided in the display region 30 of the liquid crystal display device 500, and the pixels can be driven in accordance with the gate driving signals GS(1) to GS(N), respectively. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 500, and includes a plurality of stages of shift register units SR_A(1) to SR_A(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_A(1) and clock signals CKA and XCKA respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding odd gate lines GL (1), GL(3), ..., GL(N-1). The gate driving circuit 10B is disposed in the non-display area 40R of the liquid crystal display device 500, and includes a plurality of stages of shift register units SR_B(1) to SR_B(n), which can be generated according to the start pulse signal generated by the timing controller 20. VST_B(1) and clock signals CKB and XCKB respectively output even-numbered gate drive signals GS(2), GS(4), ..., GS(N) to corresponding even-numbered gate lines GL(2) ), GL(4), ..., GL(N). The gate driving circuit 10A' is disposed in the non-display area 40L of the liquid crystal display device 500, and includes a plurality of stages of shift register units SR_A'(1) to SR_A'(n), which can be generated according to the timing controller 20. The start pulse signal VST_A'(1) and the clock signals CKA', XCKA' respectively output odd-numbered gate drive signals GS(1), GS(3), ..., GS(N-1) to corresponding ones Odd gate lines GL(1), GL(3), ..., GL(N-1). The gate driving circuit 10B' is disposed in the non-display area 40R of the liquid crystal display device 500, and includes a plurality of stages of shift register units SR_B'(1) to SR_B'(n), which can be generated according to the timing controller 20. The start pulse signal VST_B' (1) and the clock signals CKB', XCKB' respectively output the even-numbered gate drive signals GS (2), GS (4), ..., GS (N) to the corresponding even number Gate lines GL(2), GL(4), ..., GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, N and n are positive integers, and the value of N is 2n. In Fig. 8, the indication ranges of the display area 30 and the non-display areas 40L, 40R are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 500 of the present invention.

本發明第五實施例之液晶顯示裝置500採用雙邊佈局雙端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10A和10A’設置於閘極線GL(1)～GL(N)之一側，而閘極驅動電路10B和10B’則設置於閘極線GL(1)～GL(N)之另一側，但顯示畫面時僅會在閘極線GL(1)～GL(N)之兩側各開啟一閘極驅動電路。舉例來說，在顯示複數個畫面中一畫面F(N)時，閘極驅動電路10A和10B為開啟，而閘極驅動電路10A’和10B’為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A和10B來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動電路10A’和10B’為開啟，而閘極驅動電路10A和10B為關閉，此時閘極驅動訊號GS(1)～GS(N)由閘極驅動電路10A’和10B’來提供(由虛線箭頭來表示)。The liquid crystal display device 500 of the fifth embodiment of the present invention adopts a double-sided layout of a double-sided layout and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10A' are disposed on one side of the gate lines GL(1) to GL(N), and the gate driving circuits 10B and 10B' are disposed on the gate line GL(1). On the other side of ～GL(N), a gate drive circuit is turned on only on both sides of the gate lines GL(1) to GL(N) when the screen is displayed. For example, when one screen F(N) is displayed in a plurality of pictures, the gate driving circuits 10A and 10B are turned on, and the gate driving circuits 10A' and 10B' are turned off, and the gate driving signal GS (1) ) GS (N) is provided by the gate drive circuits 10A and 10B (indicated by solid arrows); when the screen F (N+1) after the subsequent picture F (N) is displayed, the gate drive circuit 10A' And 10B' are turned on, and the gate driving circuits 10A and 10B are turned off, at which time the gate driving signals GS(1) to GS(N) are provided by the gate driving circuits 10A' and 10B' (indicated by dotted arrows) ).

請參考第9圖，第9圖為本發明第三實施例之液晶顯示裝置300、本發明第四實施例之液晶顯示裝置400以及本發明第五實施例之液晶顯示裝置500在運作時之時序圖。在閘極驅動電路10A中，移位暫存單元SR_A(1)依據時序控制器20所產生之起始脈衝訊號VST_A(1)來輸出第一級閘極驅動訊號GS(1)，而移位暫存單元SR_A(2)～SR_A(n)則分別依據前一級移位暫存單元SR_A(1)～SR_A(n-1)所產生之起始脈衝訊號VST_A(2)～VST_A(n)來分別輸出奇數級閘極驅動訊號GS(3)、GS(5)、...、GS(N-1)。在閘極驅動電路10B中，移位暫存單元SR_B(1)依據時序控制器20所產生之起始脈衝訊號VST_B(1)來輸出第二級閘極驅動訊號GS(2)，而移位暫存單元SR_B(2)～SR_B(n)則分別依據前一級移位暫存單元SR_B(1)～SR_B(n-1)所產生之起始脈衝訊號VST_B(2)～VST_B(n)來分別輸出偶數級閘極驅動訊號GS(2)、GS(4)、...、GS(N)。在閘極驅動電路10A’中，移位暫存單元SR_A’(1)依據時序控制器20所產生之起始脈衝訊號VST_A’(1)來輸出第一級閘極驅動訊號GS(1)，而移位暫存單元SR_A’(2)～SR_A’(n)則分別依據前一級移位暫存單元SR_A’(1)～SR_A’(n-1)所產生之起始脈衝訊號VST_A’(2)～VST_A’(n)來分別輸出奇數級閘極驅動訊號GS(3)、GS(5)、...、GS(N-1)。在閘極驅動電路10B’中，移位暫存單元SR_B’(1)依據時序控制器20所產生之起始脈衝訊號VST_B’(1)來輸出第二級閘極驅動訊號GS(2)，而移位暫存單元SR_B(2)～SR_B(n)則分別依據前一級移位暫存單元SR_B’(1)～SR_B’(n-1)所產生之起始脈衝訊號VST_B’(2)～VST_B’(n)來分別輸出偶數級閘極驅動訊號GS(4)、GS(6)、...、GS(N)。在本發明中之液晶顯示裝置300、400和500中，閘極驅動電路10A/10B和閘極驅動電路10A’/10B’可依據不同畫面而交替地開啟和關閉，交替開關之週期可為一個或多個畫面。假設複數個畫面中兩相鄰畫面F(N)和F(N+1)之間為切換閘極驅動電路10A/10B和閘極驅動電路10A’/10B’之時間點，此時起始脈衝訊號VST_A(1)～VST_A(n)、VST_B(1)～VST_B(n)、VST_A’(1)～VST_A’(n)、和VST_B’(1)～VST_B’(n)之時序圖如第9圖所示。Please refer to FIG. 9. FIG. 9 is a timing chart of the liquid crystal display device 300 according to the third embodiment of the present invention, the liquid crystal display device 400 according to the fourth embodiment of the present invention, and the liquid crystal display device 500 according to the fifth embodiment of the present invention. Figure. In the gate driving circuit 10A, the shift register unit SR_A(1) outputs the first-stage gate driving signal GS(1) according to the start pulse signal VST_A(1) generated by the timing controller 20, and shifts. The temporary storage units SR_A(2) to SR_A(n) are respectively based on the start pulse signals VST_A(2) to VST_A(n) generated by the previous stage shift temporary storage units SR_A(1) to SR_A(n-1). The odd-numbered gate drive signals GS(3), GS(5), ..., GS(N-1) are respectively output. In the gate driving circuit 10B, the shift register unit SR_B(1) outputs the second-stage gate driving signal GS(2) according to the start pulse signal VST_B(1) generated by the timing controller 20, and shifts The temporary storage units SR_B(2) to SR_B(n) are respectively based on the start pulse signals VST_B(2) to VST_B(n) generated by the previous stage shift register units SR_B(1) to SR_B(n-1). The even-numbered gate drive signals GS(2), GS(4), ..., GS(N) are output separately. In the gate driving circuit 10A', the shift register unit SR_A'(1) outputs the first-stage gate driving signal GS(1) according to the start pulse signal VST_A'(1) generated by the timing controller 20. The shift register units SR_A'(2) to SR_A'(n) are respectively based on the start pulse signal VST_A' generated by the previous stage shift register units SR_A'(1) to SR_A'(n-1) ( 2) ~ VST_A'(n) to output odd-numbered gate drive signals GS(3), GS(5), ..., GS(N-1), respectively. In the gate driving circuit 10B', the shift register unit SR_B'(1) outputs the second-stage gate driving signal GS(2) according to the start pulse signal VST_B'(1) generated by the timing controller 20. The shift register units SR_B(2) to SR_B(n) are respectively based on the start pulse signal VST_B' (2) generated by the previous stage shift register units SR_B'(1) to SR_B'(n-1). ~VST_B'(n) outputs the even-numbered gate drive signals GS(4), GS(6), ..., GS(N), respectively. In the liquid crystal display devices 300, 400 and 500 of the present invention, the gate driving circuit 10A/10B and the gate driving circuit 10A'/10B' may be alternately turned on and off according to different screens, and the period of the alternating switching may be one. Or multiple screens. It is assumed that between two adjacent pictures F(N) and F(N+1) in a plurality of pictures is a time point at which the gate driving circuit 10A/10B and the gate driving circuit 10A'/10B' are switched, and the start pulse is at this time. Timing diagrams of signals VST_A(1) to VST_A(n), VST_B(1) to VST_B(n), VST_A'(1) to VST_A'(n), and VST_B'(1) to VST_B'(n) Figure 9 shows.

請參考第10圖，第10圖為本發明第六實施例中一液晶顯示裝置600之簡化方塊示意圖。第10圖僅顯示了液晶顯示裝置600之部分結構，包含複數條閘極線GL(1)～GL(N)、四閘極驅動電路10A、10B、10A’和10B’，以及一時序控制器20。閘極線GL(1)～GL(N)設於液晶顯示裝置600之顯示區域30內，可分別依據閘極驅動訊號GS_A(1)～GS_A(N)和GS_B(1)～GS_B(N)來驅動畫素。閘極驅動電路10A設於液晶顯示裝置600之非顯示區域40L內，其包含複數級移位暫存單元SR_A(1)～SR_A(N)，可依據時序控制器20所產生之起始脈衝訊號VST_A(1)和時脈訊號CKA、XCKA來分別輸出閘極驅動訊號GS_A(1)～GS_A(N)至相對應之閘極線GL(1)～GL(N)。閘極驅動電路10B設於液晶顯示裝置600之非顯示區域40R內，其包含複數級移位暫存單元SR_B(1)～SR_B(N)，可依據時序控制器20所產生之起始脈衝訊號VST_B(1)和時脈訊號CKB、XCKB來分別輸出閘極驅動訊號GS_B(1)～GS_B(N)至相對應之閘極線GL(1)～GL(N)。閘極驅動電路10A’設於液晶顯示裝置600之非顯示區域40L內，其包含複數級移位暫存單元SR_A’(1)～SR_A’(N)，可依據時序控制器20所產生之起始脈衝訊號VST_A’(1)和時脈訊號CKA’、XCKA’來分別輸出閘極驅動訊號GS_A(1)～GS_A(N)至相對應之閘極線GL(1)～GL(N)。閘極驅動電路10B’設於液晶顯示裝置600之非顯示區域40R內，其包含複數級移位暫存單元SR_B’(1)～SR_B’(N)，可依據時序控制器20所產生之起始脈衝訊號VST_B’(1)和時脈訊號CKB’、XCKB’來分別輸出閘極驅動訊號GS_B(1)～GS_B(N)至相對應之閘極線GL(1)～GL(N)。其中，非顯示區域40L和40R分別位於顯示區域30之兩對向側，而N為正整數。在第10圖中，顯示區域30和非顯示區域40L、40R之標示範圍僅為了說明各元件之位置，並不限定本發明液晶顯示裝置600中各元件之實際大小比例。Please refer to FIG. 10, which is a simplified block diagram of a liquid crystal display device 600 according to a sixth embodiment of the present invention. FIG. 10 shows only a part of the structure of the liquid crystal display device 600, including a plurality of gate lines GL(1) to GL(N), four gate driving circuits 10A, 10B, 10A', and 10B', and a timing controller. 20. The gate lines GL(1) to GL(N) are disposed in the display region 30 of the liquid crystal display device 600, and can be respectively driven according to the gate driving signals GS_A(1) to GS_A(N) and GS_B(1) to GS_B(N). To drive the pixels. The gate driving circuit 10A is disposed in the non-display area 40L of the liquid crystal display device 600, and includes a plurality of stages of shift register units SR_A(1) to SR_A(N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST_A(1) and the clock signals CKA and XCKA respectively output the gate drive signals GS_A(1) to GS_A(N) to the corresponding gate lines GL(1) to GL(N). The gate driving circuit 10B is disposed in the non-display area 40R of the liquid crystal display device 600, and includes a plurality of shift register units SR_B(1) to SR_B(N), which can be generated according to the start pulse signal generated by the timing controller 20. The VST_B(1) and the clock signals CKB and XCKB respectively output the gate drive signals GS_B(1) to GS_B(N) to the corresponding gate lines GL(1) to GL(N). The gate driving circuit 10A' is disposed in the non-display area 40L of the liquid crystal display device 600, and includes a plurality of stages of shift register units SR_A'(1) to SR_A'(N), which can be generated according to the timing controller 20. The start pulse signal VST_A'(1) and the clock signals CKA' and XCKA' respectively output the gate drive signals GS_A(1) to GS_A(N) to the corresponding gate lines GL(1) to GL(N). The gate driving circuit 10B' is disposed in the non-display area 40R of the liquid crystal display device 600, and includes a plurality of stages of shift register units SR_B'(1) to SR_B'(N), which can be generated according to the timing controller 20. The start pulse signal VST_B'(1) and the clock signals CKB' and XCKB' respectively output the gate drive signals GS_B(1) to GS_B(N) to the corresponding gate lines GL(1) to GL(N). The non-display areas 40L and 40R are respectively located on opposite sides of the display area 30, and N is a positive integer. In Fig. 10, the indication ranges of the display area 30 and the non-display areas 40L, 40R are only for explaining the positions of the respective elements, and do not limit the actual size ratio of each element in the liquid crystal display device 600 of the present invention.

本發明第六實施例之液晶顯示裝置600採用雙邊佈局雙端驅動之架構，並以分時啟動的方式來驅動。換而言之，閘極驅動電路10A和10B分別設置於閘極線GL(1)～GL(N)之兩對向側，而閘極驅動電路10A’和10B’分別設置於閘極線GL(1)～GL(N)之兩對向側，顯示畫面時會在閘極線GL(1)～GL(N)之兩側皆各開啟一閘極驅動電路。舉例來說，在顯示複數個畫面中一畫面F(N)時，閘極驅動電路10A和10B為開啟，而閘極驅動電路10A’和10B’為關閉，此時閘極驅動訊號GS_A(1)～GS_A(N)和GS_B(1)～GS_B(N)分別由閘極驅動電路10A和10B來提供(由實線箭頭來表示)；在顯示接續畫面F(N)之後的畫面F(N+1)時，閘極驅動電路10A’和10B’為開啟，而閘極驅動電路10A和10B為關閉，此時閘極驅動訊號GS_A(1)～GS_A(N)和GS_B(1)～GS_B(N)分別由閘極驅動電路10A’和10B’來提供(由虛線箭頭來表示)。The liquid crystal display device 600 of the sixth embodiment of the present invention adopts a double-sided layout structure of bilateral layout, and is driven in a time-division manner. In other words, the gate driving circuits 10A and 10B are respectively disposed on the opposite sides of the gate lines GL(1) to GL(N), and the gate driving circuits 10A' and 10B' are respectively disposed on the gate lines GL. On the opposite side of (1) to GL(N), a gate drive circuit is turned on on both sides of the gate lines GL(1) to GL(N) when the screen is displayed. For example, when one screen F(N) is displayed in a plurality of pictures, the gate driving circuits 10A and 10B are turned on, and the gate driving circuits 10A' and 10B' are turned off, and the gate driving signal GS_A (1) ) GS_A (N) and GS_B (1) to GS_B (N) are provided by the gate drive circuits 10A and 10B, respectively (indicated by solid arrows); the picture F (N) after the display of the subsequent screen F(N) When +1), the gate driving circuits 10A' and 10B' are turned on, and the gate driving circuits 10A and 10B are turned off. At this time, the gate driving signals GS_A(1) to GS_A(N) and GS_B(1) to GS_B are turned off. (N) is provided by gate drive circuits 10A' and 10B', respectively (indicated by dashed arrows).

請參考第11圖，第11圖為本發明第六實施例之液晶顯示裝置600在運作時之時序圖。在閘極驅動電路10A中，移位暫存單元SR_A(1)依據時序控制器20所產生之起始脈衝訊號VST_A(1)來輸出閘極驅動訊號GS_A(1)，而移位暫存單元SR_A(2)～SR_A(N)則分別依據前一級移位暫存單元SR_A(1)～SR_A(N-1)所產生之起始脈衝訊號VST_A(2)～VST_A(N)來分別輸出閘極驅動訊號GS_A(2)～GS_A(N)。在閘極驅動電路10B中，移位暫存單元SR_B(1)依據時序控制器20所產生之起始脈衝訊號VST_B(1)來輸出閘極驅動訊號GS_B(1)，而移位暫存單元SR_B(2)～SR_B(N)則分別依據前一級移位暫存單元SR_B(1)～SR_B(N-1)所產生之起始脈衝訊號VST_B(2)～VST_B(N)來分別輸出GS_B(2)～GS_B(N)。在閘極驅動電路10A’中，移位暫存單元SR_A’(1)依據時序控制器20所產生之起始脈衝訊號VST_A’(1)來輸出閘極驅動訊號GS_A(1)，而移位暫存單元SR_A’(2)～SR_A’(N)則分別依據前一級移位暫存單元SR_A’(1)～SR_A’(N-1)所產生之起始脈衝訊號VST_A’(2)～VST_A’(N)來分別輸出閘極驅動訊號GS_A(2)～GS_A(N)。在閘極驅動電路10B’中，移位暫存單元SR_B’(1)依據時序控制器20所產生之起始脈衝訊號VST_B’(1)來輸出閘極驅動訊號GS_B(1)，而移位暫存單元SR_B’(2)～SR_B’(N)則分別依據前一級移位暫存單元SR_B’(1)～SR_B’(N-1)所產生之起始脈衝訊號VST_B’(2)～VST_B’(N)來分別輸出GS_B(2)～GS_B(N)。在本發明中之液晶顯示裝置600中，閘極驅動電路10A/10B和閘極驅動電路10A’/10B’可依據不同畫面而交替地開啟和關閉，交替開關之週期可為一個或多個畫面。假設複數個畫面中兩相鄰畫面F(N)和F(N+1)之間為切換閘極驅動電路10A/10B和閘極驅動電路10A’/10B’之時間點，此時起始脈衝訊號VST_A(1)～VST_A(N)、VST_B(1)～VST_B(N)、VST_A’(1)～VST_A’(N)、和VST_B’(1)～VST_B’(N)之時序圖如第11圖所示。Please refer to FIG. 11, which is a timing chart of the liquid crystal display device 600 according to the sixth embodiment of the present invention. In the gate driving circuit 10A, the shift register unit SR_A(1) outputs the gate driving signal GS_A(1) according to the start pulse signal VST_A(1) generated by the timing controller 20, and shifts the temporary storage unit. SR_A(2)~SR_A(N) respectively output the gates according to the start pulse signals VST_A(2) to VST_A(N) generated by the previous stage shift register units SR_A(1) to SR_A(N-1). The pole drive signals GS_A(2) to GS_A(N). In the gate driving circuit 10B, the shift register unit SR_B(1) outputs the gate driving signal GS_B(1) according to the start pulse signal VST_B(1) generated by the timing controller 20, and shifts the temporary storage unit. SR_B(2) to SR_B(N) respectively output GS_B according to the start pulse signals VST_B(2) to VST_B(N) generated by the previous stage shift register units SR_B(1) to SR_B(N-1). (2) ~ GS_B (N). In the gate driving circuit 10A', the shift register unit SR_A'(1) outputs the gate driving signal GS_A(1) according to the start pulse signal VST_A'(1) generated by the timing controller 20, and shifts The temporary storage units SR_A'(2) to SR_A'(N) are respectively based on the start pulse signal VST_A'(2) generated by the previous stage shift register units SR_A'(1) to SR_A'(N-1). VST_A'(N) outputs gate drive signals GS_A(2) to GS_A(N), respectively. In the gate driving circuit 10B', the shift register unit SR_B'(1) outputs the gate driving signal GS_B(1) according to the start pulse signal VST_B'(1) generated by the timing controller 20, and shifts The temporary storage units SR_B'(2) to SR_B'(N) are respectively based on the start pulse signal VST_B'(2) generated by the previous stage shift register units SR_B'(1) to SR_B'(N-1). VST_B'(N) outputs GS_B(2) to GS_B(N), respectively. In the liquid crystal display device 600 of the present invention, the gate driving circuit 10A/10B and the gate driving circuit 10A'/10B' may be alternately turned on and off according to different screens, and the period of the alternating switching may be one or more pictures. . It is assumed that between two adjacent pictures F(N) and F(N+1) in a plurality of pictures is a time point at which the gate driving circuit 10A/10B and the gate driving circuit 10A'/10B' are switched, and the start pulse is at this time. Timing diagrams of signals VST_A(1) to VST_A(N), VST_B(1) to VST_B(N), VST_A'(1) to VST_A'(N), and VST_B'(1) to VST_B'(N) Figure 11 shows.

本發明利用多組閘極驅動電路以分時啟動之方式來驅動閘極線，可減少移位暫存單元內薄膜電晶體之閘極電壓應力，因此能增加液晶顯示器的使用期限與可靠度。The invention utilizes multiple sets of gate driving circuits to drive the gate lines in a time-division manner, which can reduce the gate voltage stress of the thin film transistor in the shift temporary storage unit, thereby increasing the service life and reliability of the liquid crystal display.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

20．．．時序控制器20. . . Timing controller

GL(1)～GL(N)．．．閘極線GL(1)～GL(N). . . Gate line

30．．．顯示區域30. . . Display area

40、40L、40R．．．非顯示區域40, 40L, 40R. . . Non-display area

10、11、10A、10A’、10B、10B’．．．閘極驅動電路10, 11, 10A, 10A', 10B, 10B'. . . Gate drive circuit

100、200、300、400、500、600、700‧‧‧液晶顯示裝置100, 200, 300, 400, 500, 600, 700‧‧‧ liquid crystal display devices

SR(1)、SR(2)、SR(N)、SR’(1)、SR’(2)、SR’(N)、SR_A(1)、SR_A(2)、SR_A(n)、SR_A(N)、SR_A’(1)、SR_A’(2)、SR_A’(n)、SR_A’(N)、SR_B(1)、SR_B(2)、SR_B(n)、SR_B(N)、SR_B’(1)、SR_B’(2)、SR_B’(n)、SR_B’(N)‧‧‧移位暫存單元SR(1), SR(2), SR(N), SR'(1), SR'(2), SR'(N), SR_A(1), SR_A(2), SR_A(n), SR_A( N), SR_A'(1), SR_A'(2), SR_A'(n), SR_A'(N), SR_B(1), SR_B(2), SR_B(n), SR_B(N), SR_B'( 1), SR_B'(2), SR_B'(n), SR_B'(N)‧‧‧ shift register unit

第1圖為先前技術中一液晶顯示裝置之簡化方塊示意圖。1 is a simplified block diagram of a prior art liquid crystal display device.

第2圖為第1圖之液晶顯示裝置在運作時之時序圖。Fig. 2 is a timing chart of the liquid crystal display device of Fig. 1 in operation.

第3圖為本發明第一實施例中一液晶顯示裝置之簡化方塊示意圖。Figure 3 is a simplified block diagram of a liquid crystal display device in the first embodiment of the present invention.

第4圖為本發明第二實施例中一液晶顯示裝置之簡化方塊示意圖。4 is a simplified block diagram of a liquid crystal display device in a second embodiment of the present invention.

第5圖為本發明第一和第二實施例之液晶顯示裝置在運作時之時序圖。Fig. 5 is a timing chart showing the operation of the liquid crystal display device of the first and second embodiments of the present invention.

第6圖為本發明第三實施例中一液晶顯示裝置之簡化方塊示意圖。Figure 6 is a simplified block diagram of a liquid crystal display device in a third embodiment of the present invention.

第7圖為本發明第四實施例中一液晶顯示裝置之簡化方塊示意圖。Figure 7 is a simplified block diagram of a liquid crystal display device in a fourth embodiment of the present invention.

第8圖為本發明第五實施例中一液晶顯示裝置之簡化方塊示意圖。Figure 8 is a simplified block diagram of a liquid crystal display device in a fifth embodiment of the present invention.

第9圖為本發明第三至第五實施例之液晶顯示裝置在運作時之時序圖。Fig. 9 is a timing chart showing the operation of the liquid crystal display device of the third to fifth embodiments of the present invention.

第10圖為本發明第六實施例中一液晶顯示裝置之簡化方塊示意圖。Figure 10 is a simplified block diagram of a liquid crystal display device in a sixth embodiment of the present invention.

第11圖為本發明第六實施例之液晶顯示裝置在運作時之時序圖。Figure 11 is a timing chart showing the operation of the liquid crystal display device of the sixth embodiment of the present invention.

20．．．時序控制器20. . . Timing controller

GL(1)～GL(N)．．．閘極線GL(1)～GL(N). . . Gate line

30．．．顯示區域30. . . Display area

40L、40R．．．非顯示區域40L, 40R. . . Non-display area

100．．．液晶顯示裝置100. . . Liquid crystal display device

10、11．．．閘極驅動電路10, 11. . . Gate drive circuit

SR(1)、SR(2)、SR(N)、SR’(1)、SR’(2)、SR’(N)．．．移位暫存單元SR(1), SR(2), SR(N), SR'(1), SR'(2), SR'(N). . . Shift register unit

Claims (14)

一種液晶顯示裝置，包含：一顯示區域，其上設有N條互相平行之閘極線，其中N為正整數；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，其依據一第一組控制訊號來運作，該第一驅動電路設於該第一非顯示區域內且包含N級串接之第一移位暫存單元，其中該N級第一移位暫存單元中一第n級第一移位暫存單元係用來驅動該N條閘極線中一相對應之第n條閘極線以在該顯示區域內顯示複數個畫面中之一第一畫面，且n為不大於N之正整數；及一第二驅動電路，其依據一第二組控制訊號來運作且包含N級串接之第二移位暫存單元，其中：該N級第二移位暫存單元中一第n級第二移位暫存單元係用來驅動該第n條閘極線以在該顯示區域內顯示該複數個畫面中接續於該第一畫面後之一第二畫面；當該顯示區域內顯示該第一畫面時，該第二驅動電路呈關閉；且當該顯示區域內顯示該第二畫面時，該第一驅動電路 呈關閉。 A liquid crystal display device comprising: a display area having N parallel gate lines, wherein N is a positive integer; a first non-display area and a second non-display area are respectively located in the display area Two opposite sides; a first driving circuit, which operates according to a first group of control signals, the first driving circuit is disposed in the first non-display area and includes a first shift register unit of N stages The nth stage first shift register unit of the Nth stage first shift register unit is configured to drive a corresponding nth gate line of the N gate lines to be in the display area Displaying a first picture of the plurality of pictures, and n is a positive integer not greater than N; and a second driving circuit that operates according to a second set of control signals and includes a second shift of the N-level series a temporary storage unit, wherein: an nth stage second shift register unit of the Nth stage second shift register unit is configured to drive the nth gate line to display the plurality of pictures in the display area a second screen connected to the first screen; the first screen is displayed in the display area The second driving circuit is turned off; and when the second picture is displayed in the display area, the first driving circuit Is closed. 如請求項1所述之液晶顯示裝置，其中該第二驅動電路設於該第一非顯示區域內。 The liquid crystal display device of claim 1, wherein the second driving circuit is disposed in the first non-display area. 如請求項1所述之液晶顯示裝置，其中該第二驅動電路設於該第二非顯示區域內。 The liquid crystal display device of claim 1, wherein the second driving circuit is disposed in the second non-display area. 如請求項1所述之液晶顯示裝置，另包含一控制電路，用來產生該第一組和第二組控制訊號。 The liquid crystal display device of claim 1, further comprising a control circuit for generating the first group and the second group of control signals. 一種液晶顯示裝置，包含：一顯示區域，其上設有複數條互相平行之閘極線；一第一非顯示區域和一第二非顯示區域，分別位於該顯示區域之兩對向側；一第一驅動電路，設於該第一非顯示區域內並依據一第一組控制訊號來運作，該第一驅動電路包含複數級串接之第一移位暫存單元，分別用來驅動該複數條閘極線中相對應之奇數條閘極線以在該顯示區域內顯示複數個畫面中之一第一畫面；一第二驅動電路，設於該第二非顯示區域內並依據一第二組控制訊號來運作，該第二驅動電路包含複數級串接之第二移位暫存單元，分別用來驅動該複數條閘極 線中相對應之偶數條閘極線以在該顯示區域內顯示該第一畫面；一第三驅動電路，其依據一第三組控制訊號來運作且包含複數級串接之第三移位暫存單元，分別用來驅動該相對應之奇數條閘極線以在該顯示區域內顯示該複數個畫面中接續於該第一畫面後之一第二畫面；及一第四驅動電路，其依據一第四組控制訊號來運作且包含複數級串接之第四移位暫存單元，分別用來驅動該相對應之偶數條閘極線以在該顯示區域內顯示該第二畫面，其中：當該顯示區域內顯示該第一畫面時，該第三驅動電路和該第四驅動電路呈關閉；且當該顯示區域內顯示該第二畫面時，該第一驅動電路和該第二驅動電路呈關閉。 A liquid crystal display device comprising: a display area on which a plurality of gate lines parallel to each other are disposed; a first non-display area and a second non-display area respectively located on opposite sides of the display area; The first driving circuit is disposed in the first non-display area and operates according to a first group of control signals, wherein the first driving circuit comprises a plurality of serially connected first shifting temporary storage units for respectively driving the plurality of Corresponding odd gate lines in the gate line display one of the plurality of pictures in the display area; a second driving circuit is disposed in the second non-display area and according to a second The group control signal is operated, and the second driving circuit comprises a plurality of serially connected second shift temporary storage units for driving the plurality of gates respectively Corresponding even-numbered gate lines in the line to display the first picture in the display area; a third driving circuit that operates according to a third group of control signals and includes a third stage of the plurality of stages a storage unit, configured to drive the corresponding odd gate lines to display a second picture subsequent to the first picture in the plurality of pictures in the display area; and a fourth driving circuit, based on a fourth group of control signals to operate and including a plurality of serially connected fourth shift register units for respectively driving the corresponding even number of gate lines to display the second picture in the display area, wherein: When the first picture is displayed in the display area, the third driving circuit and the fourth driving circuit are turned off; and when the second picture is displayed in the display area, the first driving circuit and the second driving circuit Is closed. 如請求項5所述之液晶顯示裝置，其中該第三驅動電路係設於該第一非顯示區域內，而該第四驅動電路係設於該第二非顯示區域內。 The liquid crystal display device of claim 5, wherein the third driving circuit is disposed in the first non-display area, and the fourth driving circuit is disposed in the second non-display area. 如請求項5所述之液晶顯示裝置，其中該第三驅動電路係設於該第二非顯示區域內，而該第四驅動電路係設於該第一非顯示區域內。 The liquid crystal display device of claim 5, wherein the third driving circuit is disposed in the second non-display area, and the fourth driving circuit is disposed in the first non-display area. 如請求項5所述之液晶顯示裝置，另包含一控制電路，用來產生該第一組至第四組控制訊號。 The liquid crystal display device of claim 5, further comprising a control circuit for generating the first group to the fourth group of control signals. 一種液晶顯示裝置之驅動方法，包含：以一第一驅動電路來驅動一閘極線以顯示複數個畫面中之一第一畫面；及關閉該第一驅動電路並以一第二驅動電路來驅動該閘極線以顯示該複數個畫面中接續於該第一畫面後之一第二畫面。 A driving method of a liquid crystal display device, comprising: driving a gate line with a first driving circuit to display one of a plurality of pictures; and turning off the first driving circuit and driving by a second driving circuit The gate line displays one of the plurality of pictures connected to the second picture after the first picture. 如請求項9所述之驅動方法，另包含：以該第一驅動電路來驅動該閘極線以顯示該複數個畫面中M個相鄰第一畫面；以及關閉該第一驅動電路並以該第二驅動電路來驅動該閘極線以顯示該複數個畫面中接續於該M個相鄰第一畫面後之N個相鄰第二畫面，其中M和N為正整數。 The driving method of claim 9, further comprising: driving the gate line with the first driving circuit to display M adjacent first pictures in the plurality of pictures; and turning off the first driving circuit and The second driving circuit drives the gate line to display N adjacent second pictures subsequent to the M adjacent first pictures in the plurality of pictures, where M and N are positive integers. 如請求項9所述之驅動方法，其中M和N之值相同。 The driving method of claim 9, wherein the values of M and N are the same. 如請求項9所述之驅動方法，其中該第一和第二驅動電路係從該閘極線之同一側來驅動該閘極線以分別顯示該第一和第二畫面。 The driving method of claim 9, wherein the first and second driving circuits drive the gate line from the same side of the gate line to respectively display the first and second screens. 如請求項9所述之驅動方法，其中該第一驅動電路係從該閘極線之第一側來驅動該閘極線以顯示該第一畫面，而該第二驅動電路係從該閘極線之第二側來驅動該閘極線以顯示該第二畫面。 The driving method of claim 9, wherein the first driving circuit drives the gate line from a first side of the gate line to display the first picture, and the second driving circuit is from the gate The second side of the line drives the gate line to display the second picture. 如請求項9所述之驅動方法，其中該第一驅動電路係從該閘極線之兩側來驅動該閘極線以顯示該第一畫面，而該第二驅動電路係從該閘極線之兩側來驅動該閘極線以顯示該第二畫面。 The driving method of claim 9, wherein the first driving circuit drives the gate line from both sides of the gate line to display the first picture, and the second driving circuit is from the gate line The two sides drive the gate line to display the second picture.
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