TWI409924B - 半導體封裝體及其製造方法 - Google Patents

半導體封裝體及其製造方法 Download PDF

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TWI409924B
TWI409924B TW096134069A TW96134069A TWI409924B TW I409924 B TWI409924 B TW I409924B TW 096134069 A TW096134069 A TW 096134069A TW 96134069 A TW96134069 A TW 96134069A TW I409924 B TWI409924 B TW I409924B
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carrier
semiconductor package
package
conductive film
patterned conductive
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TW096134069A
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English (en)
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TW200913194A (en
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Chia Fu Wu
Cheng Yin Lee
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Advanced Semiconductor Eng
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Priority to TW096134069A priority Critical patent/TWI409924B/zh
Priority to US12/208,881 priority patent/US20090065911A1/en
Publication of TW200913194A publication Critical patent/TW200913194A/zh
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Publication of TWI409924B publication Critical patent/TWI409924B/zh

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Description

半導體封裝體及其製造方法
本發明係關於一種關於封裝體及其製造方法，特別關於一種半導體封裝體及其製造方法。
隨著電子產品以小型化及高效率為導向，在半導體的技術發展中，係藉由提高半導體封裝裝置之容量及性能，以符合使用者之需求。因此，多晶片模組化(multi－chip module)成為近年來研究焦點之一，其係將兩個或複數個晶片以堆疊方式形成一半導體封裝體。然而，隨著堆疊的半導體封裝體體積增大，小型化亦成為重要課題，此外，如何避免半導體封裝體之電磁干擾(electromagnetic interference,EMI)亦是研究方向之一。
請參照圖1所示，一種習知之半導體封裝體1係包含一載板11、一晶片12以及一封裝材料13。晶片12係打線接合於載板11上，封裝材料13係包覆晶片12及載板11之一側。為防護電磁干擾，半導體封裝體1更具有一遮蔽體14，其係設置於封裝材料13之外圍並接地。然而，遮蔽體14不僅增加生產的成本，且遮蔽體14與載板11之間的結合力，也會因為時間而慢慢減弱，甚至造成遮蔽體14的脫離。此外，遮蔽體14也會增加半導體封裝體1的體積，而不利於小型化。
另外，其他的電子元件亦可設置於半導體封裝體1上而成為一堆疊架構。堆疊方式例如可先在封裝材料13上設置一導線架或基板，然後設置一個或複數個晶片或封裝體於導線架上。然而，導線架由於結構限制(線寬及厚度)且無法緊靠封裝材料13，故此種藉由導線架來堆疊之方式並不利於縮小半導體封裝體的尺寸。
因此，如何提供一種半導體封裝體及其製造方法，能夠減少堆疊之垂直高度並縮小半導體封裝體的尺寸，且能夠防護電磁干擾，已成為重要課題之一。
有鑑於上述課題，本發明之目的為提供一種能夠有效減少堆疊的垂直高度並縮小尺寸，且能防護電磁干擾之半導體封裝體及其製造方法。
緣是，為達上述目的，依本發明之一種半導體封裝體係包含一載板、至少一晶片、一封裝材料以及一圖案化導電薄膜。載板係具有一第一表面及第二表面，第一表面與第二表面相對設置。晶片設置於載板的第一表面，並與載板電性連接。封裝材料包覆晶片及載板的至少部分第一表面。圖案化導電薄膜係設置於封裝材料上，以電性連接至該載板。
為達上述目的，依本發明之一種半導體封裝體的製造方法係包含以下步驟：提供一封裝體，封裝體包含一載板、至少一晶片及一封裝材料，載板具有一第一表面及一第二表面，第一表面與第二表面相對設置，晶片設置於載板的第一表面，並與載板電性連接，封裝材料包覆晶片及載板的至少部分第一表面；以及形成一圖案化導電薄膜於封裝材料上，以電性連接至該載板。
承上所述，因依本發明之一種半導體封裝體及其製造方法係將一圖案化導電薄膜直接形成於封裝材料上，圖案化導電薄膜可與其他電子元件相堆疊及電性連接而形成堆疊的半導體封裝體。此外，部分圖案化導電薄膜亦可接地而具有防護電磁干擾的功效。與習知技術相較，本發明的圖案化導電薄膜並無習知導線架於結構上的限制，而能夠有效減少堆疊的垂直高度並縮小尺寸。
以下將參照相關圖式，說明依本發明較佳實施例之一種半導體封裝體及其製造方法，其中相同的元件將以相同的參照符號加以說明。
請參照圖2A所示，本發明較佳實施例之一種半導體封裝體2係包含一載板21、至少一晶片22、一封裝材料23以及一圖案化導電薄膜24。
載板21係具有一第一表面211及一第二表面212，第一表面211與第二表面212相對設置。晶片22係設置於載板21的第一表面211，並可以導電凸塊(flip－chip bonding)或銲線(wire bonding)與載板21電性連接，於此係以銲線接合為例。載板21的第二表面212具有複數個銲球(solderb all)213，用以與其他電子元件電性連接，例如與一電路板(圖未顯示)連接。封裝材料23係包覆晶片22及載板21的至少部分第一表面211。封裝材料23可為環氧樹脂(epoxy)或矽膠(silicone)。圖案化導電薄膜24係設置於封裝材料23上，並可延設至第一表面211，再經由載板21的導電孔(conductive via)，而與銲球213之至少其中之一電性連接。
請同時參照圖2A及圖2B所示，圖案化導電薄膜24係包含一線路圖樣241及一電磁防護圖樣242。線路圖樣241與第二表面212之未接地的銲球213之至少其中之一電性連接。電磁防護圖樣242可經由第二表面212之接地的銲球213電性連接而接地，以提供電磁遮蔽的效用。電磁防護圖樣242設置於線路圖樣241以外的位置。當然，電磁防護圖樣242亦可直接接地而不經由銲球213。此外，載板21可具有一線路重分佈層(圖未顯示)，線路圖樣241及電磁防護圖樣242可藉由線路重分佈層，而與對應的銲球213電性連接。
在本實施例中，並不限制線路圖樣241及電磁防護圖樣242的尺寸及形狀。圖案化導電薄膜24可形成於封裝材料23上的任意位置，並延設至載板21的第一表面211。
請參照圖3所示，本發明較佳實施例之一種半導體封裝體的製造方法係包含步驟S01至步驟S03。請同時參照圖3、圖4A及圖4B所示，以進一步說明半導體封裝體2的製造方法。
請參照圖3及圖4A所示，步驟S01係提供一封裝體。封裝體包含一載板21、至少一晶片22以及一封裝材料23。由於載板21、晶片22及封裝材料23之實施態樣已詳述於上，故不再贅述。
請參照圖3及圖4B所示，步驟S02係形成一圖案化導電薄膜24於封裝材料23上。圖案化導電薄膜24係可藉由沈積、塗佈、印刷或電鍍方式形成於封裝材料23上。其中，沈積可為物理沈積，例如濺鍍(sputtering)。本實施例之製造方法在形成圖案化導電薄膜24之前，可更包含形成一非平坦結構或一粗化結構於封裝材料23的外表面，以加強圖案化導電薄膜24與封裝材料23之間的結合力。非平坦結構例如為溝槽及/或凸部的組合，粗化結構例如為粗糙面。
然後，步驟S03係將圖案化導電薄膜24與銲球213至少其中之一電性連接，圖案化導電薄膜24與銲球213經由載板21的導電孔而電性連接。
本實施例之製造方法更包含一步驟：將圖案化導電薄膜24與至少一電子元件相堆疊及電性連接。在此並不限定電子元件的類別，例如電子元件可選自晶片、封裝體、多晶片模組(multi－chip module,MCM)、多封裝體模組(multi－package module,MPM)及其組合所構成的群組。以下說明圖案化導電薄膜24外接電子元件的不同變化態樣。
如圖5所示，一封裝體25係設置於半導體封裝體2上，而與圖案化導電薄膜24相堆疊及電性連接。封裝體25之部分銲球253可與圖案化導電薄膜24之線路圖樣241電性連接，另一部分銲球253可與圖案化導電薄膜24之電磁防護圖樣242電性連接。另外，可藉由另一封裝材料包覆半導體封裝體2及封裝體25，以提供保護作用。
如圖6所示，一晶片26例如以導電凸塊設置於半導體封裝體2上，而與圖案化導電薄膜24相堆疊及電性連接。晶片26之部分導電凸塊263可與圖案化導電薄膜24之線路圖樣241電性連接，另一部分導電凸塊263可與圖案化導電薄膜24之電磁防護圖樣242電性連接。製造方法可更包含一步驟：藉由另一封裝材料包覆晶片26及半導體封裝體2，以提供保護作用。
如圖7所示，一晶片27例如以導電凸塊設置於半導體封裝體2上，而與圖案化導電薄膜24電性連接。製造方法更包含一步驟：藉由另一封裝材料23a包覆半導體封裝體2之一部分並形成一凹穴，用以放置晶片27。封裝材料23a係裸露部份之圖案化導電薄膜24，並形成一凹穴，藉此裸露之圖案化導電薄膜24可用以選擇性相堆疊及電性連接各種電子元件，例如晶片27。
如圖8所示，一半導體封裝體2a的晶片22a係以導電凸塊設置於載板21上。一晶片28係以導電凸塊設置於半導體封裝體2a，並與其圖案化導電薄膜24電性連接。一封裝材料23b係包覆晶片28及半導體封裝體2a。一圖案化導電薄膜24b係設置於封裝材料23b上，並延設至載板21的第一表面211並與銲球213電性連接。
上述實施例之載板係以電路基板為例，另外，本發明之載板亦可為導線架。請參照圖9A所示，一種半導體封裝體3係包含一導線架31、一晶片32、一封裝材料33及一圖案化導電薄膜34。晶片32係以銲線電性連接於導線架31。封裝材料33係包覆晶片32及部分導線架31。圖案化導電薄膜34係設置在封裝材料33上並與導線架31電性連接。於此，導線架31係為一四方扁平無引腳封裝體(Quad Flat Non－leaded package,QFN)的導線架。
另外，請參照圖9B所示，一種半導體封裝體4係包含一導線架41、一晶片42、一封裝材料43及一圖案化導電薄膜44。晶片42係以銲線電性連接於導線架41。封裝材料43係包覆晶片32及部分導線架41。圖案化導電薄膜44係設置在封裝材料43上並與導線架41電性連接。於此，導線架41係為一四方扁平封裝體(Quad Flat Package,QFP)的導線架。
綜上所述，因依本發明之一種半導體封裝體及其製造方法係將一圖案化導電薄膜直接形成於封裝材料上，圖案化導電薄膜可與其他電子元件相堆疊及電性連接而形成堆疊的半導體封裝體。此外，部分圖案化導電薄膜亦可接地而具有防護電磁干擾的功效。與習知技術相較，本發明的圖案化導電薄膜並無習知導線架於結構上的限制，而能夠有效減少堆疊的垂直高度並縮小尺寸。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。
1、2、2a、3、4．．．半導體封裝體
11、21．．．載板
12、22、22a、26、27、28、29、32、42．．．晶片
13、23、23a、23b、33、43．．．封裝材料
14．．．遮蔽體
211．．．第一表面
212．．．第二表面
213、253．．．銲球
24、24b、34、44．．．圖案化導電薄膜
241．．．線路圖樣
242．．．電磁防護圖樣
25．．．封裝體
263．．．導電凸塊
31、41．．．導線架
S01~S03．．．半導體封裝體之製造方法的流程步驟
圖1為一種習知之半導體封裝體的示意圖；圖2A為依據本發明較佳實施例之一種半導體封裝體的示意圖；圖2B為圖2A之半導體封裝體及其圖案化導電薄膜的示意圖；圖3為依據本發明較佳實施例之一種半導體封裝體之製造方法的流程圖；圖4A及圖4B為圖3之製造方法的示意圖；圖5至圖8為依據本發明之半導體封裝體外接電子元件具有不同變化態樣的示意圖；以及圖9A及圖9B為本發明之半導體封裝體使用導線架作為載板的示意圖。
2．．．半導體封裝體
21．．．載板
211．．．第一表面
212．．．第二表面
213．．．銲球
22．．．晶片
23．．．封裝材料
24．．．圖案化導電薄膜

Claims (21)

  1. 一種半導體封裝體，包含：一載板，係具有一第一表面及一第二表面，該第一表面與該第二表面相對設置，該第二表面係具有複數個銲球；至少一晶片，係設置於該載板的該第一表面，並與該載板電性連接；一封裝材料，係包覆該晶片及該載板的至少部分該第一表面；以及一圖案化導電薄膜，係設置於該封裝材料上，該圖案化導電薄膜包含一線路圖樣和一電磁防護圖樣，該線路圖樣和該電磁防護圖樣彼此分離，其中該電磁防護圖樣與該第二表面之接地的銲球電性連接而接地。
  2. 如申請專利範圍第1項所述之半導體封裝體，其中該線路圖樣與該等銲球至少其中之一電性連接。
  3. 如申請專利範圍第1項所述之半導體封裝體，其中該晶片係以導電凸塊或銲線與該載板電性連接。
  4. 如申請專利範圍第1項所述之半導體封裝體，其中該圖案化導電薄膜係與至少一電子元件相堆疊及電性連接。
  5. 如申請專利範圍第4項所述之半導體封裝體，其中該電子元件係選自晶片、封裝體、多晶片模組、多封裝體模組及其組合所構成的群組。
  6. 如申請專利範圍第4項所述之半導體封裝體，其中該半導體封裝體及該電子元件係為另一封裝材料所包覆。
  7. 如申請專利範圍第4項所述之半導體封裝體，其中另一封裝材料係包覆該半導體封裝體之一部分並形成一凹穴，用以放置該電子元件。
  8. 如申請專利範圍第1項所述之半導體封裝體，其中該封裝材料的外表面係具有一非平坦結構或一粗化結構，以結合該圖案化導電薄膜。
  9. 如申請專利範圍第1項所述之半導體封裝體，其中該載板係為電路基板或導線架。
  10. 如申請專利範圍第9項所述之半導體封裝體，其中該導線架為四方扁平封裝體的導線架或四方扁平無引腳封裝體的導線架。
  11. 一種半導體封裝體的製造方法，包含以下步驟：提供一封裝體，該封裝體包含一載板、至少一晶片及一封裝材料，該載板具有一第一表面及一第二表面，該第一表面與該第二表面相對設置，該第二表面係具有複數個銲球，該晶片設置於該載板的該第一表面，並與該載板電性連接，該封裝材料包覆該晶片及該載板的至少部分該第一表面；以及形成一圖案化導電薄膜於該封裝材料上，該圖案化導電薄膜包含一線路圖樣和一電磁防護圖樣，該線路圖樣和該電磁防護圖樣彼此分離，其中該電磁防護 圖樣與該第二表面之接地的銲球電性連接而接地。
  12. 如申請專利範圍第11項所述之製造方法，其中該圖案化導電薄膜係藉由沈積、塗佈、印刷或電鍍方式形成於該封裝材料上。
  13. 如申請專利範圍第11項所述之製造方法，其中該線路圖樣與該等銲球至少其中之一電性連接。
  14. 如申請專利範圍第11項所述之製造方法，其中該晶片係以導電凸塊或銲線與該載板電性連接。
  15. 如申請專利範圍第11項所述之製造方法，更包含一步驟：將該圖案化導電薄膜與至少一電子元件相堆疊及電性連接。
  16. 如申請專利範圍第15項所述之製造方法，其中該電子元件係選自晶片、封裝體、多晶片模組、多封裝體模組及其組合所構成的群組。
  17. 如申請專利範圍第15項所述之製造方法，更包含一步驟：藉由另一封裝材料包覆該半導體封裝體及該電子元件。
  18. 如申請專利範圍第15項所述之製造方法，更包含一步驟：藉由另一封裝材料包覆該半導體封裝體之一部分並形成一凹穴，用以放置該電子元件。
  19. 如申請專利範圍第11項所述之製造方法，其中於形 成該圖案化導電薄膜之前，更包含一步驟：形成一非平坦結構或一粗化結構於該封裝材料的外表面，以結合該圖案化導電薄膜。
  20. 如申請專利範圍第11項所述之製造方法，其中該載板係為電路基板或導線架。
  21. 如申請專利範圍第20項所述之製造方法，其中該導線架為四方扁平封裝體的導線架或四方扁平無引腳封裝體的導線架。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
WO2012020064A1 (en) * 2010-08-10 2012-02-16 St-Ericsson Sa Packaging an integrated circuit die
US8084300B1 (en) 2010-11-24 2011-12-27 Unisem (Mauritius) Holdings Limited RF shielding for a singulated laminate semiconductor device package
CN102655096A (zh) * 2011-03-03 2012-09-05 力成科技股份有限公司 芯片封装方法
TWI419270B (zh) * 2011-03-24 2013-12-11 Chipmos Technologies Inc 封裝堆疊結構
CN102368494A (zh) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 一种抗电磁干扰的芯片封装结构
US9589906B2 (en) * 2015-02-27 2017-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9893058B2 (en) 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
CN112002677A (zh) * 2020-08-25 2020-11-27 济南南知信息科技有限公司 一种rf通信组件及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW417219B (en) * 1999-07-22 2001-01-01 Siliconware Precision Industries Co Ltd Ball grid array package having leads
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TWM294086U (en) * 2005-11-30 2006-07-11 Powertech Technology Inc Package structure of improving the temperature cycle life of solder ball
TWI261901B (en) * 2005-01-26 2006-09-11 Advanced Semiconductor Eng Quad flat no-lead chip package structure
US20060244157A1 (en) * 2005-04-29 2006-11-02 Flynn Carson Stacked integrated circuit package system
TWI281244B (en) * 2005-11-15 2007-05-11 Taiwan Solutions Systems Corp Chip package substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352925A (en) * 1991-03-27 1994-10-04 Kokusai Electric Co., Ltd. Semiconductor device with electromagnetic shield
US7884457B2 (en) * 2007-06-26 2011-02-08 Stats Chippac Ltd. Integrated circuit package system with dual side connection
US8183675B2 (en) * 2007-11-29 2012-05-22 Stats Chippac Ltd. Integrated circuit package-on-package system with anti-mold flash feature

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW417219B (en) * 1999-07-22 2001-01-01 Siliconware Precision Industries Co Ltd Ball grid array package having leads
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TWI261901B (en) * 2005-01-26 2006-09-11 Advanced Semiconductor Eng Quad flat no-lead chip package structure
US20060244157A1 (en) * 2005-04-29 2006-11-02 Flynn Carson Stacked integrated circuit package system
TWI281244B (en) * 2005-11-15 2007-05-11 Taiwan Solutions Systems Corp Chip package substrate
TWM294086U (en) * 2005-11-30 2006-07-11 Powertech Technology Inc Package structure of improving the temperature cycle life of solder ball

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