TWI409015B - - Google Patents

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Publication number
TWI409015B
TWI409015B TW100102661A TW100102661A TWI409015B TW I409015 B TWI409015 B TW I409015B TW 100102661 A TW100102661 A TW 100102661A TW 100102661 A TW100102661 A TW 100102661A TW I409015 B TWI409015 B TW I409015B
Authority
TW
Taiwan
Prior art keywords
substitution
palladium plating
palladium
plating layer
reduced
Prior art date
Application number
TW100102661A
Other languages
English (en)
Chinese (zh)
Other versions
TW201233280A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to TW100102661A priority Critical patent/TW201233280A/zh
Priority to CN2011101925171A priority patent/CN102605359A/zh
Priority to JP2011229483A priority patent/JP2012153974A/ja
Priority to US13/326,370 priority patent/US20120186852A1/en
Priority to KR1020120005470A priority patent/KR20120086253A/ko
Publication of TW201233280A publication Critical patent/TW201233280A/zh
Application granted granted Critical
Publication of TWI409015B publication Critical patent/TWI409015B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05001—Internal layers
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    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554—External layer
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    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2924/156—Material
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)
  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)
TW100102661A 2011-01-25 2011-01-25 Chemical palladium-gold plating film method TW201233280A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW100102661A TW201233280A (en) 2011-01-25 2011-01-25 Chemical palladium-gold plating film method
CN2011101925171A CN102605359A (zh) 2011-01-25 2011-06-28 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺
JP2011229483A JP2012153974A (ja) 2011-01-25 2011-10-19 化学パラジウム／金めっき皮膜構造及びその製造方法、銅線またはパラジウム／銅線で接合されたパラジウム／金めっき皮膜パッケージ構造及びそのパッケージプロセス
US13/326,370 US20120186852A1 (en) 2011-01-25 2011-12-15 Structure of electrolessly palladium and gold plated films and process for making the same, assembled structure of palladium and gold plated films bonded with copper or copper-palladium wire and assembling process therefore
KR1020120005470A KR20120086253A (ko) 2011-01-25 2012-01-18 무전해 팔라듐 및 금 도금 필름의 구조 및 이의 제조방법, 구리 또는 구리-팔라듐 와이어가 결합된 팔라듐 및 금 도금 필름의 조립구조 및 이의 조립방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100102661A TW201233280A (en) 2011-01-25 2011-01-25 Chemical palladium-gold plating film method

Publications (2)

Publication Number Publication Date
TW201233280A TW201233280A (en) 2012-08-01
TWI409015B true TWI409015B (fr) 2013-09-11

Family

ID=47069856

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100102661A TW201233280A (en) 2011-01-25 2011-01-25 Chemical palladium-gold plating film method

Country Status (1)

Country Link
TW (1) TW201233280A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201636454A (zh) * 2015-04-10 2016-10-16 Taiwan Uyemura Co Ltd 化學鈀銀鍍膜的製作方法及其結構
TWI542729B (zh) 2015-07-09 2016-07-21 旭德科技股份有限公司 線路板及其製作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI251920B (en) * 2003-10-17 2006-03-21 Phoenix Prec Technology Corp Circuit barrier structure of semiconductor package substrate and method for fabricating the same
TW200908180A (en) * 2007-07-17 2009-02-16 Shinko Electric Ind Co Solder bump forming method
TWI328847B (en) * 2005-12-06 2010-08-11 Seiko Epson Corp Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit board, and electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI251920B (en) * 2003-10-17 2006-03-21 Phoenix Prec Technology Corp Circuit barrier structure of semiconductor package substrate and method for fabricating the same
TWI328847B (en) * 2005-12-06 2010-08-11 Seiko Epson Corp Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit board, and electronic device
TW200908180A (en) * 2007-07-17 2009-02-16 Shinko Electric Ind Co Solder bump forming method

Also Published As

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