TWI407666B - Control circuit of interleaved pfc power converter - Google Patents

Control circuit of interleaved pfc power converter Download PDF

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TWI407666B
TWI407666B TW99122515A TW99122515A TWI407666B TW I407666 B TWI407666 B TW I407666B TW 99122515 A TW99122515 A TW 99122515A TW 99122515 A TW99122515 A TW 99122515A TW I407666 B TWI407666 B TW I407666B
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signal
slave
control circuit
control
switching
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TW99122515A
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TW201203815A (en
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Ta Yung Yang
Cheng Sung Chen
Rui Hong Lu
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System General Corp
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Abstract

A control circuit of an interleaved PFC power converter according to the present invention comprises a master switching control circuit, a slave switching control circuit, and a slave reference signal generator. The master switching control circuit generates a control signal and a first switching signal in response to an input voltage and a feedback signal. The first switching signal is utilized to control a first switch of the PFC power converter. The slave reference signal generator generates a slave control signal in response to a load condition of the PFC power converter and the control signal. The slave switching control circuit generates a second switching signal in response to the slave control signal. The slave control signal is utilized to control a second switch of the PFC power converter. The slave reference signal generator adjusts the control signal in response to the load condition for generating the slave control signal correspondingly. The slave control signal drives the slave switching control circuit to adjust the switching frequency of the second switch for reducing the switching loss.

Description

交錯式PFC功率轉換器之控制電路Control circuit of interleaved PFC power converter

本發明係關於一種功率轉換器，其係尤指一種交錯式PFC功率轉換器之控制電路。The present invention relates to a power converter, and more particularly to a control circuit for an interleaved PFC power converter.

現今輸出75W(瓦特)以上的功率轉換器採用功率因數校正(Power Factor Correction；PFC)，用而改善交流電源的功率因數以提高效能。為加強效能，新的功率因數校正電路結構已經被提出，其中以具有主/從切換控制電路(Master/Slave Switching Control Circuit)的交錯式(Interleaved)PFC功率轉換器是目前的發展重點。Today's output power converters above 75W (watts) use Power Factor Correction (PFC) to improve the power factor of the AC power supply to improve performance. In order to enhance the performance, a new power factor correction circuit structure has been proposed, in which an interleaved PFC power converter having a master/slave switching control circuit (Master/Slave Switching Control Circuit) is currently the development focus.

請參考第1圖，習知具有主/從切換控制電路的交錯式PFC功率轉換器的電路示意圖。如圖所示，其控制電路至少包含主動切換控制電路(M)1與從動切換控制電路(S)2。其中，當耦接於磁性元件L1之第一切換開關Q1 受控於主動切換控制電路1而截止時，流經磁性元件L1的電流經由整流器D11 整流後儲存於電容C1 。同時，當耦接於磁性元件L2之第二切換開關Q2 受控於從動切換控制電路2而截止時，流經磁性元件L2的電流經由整流器D22 整流後儲存於電容C1 。電容C1 儲存的能量用來作為輸出電壓V0 。Referring to FIG. 1, a schematic circuit diagram of an interleaved PFC power converter having a master/slave switching control circuit is known. As shown, its control circuit includes at least an active switching control circuit (M) 1 and a slave switching control circuit (S) 2. Wherein when coupled to the first switch Q 1 of the magnetic element L1 controlled active switch is turned off when the control circuit 1, current flows through the magnetic element L1 stored in the capacitor C 1 via the rectifying rectifier D 11. Meanwhile, when the second changeover switch Q 2 coupled to the magnetic element L2 is controlled to be turned off by the slave switching control circuit 2, the current flowing through the magnetic element L2 is rectified via the rectifier D 22 and stored in the capacitor C 1 . The energy stored by capacitor C 1 is used as the output voltage V 0 .

以下說明具有主/從切換控制電路的交錯式PFC功率轉換器的電路運作：磁性元件L1接收經整流後的輸入電壓VAC 。主動切換控制電路1根據VRMS端、IAC端、回授端FB、電流感測端CS1與VEA端所接收的訊號(如：回授訊號VFB 、電流感測訊號VCS1 與誤差訊號VEA …等)，以分別在主動切換控制電路1的VM1端與輸出端OPFC1產生控制訊號VM 以及第一切換信號SW1。其中VRMS端接收的訊號為經整流後的輸入電壓VAC 經由分壓器(由阻抗元件R15 與R16 組成)分壓後，而在電容C2 上建立的電壓；IAC端接收的訊號為經整流後的輸入電壓VAC 經阻抗元件R14 衰減後的電壓；VEA端與一接地端之間連接一RC補償電路(由阻抗元件R17 與電容C3 組成)以產生誤差訊號VEA 。The circuit operation of the interleaved PFC power converter with the master/slave switching control circuit is described below: the magnetic element L1 receives the rectified input voltage V AC . The active switching control circuit 1 receives signals according to the VRMS terminal, the IAC terminal, the feedback terminal FB, the current sensing terminals CS1 and the VEA terminal (eg, the feedback signal V FB , the current sensing signal V CS1 and the error signal V EA ... And so on, to generate the control signal V M and the first switching signal SW1 at the VM1 end and the output end OPFC1 of the active switching control circuit 1, respectively. The signal received by the VRMS terminal is a voltage that is established on the capacitor C 2 after the rectified input voltage V AC is divided by the voltage divider (composed of the impedance components R 15 and R 16 ); the signal received by the IAC terminal is The rectified input voltage V AC is attenuated by the impedance element R 14 ; an RC compensation circuit (composed of the impedance element R 17 and the capacitor C 3 ) is connected between the VEA terminal and a ground terminal to generate an error signal V EA .

其中，VRMS端接收的訊號與輸入電壓VAC 相關，IAC端接收的訊號與輸入電流相關。當PFC功率轉換器耦接的負載變輕時，回授訊號VFB 會上升而誤差訊號VEA 會下降。因此，誤差訊號VEA 與負載狀態(負載輕重)相關。控制訊號VM 用以控制輸入電流追隨輸入電壓VAC ，以達到高功率因數。第一切換信號SW1控制第一切換開關Q1 。The signal received by the VRMS terminal is related to the input voltage V AC , and the signal received by the IAC terminal is related to the input current. When the load coupled to the PFC power converter becomes light, the feedback signal V FB will rise and the error signal V EA will decrease. Therefore, the error signal V EA is related to the load state (load weight). The control signal V M is used to control the input current to follow the input voltage V AC to achieve a high power factor. The first switching signal SW1 controls the first switching switch Q 1 .

當第一切換開關Q1 受控於第一切換信號SW1而導通時，流經磁性元件L1的電流在耦接於第一切換開關Q1 之阻抗元件R11 上產生電流感測訊號VCS1 。當第一切換開關Q1 受控於主動切換控制電路1而截止時，流經磁性元件L1的電流經由整流器D11 整流後儲存於電容C1 。另外，輸出電壓V0 經阻抗元件R12 與R13 組成的分壓器分壓後產生回授訊號VFB ，並耦接於回授端FB。When the first switching switch Q 1 is turned on by the first switching signal SW1 , the current flowing through the magnetic element L1 generates a current sensing signal V CS1 on the impedance element R 11 coupled to the first switching switch Q 1 . When the first switch is controlled by an active Q switching control circuit 1 is turned off, L1 current flows through the magnetic element via the rectifier D 11 is stored in the rectifier capacitor C 1. In addition, the output voltage V 0 is divided by a voltage divider composed of the impedance elements R 12 and R 13 to generate a feedback signal V FB and coupled to the feedback terminal FB.

磁性元件L2接收經整流後的輸入電壓VAC 。從動切換控制電路2依據VM2端與電流感測端CS2所接收的控制訊號VM 與電流感測訊號VCS2 而在從動切換控制電路2的輸出端OPFC2產生第二切換信號SW2。第二切換信號SW2控制耦接於磁性元件L2的第二切換開關Q2 。當第二切換開關Q2 受控於第二切換信號SW2而導通時，流經磁性元件L2的電流在耦接於第二切換開關Q2 之阻抗元件R21 上產生電流感測訊號VCS2 。當第二切換開關Q2 受控於第二切換信號SW2而截止時，流經磁性元件L2的電流經由整流器D22 整流後儲存於電容C1 。The magnetic element L2 receives the rectified input voltage V AC . The slave switching control circuit 2 generates a second switching signal SW2 at the output terminal OPFC2 of the slave switching control circuit 2 according to the control signal V M and the current sensing signal V CS2 received by the VM2 terminal and the current sensing terminal CS2. The second switching signal SW2 controls the second switching switch Q 2 coupled to the magnetic element L2. When the second switching switch Q 2 is turned on by the second switching signal SW2, the current flowing through the magnetic element L2 generates a current sensing signal V CS2 on the impedance element R 21 coupled to the second switching switch Q 2 . When the second changeover switch Q 2 is turned off by the second switching signal SW2, the current flowing through the magnetic element L2 is rectified via the rectifier D 22 and stored in the capacitor C 1 .

第2圖為習知具有主/從切換控制電路的交錯式PFC功率轉換器的主/從切換控制電路的電路示意圖。請一併參閱第1圖，主動切換控制電路1中的電壓誤差放大器11的正/負輸入端分別接收參考訊號VR 與回授訊號VFB 。電壓誤差放大器11的輸出端耦接主動切換控制電路1的VEA端以產生誤差訊號VEA 。乘除法器12連接主動切換控制電路1的VEA端、VRMS端與IAC端以產生控制訊號VM 。乘除法器12產生控制訊號VM 為習知技術，因此不再贅述。2 is a circuit diagram of a master/slave switching control circuit of an interleaved PFC power converter having a master/slave switching control circuit. Referring to FIG. 1 together, the positive/negative input terminals of the voltage error amplifier 11 in the active switching control circuit 1 receive the reference signal V R and the feedback signal V FB , respectively . The output of the voltage error amplifier 11 is coupled to the VEA terminal of the active switching control circuit 1 to generate an error signal V EA . The multiplier and divider 12 is connected to the VEA terminal, the VRMS terminal and the IAC terminal of the active switching control circuit 1 to generate a control signal V M . The multiplier divider 12 generates the control signal V M as a conventional technique, and therefore will not be described again.

電流誤差放大器13、比較器15與取樣-維持電路(Sample and Hold Circuit)S-H形成一電流回授補償電路。控制訊號VM 傳送至電流誤差放大器13之負輸入端與主動切換控制電路1的VM1端。電流誤差放大器13之正輸入端接收訊號VS1 。訊號VS1 為電流感測訊號VCS1 經過取樣-維持電路S-H進行取樣所產生。電流誤差放大器13根據訊號VS1 與控制訊號VM 產生訊號IEA1 。訊號IEA1 傳送至比較器15的正輸入端。比較器15的負輸入端接收振盪器14產生的一第一鋸齒訊號ISAW1 。比較器15的輸出端耦接正反器16的重置端R。正反器16的設定端S與時脈端CK分別接收輸入電源VCC 與振盪器14所產生之時脈訊號CLK。正反器16的輸出端Q耦接主動切換控制電路1的輸出端OPFC1，並輸出第一切換訊號SW1。正反器16的重置端R經由一反閘受控於比較器15的輸出端。比較器15的輸出端依據第一鋸齒訊號ISAW1 和訊號IEA1 而控制第一切換訊號SW1的截止。因此，當控制訊號VM 因負載調整而改變時，比較器15的輸出端會即時反應，以控制第一切換訊號SW1的脈波寬度。The current error amplifier 13, the comparator 15 and the sample and hold circuit SH form a current feedback compensation circuit. The control signal V M is transmitted to the negative input terminal of the current error amplifier 13 and the VM1 terminal of the active switching control circuit 1. The positive input of current error amplifier 13 receives signal V S1 . The signal V S1 is generated by sampling the current sensing signal V CS1 through the sample-and-hold circuit SH. The current error amplifier 13 generates a signal I EA1 according to the signal V S1 and the control signal V M . Signal I EA1 is passed to the positive input of comparator 15. The negative input of the comparator 15 receives a first sawtooth signal I SAW1 generated by the oscillator 14. The output of the comparator 15 is coupled to the reset terminal R of the flip-flop 16. The set terminal S and the clock terminal CK of the flip-flop 16 receive the clock signal CLK generated by the input power source V CC and the oscillator 14, respectively. The output terminal Q of the flip-flop 16 is coupled to the output terminal OPFC1 of the active switching control circuit 1 and outputs a first switching signal SW1. The reset terminal R of the flip-flop 16 is controlled by the output of the comparator 15 via a reverse gate. The output of the comparator 15 controls the turn-off of the first switching signal SW1 according to the first sawtooth signal I SAW1 and the signal I EA1 . Therefore, when the control signal V M changes due to the load adjustment, the output of the comparator 15 reacts immediately to control the pulse width of the first switching signal SW1.

請繼續參閱第2圖，電流誤差放大器23、比較器25與取樣-維持電路S-H形成從動切換控制電路2的電流回授補償電路。從動切換控制電路2的VM2端耦接主動切換控制電路1的VM1端以接收控制訊號VM 。因此，當控制訊號VM 產生時，電流放大器23的正輸入端將經由從動切換控制電路2的VM2端接收控制訊號VM 。電流誤差放大器23的負輸入端接收訊號VS2 ，訊號VS2 為電流感測訊號VCS2 經過取樣-維持電路S-H進行取樣所產生。電流誤差放大器23的負輸入端即經由取樣-維持電路S-H耦接從動切換控制電路2的CS2端，以接收電流感測訊號VCS2 。電流誤差放大器23的輸出端依據控制訊號VM 與訊號VS2 輸出訊號IEA2 。比較器25的正輸入端與負輸入端分別接收第二鋸齒訊號ISAW2 與訊號IEA2 。正反器26的設定端S與時脈端CK分別接收輸入電源VCC 與時脈訊號CLK。正反器26的輸出端Q耦接從動切換控制電路2的輸出端OPFC2，並輸出第二切換訊號SW2。正反器26的重置端R經由一反閘受控於比較器25的輸出端。比較器25的輸出端依據第二鋸齒訊號ISAW2 與訊號IEA2 控制第二切換訊號SW2的截止。其中，當控制訊號VM 改變時，比較器25的輸出將即時反應，以同時調整第二切換訊號SW2的的脈波寬度。Referring to FIG. 2, the current error amplifier 23, the comparator 25 and the sample-and-hold circuit SH form a current feedback compensation circuit of the slave switching control circuit 2. The VM2 end of the slave switching control circuit 2 is coupled to the VM1 end of the active switching control circuit 1 to receive the control signal V M . Therefore, when the control signal V M is generated, the positive input terminal of the current amplifier 23 will receive the control signal V M via the VM2 terminal of the slave switching control circuit 2. The negative input terminal of the current error amplifier 23 receives the signal V S2 , and the signal V S2 is generated by sampling the current sense signal V CS2 through the sample-and-hold circuit SH. The negative input terminal of the current error amplifier 23 is coupled to the CS2 terminal of the slave switching control circuit 2 via the sample-and-hold circuit SH to receive the current sensing signal V CS2 . The output of the current error amplifier 23 outputs a signal I EA2 according to the control signal V M and the signal V S2 . The positive input terminal and the negative input terminal of the comparator 25 receive the second sawtooth signal I SAW2 and the signal I EA2 , respectively . The set terminal S and the clock terminal CK of the flip-flop 26 receive the input power V CC and the clock signal CLK, respectively. The output terminal Q of the flip-flop 26 is coupled to the output terminal OPFC2 of the slave switching control circuit 2 and outputs a second switching signal SW2. The reset terminal R of the flip-flop 26 is controlled by the output of the comparator 25 via a reverse gate. The output of the comparator 25 controls the turn-off of the second switching signal SW2 according to the second sawtooth signal I SAW2 and the signal I EA2 . Wherein, when the control signal V M is changed, the output of the comparator 25 will react immediately to adjust the pulse width of the second switching signal SW2 at the same time.

由於習知具主/從切換控制電路的交錯式PFC功率轉換器的特徵為主動切換控制電路1與從動切換控制電路2各控制功率轉換器之一半的功率輸出，因此切換開關Q1 與Q2 的切換頻率相同。而新興的效能標準要求功率轉換器提供更高的系統效能。因此，在輕載時，減少切換開關的切換損失以提昇效率，達到最新效能標準，是目前具有主/從切換控制電路的交錯式PFC功率轉換器發展的重點。Since the conventional PFC power converter with the master/slave switching control circuit is characterized in that the active switching control circuit 1 and the slave switching control circuit 2 each control the power output of one half of the power converter, the switching switches Q 1 and Q are The switching frequency of 2 is the same. Emerging performance standards require power converters to provide higher system performance. Therefore, at light load, reducing the switching loss of the switch to improve efficiency and achieve the latest performance standards is the focus of the development of interleaved PFC power converters with master/slave switching control circuits.

本發明之一目的，在於提供一種具有從動參考訊號產生電路的控制電路，其可運用於具有主/從切換控制電路的交錯式(Interleaved)PFC功率轉換器。在輕載的磁滯範圍時，本發明可控制從動切換控制電路所控制的第二切換開關依據負載減少而逐漸降低切換頻率，最後完全截止。如此，有效減少切換開關的切換損失達到效率提昇之目的。It is an object of the present invention to provide a control circuit having a driven reference signal generating circuit that can be applied to an interleaved PFC power converter having a master/slave switching control circuit. In the light hysteresis range of the light load, the present invention can control the second switching switch controlled by the slave switching control circuit to gradually reduce the switching frequency according to the load reduction, and finally completely cut off. In this way, the switching loss of the switch is effectively reduced to achieve the purpose of improving efficiency.

本發明交錯式PFC功率轉換器之控制電路，其包含主動切換控制電路、從動切換控制電路與從動參考訊號產生電路。主動切換控制電路依據一輸入電壓與一回授訊號，而產生一控制訊號與一第一切換訊號。第一切換訊號用於控制PFC功率轉換器之一第一切換開關。從動參考訊號產生電路依據PFC功率轉換器之一負載狀態與控制訊號而產生一從動控制訊號。從動切換控制電路依據從動控制訊號產生一第二切換訊號，以控制PFC功率轉換器的一第二切換開關。本發明之從動參考訊號產生電路依據負載狀態調整控制訊號而產生從動控制訊號，以在負載落在輕載的磁滯範圍時，控制從動切換控制電路逐漸降低第二切換開關之切換頻率，而降低切換損失。The control circuit of the interleaved PFC power converter of the present invention comprises an active switching control circuit, a slave switching control circuit and a driven reference signal generating circuit. The active switching control circuit generates a control signal and a first switching signal according to an input voltage and a feedback signal. The first switching signal is used to control one of the first switching switches of the PFC power converter. The slave reference signal generating circuit generates a slave control signal according to one of the load state and the control signal of the PFC power converter. The slave switching control circuit generates a second switching signal according to the slave control signal to control a second switching switch of the PFC power converter. The slave reference signal generating circuit of the present invention generates a slave control signal according to the load state adjustment control signal, so as to control the slave switching control circuit to gradually reduce the switching frequency of the second switch when the load falls within the light load hysteresis range And reduce switching losses.

茲為使　貴審查委員對本發明之技術特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：In order to give the reviewer a better understanding and understanding of the technical features of the present invention and the efficacies achieved, the following is a description of the preferred embodiment and a detailed description.

請參閱第3圖，本發明之控制電路運用於具有主/從切換控制電路的交錯式(Interleaved)PFC功率轉換器的較佳實施例的電路示意圖。本發明之控制電路除了第2圖所示之主動切換控制電路1與從動切換控制電路2之外，係增加了從動參考訊號產生電路(Slave Reference Signal Generator)3。本發明之控制電路即包含主動切換控制電路1、從動切換控制電路2與從動參考訊號產生電路3。本實施例是將從動參考訊號產生電路3設計於主動切換控制電路1中，但在實際的運用中，從動參考訊號產生電路3可以設計於從動切換控制電路2或者為獨立電路，僅需與主動切換控制電路1和從動切換控制電路2耦接即可。Referring to Figure 3, a circuit diagram of a preferred embodiment of an interleaved PFC power converter having a master/slave switching control circuit is provided for the control circuit of the present invention. In addition to the active switching control circuit 1 and the slave switching control circuit 2 shown in FIG. 2, the control circuit of the present invention adds a slave reference signal generator (Slave Reference Signal Generator) 3. The control circuit of the present invention comprises an active switching control circuit 1, a slave switching control circuit 2 and a slave reference signal generating circuit 3. In this embodiment, the slave reference signal generating circuit 3 is designed in the active switching control circuit 1. However, in actual operation, the slave reference signal generating circuit 3 can be designed as the slave switching control circuit 2 or as an independent circuit. It is necessary to be coupled to the active switching control circuit 1 and the slave switching control circuit 2.

復參閱第3圖，主動切換控制電路1之乘除法器12根據誤差訊號VEA 產生控制訊號VMM 。從動參考信號產生電路3根據誤差訊號VEA 調整控制訊號VMM 以產生從動控制訊號VM 。由於誤差訊號VEA 關聯於負載狀態，換句話說：從動參考信號產生電路3根據負載狀態(誤差訊號VEA )調整控制訊號VMM 而產生從動控制訊號VM 。此控制訊號VMM 相同於第2圖之乘除法器12所產生之控制訊號VM 。從動參考信號產生電路3產生之從動控制訊號VM 傳送至從動切換控制電路2。從動控制訊號VM 由主動切換控制電路1的VM1端輸出至從動切換控制電路2的VM2端。因此，從動切換控制電路2將根據從動控制訊號VM調整第二切換訊號SW2與第二切換開關Q2 的切換頻率。Referring to FIG. 3, the multiplier/divider 12 of the active switching control circuit 1 generates the control signal V MM based on the error signal V EA . The slave reference signal generating circuit 3 adjusts the control signal V MM according to the error signal V EA to generate the slave control signal V M . Since the error signal V EA is associated with the load state, in other words, the slave reference signal generating circuit 3 adjusts the control signal V MM according to the load state (error signal V EA ) to generate the slave control signal V M . This control signal V MM is identical to the control signal V M generated by the multiplier divider 12 of FIG. The slave control signal V M generated by the slave reference signal generating circuit 3 is transmitted to the slave switching control circuit 2. The slave control signal V M is output from the VM1 terminal of the active switching control circuit 1 to the VM2 terminal of the slave switching control circuit 2. Therefore, the slave switching control circuit 2 adjusts the switching frequency of the second switching signal SW2 and the second switching switch Q 2 according to the slave control signal VM.

請參閱第4圖，本發明之從動參考訊號產生電路3之一實施例的電路架構圖。如第4圖所示，從動參考訊號產生電路3根據誤差訊號VEA 調整控制訊號VMM ，以產生從動控制訊號VM 。從動參考訊號產生電路3包括負載偵測器(load detector)10、計數單元(counter unit)30、電流調整單元(current adjustment unit)40與參考調整單元(reference adjustment unit)50。Please refer to FIG. 4, which is a circuit diagram of an embodiment of the slave reference signal generating circuit 3 of the present invention. As shown in FIG. 4, the slave reference signal generating circuit 3 adjusts the control signal V MM according to the error signal V EA to generate the slave control signal V M . The slave reference signal generating circuit 3 includes a load detector 10, a counter unit 30, a current adjustment unit 40, and a reference adjustment unit 50.

負載偵測器10用於根據與負載相關的誤差訊號VEA 而偵測PFC功率轉換器的負載狀態，並產生偵測訊號，偵測訊號包含模式訊號Mode與保持訊號Hold。計數單元30耦接負載偵測器10，並依據模式訊號Mode以及保持訊號Hold相應進行計數而產生計數訊號N0 ~NN 。當負載狀態未落入預設的輕載的遲滯範圍(例如：重載)時，計數單元30受控於保持訊號Hold而停止計數動作且計數訊號N0 ~NN 保持高準位。當負載狀態在預設的輕載的磁滯範圍時，計數單元30依據模式訊號Mode進行上數或下數，並相應地產生計數訊號N0 ~NN 。其中，當負載狀態在預設的輕載的磁滯範圍且負載逐漸變輕時，計數單元30下數；當負載狀態在預設的輕載的磁滯範圍且負載逐漸變重時，計數單元30上數。The load detector 10 is configured to detect the load state of the PFC power converter according to the load-related error signal V EA and generate a detection signal, and the detection signal includes a mode signal Mode and a hold signal Hold. The counting unit 30 is coupled to the load detector 10 and generates counting signals N 0 ~N N according to the mode signal Mode and the holding signal Hold. When the load state does not fall within the preset light load hysteresis range (for example, heavy load), the counting unit 30 is controlled to hold the signal Hold to stop the counting operation and the counting signals N 0 to N N remain at the high level. When the load state is within the preset hysteresis range of the light load, the counting unit 30 performs the up or down number according to the mode signal Mode, and accordingly generates the count signals N 0 ~N N . Wherein, when the load state is within a preset light load hysteresis range and the load is gradually lightened, the counting unit 30 counts; when the load state is within a preset light load hysteresis range and the load gradually becomes heavy, the counting unit 30 on the number.

電流調整單元40耦接計數單元30，並依據計數訊號N0 ~NN 調整一調整電流IL 。參考調整單元50耦接計數單元30，並依據計數訊號N0 ~NN 調整控制訊號VMM 以產生從動控制訊號VM 。從動控制訊號VM 透過VM1端傳送至從動切換控制電路2(如第3圖所示)以減少第二切換開關Q2 (如第1圖所示)的切換頻率。其中，負載偵測器10將依據調整電流IL 與負載狀態調整偵測訊號之準位，即調整模式運訊號Mode與保持訊號Hold之準位。The current adjustment unit 40 is coupled to the counting unit 30 and adjusts an adjustment current I L according to the counting signals N 0 to N N . The reference adjustment unit 50 is coupled to the counting unit 30 and adjusts the control signal V MM according to the counting signals N 0 to N N to generate the slave control signal V M . The slave control signal V M is transmitted through the VM1 terminal to the slave switching control circuit 2 (as shown in FIG. 3) to reduce the switching frequency of the second switching switch Q 2 (shown in FIG. 1). The load detector 10 adjusts the level of the detection signal according to the adjustment current I L and the load state, that is, adjusts the level of the mode signal mode and the hold signal Hold.

請參閱第5A圖與第5B圖所示的從動參考訊號產生電路3的電路架構圖。請先參考第5A圖，負載偵測器10包含電流源IB、 阻抗元件120與130、比較器140與150、反及閘170與180以及反及閘160。計數單元30包含及閘320與上/下數計數器(Up/Down Counter)310。電流調整單元40包含複數個電流源410~490與複數個開關S1 ~SN 。其中，電流源410~490的電流大小，可依據比例設置。輕載的磁滯範圍由負載偵測器10之第一門檻信號VT1 與第二門檻信號VT2 來限定，其中第一門檻信號VT1 大於第二門檻信號VT2 。再請參考第5B圖，參考調整單元50包含解碼器(Decoder)510、複數個反閘511~519、複數個開關521~529以及複數個阻抗元件532~539。其中，複數個阻抗元件532~539相串聯而為一分壓器，用於分壓控制訊號VMM 以調整控制訊號VMM ，而產生從動控制訊號VM ，該些阻抗元件532~539的阻抗大小，可依據比例設置。開關521~529分別耦接於阻抗元件532~539。開關521~529受控於解碼器510以控制從動控制訊號VM 的輸出。Please refer to the circuit architecture diagram of the driven reference signal generating circuit 3 shown in FIGS. 5A and 5B. Referring first to FIG. 5A, the load detector 10 includes a current source I B , impedance elements 120 and 130 , comparators 140 and 150 , inverse gates 170 and 180 , and a reverse gate 160 . The counting unit 30 includes a AND gate 320 and an Up/Down Counter 310. The current adjustment unit 40 includes a plurality of current sources 410 to 490 and a plurality of switches S 1 to S N . Among them, the current of the current source 410~490 can be set according to the ratio. The light hysteresis range of the light load is defined by the first threshold signal V T1 and the second threshold signal V T2 of the load detector 10, wherein the first threshold signal V T1 is greater than the second threshold signal V T2 . Referring again to FIG. 5B, the reference adjustment unit 50 includes a decoder (Decoder) 510, a plurality of reverse gates 511-519, a plurality of switches 521-529, and a plurality of impedance elements 532-539. Wherein, the plurality of impedance components 532-539 are connected in series to form a voltage divider for dividing the control signal V MM to adjust the control signal V MM to generate the slave control signal V M , the impedance components 532-539 The size of the impedance can be set according to the ratio. The switches 521-529 are respectively coupled to the impedance elements 532-539. Switches 521 to 529 controlled by the decoder 510 to control the output of the slave control signal V M.

請一併參閱第5A圖與第5B圖。負載偵測器10接收的誤差訊號VEA 與負載相關。當負載變輕時，誤差訊號VEA 將相應的變小。當誤差訊號VEA 小於第二門檻信號VT2 的初始值時，即表示負載落入於預設的輕載的磁滯範圍。當負載落入於預設的輕載的磁滯範圍時，負載偵測器10將產生高準位的維持訊號Hold與低準位的模式訊號Mode。計數單元30依據高準位的維持訊號Hold與低準位的模式訊號Mode進行下數，並相應產生下數的計數訊號N0 ~NN 。電流調整單元40將根據下數的計數訊號N0 ~NN 相應地控制開關S1 ~SN 導通或截止，進而調整調整電流IL (變小)。第一門檻信號VT1 與第二門檻信號VT2 也相應調整電流IL 而變小。負載偵測器10將進一步依據誤差訊號VEA 與調整後之第一門檻信號VT1 與第二門檻信號VT2 調整模式訊號Mode與保持訊號Hold之準位。Please refer to Figures 5A and 5B together. The error signal V EA received by the load detector 10 is related to the load. When the load becomes lighter, the error signal V EA will be correspondingly smaller. When the error signal V EA is smaller than the initial value of the second threshold signal V T2 , it means that the load falls within the preset hysteresis range of the light load. When the load falls within the preset hysteresis range of the light load, the load detector 10 will generate a high level of the sustain signal Hold and the low level mode signal Mode. The counting unit 30 performs the lowering according to the high level maintaining signal Hold and the low level mode signal Mode, and correspondingly generates the lower counting signals N 0 ~N N . The current adjustment unit 40 controls the switches S 1 to S N to be turned on or off according to the count signals N 0 to N N of the lower number, thereby adjusting the adjustment current I L (smaller). The first threshold signal V T1 and the second threshold signal V T2 also decrease in accordance with the current I L . The load detector 10 further adjusts the level of the mode signal Mode and the hold signal Hold according to the error signal V EA and the adjusted first threshold signal V T1 and the second threshold signal V T2 .

同時，當誤差訊號VEA 小於第二門檻信號VT2 時，參考調整單元50(第5B圖所示)之解碼器510經由反閘511~519接收下數的計數訊號N0 ~NN ，並相應地產生解碼訊號D0 ~DN 。解碼訊號D0 ~DN 相應地控制開關521、522…或529。也就是參考調整單元50則將依據下數的計數訊號N0 ~NN 相應地控制開關521、522…或529。當開關521、522…或529受控而導通時，從動控制訊號VMM 將依據開關521、522…或529所連接的阻抗元件532、533…或539相應地衰減，以產生從動控制訊號VM 。如此，第3圖所示之從動切換控制電路2將依據從動控制訊號VM 控制第二切換開關Q2 (如第1圖所示)而逐漸減少切換。其中，該些阻抗元件532~539的阻抗大小與第二切換開關Q2 切換頻率減少的比例相關。其中，開關529受控而導通時，從動控制訊號VM 為零，第二切換開關Q2 將截止。如此，本發明有效減少第二切換開關Q2 的切換損失達到效率提昇。Meanwhile, when the error signal V EA is smaller than the second threshold signal V T2 , the decoder 510 of the reference adjusting unit 50 (shown in FIG. 5B) receives the count signals N 0 to N N of the next number via the reverse gates 511 519 519 , and The decoded signals D 0 ~D N are generated accordingly. The decoded signals D 0 to D N control the switches 521, 522, ..., or 529 accordingly. That is, the reference adjustment unit 50 controls the switches 521, 522, . . . , or 529 accordingly according to the count signals N 0 to N N of the lower numbers. When the switches 521, 522, ..., or 529 are controlled and turned on, the slave control signal V MM is correspondingly attenuated according to the impedance elements 532, 533, ..., or 539 to which the switches 521, 522, ..., 529 are connected to generate a slave control signal. V M . Thus, the slave switching control circuit 2 shown in FIG. 3 will gradually reduce the switching by controlling the second switching switch Q 2 (as shown in FIG. 1) in accordance with the slave control signal V M . Wherein the ratio of the impedance magnitude of these impedance elements 539 and 532 to the second switch Q 2 to reduce the switching frequency correlation. Wherein, when the switch 529 is controlled and turned on, the slave control signal V M is zero, and the second switch Q 2 will be turned off. As such, the present invention effectively reduces the switching loss of the second changeover switch Q 2 to achieve an efficiency improvement.

復參考第5A圖，比較器140的負輸入端與正輸入端分別接收誤差訊號VEA 與第一門檻信號VT1 。比較器140的輸出端產生VH 訊號。另外，誤差訊號VEA 更傳送至比較器150的正輸入端。比較器150的負輸入端接收第二門檻信號VT2 。比較器150的輸出端產生VL 訊號。反及閘170的第一輸入端耦接比較器140的輸出端，以接收VH 訊號。反及閘170的輸出端產生模式訊號Mode。反及閘180第一輸入端耦接比較器150的輸出端以接收VL 訊號。反及閘180第二輸入端耦接反及閘170的輸出端以接收模式訊號Mode。反及閘180的輸出端耦接至反及閘170的第二輸入端。另外，反及閘160的兩個輸入端分別耦接比較器140與150的輸出端，以接收VH 訊號與VL 訊號。反及閘160的輸出端產生保持訊號Hold。其中，輕載的遲滯範圍由第一門檻信號VT1 與第二門檻信號VT2 來限定。第一門檻信號VT1 與第二門檻信號VT2 的初始值可由電流源IB 的電流大小以及相串聯之阻抗元件120與130的阻抗值來規劃。Referring to FIG. 5A, the negative input terminal and the positive input terminal of the comparator 140 receive the error signal V EA and the first threshold signal V T1 , respectively . The output of comparator 140 produces a V H signal. In addition, the error signal V EA is further transmitted to the positive input terminal of the comparator 150. The negative input of comparator 150 receives a second threshold signal V T2 . The output of comparator 150 produces a V L signal. The first input end of the NAND gate 170 is coupled to the output of the comparator 140 to receive the V H signal. The output of the opposite gate 170 generates a mode signal Mode. The first input end of the gate 180 is coupled to the output of the comparator 150 to receive the V L signal. The second input end of the anti-gate 180 is coupled to the output of the anti-gate 170 to receive the mode signal Mode. The output of the anti-gate 180 is coupled to the second input of the anti-gate 170. In addition, the two input terminals of the anti-gate 160 are coupled to the outputs of the comparators 140 and 150, respectively, to receive the V H signal and the V L signal. The output of the opposite gate 160 produces a hold signal Hold. Wherein, the hysteresis range of the light load is defined by the first threshold signal V T1 and the second threshold signal V T2 . The initial values of the first threshold signal V T1 and the second threshold signal V T2 may be planned by the magnitude of the current of the current source I B and the impedance values of the impedance elements 120 and 130 connected in series.

電流源IB 耦接於輸入電源VCC 與阻抗元件120之間。比較器140的正輸入端耦接於電流源IB 與阻抗元件120之連接點，以接收第一門檻信號VT1 。比較器150的負輸入端耦接於阻抗元件120和130之連接點，以接收第二門檻信號VT2 。調整電流IL 耦接於阻抗元件120和130之連接點。因此，第一門檻信號VT1 與第二門檻信號VT2 將依據調整電流IL 的電流大小而調整。而調整電流IL 將依據負載而調整。其中，調整電流IL 的電流大小為電流源410~490受控於開關S1 ~SN 而輸出的加總值。電流源410~490兩端分別耦接輸入電源VCC 與相對應的開關S1 ~SN 之一端。開關S1 ~SN 之另一端則耦接於阻抗元件120和130之連接點。The current source I B is coupled between the input power source V CC and the impedance element 120. The positive input terminal of the comparator 140 is coupled to the connection point of the current source I B and the impedance element 120 to receive the first threshold signal V T1 . The negative input terminal of the comparator 150 is coupled to the connection point of the impedance elements 120 and 130 to receive the second threshold signal V T2 . The adjustment current I L is coupled to the connection point of the impedance elements 120 and 130. Therefore, the first threshold signal V T1 and the second threshold signal V T2 will be adjusted according to the magnitude of the current of the adjustment current I L . The adjustment current I L will be adjusted according to the load. The current of the current I L is adjusted to be the total value of the current sources 410 to 490 controlled by the switches S 1 to S N . The two ends of the current source 410~490 are respectively coupled to the input power source V CC and the corresponding switch S 1 ~S N . The other ends of the switches S 1 to S N are coupled to the connection points of the impedance elements 120 and 130.

請復參考第5A圖，當誤差訊號VEA 介於第一門檻信號VT1 與第二門檻信號VT2 (未落入輕載的遲滯範圍)時，比較器140與150產生的VH 訊號與VL 訊號皆為高準位。反及閘160產生的保持訊號Hold與及閘320的輸出端之輸出皆低準位。上/下計數器310的時脈端CK接收低準位訊號時，不進行計數動作，計數訊號N0 ~NN 保持高準位。此時，電流調整單元40中的開關S1 ~SN 會受控於計數訊號N0 ~NN 而導通，調整電流IL 為最大值(電流源410~490的加總)。同時，參考調整單元50(參考第5B圖)中之解碼器510經由反閘511~519接收計數訊號N0 ~NN ，並依據經反閘511~519反相後為低準位的計數訊號N0 ~NN 相應地產生可導通開關521的解碼訊號D0 ~DN ，其餘開關522~529被截止。開關521被導通且其餘開關522~529被截止時，從動控制訊號VM 等於控制訊號VMM 。從動控制訊號VM 等於控制訊號VMM 時，切換開關Q1 與Q2 (參考第1圖)的切換頻率相同，主動控制電路1與從動切換控制電路2各控制一半的功率輸出。Please refer to FIG. 5A. When the error signal V EA is between the first threshold signal V T1 and the second threshold signal V T2 (not falling into the light load hysteresis range), the V H signals generated by the comparators 140 and 150 are The V L signals are all high-level. The output of the hold signal Hold generated by the gate 160 and the output of the gate 320 are both low. When the clock terminal CK of the up/down counter 310 receives the low level signal, the counting operation is not performed, and the counting signals N 0 to N N remain at the high level. At this time, the switches S 1 to S N in the current adjusting unit 40 are controlled by the counting signals N 0 to N N to be turned on, and the adjusting current I L is the maximum value (the sum of the current sources 410 to 490). At the same time, the decoder 510 in the reference adjusting unit 50 (refer to FIG. 5B) receives the counting signals N 0 ~N N via the reverse gates 511 519 519, and is based on the counting signals of the low level after the reverse gates 511 519 519 are inverted. N 0 ~ N N correspondingly generate the decoded signals D 0 ~ D N of the turn-on switch 521, and the remaining switches 522 - 529 are turned off. When the switch 521 is turned on and the remaining switches 522 to 529 are turned off, the slave control signal V M is equal to the control signal V MM . When the slave control signal V M is equal to the control signal V MM , the switching frequency of the switching switches Q 1 and Q 2 (refer to FIG. 1 ) is the same, and the active control circuit 1 and the slave switching control circuit 2 each control half of the power output.

另外，當負載變輕且誤差訊號VEA 小於初始第二門檻信號VT2 而落入預設輕載的磁滯範圍時，比較器140與150產生的VH 訊號與VL 訊號分別為高準位與低準位。因此，反及閘160輸出高準位的保持訊號Hold。及閘320之輸出端的輸出準位，係對應於其接收的脈波訊號CLK的準位。當反及閘170的第一輸入端與反及閘180的第一輸入端分別接收高準位的VH 訊號與低準位的VL 訊號時，反及閘170的輸出端產生低準位的模式訊號Mode。In addition, when the load becomes lighter and the error signal V EA is smaller than the initial second threshold signal V T2 and falls within the hysteresis range of the preset light load, the V H signal and the V L signal generated by the comparators 140 and 150 are respectively high-precision. Bit and low level. Therefore, the gate 160 outputs a high level of the hold signal Hold. The output level of the output of the gate 320 corresponds to the level of the pulse signal CLK that it receives. When the first input of the anti-gate 170 and the first input of the anti-gate 180 respectively receive the high-level V H signal and the low-level V L signal, the output of the anti-gate 170 generates a low level. Mode signal Mode.

當上/下數計數器310的模式端MODE接收到低準位的模式訊號Mode時，進行下數並產生下數的計數訊號N0 ~NN 。當上/下數計數器310進行下數時，下數的計數訊號N0 ~NN 將依序控制開關S1 ~SN 導通或截止。調整電流IL 將受控於開關S1 ~SN 並根據上/下數計數器310的下數而逐漸減少。如此，第一門檻信號VT1 與第二門檻信號VT2 將依據調整電流IL 之減少而變小。同時，參考調整單元50(參考第5B圖)依據下數的計數訊號N0 ~NN 產生可控制開關521、522…或529導通的解碼訊號D0 ~DN 。當開關521、522…或529受控而依序導通時，從動控制訊號VM 將逐漸變小，從動切換控制電路2(參考第3圖)將控制第二切換開關Q2 (請見第1圖)逐漸減少切換頻率，以提升效率。其中，開關529導通時，從動控制訊號VM 為零，從動切換控制電路2產生的第二切換訊號SW2為低準位。因此，受控於第二切換訊號SW2的切換開關Q2 將截止，更有效減少切換損失，達到效率提昇。When the mode terminal MODE of the up/down counter 310 receives the mode signal Mode of the low level, the number is counted and the count signal N 0 ~N N of the next number is generated. When the up/down counter 310 performs the next number, the lower count signals N 0 ~N N will sequentially control the switches S 1 -S N to be turned on or off. The adjustment current I L will be controlled by the switches S 1 -S N and will gradually decrease according to the number of up/down counters 310. Thus, the first threshold signal V T1 and the second threshold signal V T2 will become smaller according to the decrease of the adjustment current I L . At the same time, the reference adjustment unit 50 (refer to FIG. 5B) generates the decoded signals D 0 to D N that can be controlled to be turned on according to the count signals N 0 to N N of the lower number. When the switches 521, 522, ..., or 529 are controlled and sequentially turned on, the slave control signal V M will gradually become smaller, and the slave switching control circuit 2 (refer to FIG. 3) will control the second switch Q 2 (see Figure 1) Gradually reduce the switching frequency to improve efficiency. When the switch 529 is turned on, the slave control signal V M is zero, and the second switching signal SW2 generated by the slave switching control circuit 2 is at a low level. Therefore, the switch Q 2 controlled by the second switching signal SW2 will be turned off, which is more effective in reducing switching loss and achieving efficiency improvement.

除此之外，當誤差訊號VEA 落入預設的輕載的磁滯範圍但負載突然增加，並且誤差訊號VEA 大於第一門檻信號VT1 時，比較器140與150產生的VH 訊號與VL 訊號分別為低準位與高準位。因此，反及閘160輸出高準位的保持訊號Hold，及閘320輸出端的輸出準位係對應於脈波訊號CLK的準位。當反及閘170的第一輸入端接收低準位的VH 訊號時，其輸出端產生高準位的模式訊號Mode。In addition, when the error signal V EA falls within the preset light load hysteresis range but the load suddenly increases, and the error signal V EA is greater than the first threshold signal V T1 , the V H signals generated by the comparators 140 and 150 The V L signal is low level and high level respectively. Therefore, the gate 160 outputs a high level of the hold signal Hold, and the output level of the output of the gate 320 corresponds to the level of the pulse signal CLK. When the first input of the anti-gate 170 receives the low-level V H signal, its output generates a high-level mode signal Mode.

當上/下數計數器310的模式端MODE接收到高準位的模式訊號Mode時，進行上數並產生上數的計數訊號N0 ~NN 。當上/下數計數器310上數時，上數的計數訊號N0 ~NN 依序控制開關S1 ~SN 導通或截止。調整電流IL 將受控於開關S1 ~SN 並根據上/下數計數器310的上數而逐漸增加。如此，第一門檻信號VT1 與第二門檻信號VT2 將依調整電流IL 之增加而變大。同時，參考調整單元50(參考第5B圖)依據上數的計數訊號N0 ~NN 相對產生可分別控制開關521、522…或529導通的解碼訊號D0 ~DN ，以控制從動控制訊號VM 逐漸變大。受從動切換控制電路2(參考第3圖)控制的第二切換開關Q2 (參考第1圖)將增加切換頻率，以反應負載狀態。When the mode terminal MODE of the up/down counter 310 receives the mode signal Mode of the high level, the upper number is generated and the counting signals N 0 ~N N of the upper number are generated. When the up/down counter 310 is counted, the upper count signals N 0 to N N sequentially control the switches S 1 to S N to be turned on or off. The adjustment current I L will be controlled by the switches S 1 -S N and gradually increase according to the number of up/down counters 310. As such, the first threshold signal V T1 and the second threshold signal V T2 will increase as the adjustment current I L increases. At the same time, the reference adjustment unit 50 (refer to FIG. 5B) relatively generates the decoded signals D 0 ~D N which can respectively control the switches 521, 522 or 529 to be turned on according to the counting signals N 0 to N N of the upper numbers to control the slave control. The signal V M gradually becomes larger. The second changeover switch Q 2 (refer to FIG. 1) controlled by the slave switching control circuit 2 (refer to FIG. 3) will increase the switching frequency to reflect the load state.

第6圖為本發明之控制電路運作的波形圖。當負載未落入預設的輕載的磁滯範圍時，回授訊號VFB 小於參考訊號VR 。因此，負載偵測器10(參考第4圖)接收的誤差訊號VEA 介於第一門檻信號VT1 與第二門檻信號VT2 之間。此時，負載偵測器10將輸出高準位的模式訊號Mode與低準位的保持訊號Hold(第6圖未顯示)。此時，計數單元30將輸出皆為高準位計數訊號N0 ~NN ，而參考調整單元50產生的從動控制訊號VM 與控制訊號VMM 相同。Figure 6 is a waveform diagram showing the operation of the control circuit of the present invention. When the load does not fall within the preset hysteresis range of the light load, the feedback signal V FB is smaller than the reference signal V R . Therefore, the error signal V EA received by the load detector 10 (refer to FIG. 4) is between the first threshold signal V T1 and the second threshold signal V T2 . At this time, the load detector 10 outputs a high level mode signal Mode and a low level hold signal Hold (not shown in FIG. 6). At this time, the counting unit 30 outputs the high-level counting signals N 0 to N N , and the slave control signal V M generated by the reference adjusting unit 50 is the same as the control signal V MM .

另外，當負載落入預設的輕載的磁滯範圍時，回授訊號VFB 大於參考訊號VR 。此時，負載偵測器10接收的誤差訊號VEA 小於第二門檻信號VT2 ，負載偵測器10將輸出低準位的模式訊號Mode與高準位的保持訊號Hold(第6圖未顯示)。此時，計數單元30將輸出下數的計數訊號N0 ~NN 。參考調整單元50依據下數的計數訊號N0 ~NN 相應產生逐漸變小的從動控制訊號VM 。其中，當負載逐漸變輕，計數訊號N0 ~NN 將逐漸向下計數以分別控制開關521、522…或529導通或截止。當計數單元30下數到最後所產生之計數訊號N0 ~NN ，使參考調整單元50中的開關529導通時，從動控制訊號VM 為零。此時，受控於第二切換訊號SW2的第二切換開關Q2 將截止，更有效減少切換損失，達到效率提昇。In addition, when the load falls within the preset hysteresis range of the light load, the feedback signal V FB is greater than the reference signal V R . At this time, the error signal V EA received by the load detector 10 is smaller than the second threshold signal V T2 , and the load detector 10 outputs the low level mode signal Mode and the high level hold signal Hold (not shown in FIG. 6 ). ). At this time, the counting unit 30 will output the counted signals N 0 to N N of the next number. The reference adjustment unit 50 generates a gradually decreasing slave control signal V M according to the count signals N 0 to N N of the lower number. Wherein, as the load gradually becomes lighter, the counting signals N 0 ~ N N will gradually count down to control whether the switches 521, 522 ... or 529 are turned on or off, respectively. When the counting unit 30 counts down to the last generated counting signal N 0 ~ N N , the switch 529 in the reference adjusting unit 50 is turned on, the slave control signal V M is zero. At this time, the second switching switch Q 2 controlled by the second switching signal SW2 will be turned off, which is more effective in reducing switching loss and achieving efficiency improvement.

故本發明實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出發明專利申請，祈　鈞局早日賜准專利，至感為禱。Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the requirements of patent applications for patent law in China. It is undoubtedly to file an invention patent application according to law, and the Prayer Council will grant patents as soon as possible.

惟以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

1．．．主動切換控制電路1. . . Active switching control circuit

10．．．負載偵測器10. . . Load detector

11．．．電壓誤差放大器11. . . Voltage error amplifier

12．．．乘除法器12. . . Multiplier divider

13．．．電流誤差放大器13. . . Current error amplifier

14．．．振盪器14. . . Oscillator

15．．．比較器15. . . Comparators

16．．．正反器16. . . Positive and negative

120．．．阻抗元件120. . . Impedance component

130．．．阻抗元件130. . . Impedance component

140．．．比較器140. . . Comparators

150．．．比較器150. . . Comparators

160．．．反及閘160. . . Reverse gate

170．．．反及閘170. . . Reverse gate

180．．．反及閘180. . . Reverse gate

2．．．從動切換控制電路2. . . Slave switching control circuit

23．．．電流誤差放大器twenty three. . . Current error amplifier

25．．．比較器25. . . Comparators

26．．．正反器26. . . Positive and negative

3．．．從動參考訊號產生電路3. . . Slave reference signal generation circuit

30．．．計數單元30. . . Counting unit

310．．．上/下數計數器310. . . Up/down counter

320．．．及閘320. . . Gate

40．．．電流調整單元40. . . Current adjustment unit

410~490．．．電流源410~490. . . Battery

50．．．參考調整單元50. . . Reference adjustment unit

510．．．解碼器510. . . decoder

511~519．．．反閘511~519. . . Reverse gate

521~529．．．開關521~529. . . switch

532~539．．．阻抗元件532~539. . . Impedance component

C1 ．．．電容C 1 . . . capacitance

C2 ．．．電容C 2 . . . capacitance

C3 ．．．電容C 3 . . . capacitance

CLK．．．時脈訊號CLK. . . Clock signal

D0 ~DN ．．．解碼訊號D 0 ~ D N . . . Decoding signal

D11 ．．．整流器D 11 . . . Rectifier

D22 ．．．整流器D 22 . . . Rectifier

Hold．．．保持訊號Hold. . . Keep signal

IB ．．．電流源I B . . . Battery

IEA1 ．．．訊號I EA1 . . . Signal

IEA2 ．．．訊號I EA2 . . . Signal

IL ．．．調整電流I L . . . Adjust current

ISAW1 ．．．第一鋸齒訊號I SAW1 . . . First sawtooth signal

ISAW2 ．．．第二鋸齒訊號I SAW2 . . . Second sawtooth signal

L1．．．磁性元件L1. . . Magnetic component

L2．．．磁性元件L2. . . Magnetic component

Mode．．．模式訊號Mode. . . Mode signal

N0 ~NN ．．．計數訊號N 0 ~N N . . . Counting signal

Q1 ．．．第一切換開關Q 1 . . . First switch

Q2 ．．．第二切換開關Q 2 . . . Second switch

R11 ．．．阻抗元件R 11 . . . Impedance component

R12 ．．．阻抗元件R 12 . . . Impedance component

R13 ．．．阻抗元件R 13 . . . Impedance component

R14 ．．．阻抗元件R 14 . . . Impedance component

R15 ．．．阻抗元件R 15 . . . Impedance component

R16 ．．．阻抗元件R 16 . . . Impedance component

R17 ．．．阻抗元件R 17 . . . Impedance component

R21 ．．．阻抗元件R 21 . . . Impedance component

S1 ~SN ．．．開關S 1 ~S N . . . switch

S-H．．．取樣-維持電路S-H. . . Sampling-maintaining circuit

SW1．．．第一切換信號SW1. . . First switching signal

SW2．．．第二切換信號SW2. . . Second switching signal

VAC ．．．輸入電壓V AC . . . Input voltage

VCC ．．．輸入電源V CC . . . Input power

VCS1 ．．．電流感測訊號V CS1 . . . Current sensing signal

VCS2 ．．．電流感測訊號V CS2 . . . Current sensing signal

VEA ．．．誤差訊號V EA . . . Error signal

VFB ．．．回授訊號V FB . . . Feedback signal

VH ．．．訊號V H . . . Signal

VL ．．．訊號V L . . . Signal

VM ．．．控制訊號V M . . . Control signal

VM ．．．從動控制訊號V M . . . Slave control signal

VMM ．．．控制訊號V MM . . . Control signal

VO ．．．輸出電壓V O . . . The output voltage

VR ．．．參考訊號V R . . . Reference signal

VS1 ．．．訊號V S1 . . . Signal

VS2 ．．．訊號V S2 . . . Signal

VT1 ．．．第一門檻信號V T1 . . . First threshold signal

VT2 ．．．第二門檻信號V T2 . . . Second threshold signal

第1圖係習知具有主/從切換控制電路的交錯式PFC功率轉換器的電路示意圖；1 is a schematic circuit diagram of an interleaved PFC power converter having a master/slave switching control circuit;

第2圖係習知具有主/從切換控制電路的交錯式PFC功率轉換器的主/從切換控制電路的電路示意圖；2 is a circuit diagram of a master/slave switching control circuit of an interleaved PFC power converter having a master/slave switching control circuit;

第3圖係本發明具有主/從切換控制電路的交錯式PFC功率轉換器的控制電路之一實施例的電路示意圖；3 is a circuit diagram of an embodiment of a control circuit of an interleaved PFC power converter having a master/slave switching control circuit of the present invention;

第4圖係本發明之從動參考訊號產生電路之一實施例的電路架構圖；Figure 4 is a circuit diagram of an embodiment of the slave reference signal generating circuit of the present invention;

第5A圖係本發明之負載偵測器、計數單元與電流調整單元之一實施例的電路架構圖；5A is a circuit architecture diagram of an embodiment of the load detector, the counting unit and the current adjusting unit of the present invention;

第5B圖係本發明之參考調整單元之一實施例的電路架構圖；以及5B is a circuit architecture diagram of an embodiment of a reference adjustment unit of the present invention;

第6圖係本發明控制電路之一實施例的波形圖。Figure 6 is a waveform diagram of one embodiment of the control circuit of the present invention.

1．．．主動切換控制電路1. . . Active switching control circuit

11．．．電壓誤差放大器11. . . Voltage error amplifier

12．．．乘除法器12. . . Multiplier divider

13．．．電流誤差放大器13. . . Current error amplifier

14．．．振盪器14. . . Oscillator

15．．．比較器15. . . Comparators

16．．．正反器16. . . Positive and negative

2．．．從動切換控制電路2. . . Slave switching control circuit

23．．．電流誤差放大器twenty three. . . Current error amplifier

25．．．比較器25. . . Comparators

26．．．正反器26. . . Positive and negative

3．．．從動參考訊號產生電路3. . . Slave reference signal generation circuit

CLK．．．時脈訊號CLK. . . Clock signal

IEA1 ．．．訊號I EA1 . . . Signal

IEA2 ．．．訊號I EA2 . . . Signal

ISAW1 ．．．第一鋸齒訊號I SAW1 . . . First sawtooth signal

ISAW2 ．．．第二鋸齒訊號I SAW2 . . . Second sawtooth signal

S-H．．．取樣-維持電路S-H. . . Sampling-maintaining circuit

SW1．．．第一切換信號SW1. . . First switching signal

SW2．．．第二切換信號SW2. . . Second switching signal

VCC ．．．輸入電源V CC . . . Input power

VCS1 ．．．電流感測訊號V CS1 . . . Current sensing signal

VCS2 ．．．電流感測訊號V CS2 . . . Current sensing signal

VEA ．．．誤差訊號V EA . . . Error signal

VFB ．．．回授訊號V FB . . . Feedback signal

VM 從動控制訊號V M slave control signal

VMM ．．．控制訊號V MM . . . Control signal

VR ．．．參考訊號V R . . . Reference signal

VS1 ．．．訊號V S1 . . . Signal

VS2 ．．．訊號V S2 . . . Signal

Claims (11)

一種交錯式PFC功率轉換器的控制電路，其包含：一主動切換控制電路，依據一輸入電壓與一回授訊號，產生一第一切換訊號與一控制訊號，該第一切換訊號控制該PFC功率轉換器的一第一切換開關；一從動參考訊號產生電路，依據該PFC功率轉換器之一負載狀態與該控制訊號，產生一從動控制訊號；以及一從動切換控制電路，依據該從動控制訊號產生一第二切換訊號，以控制該PFC功率轉換器的一第二切換開關。A control circuit for an interleaved PFC power converter, comprising: an active switching control circuit, generating a first switching signal and a control signal according to an input voltage and a feedback signal, wherein the first switching signal controls the PFC power a first switching switch of the converter; a slave reference signal generating circuit, generating a slave control signal according to a load state of the PFC power converter and the control signal; and a slave switching control circuit, according to the slave The motion control signal generates a second switching signal to control a second switching switch of the PFC power converter. 如申請專利範圍第1項所述之控制電路，其中該從動參考訊號產生電路包含：一負載偵測器，偵測該負載狀態而產生一偵測訊號；一計數單元，耦接該負載偵測器，並依據該偵測訊號相應產生一計數訊號：一電流調整單元，耦接該計數單元，並依據該計數訊號調整一調整電流；以及一參考調整單元，耦接該計數單元，並依據該計數訊號調整該控制訊號以產生該從動控制訊號；其中，該負載偵測器依據該調整電流與該負載狀態產生該偵測訊號。The control circuit of claim 1, wherein the slave reference signal generating circuit comprises: a load detector that detects the load state to generate a detection signal; and a counting unit coupled to the load detector And correspondingly generating a counting signal according to the detecting signal: a current adjusting unit coupled to the counting unit and adjusting an adjusting current according to the counting signal; and a reference adjusting unit coupled to the counting unit, and The counting signal adjusts the control signal to generate the slave control signal; wherein the load detector generates the detection signal according to the adjusted current and the load state. 如申請專利範圍第2項所述之控制電路，其中該負載偵測器依據一誤差訊號偵測該負載狀態並產生該偵測訊號；該誤差訊號小於該負載偵測器之一第二門檻信號時，該偵測訊號驅使該計數單元向下計數並對應產生該計數訊號；該參考調整單元依據該計數訊號相應地逐漸減小該從動控制訊號。The control circuit of claim 2, wherein the load detector detects the load state according to an error signal and generates the detection signal; the error signal is smaller than a second threshold signal of the load detector The detecting signal drives the counting unit to count down and correspondingly generate the counting signal; the reference adjusting unit gradually reduces the slave control signal according to the counting signal. 如申請專利範圍第3項所述之控制電路，其中該電流調整單元依據向下計數的該計數訊號逐漸地減小該調整電流；該負載偵測器依據該調整電流調整該第二門檻信號與一第一門檻信號，並依據該誤差訊號與調整後之該第一門檻信號與該第二門檻信號調整該偵測訊號；其中該第一門檻信號大於該第二門檻信號。The control circuit of claim 3, wherein the current adjustment unit gradually reduces the adjustment current according to the counting signal that counts down; the load detector adjusts the second threshold signal according to the adjustment current a first threshold signal, and adjusting the detection signal according to the error signal and the adjusted first threshold signal and the second threshold signal; wherein the first threshold signal is greater than the second threshold signal. 如申請專利範圍第3項所述之控制電路，其中該計數單元下數到最後所對應產生之該計數訊號，係驅使該參考調整單元調整該從動控制訊號為零，而截止該交錯式PFC功率轉換器之該第二切換開關。The control circuit of claim 3, wherein the counting unit generates the counting signal corresponding to the last corresponding number, and drives the reference adjusting unit to adjust the slave control signal to zero, and the interleaved PFC is cut off. The second switch of the power converter. 如申請專利範圍第2項所述之控制電路，其中該負載偵測器依據一誤差訊號偵測該負載狀態並產生該偵測訊號；該誤差訊號大於該負載偵測器之一第一門檻信號時，該偵測訊號驅使該計數單元向上計數並對應產生該計數訊號；該參考調整單元依據該計數訊號相應地逐漸增加該從動控制訊號。The control circuit of claim 2, wherein the load detector detects the load state according to an error signal and generates the detection signal; the error signal is greater than a first threshold signal of the load detector The detecting signal drives the counting unit to count up and correspondingly generate the counting signal; the reference adjusting unit gradually increases the slave control signal according to the counting signal. 如申請專利範圍第6項所述之控制電路，其中該電流調整單元依據向上計數的該計數訊號逐漸地增加該調整電流；該負載偵測器依據該調整電流調整該第一門檻信號與一第二門檻信號，並依據該誤差訊號與調整後之該第一門檻信號與該第二門檻信號調整該偵測訊號；其中該第一門檻信號大於該第二門檻信號。The control circuit of claim 6, wherein the current adjustment unit gradually increases the adjustment current according to the count signal that is counted up; the load detector adjusts the first threshold signal according to the adjustment current The second threshold signal is adjusted according to the error signal and the adjusted first threshold signal and the second threshold signal; wherein the first threshold signal is greater than the second threshold signal. 如申請專利範圍第2項所述之控制電路，其中該誤差訊號介於該負載偵測器之一第一門檻信號與一第二門檻信號之間時，該計數單元依據該偵測訊號不進行計數；該參考調整單元不調整該控制訊號，該控制訊號等於該從動控制訊號。The control circuit of claim 2, wherein the error signal is not between the first threshold signal and the second threshold signal of the load detector, and the counting unit does not perform the detection signal according to the detection signal Counting; the reference adjustment unit does not adjust the control signal, and the control signal is equal to the slave control signal. 如申請專利範圍第2項所述之控制電路，其中該電流調整單元包含：複數電流源；以及複數開關，分別耦接於該些電流源與該負載偵測器之間，並受控於該計數訊號，以調整該調整電流。The control circuit of claim 2, wherein the current adjustment unit comprises: a plurality of current sources; and a plurality of switches respectively coupled between the current sources and the load detector, and controlled by the Count the signal to adjust the adjustment current. 如申請專利範圍第2項所述之控制電路，其中該參考調整單元包含：複數阻抗元件，該些阻抗元件相互串聯且耦接該控制訊號，以調整該控制訊號產生該從動控制訊號；複數開關，分別耦接於該些阻抗元件，以控制該從動控制訊號輸出；以及一解碼器，依據該計數訊號產生一解碼訊號，以控制該些開關。The control circuit of claim 2, wherein the reference adjustment unit comprises: a plurality of impedance elements connected in series with each other and coupled to the control signal to adjust the control signal to generate the slave control signal; The switches are respectively coupled to the impedance components to control the output of the slave control signals; and a decoder generates a decoded signal according to the counting signals to control the switches. 如申請專利範圍第2項所述之控制電路，其中該偵測訊號包含一模式訊號以及一保持訊號。The control circuit of claim 2, wherein the detection signal comprises a mode signal and a hold signal.
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