TWI405311B - Semiconductor device, packaging substrate having electronic component embedded therein, and method for manufacturing the same - Google Patents
Semiconductor device, packaging substrate having electronic component embedded therein, and method for manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
Description
本發明係關於一種半導體裝置、嵌埋電子元件之封裝結構、及其製法，尤指一種適用於大區域且多電子元件之半導體裝置、嵌埋電子元件之封裝結構、及其製法，以提升對位之精準度。The present invention relates to a semiconductor device, a package structure for embedded electronic components, and a method of fabricating the same, and more particularly to a semiconductor device suitable for a large area and multi-electronic components, a package structure for embedding electronic components, and a method for fabricating the same, to improve The accuracy of the position.
隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體封裝件高積集度(integration)以及微型化(miniaturization)的封裝要求，提供多數主被動元件及線路連接之電路板，亦逐漸由單層板演變成多層板，以使在有限的空間下，藉由層間連接技術(interlayer connection)擴大電路板上可利用的佈線面積而配合高電子密度之積體電路(integrated circuit)需求。With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the high integration and miniaturization packaging requirements of semiconductor packages, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. In space, the area of the available wiring on the board is expanded by the interlayer connection technology to match the demand for integrated circuits with high electron density.
一般半導體裝置之製程，首先係由晶片載板製造業者生產適用於該半導體裝置之晶片載板，如基板或導線架。之後再將該些晶片載板交由半導體封裝業者進行置晶、打線、封膠以及植球等封裝製程。又一般半導體封裝是將半導體晶片背面黏貼於封裝基板頂面進行打線接合(wire bonding)，或者將半導體晶片之作用面以覆晶接合(flip chip)方式與封裝基板接合，再於基板之背面植以焊料球以供與其他電子裝置進行電性連接。In general, the process of a semiconductor device is firstly produced by a wafer carrier manufacturer for a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. The wafer carriers are then handed over to the semiconductor package manufacturer for packaging processes such as crystallization, wire bonding, encapsulation, and ball placement. In a general semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding, and then implanted on the back surface of the substrate. A solder ball is used for electrical connection with other electronic devices.
隨著技術發展，近來有許多研究發展出電子元件嵌埋於基板中之方法，在相同封裝單位體積中容納更多數量的線路及電子元件，以滿足電子產品輕薄短小化之需求。業界現行嵌埋晶片於基板之技術中，多將晶片埋入基板後，於晶片及基板表面同時進行增層。其中，美國專利第6928726號，係揭示一種嵌埋電子元件之封裝結構及其製作方法，以將電子元件嵌埋於封裝基板。With the development of technology, many recent studies have developed a method in which electronic components are embedded in a substrate, and a larger number of lines and electronic components are accommodated in the same package unit volume to meet the demand for light and thin electronic products. In the current technology of embedding a wafer in a substrate, the wafer is buried in a substrate, and a layer is simultaneously formed on the surface of the wafer and the substrate. Among them, U.S. Patent No. 6,928, 726 discloses a package structure for embedding electronic components and a manufacturing method thereof for embedding electronic components in a package substrate.
請參閱圖1A至圖1D，此為習知之嵌埋電子元件之封裝結構之製作流程剖視圖。首先，如圖1A所示，提供一表面具有線路層51a之核心板4。接著，於核心板4形成一貫穿開口420，而後將一電子元件1置入此貫穿開口420。而後，利用增層技術，形成一增層結構6a於電子元件1及核心板4之表面，其中此增層結構6a具有一介電層60、介電層60表面之第二線路層62、及導電盲孔63，如圖1B所示。在形成增層結構的過程中，經熱壓後，介電層60會流入電子元件1及貫穿開口420間的間隙44中，使電子元件1固定於核心板4之貫穿開口中。此外，增層結構6a之導電盲孔63係使用雷射燒灼(laser ablation)的方式形成在介電層60中，且部分之導電盲孔63係電性連接於電子元件1之電極墊11。此外，更於核心板4之兩側分別進行增層製程，以形成一嵌埋電子元件之封裝基板，如圖1C所示。Please refer to FIG. 1A to FIG. 1D , which are cross-sectional views showing a manufacturing process of a conventional package structure for embedding electronic components. First, as shown in Fig. 1A, a core board 4 having a wiring layer 51a on its surface is provided. Next, a through opening 420 is formed in the core board 4, and then an electronic component 1 is placed in the through opening 420. Then, a build-up structure 6a is formed on the surface of the electronic component 1 and the core board 4 by using a build-up structure 6a, wherein the build-up structure 6a has a dielectric layer 60, a second trace layer 62 on the surface of the dielectric layer 60, and Conductive blind via 63, as shown in Figure 1B. In the process of forming the build-up structure, after the hot pressing, the dielectric layer 60 flows into the gap 44 between the electronic component 1 and the through opening 420, so that the electronic component 1 is fixed in the through opening of the core board 4. In addition, the conductive blind vias 63 of the build-up structure 6a are formed in the dielectric layer 60 by laser ablation, and a part of the conductive vias 63 are electrically connected to the electrode pads 11 of the electronic component 1. In addition, a build-up process is separately performed on both sides of the core board 4 to form a package substrate in which electronic components are embedded, as shown in FIG. 1C.
因此，若要電性連接電子元件與增層結構之第二線路層，必須在對應於電子元件之電極墊位置之介電層進行雷射燒灼以形成導電盲孔，以達到最佳的對位精準度。然而，對各個電子元件分別進行對位，將增加製程的時間，此外，其他各增層線路的電性連接更須重新對位以雷射燒灼形成導電盲孔，無法達到高產量之需求。同時，在形成與電子元件電性連接之導電盲孔時，若產生對位偏移的情形，可能會造成雷射加工損害到電子元件的問題，更可能會造成電性失效。Therefore, if the second circuit layer of the electronic component and the build-up structure is to be electrically connected, laser cauterization must be performed on the dielectric layer corresponding to the position of the electrode pad of the electronic component to form a conductive blind via hole for optimal alignment. Precision. However, the alignment of the individual electronic components will increase the processing time. In addition, the electrical connections of the other build-up lines must be re-aligned with laser cauterization to form conductive blind holes, which cannot meet the high output requirements. At the same time, when a conductive blind hole electrically connected to the electronic component is formed, if the alignment offset occurs, the laser processing may be damaged to the electronic component, and the electrical failure may be caused.
因此，現行亟需研發出能改善上述問題或缺點之封裝基板結構，以提升電子元件之對位精準度，並避免因雷射燒灼而造成電子元件之損傷。Therefore, there is an urgent need to develop a package substrate structure that can improve the above problems or shortcomings, to improve the alignment accuracy of electronic components, and to avoid damage to electronic components caused by laser cauterization.
本發明之主要目的係在提供一種半導體裝置及包含其之嵌埋電子元件之封裝基板結構，俾能藉由提升電子元件之對位精準度，而改善因電子元件對位偏移而影響品質及良率的問題。The main object of the present invention is to provide a semiconductor device and a package substrate structure including the embedded electronic component thereof, which can improve the quality of the alignment of the electronic component by improving the alignment accuracy of the electronic component and The problem of yield.
本發明之另一目的係在提供一種半導體裝置及包含其之嵌埋電子元件之封裝基板結構之製法，俾能大面積進行電子元件之對位，而節省製作成本且提升量產能力。Another object of the present invention is to provide a method for fabricating a semiconductor device and a package substrate structure including the embedded electronic component thereof, which can perform alignment of electronic components over a large area, thereby saving manufacturing costs and improving mass production capability.
為達成上述目的，本發明提供一種半導體裝置，包括：一電子元件，係具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係設於該作用面，且該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋；一承載板，係具有一第一表面及一相對之第二表面，該第一表面設有複數金屬凸塊，該等金屬凸塊具有與該第一表面接著之第二端及面向該等電極墊之第一端；以及複數焊料凸塊，係設於該等電極墊與該等金屬凸塊間，以電性連接該等電極墊與該等金屬凸塊。In order to achieve the above object, the present invention provides a semiconductor device comprising: an electronic component having a relatively active surface, an inactive surface, and a protective layer, the active surface having a plurality of electrode pads, the protective layer being disposed on The protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer; a carrier plate having a first surface and a second opposite a surface, the first surface is provided with a plurality of metal bumps, the metal bumps having a second end adjacent to the first surface and a first end facing the electrode pads; and a plurality of solder bumps disposed on the surface The electrode pads and the metal bumps are electrically connected to the electrode pads and the metal bumps.
此外，本發明亦提供一種嵌埋電子元件之封裝結構，包括：一電子元件，係具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係覆蓋該作用面，且該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋；複數金屬凸塊，係具有第一端及相對之第二端，且該等第一端係面向該等電極墊；複數焊料凸塊，係設於該電子元件之該等電極墊及該等金屬凸塊間，以電性連接該等電極墊與該等金屬凸塊；以及一核心板，其包括一核心層及一第一介電層，該核心層具有一第三表面、一第四表面、及一貫穿開口，該第一介電層具有一第五表面及一第六表面，該核心層之該第四表面係與該第一介電層之該第五表面相結合，而該電子元件係設於該貫穿開口內。In addition, the present invention also provides a package structure for embedding an electronic component, comprising: an electronic component having a relatively active surface, a non-active surface, and a protective layer, the active surface having a plurality of electrode pads, the protective layer Covering the active surface, and the protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer; the plurality of metal bumps have a first end and a relative first a second end, and the first end faces the electrode pads; a plurality of solder bumps are disposed between the electrode pads of the electronic component and the metal bumps to electrically connect the electrode pads and the And a core plate comprising a core layer and a first dielectric layer, the core layer having a third surface, a fourth surface, and a through opening, the first dielectric layer having a And a fifth surface and a sixth surface, the fourth surface of the core layer is combined with the fifth surface of the first dielectric layer, and the electronic component is disposed in the through opening.
於本發明之一實施態樣中，上述之嵌埋電子元件之封裝結構可更包括一第一線路層，該第一線路層係設於該第一介電層之該第六表面並電性連接至該等金屬凸塊之該第二端。此外，於本實施態樣中，嵌埋電子元件之封裝結構可更包括至少一第一增層結構，係設於該核心板之該第一介電層之該第六表面及該第一線路層上，其中該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層與該第二線路層之導電盲孔。In an embodiment of the present invention, the package structure for embedding the electronic component further includes a first circuit layer disposed on the sixth surface of the first dielectric layer and electrically Connected to the second end of the metal bumps. In addition, in this embodiment, the package structure for embedding the electronic component further includes at least one first build-up structure disposed on the sixth surface of the first dielectric layer of the core board and the first line On the layer, wherein the first build-up structure has at least one third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically connected to the first circuit layer and the first Conductive blind holes in the two circuit layers.
此外，於本發明之另一實施態樣中，嵌埋電子元件之封裝結構之核心板可更包括一第二介電層，該第二介電層具有一第七表面及一第八表面，該第二介電層之該第八表面係與該核心層之該第三表面相結合，使該核心層設於該第一介電層及該第二介電層間，且該第二介電層係與該電子元件之該非作用面相結合。於本實施態樣中，嵌埋電子元件之封裝結構可更包括二第一線路層，該等第一線路層係分別設於該第一介電層之該第六表面、及該第二介電層之該第七表面。此外，核心板可更包括複數導電通孔，該等導電通孔係貫穿該核心層、該第一介電層、及該第二介電層，以電性連接該等第一線路層。同時，於本實施態樣中，封裝結構可更包括二第一增層結構，係分別設於該核心板之該第一介電層之該第六表面、該第二介電層之該第七表面、及該等第一線路層上，其中各該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該等第一線路層與該第二線路層之導電盲孔。In addition, in another embodiment of the present invention, the core board of the package structure for embedding the electronic component further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface. The eighth surface of the second dielectric layer is combined with the third surface of the core layer, the core layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric The layer is combined with the non-active surface of the electronic component. In this embodiment, the package structure for embedding the electronic component further includes two first circuit layers respectively disposed on the sixth surface of the first dielectric layer and the second dielectric layer The seventh surface of the electrical layer. In addition, the core board may further include a plurality of conductive vias extending through the core layer, the first dielectric layer, and the second dielectric layer to electrically connect the first circuit layers. In the embodiment, the package structure may further include two first build-up structures disposed on the sixth surface of the first dielectric layer of the core board and the second dielectric layer. And a plurality of the first circuit layer, wherein each of the first build-up structures has at least a third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of Conductive blind holes connecting the first circuit layer and the second circuit layer.
另一方面，本發明亦提供另一種嵌埋電子元件之封裝結構，包括：一電子元件，係具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係覆蓋該作用面，且該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋；複數金屬凸塊，係具有第一端及相對之第二端，且該等第一端係面向該等電極墊；複數焊料凸塊，係設於該電子元件之該等電極墊及該等金屬凸塊間，以電性連接該等電極墊與該等金屬凸塊；以及一核心板，其包括一第一介電層，該第一介電層具有一第五表面及一第六表面，而該電子元件係嵌埋於該第一介電層中。In another aspect, the present invention also provides another package structure for embedding electronic components, comprising: an electronic component having a relatively active surface, a non-active surface, and a protective layer having a plurality of electrode pads. The protective layer covers the active surface, and the protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer; the plurality of metal bumps have a first end and Opposite the second end, and the first end faces the electrode pads; the plurality of solder bumps are disposed between the electrode pads of the electronic component and the metal bumps to electrically connect the electrodes a pad and the metal bumps; and a core plate including a first dielectric layer, the first dielectric layer having a fifth surface and a sixth surface, and the electronic component is embedded in the first In the dielectric layer.
於本發明之再一實施態樣中，上述之嵌埋電子元件之封裝結構可更包括一第一線路層，該第一線路層係設於該第一介電層之該第六表面並電性連接至該等金屬凸塊之該第二端。此外，於本實施態樣中，封裝結構可更包括至少一第一增層結構，係設於該核心板之該第一介電層之該第六表面及該第一線路層上，其中該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層與該第二線路層之導電盲孔。In a further embodiment of the present invention, the package structure for embedding the electronic component further includes a first circuit layer disposed on the sixth surface of the first dielectric layer and electrically Sexually connected to the second end of the metal bumps. In addition, in the embodiment, the package structure may further include at least one first build-up structure disposed on the sixth surface of the first dielectric layer of the core board and the first circuit layer, wherein the The first build-up structure has at least one third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically connected electrically connected to the first circuit layer and the second circuit layer Blind hole.
此外，於本發明之更一實施態樣中，嵌埋電子元件之封裝結構之核心板可更包括一第二介電層，該第二介電層具有一第七表面及一第八表面，該第二介電層之該第八表面係與該第一介電層之該第五表面相結合，且該第二介電層係覆蓋該電子元件之該非作用面。於此實施態樣中，封裝結構可更包括二第一線路層，該等第一線路層係分別設於該第一介電層之該第六表面及該第二介電層之該第七表面。同時，於本實施態樣中，核心板可更包括複數導電通孔，該等導電通孔係貫穿該第一介電層、及該第二介電層，以電性連接該等第一線路層。此外，於本實施態樣中，封裝結構可更包括二第一增層結構，係分別設於該核心板之該第一介電層之該第六表面、該第二介電層之該第七表面、及該等第一線路層上，其中該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該等第一線路層與該第二線路層之導電盲孔。In addition, in a further embodiment of the present invention, the core board of the package structure for embedding the electronic component further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface. The eighth surface of the second dielectric layer is bonded to the fifth surface of the first dielectric layer, and the second dielectric layer covers the inactive surface of the electronic component. In this embodiment, the package structure may further include two first circuit layers respectively disposed on the sixth surface of the first dielectric layer and the seventh surface of the second dielectric layer surface. In the embodiment, the core board may further include a plurality of conductive vias extending through the first dielectric layer and the second dielectric layer to electrically connect the first lines. Floor. In addition, in this embodiment, the package structure may further include two first build-up structures disposed on the sixth surface of the first dielectric layer of the core board and the second dielectric layer. And a first circuit layer, wherein the first build-up structure has at least a third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrical layers Connecting the first circuit layer and the conductive via hole of the second circuit layer.
於上述之半導體裝置及嵌埋電子元件之封裝結構中，電子元件可更包括複數金屬墊，係覆蓋該等電極墊，且該等焊料凸塊係藉由該等金屬墊電性連接該等電極墊。此外，金屬墊之材料可分別選自焊料、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。In the above-mentioned semiconductor device and the package structure of the embedded electronic component, the electronic component may further include a plurality of metal pads covering the electrode pads, and the solder bumps are electrically connected to the electrodes by the metal pads. pad. In addition, the material of the metal pad may be selected from the group consisting of solder, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively.
再者，於上述之半導體裝置及嵌埋電子元件之封裝結構中，半導體裝置可更包括一保護金屬層，係完全覆蓋該承載板之第一表面，且該等金屬凸塊係設於該保護金屬層之表面上。Furthermore, in the above-described package structure of the semiconductor device and the embedded electronic component, the semiconductor device may further include a protective metal layer completely covering the first surface of the carrier, and the metal bumps are provided in the protection On the surface of the metal layer.
於上述之半導體裝置及嵌埋電子元件之封裝結構中，金屬凸塊之材料可分別選自焊料、銅、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。In the above package structure of the semiconductor device and the embedded electronic component, the material of the metal bumps may be selected from the group consisting of solder, copper, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof. One of them.
另一方面，本發明提供一種半導體裝置之製法，包括下列步驟：(A)提供一電子元件及一承載板，其中該電子元件具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係設於該作用面，該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋，該承載板具有一第一表面及一相對之第二表面，該第一表面設有複數金屬凸塊，且該等金屬凸塊具有與該第一表面接著之第二端及面向該等電極墊之第一端；以及(B)形成複數焊料凸塊於該電子元件及該承載板間，該等焊料凸塊係分別對應且電性連接該等電極墊與該等金屬凸塊。In another aspect, the present invention provides a method of fabricating a semiconductor device, comprising the steps of: (A) providing an electronic component and a carrier board, wherein the electronic component has a relatively active surface, a non-active surface, and a protective layer. The active surface has a plurality of electrode pads, the protective layer is disposed on the active surface, and the protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer, the carrier plate Having a first surface and an opposite second surface, the first surface is provided with a plurality of metal bumps, and the metal bumps have a second end adjacent to the first surface and a first surface facing the electrode pads And (B) forming a plurality of solder bumps between the electronic component and the carrier, the solder bumps respectively correspondingly and electrically connecting the electrode pads and the metal bumps.
此外，本發明亦提供一種嵌埋電子元件封裝結構之製法，包括下列步驟：(A)提供一電子元件及一承載板，其中該電子元件具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係設於該作用面，該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋，該承載板具有一第一表面及一相對之第二表面，該第一表面設有複數金屬凸塊，且該等金屬凸塊具有與該第一表面接著之第二端及面向該等電極墊之第一端；(B)形成複數焊料凸塊於該電子元件及該承載板間，該等焊料凸塊係分別對應且電性連接該等電極墊與該等金屬凸塊；(C)形成一核心板，其包括一核心層及一第一介電層，該核心層具有一第三表面、一第四表面、及一貫穿開口，該第一介電層具有一第五表面及一第六表面，該核心層之該第四表面係與該第一介電層之該第五表面相結合，而該電子元件係設於該貫穿開口內；以及(D)移除該承載板。In addition, the present invention also provides a method for fabricating an embedded electronic component package structure, comprising the steps of: (A) providing an electronic component and a carrier board, wherein the electronic component has a relative active surface, a non-active surface, and a a protective layer, the active surface has a plurality of electrode pads, the protective layer is disposed on the active surface, the protective layer has a plurality of first openings such that the electrode pads in the first opening are not covered by the protective layer, The carrier board has a first surface and an opposite second surface, the first surface is provided with a plurality of metal bumps, and the metal bumps have a second end adjacent to the first surface and face the electrode pads The first end; (B) forming a plurality of solder bumps between the electronic component and the carrier plate, the solder bumps respectively corresponding to and electrically connecting the electrode pads and the metal bumps; (C) forming a core board comprising a core layer and a first dielectric layer, the core layer having a third surface, a fourth surface, and a through opening, the first dielectric layer having a fifth surface and a first a six surface, the fourth surface of the core layer The fifth surface of the first dielectric layer combination, which is provided in the electronic device system through the opening; and (D) removing the carrier plate.
於本發明之一實施態樣中，於步驟(D)後，可更包括一步驟(D1)：於該第一介電層之該第六表面及該等金屬凸塊之該第二端上，形成一第一線路層。此外，於本實施態樣中，於步驟(D1)後，可更包括一步驟(D2)：於該第一介電層之該第六表面及該第一線路層上，形成至少一第一增層結構，其中該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層與該第二線路層之導電盲孔。In an embodiment of the present invention, after the step (D), the method further includes a step (D1): the sixth surface of the first dielectric layer and the second end of the metal bumps Forming a first circuit layer. In addition, in this embodiment, after the step (D1), the method further includes a step (D2) of forming at least one first on the sixth surface of the first dielectric layer and the first circuit layer. a build-up structure, wherein the first build-up structure has at least a third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically connected to the first circuit layer and the Conductive blind hole of the second circuit layer.
此外，於本發明之另一實施態樣中，步驟(D)中之該核心板更包括一第二介電層，該第二介電層具有一第七表面及一第八表面，該第二介電層之該第八表面係與該核心層之該第三表面相結合，使該核心層設於該第一介電層及該第二介電層間，且該第二介電層係覆蓋該電子元件之該非作用面。於本實施態樣中，步驟(D1)後，更包括一步驟(D1’)：形成複數導電通孔、及二第一線路層，其中，該等導電通孔係貫穿該核心層、該第一介電層、及該第二介電層，以電性連接該等第一線路層，且該等第一線路層係分別設於該第一介電層之第六表面及該第二介電層之第七表面。同時，在本實施態樣中，步驟(D1’)後，更包括一步驟(D2’)：於該核心板之該第一介電層之該第六表面、該第二介電層之該第七表面、及該等第一線路層上，分別形成二第一增層結構，其中各該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層與該第二線路層之導電盲孔。In another embodiment of the present invention, the core board in the step (D) further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface, the The eighth surface of the second dielectric layer is combined with the third surface of the core layer such that the core layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is Covering the non-active surface of the electronic component. In this embodiment, after the step (D1), the method further includes a step (D1′) of forming a plurality of conductive vias and two first circuit layers, wherein the conductive vias penetrate the core layer, the first a dielectric layer and the second dielectric layer are electrically connected to the first circuit layers, and the first circuit layers are respectively disposed on the sixth surface of the first dielectric layer and the second dielectric layer The seventh surface of the electrical layer. In the embodiment, after the step (D1′), the method further includes a step (D2′): the sixth surface of the first dielectric layer of the core board, and the second dielectric layer Forming two first build-up structures on the seventh surface and the first circuit layers, wherein each of the first build-up structures has at least one third dielectric layer, at least one of which is stacked on the third dielectric layer The second circuit layer on the second circuit layer and the plurality of conductive blind holes electrically connected to the first circuit layer and the second circuit layer.
另一方面，本發明亦提供另一種嵌埋電子元件封裝結構之製法，包括下列步驟：(A)提供一電子元件及一承載板，其中該電子元件具有相對之一作用面、一非作用面、及一保護層，該作用面具有複數電極墊，該保護層係設於該作用面，該保護層具有複數第一開孔以使該第一開孔中之該等電極墊不被保護層所覆蓋，該承載板具有一第一表面及一相對之第二表面，該第一表面設有複數金屬凸塊，且該等金屬凸塊具有與該第一表面接著之第二端及面向該等電極墊之第一端；(B)形成複數焊料凸塊於該電子元件及該承載板間，該等焊料凸塊係分別對應且電性連接該等電極墊與該等金屬凸塊；(C)形成一核心板，其包括一第一介電層，該第一介電層具有一第五表面及一第六表面，而該電子元件係嵌埋於該第一介電層中；以及(D)移除該承載板。In another aspect, the present invention also provides a method for fabricating another embedded electronic component package structure, comprising the steps of: (A) providing an electronic component and a carrier board, wherein the electronic component has a relative active surface and a non-active surface And a protective layer having a plurality of electrode pads, the protective layer being disposed on the active surface, the protective layer having a plurality of first openings such that the electrode pads in the first opening are not protected Covered, the carrier has a first surface and an opposite second surface, the first surface is provided with a plurality of metal bumps, and the metal bumps have a second end adjacent to the first surface and face the (B) forming a plurality of solder bumps between the electronic component and the carrier plate, the solder bumps respectively correspondingly and electrically connecting the electrode pads and the metal bumps; C) forming a core plate comprising a first dielectric layer, the first dielectric layer having a fifth surface and a sixth surface, and the electronic component is embedded in the first dielectric layer; (D) Remove the carrier board.
於本發明之再一實施態樣中，於步驟(D)後，可更包括一步驟(D1)：於該第一介電層之該第六表面及該等金屬凸塊之該第二端上，形成一第一線路層。此外，於本實施態樣中，步驟(D1)後可更包括一步驟(D2)：於該第一介電層之該第六表面及該第一線路層上，形成至少一第一增層結構，其中該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層5與該第二線路層之導電盲孔。In a further embodiment of the present invention, after the step (D), the method further includes a step (D1): the sixth surface of the first dielectric layer and the second end of the metal bumps Above, a first circuit layer is formed. In addition, in this embodiment, the step (D1) may further include a step (D2) of forming at least one first buildup layer on the sixth surface of the first dielectric layer and the first circuit layer. The structure, wherein the first build-up structure has at least one third dielectric layer, at least one second circuit layer stacked on the third dielectric layer, and a plurality of electrically connected to the first circuit layer 5 and the first Conductive blind holes in the two circuit layers.
另一方面，於本發明之更一實施態樣中，步驟(D)中之該核心板更包括一第二介電層，該第二介電層具有一第七表面及一第八表面，該第二介電層之該第八表面係與該第一介電層之該第五表面相結合，且該第二介電層係覆蓋該電子元件之該非作用面。此外，於本實施態樣中，步驟(D1)後可更包括一步驟(D1’)：形成複數導電通孔、及二第一線路層，其中，該等導電通孔係貫穿該第一介電層、及該第二介電層，以電性連接該等第一線路層，且該等第一線路層係分別設於該第一介電層之第六表面及該第二介電層之第七表面。同時，在本實施態樣中，步驟(D1’)後可更包括一步驟(D2’)：於該核心板之該第一介電層之該第六表面、該第二介電層之該第七表面、及該等第一線路層上，分別形成二第一增層結構，其中各該第一增層結構具有至少一第三介電層、至少一疊置於該第三介電層上之第二線路層、及複數電性連接該第一線路層與該第二線路層62之導電盲孔。In another aspect of the present invention, the core board in the step (D) further includes a second dielectric layer, the second dielectric layer having a seventh surface and an eighth surface. The eighth surface of the second dielectric layer is bonded to the fifth surface of the first dielectric layer, and the second dielectric layer covers the inactive surface of the electronic component. In addition, in this embodiment, the step (D1) may further include a step (D1′) of forming a plurality of conductive vias and two first circuit layers, wherein the conductive vias extend through the first dielectric layer An electrical layer and the second dielectric layer are electrically connected to the first circuit layer, and the first circuit layers are respectively disposed on the sixth surface of the first dielectric layer and the second dielectric layer The seventh surface. In the embodiment, the step (D1′) may further include a step (D2′): the sixth surface of the first dielectric layer of the core board, and the second dielectric layer Forming two first build-up structures on the seventh surface and the first circuit layers, wherein each of the first build-up structures has at least one third dielectric layer, at least one of which is stacked on the third dielectric layer The second circuit layer and the plurality of conductive blind holes electrically connected to the first circuit layer and the second circuit layer 62.
於上述之半導體裝置及嵌埋電子元件之封裝結構中，承載板可更包括一保護金屬層，係完全覆蓋該承載板之第一表面，且該等金屬凸塊係設於該保護金屬層之表面上。In the above-mentioned semiconductor device and the package structure of the embedded electronic component, the carrier board further includes a protective metal layer completely covering the first surface of the carrier board, and the metal bumps are disposed on the protective metal layer. On the surface.
同時，於上述之半導體裝置及嵌埋電子元件之封裝結構中，電子元件可更包括複數金屬墊，係覆蓋該等電極墊，且該等焊料凸塊係藉由該等金屬墊電性連接該等電極墊。此外，金屬墊13之材料可分別選自焊料、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。In the above-mentioned semiconductor device and the package structure of the embedded electronic component, the electronic component may further include a plurality of metal pads covering the electrode pads, and the solder bumps are electrically connected by the metal pads. Electrode pad. In addition, the material of the metal pad 13 may be selected from the group consisting of solder, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively.
再者，於上述之半導體裝置及嵌埋電子元件之封裝結構中，於步驟(B)中，該等焊料凸塊可先形成在該等金屬凸塊之第一端上，再與該金屬凸塊焊接。或者，步驟(B)中，該等焊料凸塊係先形成在該等金屬墊上，再與該金屬凸塊焊接。Furthermore, in the above package structure of the semiconductor device and the embedded electronic component, in the step (B), the solder bumps may be formed on the first end of the metal bumps, and then the metal bumps Block welding. Alternatively, in step (B), the solder bumps are first formed on the metal pads and soldered to the metal bumps.
此外，於上述之半導體裝置及嵌埋電子元件之封裝結構中，金屬凸塊之材料可分別選自焊料、銅、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。In addition, in the above package structure of the semiconductor device and the embedded electronic component, the material of the metal bumps may be selected from the group consisting of solder, copper, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively. One of the groups.
習知之嵌埋電子元件之封裝結構，需對增層結構進行雷射燒灼，以將各個電子元件之電極墊與電性連接墊電性連接。然而，電子元件所置入的位置，往往造成電極墊與電性連接墊電性連接之誤差。反之，本發明之半導體裝置、嵌埋電子元件之封裝結構、及其製法，先利用金屬凸塊(可用以做為電性連接墊)與電子元件覆蓋於電極墊上之金屬墊進行對位，再利用焊料凸塊連接金屬凸塊與電子元件，而達到提升對位精準度之效果。因此，利用本發明之半導體裝置、嵌埋電子元件之封裝結構、及其製法，可減少一次雷射燒灼，即不需進行雷射燒灼形成將電子元件之電極墊與電性連接墊電性連接之導電盲孔，不僅可避免電子元件受到損害，且由於對位精準度之提高，以一次對位即可同時進行整版面基板上全數晶片之電性連接，後續每次增層之製作亦只須一次對位，同時提高封裝結構之品質及良率，並簡化製程以滿足量產之效率，且更易於應用在大面積且多電子元件之封裝結構中。In a conventional package structure for embedding electronic components, a laser ablation of the build-up structure is required to electrically connect the electrode pads of the respective electronic components to the electrical connection pads. However, the position where the electronic component is placed often causes an error in the electrical connection between the electrode pad and the electrical connection pad. On the contrary, the semiconductor device of the present invention, the package structure of the embedded electronic component, and the manufacturing method thereof are first aligned with the metal pad covered with the electronic component on the electrode pad by using the metal bump (which can be used as an electrical connection pad), and then The use of solder bumps to connect metal bumps and electronic components achieves the effect of improved alignment accuracy. Therefore, by using the semiconductor device of the present invention, the package structure of the embedded electronic component, and the manufacturing method thereof, the laser cauterization can be reduced, that is, the electrode pad of the electronic component is electrically connected to the electrical connection pad without laser ablation. The conductive blind hole can not only avoid the damage of the electronic components, but also the electrical connection of all the wafers on the entire surface substrate can be simultaneously performed by one alignment, due to the improvement of the alignment accuracy, and the subsequent production of each layer is only It must be aligned once, improving the quality and yield of the package structure, simplifying the process to meet the efficiency of mass production, and easier to apply in the packaging structure of large-area and multi-electronic components.
以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.
實施例1Example 1
請參考圖2A至圖2G，此為本實施例之嵌埋電子元件之封裝結構之製作流程剖視圖。Please refer to FIG. 2A to FIG. 2G , which are cross-sectional views showing the manufacturing process of the package structure of the embedded electronic component of the embodiment.
如圖2A所示，首先，提供一電子元件1及一承載板20，其中電子元件1具有相對之一作用面1b、一非作用面1a、及一保護層12，作用面1b具有複數電極墊11，保護層12係設於作用面1b，保護層12具有複數第一開孔121以使第一開孔121中之電極墊11不被保護層12所覆蓋，承載板20具有一第一表面2a及一相對之第二表面2b，第一表面2a設有複數金屬凸塊21，且金屬凸塊21具有與第一表面2a接著之第二端21b及面向電極墊11之第一端21a。As shown in FIG. 2A, first, an electronic component 1 and a carrier 20 are provided. The electronic component 1 has a pair of active surfaces 1b, an inactive surface 1a, and a protective layer 12. The active surface 1b has a plurality of electrode pads. The protective layer 12 is disposed on the active surface 1b. The protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first opening 121 are not covered by the protective layer 12. The carrier 20 has a first surface. 2a and an opposite second surface 2b, the first surface 2a is provided with a plurality of metal bumps 21, and the metal bumps 21 have a second end 21b followed by the first surface 2a and a first end 21a facing the electrode pad 11.
此外，如圖2A所示，承載板20可更包括一保護金屬層22，係完全覆蓋承載板20之第一表面2a，且金屬凸塊21係設於保護金屬層22之表面22a上。藉由此保護金屬層22可防止後續製程破壞電子元件1。In addition, as shown in FIG. 2A, the carrier board 20 may further include a protective metal layer 22 covering the first surface 2a of the carrier board 20, and the metal bumps 21 are disposed on the surface 22a of the protective metal layer 22. By thus protecting the metal layer 22, the subsequent process can be prevented from damaging the electronic component 1.
再者，如圖2A所示，電子元件1可更包括複數金屬墊13，係覆蓋電極墊11，且焊料凸塊31係藉由金屬墊13電性連接電極墊11。其中，金屬墊13之材料可分別選自焊料、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。此外，金屬墊13可以焊料下凸塊(under bump metal,UBM)、化鎳浸金(Electroless Ni ＆ Immersion Gold,ENIG)、化學鍍鎳鈀浸金(electroless nickel ＆ electroless palladium ＆ immersion gold,ENEPIG)等方式形成。於本實施例中，覆蓋電極墊11之金屬墊13，係以焊料下凸塊之方式形成。Furthermore, as shown in FIG. 2A , the electronic component 1 further includes a plurality of metal pads 13 covering the electrode pads 11 , and the solder bumps 31 are electrically connected to the electrode pads 11 by the metal pads 13 . The material of the metal pad 13 may be selected from the group consisting of solder, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively. In addition, the metal pad 13 may be an under bump metal (UBM), an electroless nickel & electroless palladium & immersion gold (ENEPIG). Formed by other means. In the present embodiment, the metal pad 13 covering the electrode pad 11 is formed by solder bumps.
另一方面，金屬凸塊21之材料可分別選自焊料、銅、銀、金、鎳/金、鎳/鈀/金、及其組合所組群組之其中一者。其中，金屬凸塊21可為一銅塊、一具有電性連接墊之銅塊、或一外表面鍍有金屬層(Ni/Au或Ni/Pd/Au)之銅塊。於本實施例中，金屬凸塊21係為一銅塊。此外，金屬凸塊21可為長方體、圓柱體、或梯形體。於本實施例中，金屬凸塊21為一圓柱體。Alternatively, the material of the metal bumps 21 may be selected from the group consisting of solder, copper, silver, gold, nickel/gold, nickel/palladium/gold, and combinations thereof, respectively. The metal bump 21 may be a copper block, a copper block having an electrical connection pad, or a copper block with a metal layer (Ni/Au or Ni/Pd/Au) on its outer surface. In this embodiment, the metal bumps 21 are a copper block. Further, the metal bump 21 may be a rectangular parallelepiped, a cylinder, or a trapezoidal body. In this embodiment, the metal bump 21 is a cylinder.
此外，如圖2A’所示，此為本發明之另一實施態樣，其中，覆蓋電子元件1電極墊11之金屬墊13係以化學鍍鎳鈀浸金的方式形成，且設於承載板20上之金屬凸塊21更具有一電性連接墊21’。In addition, as shown in FIG. 2A′, this is another embodiment of the present invention, in which the metal pad 13 covering the electrode pad 11 of the electronic component 1 is formed by electroless nickel-palladium immersion gold, and is disposed on the carrier plate. The metal bumps 21 on the 20 further have an electrical connection pad 21'.
接下來，如圖2A所示，形成複數焊料凸塊31於電子元件1及承載板20間，而焊料凸塊31係分別對應且電性連接電極墊11與金屬凸塊21。在此，焊料凸塊31可先形成在金屬凸塊21之第一端21a上，再與金屬凸塊21焊接；或者焊料凸塊31可先形成在金屬墊13上，再與金屬凸塊21焊接。於本實施例中，焊料凸塊31係先形成在金屬凸塊21之第一端21a上，再與金屬凸塊21焊接，以形成一半導體裝置，如圖2B所示。Next, as shown in FIG. 2A, a plurality of solder bumps 31 are formed between the electronic component 1 and the carrier 20, and the solder bumps 31 are electrically connected to the electrode pads 11 and the metal bumps 21, respectively. Here, the solder bump 31 may be formed on the first end 21a of the metal bump 21 and then soldered to the metal bump 21; or the solder bump 31 may be formed on the metal pad 13 first, and then the metal bump 21 welding. In the present embodiment, the solder bumps 31 are first formed on the first end 21a of the metal bumps 21, and then soldered to the metal bumps 21 to form a semiconductor device, as shown in FIG. 2B.
因此，如圖2B所示，本實施例所製備之半導體裝置，其包括：一電子元件1，係具有相對之一作用面1b、一非作用面1a、及一保護層12，作用面1b具有複數電極墊11，保護層12係設於作用面1b，且保護層12具有複數第一開孔121以使第一開孔121中之電極墊11不被保護層12所覆蓋；一承載板20，係具有一第一表面2a及一相對之第二表面2b，第一表面2a設有複數金屬凸塊21，金屬凸塊21具有與第一表面2a接著之第二端21b及面向電極墊11之第一端21a；以及複數焊料凸塊31，係設於電極墊11與金屬凸塊21間，以電性連接電極墊11與金屬凸塊21。Therefore, as shown in FIG. 2B, the semiconductor device prepared in this embodiment includes: an electronic component 1 having a pair of active surfaces 1b, a non-active surface 1a, and a protective layer 12, the active surface 1b having The plurality of electrode pads 11 are disposed on the active surface 1b, and the protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first openings 121 are not covered by the protective layer 12; And having a first surface 2a and an opposite second surface 2b, the first surface 2a is provided with a plurality of metal bumps 21, the metal bumps 21 having a second end 21b adjacent to the first surface 2a and facing the electrode pads 11 The first end 21a and the plurality of solder bumps 31 are disposed between the electrode pad 11 and the metal bump 21 to electrically connect the electrode pad 11 and the metal bump 21.
接下來，如圖2C所示，形成一核心板4，其包括一核心層42及一第一介電層41，核心層42具有一第三表面42a、一第四表面42b、及一貫穿開口420，第一介電層41具有一第五表面41a及一第六表面41b，核心層42之第四表面42b係與第一介電層41之第五表面41a相結合，而電子元件1係設於貫穿開口420內。Next, as shown in FIG. 2C, a core board 4 is formed, which includes a core layer 42 and a first dielectric layer 41. The core layer 42 has a third surface 42a, a fourth surface 42b, and a through opening. 420, the first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the fourth surface 42b of the core layer 42 is combined with the fifth surface 41a of the first dielectric layer 41, and the electronic component 1 is It is disposed in the through opening 420.
此外，如圖2C所示，核心板4更包括一第二介電層43，該第二介電層43具有一第七表面43a及一第八表面43b，第二介電層43之第八表面43b係與核心層42之第三表面42a相結合，使核心層42設於第一介電層41及第二介電層43間，且第二介電層43係覆蓋電子元件1之非作用面1a。In addition, as shown in FIG. 2C, the core board 4 further includes a second dielectric layer 43 having a seventh surface 43a and an eighth surface 43b, and an eighth dielectric layer 43. The surface 43b is combined with the third surface 42a of the core layer 42 such that the core layer 42 is disposed between the first dielectric layer 41 and the second dielectric layer 43, and the second dielectric layer 43 covers the non-electronic component 1 Action surface 1a.
其中，核心板4可以習知之方法形成，如壓合、真空貼合、塗佈、或印刷等方式。此外，上述之第一介電層41與第二介電層43之材料，可為習知常用之有機介電材料，如：ABF(Ajinomoto Build-up Film)、雙順丁醯二酸醯亞胺/三氮阱(Bismaleimide triazine,BT)、聯二苯環丁二烯(benzocylobutene,BCB)、液晶聚合物(Liquid Crystal Polymer)、聚亞醯胺(Polyimide,PI)、聚乙烯醚(Poly(phenylene ether))、聚四氟乙烯(Poly(tetra-fluoroethylene))、芳香尼龍(Aramide)、環氧樹脂或玻璃纖維等感光或非感光有機樹脂，或混合環氧樹脂與玻璃纖維等材質。Among them, the core plate 4 can be formed by a conventional method such as press bonding, vacuum bonding, coating, or printing. In addition, the materials of the first dielectric layer 41 and the second dielectric layer 43 may be commonly used organic dielectric materials, such as: ABF (Ajinomoto Build-up Film), and Amine/Bismaleimide triazine (BT), benzocylobutene (BCB), Liquid Crystal Polymer, Polyimide (PI), Polyether (Poly) Phenolic resin or non-photosensitive organic resin such as phenylene ether)), poly(tetra-fluoroethylene), aromatic polyamide (Aramide), epoxy resin or glass fiber, or mixed epoxy resin and glass fiber.
此外，第一介電層41或第二介電層43之介電材料，可填充於核心層42貫穿開口421與晶片1之間之間隙44。電性連接結構3間之間隙410，可能會未填充介電材料、部分填充有第一介電層41之介電材料、或完全填充有第一介電層41之介電材料等情形發生。In addition, the dielectric material of the first dielectric layer 41 or the second dielectric layer 43 may be filled in the gap 44 between the core layer 42 and the opening 421 and the wafer 1. The gap 410 between the electrical connection structures 3 may occur without filling the dielectric material, the dielectric material partially filled with the first dielectric layer 41, or the dielectric material completely filled with the first dielectric layer 41.
接下來，如圖2D所示，移除承載板20。此外，移除承載板20時，也可同時移除保護金屬層22。其中，電性連接結構3間之間隙410未填充有任何介電材料。或者，如圖2D’所示，電性連接結構3間之間隙410完全填充有第一介電層41之介電材料。Next, as shown in FIG. 2D, the carrier board 20 is removed. Further, when the carrier 20 is removed, the protective metal layer 22 can also be removed at the same time. The gap 410 between the electrical connection structures 3 is not filled with any dielectric material. Alternatively, as shown in Fig. 2D', the gap 410 between the electrical connection structures 3 is completely filled with the dielectric material of the first dielectric layer 41.
接著，如圖2E所示，於第二介電層43之第七表面43a及第一介電層41之第六表面41b上，分別形成金屬層51,51’，以用於圖案化形成線路層。Next, as shown in FIG. 2E, metal layers 51, 51' are formed on the seventh surface 43a of the second dielectric layer 43 and the sixth surface 41b of the first dielectric layer 41, respectively, for pattern formation. Floor.
如圖2F所示，形成複數導電通孔45、及二第一線路層51b,51a，其中，導電通孔45係貫穿核心層42、第一介電層41、及第二介電層43，以電性連接第一線路層51a,51b，且第一線路層51b,51a係分別設於第一介電層41之第六表面41b及該第二介電層43之第七表面43a。As shown in FIG. 2F, a plurality of conductive vias 45 and two first wiring layers 51b, 51a are formed, wherein the conductive vias 45 extend through the core layer 42, the first dielectric layer 41, and the second dielectric layer 43, The first circuit layers 51a, 51b are electrically connected, and the first circuit layers 51b, 51a are respectively disposed on the sixth surface 41b of the first dielectric layer 41 and the seventh surface 43a of the second dielectric layer 43.
接下來，如圖2G所示，於核心板4之第一介電層41之第六表面41b、第二介電層43之第七表面43a、及第一線路層51b,51a上，分別形成二第一增層結構6b,6a，其中各第一增層結構6b,6a具有至少一第三介電層61、至少一疊置於第三介電層61上之第二線路層62、及複數電性連接第一線路層51b,51a與第二線路層62之導電盲孔63。Next, as shown in FIG. 2G, the sixth surface 41b of the first dielectric layer 41 of the core board 4, the seventh surface 43a of the second dielectric layer 43, and the first wiring layers 51b, 51a are respectively formed. Two first build-up structures 6b, 6a, wherein each of the first build-up structures 6b, 6a has at least a third dielectric layer 61, at least one second circuit layer 62 stacked on the third dielectric layer 61, and The plurality of conductive blind vias 63 are electrically connected to the first circuit layers 51b, 51a and the second wiring layer 62.
此外，各第一增層結構6a,6b分別具有一防焊層7a,7b，而防焊層7a,7b具有複數開孔70，以顯露電性連接墊64，如圖2G所示。In addition, each of the first build-up structures 6a, 6b has a solder resist layer 7a, 7b, respectively, and the solder resist layers 7a, 7b have a plurality of openings 70 to expose the electrical connection pads 64, as shown in Figure 2G.
實施例2Example 2
本實施例之半導體裝置之製法與實施例1相同，除了覆蓋電子元件1電極墊11之金屬墊13係以化學鍍鎳鈀浸金的方式形成，如圖3A所示。接著，形成一核心板4，其包括一核心層42及一第一介電層41，且核心層42之貫穿開口421與晶片1之間的間隙，係填充有第一介電層41之介電材料。The semiconductor device of this embodiment is produced in the same manner as in the first embodiment except that the metal pad 13 covering the electrode pad 11 of the electronic component 1 is formed by electroless nickel-palladium immersion gold, as shown in FIG. 3A. Next, a core board 4 is formed, which includes a core layer 42 and a first dielectric layer 41, and a gap between the through opening 421 of the core layer 42 and the wafer 1 is filled with the first dielectric layer 41. Electrical material.
接著，如圖3B所示，移除該承載板20及保護金屬層22後，即形成一種嵌埋電子元件之封裝結構。本實施例之嵌埋電子元件之封裝結構，包括：一電子元件1，係具有相對之一作用面1b、一非作用面1a、及一保護層12，作用面1b具有複數電極墊11，保護層12係覆蓋作用面1b，且保護層12具有複數第一開孔121以使第一開孔121中之電極墊11不被保護層12所覆蓋；複數金屬凸塊21，係具有第一端21a及相對之第二端21b，且該等第一端21a係面向該等電極墊11；複數焊料凸塊31，係設於電子元件1之電極墊11及金屬凸塊21間，以電性連接電極墊11與金屬凸塊21；以及一核心板4，其包括一核心層42及一第一介電層41，核心層42具有一第三表面42a、一第四表面42b、及一貫穿開口420，第一介電層41具有一第五表面41a及一第六表面41b，核心層42之第四表面42b係與第一介電層41之第五表面41a相結合，而電子元件1係設於貫穿開口420內。Next, as shown in FIG. 3B, after the carrier 20 and the protective metal layer 22 are removed, a package structure in which electronic components are embedded is formed. The package structure of the embedded electronic component of the embodiment includes: an electronic component 1 having a relatively active surface 1b, an inactive surface 1a, and a protective layer 12, the active surface 1b having a plurality of electrode pads 11 for protection The layer 12 covers the active surface 1b, and the protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first openings 121 are not covered by the protective layer 12; the plurality of metal bumps 21 have a first end 21a and the opposite second end 21b, and the first end 21a faces the electrode pad 11; the plurality of solder bumps 31 are disposed between the electrode pad 11 of the electronic component 1 and the metal bump 21 to be electrically Connecting the electrode pad 11 and the metal bump 21; and a core plate 4 including a core layer 42 and a first dielectric layer 41, the core layer 42 having a third surface 42a, a fourth surface 42b, and a through The opening 420, the first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the fourth surface 42b of the core layer 42 is combined with the fifth surface 41a of the first dielectric layer 41, and the electronic component 1 It is disposed in the through opening 420.
接著，如圖3C所示，於第一介電層41之第六表面41b及金屬凸塊21之該第二端21b上，形成一第一線路層51b。其中，第一線路層51b係設於第一介電層41之第六表面41b並電性連接至金屬凸塊21之第二端21b。Next, as shown in FIG. 3C, a first wiring layer 51b is formed on the sixth surface 41b of the first dielectric layer 41 and the second end 21b of the metal bump 21. The first circuit layer 51b is disposed on the sixth surface 41b of the first dielectric layer 41 and electrically connected to the second end 21b of the metal bump 21.
如圖3D所示，於第一介電層41之第六表面41b及第一線路層51b上，形成至少一第一增層結構6b，其中第一增層結構6b具有至少一第三介電層61、至少一疊置於第三介電層61上之第二線路層62、及複數電性連接第一線路層51b與第二線路層62之導電盲孔63。As shown in FIG. 3D, at least a first build-up structure 6b is formed on the sixth surface 41b of the first dielectric layer 41 and the first circuit layer 51b, wherein the first build-up structure 6b has at least a third dielectric The layer 61, the second circuit layer 62 disposed on the third dielectric layer 61, and the conductive blind vias 63 electrically connected to the first circuit layer 51b and the second circuit layer 62.
此外，第一增層結構6b更具有一防焊層7b，而防焊層7b具有複數開孔70，以顯露電性連接墊64，如圖3D所示。In addition, the first build-up structure 6b further has a solder resist layer 7b, and the solder resist layer 7b has a plurality of openings 70 to expose the electrical connection pads 64, as shown in FIG. 3D.
另一方面，本實施例之嵌埋電子元件之封裝結構，更可進行雙邊增層，如圖3D’所示。於核心層42之第三表面42a及電子元件1非作用面1a上，更形成至少一第一增層結構6a，其中第一增層結構6a具有至少一第三介電層61、至少一疊置於第三介電層61上之第二線路層62、及複數電性連接第一線路層51b與第二線路層62之導電盲孔63。且第一增層結構6a更具有一防焊層7a，而防焊層7a具有複數開孔70，以顯露電性連接墊64。On the other hand, the package structure of the embedded electronic component of the present embodiment can be double-layered as shown in Fig. 3D'. On the third surface 42a of the core layer 42 and the non-active surface 1a of the electronic component 1, at least one first build-up structure 6a is further formed, wherein the first build-up structure 6a has at least one third dielectric layer 61, at least one stack The second circuit layer 62 disposed on the third dielectric layer 61 and the conductive blind vias 63 electrically connected to the first circuit layer 51b and the second circuit layer 62 are electrically connected. The first build-up structure 6a further has a solder resist layer 7a, and the solder resist layer 7a has a plurality of openings 70 to expose the electrical connection pads 64.
實施例3Example 3
請參考圖4A至圖4G，此為本實施例之嵌埋電子元件之封裝結構之製作流程剖視圖。Please refer to FIG. 4A to FIG. 4G , which are cross-sectional views showing the manufacturing process of the package structure of the embedded electronic component of the embodiment.
首先，如圖4A所示，提供一電子元件1及一承載板20，其中電子元件1具有相對之一作用面1b、一非作用面1a、及一保護層12，作用面1b具有複數電極墊11，保護層12係設於作用面1b，保護層12具有複數第一開孔121以使第一開孔121中之電極墊11不被保護層12所覆蓋，承載板20具有一第一表面2a及一相對之第二表面2b，第一表面2a設有複數金屬凸塊21，且金屬凸塊21具有與第一表面2a接著之第二端21b及面向電極墊11之第一端21a。First, as shown in FIG. 4A, an electronic component 1 and a carrier 20 are provided. The electronic component 1 has a pair of active surfaces 1b, an inactive surface 1a, and a protective layer 12. The active surface 1b has a plurality of electrode pads. The protective layer 12 is disposed on the active surface 1b. The protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first opening 121 are not covered by the protective layer 12. The carrier 20 has a first surface. 2a and an opposite second surface 2b, the first surface 2a is provided with a plurality of metal bumps 21, and the metal bumps 21 have a second end 21b followed by the first surface 2a and a first end 21a facing the electrode pad 11.
其中，本實施例之金屬凸塊21係為一外表面鍍有金屬層211之銅塊。於本實施例中，鍍在金屬凸塊21外表面之金屬層211係為一鎳層。The metal bump 21 of the embodiment is a copper block with an outer surface plated with a metal layer 211. In the present embodiment, the metal layer 211 plated on the outer surface of the metal bump 21 is a nickel layer.
此外，如圖4A所示，承載板20可更包括一保護金屬層22，係完全覆蓋承載板20之第一表面2a，且金屬凸塊21係設於保護金屬層22之表面22a上。藉由此保護金屬層22可防止後續製程破壞電子元件1。In addition, as shown in FIG. 4A, the carrier board 20 may further include a protective metal layer 22 covering the first surface 2a of the carrier board 20, and the metal bumps 21 are disposed on the surface 22a of the protective metal layer 22. By thus protecting the metal layer 22, the subsequent process can be prevented from damaging the electronic component 1.
再者，如圖4A所示，電子元件1可更包括複數金屬墊13，係覆蓋電極墊11，且焊料凸塊31係藉由金屬墊13電性連接電極墊11。於本實施例中，覆蓋電極墊11之金屬墊13，係以焊料下凸塊之方式形成。Furthermore, as shown in FIG. 4A , the electronic component 1 further includes a plurality of metal pads 13 covering the electrode pads 11 , and the solder bumps 31 are electrically connected to the electrode pads 11 by the metal pads 13 . In the present embodiment, the metal pad 13 covering the electrode pad 11 is formed by solder bumps.
接下來，如圖2A所示，形成複數焊料凸塊31於電子元件1及承載板20間，而焊料凸塊31係分別對應且電性連接電極墊11與金屬凸塊21。在此，焊料凸塊31可先形成在金屬凸塊21之第一端21a上，再與金屬凸塊21焊接；或者焊料凸塊31可先形成在金屬墊13上，再與金屬凸塊21焊接。於本實施例中，焊料凸塊31係先形成在金屬墊13上，再與金屬凸塊21焊接，以形成一半導體裝置，如圖4B所示。Next, as shown in FIG. 2A, a plurality of solder bumps 31 are formed between the electronic component 1 and the carrier 20, and the solder bumps 31 are electrically connected to the electrode pads 11 and the metal bumps 21, respectively. Here, the solder bump 31 may be formed on the first end 21a of the metal bump 21 and then soldered to the metal bump 21; or the solder bump 31 may be formed on the metal pad 13 first, and then the metal bump 21 welding. In the present embodiment, the solder bumps 31 are first formed on the metal pad 13 and then soldered to the metal bumps 21 to form a semiconductor device as shown in FIG. 4B.
如圖4C所示，形成一核心板4，其包括一第一介電層41，第一介電層41具有一第五表面41a及一第六表面41b，而電子元件1係嵌埋於第一介電層41中。As shown in FIG. 4C, a core board 4 is formed, which includes a first dielectric layer 41. The first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the electronic component 1 is embedded in the first layer. In a dielectric layer 41.
此外，如圖4C所示，核心板4更包括一第二介電層43，第二介電層43具有一第七表面43a及一第八表面43b，第二介電層43之第八表面43b係與第一介電層41之第五表面41a相結合，且第二介電層43係覆蓋電子元件1之非作用面1a.In addition, as shown in FIG. 4C, the core board 4 further includes a second dielectric layer 43 having a seventh surface 43a and an eighth surface 43b, and an eighth surface of the second dielectric layer 43. 43b is combined with the fifth surface 41a of the first dielectric layer 41, and the second dielectric layer 43 covers the non-active surface 1a of the electronic component 1.
移除該承載板20及保護金屬層22，及形成一嵌埋電子元件之封裝結構，如圖4D所示。在此，本實施例之嵌埋電子元件之封裝結構，包括：一電子元件1，係具有相對之一作用面1b、一非作用面1a、及一保護層12，作用面1b具有複數電極墊11，保護層12係覆蓋作用面1b，且保護層12具有複數第一開孔121以使第一開孔121中之電極墊11不被保護層12所覆蓋；複數金屬凸塊21，係具有第一端21a及相對之第二端21b，且該等第一端21a係面向該等電極墊11；複數焊料凸塊31，係設於電子元件1之電極墊11及金屬凸塊21間，以電性連接電極墊11與金屬凸塊21；以及一核心板4，其包括一第一介電層41，第一介電層41具有一第五表面41a及一第六表面41b，而電子元件1係嵌埋於第一介電層41中。此外，核心板4更包括一第二介電層43，而第二介電層43係覆蓋電子元件1之非作用面1a。The carrier board 20 and the protective metal layer 22 are removed, and a package structure for embedding electronic components is formed, as shown in FIG. 4D. Here, the package structure of the embedded electronic component of the embodiment includes: an electronic component 1 having a relatively active surface 1b, an inactive surface 1a, and a protective layer 12, the active surface 1b having a plurality of electrode pads 11. The protective layer 12 covers the active surface 1b, and the protective layer 12 has a plurality of first openings 121 such that the electrode pads 11 in the first openings 121 are not covered by the protective layer 12; the plurality of metal bumps 21 have The first end 21a and the opposite second end 21b, and the first ends 21a face the electrode pads 11; the plurality of solder bumps 31 are disposed between the electrode pads 11 of the electronic component 1 and the metal bumps 21, The electrode pad 11 and the metal bump 21 are electrically connected; and a core plate 4 includes a first dielectric layer 41. The first dielectric layer 41 has a fifth surface 41a and a sixth surface 41b, and the electrons The element 1 is embedded in the first dielectric layer 41. In addition, the core board 4 further includes a second dielectric layer 43, and the second dielectric layer 43 covers the non-active surface 1a of the electronic component 1.
接著，如圖2E所示，於第二介電層43之第七表面43a及第一介電層41之第六表面41b上，分別形成金屬層51,51’，以用於圖案化形成線路層。Next, as shown in FIG. 2E, metal layers 51, 51' are formed on the seventh surface 43a of the second dielectric layer 43 and the sixth surface 41b of the first dielectric layer 41, respectively, for pattern formation. Floor.
此外，如圖4E’所示，此為本實施例之另一實施態樣，其中，核心板4除有第一介電層41及第二介電層43外，更包括一核心層42，其中，核心層42係位於第一介電層41與第二介電層43之間。In addition, as shown in FIG. 4E ′, this is another embodiment of the embodiment, wherein the core board 4 includes a core layer 42 in addition to the first dielectric layer 41 and the second dielectric layer 43 . The core layer 42 is located between the first dielectric layer 41 and the second dielectric layer 43.
接下來，如圖4F所示，形成複數導電通孔45、及二第一線路層51b,51a，其中，導電通孔45係貫穿核心層42、第一介電層41、及第二介電層43，以電性連接第一線路層51b,51a，且第一線路層51b,51a係分別設於第一介電層41之第六表面41b及該第二介電層43之第七表面43a。Next, as shown in FIG. 4F, a plurality of conductive vias 45 and two first wiring layers 51b, 51a are formed, wherein the conductive vias 45 penetrate the core layer 42, the first dielectric layer 41, and the second dielectric. The layer 43 is electrically connected to the first circuit layers 51b, 51a, and the first circuit layers 51b, 51a are respectively disposed on the sixth surface 41b of the first dielectric layer 41 and the seventh surface of the second dielectric layer 43. 43a.
最後，如圖4G所示，於核心板4之第一介電層41之第六表面41b、第二介電層43之第七表面43a、及第一線路層51b,51a上，分別形成二第一增層結構6b,6a，其中各第一增層結構6b,6a具有至少一第三介電層61、至少一疊置於第三介電層61上之第二線路層62、及複數電性連接第一線路層51b,51a與第二線路層62之導電盲孔63。Finally, as shown in FIG. 4G, on the sixth surface 41b of the first dielectric layer 41 of the core board 4, the seventh surface 43a of the second dielectric layer 43, and the first circuit layer 51b, 51a, respectively, two a first build-up structure 6b, 6a, wherein each of the first build-up structures 6b, 6a has at least a third dielectric layer 61, at least one second circuit layer 62 stacked on the third dielectric layer 61, and a plurality The first wiring layers 51b, 51a and the conductive blind vias 63 of the second wiring layer 62 are electrically connected.
此外，各第一增層結構6a,6b分別具有一防焊層7a,7b，而防焊層7a,7b具有複數開孔70，以顯露電性連接墊64，如圖4G所示。In addition, each of the first build-up structures 6a, 6b has a solder resist layer 7a, 7b, respectively, and the solder resist layers 7a, 7b have a plurality of openings 70 to expose the electrical connection pads 64, as shown in Figure 4G.
綜上所述，利用本發明製法所製得之嵌埋電子元件之封裝結構，利用覆蓋於電子元件電極墊上之金屬墊和承載板上之金屬凸塊，透過焊料凸塊之連接，可提高自我對位之能力，並提升對位精準度。同時，不需經過雷射燒灼形成導電盲孔，即可使電子元件與增層結構之線路層電性連接。另一方面，由於本發明是先進行電子元件對位再形成核心板及增層結構，故可大面積的進行對位，節省封裝基板之製作成本，更能提升封裝基板之量產能力。此外，本發明之嵌埋電子元件之封裝結構，因電子元件的對位精準度高，更可避免增層加工時產生對位偏移的問題，而提升產品之品質及良率。In summary, the package structure of the embedded electronic component obtained by the method of the present invention can improve self by connecting the metal bumps on the electrode pads of the electronic component and the metal bumps on the carrier board through the solder bumps. The ability to align and improve alignment accuracy. At the same time, the conductive elements can be electrically connected to the circuit layer of the build-up structure without laser ablation to form a conductive blind hole. On the other hand, the present invention firstly performs the alignment of the electronic component to form the core board and the build-up structure, so that the alignment can be performed over a large area, the manufacturing cost of the package substrate can be saved, and the mass production capability of the package substrate can be improved. In addition, the package structure of the embedded electronic component of the invention has high alignment accuracy of the electronic component, and can avoid the problem of offset displacement during the layering process, thereby improving the quality and yield of the product.
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.
1．．．電子元件1. . . Electronic component
1a．．．非作用面1a. . . Non-active surface
1b．．．作用面1b. . . Action surface
11．．．電極墊11. . . Electrode pad
12．．．保護層12. . . The protective layer
121．．．第一開孔121. . . First opening
13．．．金屬墊13. . . Metal pad
20．．．承載板20. . . Carrier board
2a．．．第一表面2a. . . First surface
2b．．．第二表面2b. . . Second surface
21．．．金屬凸塊twenty one. . . Metal bump
21a．．．第一端21a. . . First end
21b．．．第二端21b. . . Second end
21’．．．電性連接墊twenty one'. . . Electrical connection pad
22．．．保護金屬層twenty two. . . Protective metal layer
22a．．．表面22a. . . surface
3．．．電性連接結構3. . . Electrical connection structure
31．．．焊料凸塊31. . . Solder bump
4．．．核心板4. . . Core board
41．．．第一介電層41. . . First dielectric layer
410．．．間隙410. . . gap
41a．．．第五表面41a. . . Fifth surface
41b．．．第六表面41b. . . Sixth surface
42．．．核心層42. . . Core layer
420．．．貫穿開口420. . . Through opening
42a．．．第三表面42a. . . Third surface
42b．．．第四表面42b. . . Fourth surface
43．．．第二介電層43. . . Second dielectric layer
43a．．．第七表面43a. . . Seventh surface
43b．．．第八表面43b. . . Eighth surface
44．．．間隙44. . . gap
45．．．導電通孔45. . . Conductive through hole
51,51’．．．金屬層51,51’. . . Metal layer
51a,51b．．．第一線路層51a, 51b. . . First circuit layer
6a,6b．．．第一增層結構6a, 6b. . . First buildup structure
60．．．介電層60. . . Dielectric layer
61．．．第三介電層61. . . Third dielectric layer
62．．．第二線路層62. . . Second circuit layer
63．．．導電盲孔63. . . Conductive blind hole
64．．．電性連接墊64. . . Electrical connection pad
7a,7b．．．防焊層7a, 7b. . . Solder mask
70．．．開孔70. . . Opening
圖1A至圖1C係習知之嵌埋電子元件之封裝結構之製作流程剖視圖。1A to 1C are cross-sectional views showing a manufacturing process of a conventional package structure for embedding electronic components.
圖2A至圖2G係本發明實施例1之嵌埋電子元件之封裝結構之製作流程剖視圖。2A to 2G are cross-sectional views showing a manufacturing process of a package structure of an embedded electronic component according to Embodiment 1 of the present invention.
圖3A至圖3D’係本發明實施例2之嵌埋電子元件之封裝結構之製作流程剖視圖。3A to 3D are cross-sectional views showing a manufacturing process of a package structure of an embedded electronic component according to a second embodiment of the present invention.
圖4A至圖4G係本發明實施例3之嵌埋電子元件之封裝結構之製作流程剖視圖。4A to 4G are cross-sectional views showing a manufacturing process of a package structure of an embedded electronic component according to Embodiment 3 of the present invention.
1．．．電子元件1. . . Electronic component
1a．．．非作用面1a. . . Non-active surface
1b．．．作用面1b. . . Action surface
11．．．電極墊11. . . Electrode pad
12．．．保護層12. . . The protective layer
121．．．第一開孔121. . . First opening
13．．．金屬墊13. . . Metal pad
20．．．承載板20. . . Carrier board
2a．．．第一表面2a. . . First surface
2b．．．第二表面2b. . . Second surface
21．．．金屬凸塊twenty one. . . Metal bump
21a．．．第一端21a. . . First end
21b．．．第二端21b. . . Second end
22．．．保護金屬層twenty two. . . Protective metal layer
22a．．．表面22a. . . surface
3．．．電性連接結構3. . . Electrical connection structure
31．．．焊料凸塊31. . . Solder bump
Claims (44)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW097142532A TWI405311B (en) | 2008-11-04 | 2008-11-04 | Semiconductor device, packaging substrate having electronic component embedded therein, and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW097142532A TWI405311B (en) | 2008-11-04 | 2008-11-04 | Semiconductor device, packaging substrate having electronic component embedded therein, and method for manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| TW201019437A TW201019437A (en) | 2010-05-16 |
| TWI405311B true TWI405311B (en) | 2013-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW097142532A TWI405311B (en) | 2008-11-04 | 2008-11-04 | Semiconductor device, packaging substrate having electronic component embedded therein, and method for manufacturing the same |
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| Country | Link |
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| TW (1) | TWI405311B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030052409A1 (en) * | 2001-08-29 | 2003-03-20 | Mie Matsuo | Semiconductor device and method of manufacturing the same |
| US20040115919A1 (en) * | 2001-05-14 | 2004-06-17 | Yuji Takaoka | Semiconductor device and its manufacturing method |
| US20050104211A1 (en) * | 2002-05-07 | 2005-05-19 | Shinji Baba | Semiconductor device having semiconductor chips mounted on package substrate |
| US6928726B2 (en) * | 2003-07-24 | 2005-08-16 | Motorola, Inc. | Circuit board with embedded components and method of manufacture |
| US20060055032A1 (en) * | 2004-09-14 | 2006-03-16 | Kuo-Chin Chang | Packaging with metal studs formed on solder pads |
| US20070210429A1 (en) * | 2006-03-07 | 2007-09-13 | Industrial Technology Research Institute | Package structure for electronic device |
-
2008
- 2008-11-04 TW TW097142532A patent/TWI405311B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040115919A1 (en) * | 2001-05-14 | 2004-06-17 | Yuji Takaoka | Semiconductor device and its manufacturing method |
| US20030052409A1 (en) * | 2001-08-29 | 2003-03-20 | Mie Matsuo | Semiconductor device and method of manufacturing the same |
| US20050104211A1 (en) * | 2002-05-07 | 2005-05-19 | Shinji Baba | Semiconductor device having semiconductor chips mounted on package substrate |
| US6928726B2 (en) * | 2003-07-24 | 2005-08-16 | Motorola, Inc. | Circuit board with embedded components and method of manufacture |
| US20060055032A1 (en) * | 2004-09-14 | 2006-03-16 | Kuo-Chin Chang | Packaging with metal studs formed on solder pads |
| US20070210429A1 (en) * | 2006-03-07 | 2007-09-13 | Industrial Technology Research Institute | Package structure for electronic device |
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| Publication number | Publication date |
|---|---|
| TW201019437A (en) | 2010-05-16 |
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