TWI405169B - Liquid crystal display device - Google Patents
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Abstract
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本發明係關於一種液晶顯示裝置。The present invention relates to a liquid crystal display device.
液晶顯示裝置由於具有重量輕、耗電少、輻射低及攜帶方便等優點而在電子產品中得到廣泛應用。隨著液晶顯示裝置之面板尺寸及解析度逐漸增大，視頻訊號於該液晶顯示裝置內部傳輸過程中所受到電磁干擾之挑戰越來越大，為此目前業界通常採用低擺幅差分訊號(Reduced Swing Differential Signal,RSDS)格式進行視頻訊號之傳輸。The liquid crystal display device is widely used in electronic products because of its advantages of light weight, low power consumption, low radiation, and convenient carrying. As the panel size and resolution of the liquid crystal display device gradually increase, the video signal is more and more challenged by the electromagnetic interference during the internal transmission of the liquid crystal display device. For this reason, the industry generally adopts a low swing differential signal (Reduced). Swing Differential Signal (RSDS) format for video signal transmission.
請參閱圖1，係一種先前技術液晶顯示裝置之結構示意圖。該液晶顯示裝置100包括一液晶面板110、一內部介面電路180及一控制電路190。其中該內部介面電路180用於實現該控制電路190與該液晶面板110間之訊號傳輸。Please refer to FIG. 1 , which is a schematic structural diagram of a prior art liquid crystal display device. The liquid crystal display device 100 includes a liquid crystal panel 110, an internal interface circuit 180, and a control circuit 190. The internal interface circuit 180 is configured to implement signal transmission between the control circuit 190 and the liquid crystal panel 110.
該液晶面板110包括一主動矩陣150、一閘極驅動器120、一第一源極驅動器130及一第二源極驅動器140。其中該主動矩陣150包括複數平行間隔設置之閘極線X1 、X2 、…X2m ，複數與該閘極線X1 、X2 、…X2m 絕緣垂直設置之資料線Y1 、Y2 、…Y2n ，以及複數由該閘極線X1 、X2 、…X2m 與該資料線Y1 、Y2 、…Y2n 分隔界定且呈矩陣分佈之畫素單元170。其中，該閘極線X1 、X2 、…X2m 連接至該閘極驅動器120，該資料線Y1 、Y2 、…Yn 連接至該第一源極驅動器130，該資料線Yn＋1 、Yn＋2 、…Y2n 連接至該第二源極驅動器140。The liquid crystal panel 110 includes an active matrix 150, a gate driver 120, a first source driver 130, and a second source driver 140. Wherein the active matrix 150 includes a shutter plurality of parallel spaced from the source line X 1, X 2, ... X 2m, a plurality of the gate lines X 1, X 2, ... X 2m insulating vertically disposed of data lines Y 1, Y 2 And Y 2n , and a plurality of pixel units 170 defined by the gate lines X 1 , X 2 , ..., X 2m and the data lines Y 1 , Y 2 , ..., Y 2n are divided and arranged in a matrix. The gate line X 1 , X 2 , ... X 2m is connected to the gate driver 120, and the data lines Y 1 , Y 2 , . . . Y n are connected to the first source driver 130, and the data line Y n+1 Y n+2 , . . . , Y 2n are connected to the second source driver 140.
該畫素單元170包括一薄膜電晶體171、一畫素電極172及一公共電極173。將處於第i列第j行之畫素單元170記為P(i,j) (1i2m，1j2n)，則該液晶面板110之主動矩陣150中，位於第1至n行之所有畫素單元P(i,j) (1i2m，1jn)由該第一源極驅動器130驅動，其薄膜電晶體171之源極分別與該資料線Yj (1jn)對應連接，其閘極及汲極分別與該閘極線Xi (1i2m)及該畫素電極172對應連接。而位於第n＋1至2n行之畫素單元P(i,j) (1i2m，n＋1j2n)由該第二源極驅動器140驅動，其薄膜電晶體171之源極分別與該資料線Yj (n＋1j2n)對應連接，其閘極及汲極亦分別與該閘極線Xi (1i2m)及該畫素電極172對應連接。且，該畫素電極172、該公共電極173及夾於其間之液晶層(圖未示)形成一液晶電容174。The pixel unit 170 includes a thin film transistor 171, a pixel electrode 172, and a common electrode 173. The pixel unit 170 in the jth row of the i-th column is denoted as P (i, j) (1 ) i 2m, 1 j 2n), in the active matrix 150 of the liquid crystal panel 110, all the pixel units P (i, j) located in the first to nth rows (1 ) i 2m, 1 j n) driven by the first source driver 130, the source of the thin film transistor 171 and the data line Y j (1) j n) corresponding connection, the gate and the drain are respectively connected to the gate line X i (1 i 2m) and the pixel electrode 172 are connected correspondingly. And the pixel unit P (i, j) located at the n+1th to 2nth rows (1 ) i 2m, n+1 j 2n) driven by the second source driver 140, the source of the thin film transistor 171 and the data line Y j (n+1) j 2n) Corresponding connection, the gate and the drain are also respectively connected to the gate line X i (1 i 2m) and the pixel electrode 172 are connected correspondingly. Moreover, the pixel electrode 172, the common electrode 173, and a liquid crystal layer (not shown) sandwiched therebetween form a liquid crystal capacitor 174.
該內部介面電路180包括一第一連接器101及一第二連接器102。該控制電路190包括一時序控制器192。該第一連接器101及該第二連接器102分別用於傳輸由該時序控制器150輸出之視頻訊號至該液晶面板110。該視頻訊號包括顯示資料訊號及其他時序訊號。該顯示資料訊號為6位R/G/B二進制訊號，其係以低擺幅差分訊號格式進行傳輸，且其包括6位紅基色二進制訊號、6位綠基色二進制訊號及6位藍基色二進制訊號。該6位紅基色二進制訊號、該6位綠基色二進制訊號及該6位藍基色二進制訊號分別包括三個差分對，且每一差分對分別包括一正極性訊號及一負極性訊號。以該6位藍基色二進制訊號為例，其三個差分對之正負極性訊號可分別記為B0P、B0N、B1P、B1N、B2P及B2N；該6位紅基色二進制訊號及該6位綠基色二進制訊號可相應進行標記。The internal interface circuit 180 includes a first connector 101 and a second connector 102. The control circuit 190 includes a timing controller 192. The first connector 101 and the second connector 102 are respectively configured to transmit the video signal output by the timing controller 150 to the liquid crystal panel 110. The video signal includes display data signals and other timing signals. The display data signal is a 6-bit R/G/B binary signal, which is transmitted in a low-swing differential signal format, and includes a 6-bit red primary binary signal, a 6-bit green primary binary signal, and a 6-bit blue primary binary signal. . The 6-bit red primary binary signal, the 6-bit green primary binary signal, and the 6-bit blue primary binary signal respectively comprise three differential pairs, and each differential pair includes a positive polarity signal and a negative polarity signal. Taking the 6-bit blue primary binary signal as an example, the positive and negative polarity signals of the three differential pairs can be respectively recorded as B0P, B0N, B1P, B1N, B2P and B2N; the 6-bit red primary binary signal and the 6-bit green primary binary The signal can be marked accordingly.
該第一連接器101包括五十引腳(pins)，其分別被定義為第一至第五十號引腳；該第二連接器102包括三十引腳，其分別被定義為第五十一至第八十號引腳。其中，各引腳之功能分別如表1所示。The first connector 101 includes fifty pins, which are respectively defined as first to fiftyth pins; the second connector 102 includes thirty pins, which are respectively defined as the fiftyth Pins one through eighty. Among them, the functions of each pin are shown in Table 1.
由表1可以看出，該第一連接器101及該第二連接器102中每個差分對所對應之引腳間均採用一接地引腳進行電氣隔離，這主要是由於低擺幅差分訊號格式係由低壓差分訊號(Low Voltage Differential Signal,LVDS)格式發展而來。具體而言，傳統之低壓差分訊號由於每一差分對之正負極性訊號在傳輸過程中分別受鄰近差分對之電磁干擾不一致，且由於低壓差分訊號之電壓擺幅較大(400mV左右)，因而其差模噪聲亦較大從而容易引起訊號惡化。因此，傳統採用低壓差分訊號格式進行顯示資料訊號傳輸時需要在相鄰低壓差分對所對應之引腳間採用一接地引腳進行電氣隔離以抑制差模噪聲。基於同樣原因，目前業界採用低擺幅差分訊號格式進行資料傳輸時，通常亦會在該內部介面電路180之第一連接器101及第二連接器102中相鄰差分對所對應之引腳間引入一接地引腳進行電氣隔離。It can be seen from Table 1 that the pins corresponding to each differential pair in the first connector 101 and the second connector 102 are electrically isolated by a ground pin, which is mainly due to the low swing differential signal. The format is developed from the Low Voltage Differential Signal (LVDS) format. Specifically, the conventional low-voltage differential signal is inconsistent with the electromagnetic interference of the adjacent differential pair during the transmission process, and the voltage swing of the low-voltage differential signal is large (about 400 mV), so The differential mode noise is also large and it is easy to cause signal deterioration. Therefore, the traditional low-voltage differential signal format for display data signal transmission requires a ground pin to be electrically isolated between the pins corresponding to adjacent low-voltage differential pairs to suppress differential mode noise. For the same reason, when the data transmission is performed by the low swing digital signal format in the industry, it is usually also between the pins corresponding to the adjacent differential pairs in the first connector 101 and the second connector 102 of the internal interface circuit 180. A ground pin is introduced for electrical isolation.
然，由於該內部介面電路180之第一連接器101及第二連接器102中引入大量接地引腳，因而該內部介面電路180之引腳總數目較大，由此使得該內部介面電路180所採用之第一連接器101及第二連接器102所耗費之成本較高，並進一步導致該液晶顯示裝置100之成本較高。另一方面，上述大量接地引腳使得該第一連接器101及該第二連接器102總尺寸增大，因此該內部介面電路180內部需要配備相應面積之印製電路板及資料傳輸線，此進一步提高該液晶顯示裝置100之成本。However, since a large number of ground pins are introduced in the first connector 101 and the second connector 102 of the internal interface circuit 180, the total number of pins of the internal interface circuit 180 is large, thereby causing the internal interface circuit 180 to The cost of using the first connector 101 and the second connector 102 is relatively high, and further causes the cost of the liquid crystal display device 100 to be high. On the other hand, the plurality of grounding pins are used to increase the overall size of the first connector 101 and the second connector 102. Therefore, the internal interface circuit 180 needs to be provided with a corresponding area of the printed circuit board and the data transmission line. The cost of the liquid crystal display device 100 is increased.
有鑑於此，有必要提供一種低成本之液晶顯示裝置。In view of this, it is necessary to provide a low-cost liquid crystal display device.
一種液晶顯示裝置，其包括一液晶面板、一內部介面電路及一控制電路。該液晶面板包括一主動矩陣及一用於驅動該主動矩陣之源極驅動器。該內部介面電路包括一連接單元。該控制電路藉由該連接單元連接至該源極驅動器。該連接單元包括複數用於傳輸顯示資料訊號之資料引腳，且該複數資料引腳連續設置。該顯示資料訊號於該控制電路中轉換為低擺幅差分訊號，並藉由該連接單元之資料引腳輸出至該源極驅動器。A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes an active matrix and a source driver for driving the active matrix. The internal interface circuit includes a connection unit. The control circuit is connected to the source driver by the connection unit. The connection unit includes a plurality of data pins for transmitting a display data signal, and the plurality of data pins are continuously set. The display data signal is converted into a low swing differential signal in the control circuit, and is output to the source driver through a data pin of the connection unit.
一種液晶顯示裝置，其包括一液晶面板、一內部介面電路及一控制電路。該液晶面板包括複數畫素單元。該內部介面電路包括一連接單元。該控制電路藉由該連接單元連接至該液晶面板。該連接單元包括複數用於傳輸顯示資料訊號且依次設置之資料引腳。該顯示資料訊號於該控制電路中轉換為低擺幅差分訊號，並藉由該連接單元之資料引腳輸出至該液晶面板，以驅動該畫素單元顯示畫面。A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes a plurality of pixel units. The internal interface circuit includes a connection unit. The control circuit is connected to the liquid crystal panel by the connecting unit. The connection unit includes a plurality of data pins for transmitting display data signals and sequentially setting them. The display data signal is converted into a low swing differential signal in the control circuit, and outputted to the liquid crystal panel by the data pin of the connection unit to drive the pixel unit display screen.
一種液晶顯示裝置，其包括一液晶面板、一內部介面電路及一控制電路。該液晶面板包括複數畫素單元、一第一源極驅動器及一第二源極驅動器，且該複數畫素單元一部份由該第一源極驅動器驅動，另一部份由該第二源極驅動器驅動。該內部介面電路包括一第一連接單元及一第二連接單元。該第一連接單元包括複數連續設置之第一資料引腳，該第二連接單元包括複數連續設置之第二資料引腳。該第一資料引腳及該第二資料引腳分別用於傳輸該第一源極驅動器及該複數第二資料引腳對應之顯示資料訊號。該顯示資料訊號於該控制電路中轉換為低擺幅差分訊號，並藉由該第一資料引腳及第二資料引腳分別輸出至該第一源極驅動器及該第二源極驅動器以驅動該畫素單元。A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes a plurality of pixel units, a first source driver and a second source driver, and the plurality of pixel units are partially driven by the first source driver and the other portion is driven by the second source Pole driver drive. The internal interface circuit includes a first connection unit and a second connection unit. The first connection unit includes a plurality of consecutively disposed first data pins, and the second connection unit includes a plurality of consecutively disposed second data pins. The first data pin and the second data pin are respectively configured to transmit the display data signals corresponding to the first source driver and the plurality of second data pins. The display data signal is converted into a low swing differential signal in the control circuit, and is output to the first source driver and the second source driver by the first data pin and the second data pin respectively. The pixel unit.
相較於先前技術，本發明液晶顯示裝置之內部介面電路中，該連接單元用於傳輸顯示資料訊號之複數資料引腳依次設置或連續設置，從而有效減小該液晶顯示裝置內部連接單元之尺寸。採用該小尺寸之連接單元有效降低該液晶顯示裝置之成本。且，由於該連接單元尺寸較小，該內部介面電路中可採用小尺寸之印製電路板及資料傳輸線，由此，該液晶顯示裝置之成本得到進一步降低。Compared with the prior art, in the internal interface circuit of the liquid crystal display device of the present invention, the connection unit is configured to sequentially or continuously set the plurality of data pins for displaying the data signal, thereby effectively reducing the size of the internal connection unit of the liquid crystal display device. . The use of the small-sized connecting unit effectively reduces the cost of the liquid crystal display device. Moreover, since the size of the connecting unit is small, a small-sized printed circuit board and a data transmission line can be used in the internal interface circuit, whereby the cost of the liquid crystal display device is further reduced.
請參閱圖2，係本發明液晶顯示裝置第一實施方式之結構示意圖。該液晶顯示裝置200包括一液晶面板210、一內部介面電路280及一控制電路290。其中，該內部介面電路280用於實現該控制電路290與該液晶面板210間之訊號傳輸。2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. The liquid crystal display device 200 includes a liquid crystal panel 210, an internal interface circuit 280, and a control circuit 290. The internal interface circuit 280 is configured to implement signal transmission between the control circuit 290 and the liquid crystal panel 210.
該液晶面板210包括一主動矩陣250、一閘極驅動器220、一第一源極驅動器230及一第二源極驅動器240。其中該主動矩陣250包括複數平行間隔設置之閘極線X1 、X2 、…X2m ，複數與該閘極線X1 、X2 、…X2m 絕緣垂直設置之資料線Y1 、Y2 、…Y2n ，以及複數由該閘極線X1 、X2 、…X2m 與該資料線Y1 、Y2 、…Y2n 分隔界定且呈矩陣分佈之畫素單元270。其中，該閘極線X1 、X2 、…X2m 連接至該閘極驅動器220，該資料線Y1 、Y2 、…Yn 連接至該第一源極驅動器230，該資料線Yn＋1 、Yn＋2 、…Y2n 連接至該第二源極驅動器240。The liquid crystal panel 210 includes an active matrix 250, a gate driver 220, a first source driver 230, and a second source driver 240. Wherein the active matrix 250 includes a shutter plurality of parallel spaced from the source line X 1, X 2, ... X 2m, a plurality of the gate lines X 1, X 2, ... X 2m insulating vertically disposed of data lines Y 1, Y 2 And Y 2n , and a plurality of pixel units 270 defined by the gate lines X 1 , X 2 , ..., X 2m and the data lines Y 1 , Y 2 , ..., Y 2n are divided and arranged in a matrix. The gate line X 1 , X 2 , . . . , X 2m is connected to the gate driver 220, and the data lines Y 1 , Y 2 , . . . , Y n are connected to the first source driver 230, and the data line Y n+1 Y n+2 , . . . , Y 2n are connected to the second source driver 240.
該畫素單元270包括一薄膜電晶體271、一畫素電極272及一公共電極273。將處於第i列第j行之畫素單元270記為P(i,j) (1i2m，1j2n)，則該液晶面板210之主動矩陣250中，位於第1至n行之所有畫素單元P(i,j) (1i2m，1jn)由該第一源極驅動器230驅動，且該畫素單元P(i,j) (1i2m，1jn)中，該薄膜電晶體271之源極分別與該資料線Yj (1jn)對應連接，其閘極及汲極分別與該閘極線Xi (1i2m)及該畫素電極272對應連接。而位於第n＋1至2n行之畫素單元P(i,j) (1i2m，n＋1j2n)由該第二源極驅動器240驅動，且該畫素單元P(i,j) (1i2m，n＋1j2n)中，該薄膜電晶體271之源極分別與該資料線Yj (n＋1j2n)對應連接，其閘極及汲極亦分別與該閘極線Xi (1i2m)及該畫素電極272對應連接。該畫素電極272、該公共電極273及夾於其間之液晶層(圖未示)形成一液晶電容274。The pixel unit 270 includes a thin film transistor 271, a pixel electrode 272, and a common electrode 273. The pixel unit 270 in the jth row of the i-th column is denoted as P (i, j) (1 ) i 2m, 1 j 2n), in the active matrix 250 of the liquid crystal panel 210, all the pixel units P (i, j) located in the first to nth rows (1 ) i 2m, 1 j n) driven by the first source driver 230, and the pixel unit P (i, j) (1 ) i 2m, 1 j In n), the source of the thin film transistor 271 and the data line Y j (1, respectively) j n) corresponding connection, the gate and the drain are respectively connected to the gate line X i (1 i 2m) and the pixel electrode 272 are connected correspondingly. And the pixel unit P (i, j) located at the n+1th to 2nth rows (1 ) i 2m, n+1 j 2n) driven by the second source driver 240, and the pixel unit P (i, j) (1 ) i 2m, n+1 j In 2n), the source of the thin film transistor 271 and the data line Y j (n+1) j 2n) Corresponding connection, the gate and the drain are also respectively connected to the gate line X i (1 i 2m) and the pixel electrode 272 are connected correspondingly. The pixel electrode 272, the common electrode 273, and a liquid crystal layer (not shown) sandwiched therebetween form a liquid crystal capacitor 274.
該控制電路290包括一時序控制器292。該內部介面電路280包括一連接單元201。該連接單元201係一連接器，其用於傳輸由該時序控制器292輸出之視頻訊號至該液晶面板210。該視頻訊號包括顯示資料訊號及其他時序訊號。其中，該顯示資料訊號為6位R/G/B二進制訊號，其係以低擺幅差分訊號格式進行傳輸，且其包括6位紅基色(R)二進制訊號、6位綠基色(G)二進制訊號及6位藍基色(B)二進制訊號。該6位紅基色二進制訊號、該6位綠基色二進制訊號及該6位藍基色二進制訊號分別包括三個差分對，且每一差分對分別包括一正極性訊號及一負極性訊號。以該6位藍基色二進制訊號為例，其三個差分對之正負極性訊號可分別記為B0P、B0N、B1P、B1N、B2P及B2N；該6位紅基色二進制訊號及該6位綠基色二進制訊號可相應進行標記。The control circuit 290 includes a timing controller 292. The internal interface circuit 280 includes a connection unit 201. The connecting unit 201 is a connector for transmitting the video signal output by the timing controller 292 to the liquid crystal panel 210. The video signal includes display data signals and other timing signals. The display data signal is a 6-bit R/G/B binary signal, which is transmitted in a low-swing differential signal format, and includes a 6-bit red primary color (R) binary signal and a 6-bit green primary color (G) binary. Signal and 6-bit blue primary (B) binary signal. The 6-bit red primary binary signal, the 6-bit green primary binary signal, and the 6-bit blue primary binary signal respectively comprise three differential pairs, and each differential pair includes a positive polarity signal and a negative polarity signal. Taking the 6-bit blue primary binary signal as an example, the positive and negative polarity signals of the three differential pairs can be respectively recorded as B0P, B0N, B1P, B1N, B2P and B2N; the 6-bit red primary binary signal and the 6-bit green primary binary The signal can be marked accordingly.
請一併參閱圖3，其係該連接單元201之電路示意圖。該連接單元201包括六十引腳，其分別被定義為第一至第六十號引腳。相鄰兩個引腳之間的距離為0.45－0.55mm，優選為0.5mm。其中，各引腳之功能分別如表2所示。Please refer to FIG. 3 together, which is a schematic circuit diagram of the connection unit 201. The connection unit 201 includes sixty pins, which are defined as first to sixtyth pins, respectively. The distance between two adjacent pins is 0.45-0.55 mm, preferably 0.5 mm. Among them, the functions of each pin are shown in Table 2.
由表2可看出，該連接單元201包括用於傳輸該第一源極驅動器230對應之顯示資料訊號之複數第一資料引腳(即第17－34號引腳)，且該複數第一資料引腳依次設置。具體而言，該複數依次設置第一資料引包括一首端資料引腳及一末端資料引腳，且除該首端資料引腳及該末端資料引腳外，任一第一資料引腳之相鄰二引腳亦為該第一資料引腳。因而該複數第一資料引腳係連續設置於該連接單元201，相鄰第一資料引腳之間並無引入接地引腳進行電氣隔離。該連接單元201還包括用於傳輸該第二源極驅動器240對應之顯示資料訊號之複數第二資料引腳(即第42－59號引腳)，且該複數第二資料引腳亦為依次設置，相鄰第二資料引腳之間亦無引入接地引腳進行電氣隔離。As can be seen from Table 2, the connection unit 201 includes a plurality of first data pins (ie, pins 17-34) for transmitting the display data signals corresponding to the first source driver 230, and the plural number is first. The data pins are set in order. Specifically, the plurality of data references sequentially includes a head data pin and an end data pin, and any first data pin except the first end data pin and the end data pin The adjacent two pins are also the first data pin. Therefore, the plurality of first data pins are continuously disposed on the connection unit 201, and no ground pin is introduced between adjacent first data pins for electrical isolation. The connection unit 201 further includes a plurality of second data pins (ie, pins 42-59) for transmitting the display data signals corresponding to the second source driver 240, and the plurality of second data pins are also sequentially Set, there is no grounding pin between adjacent second data pins for electrical isolation.
當該液晶顯示裝置200工作時，該控制電路290接收該視頻訊號，且藉由其內部之時序控制器292將該視頻訊號解析為上述顯示資料訊號及時序控制訊號。該時序控制器292進一步將該顯示資料訊號轉換成低擺幅差分訊號格式，並藉由該連接單元201將該顯示資料訊號分別傳輸至對應之第一源極驅動器230及第二源極驅動器240。該時序控制器292同時將該時序控制訊號對應傳輸至該閘極驅動器220、該第一源極驅動器230及該第二源極驅動器240。When the liquid crystal display device 200 is in operation, the control circuit 290 receives the video signal, and the video signal is parsed into the display data signal and the timing control signal by its internal timing controller 292. The timing controller 292 further converts the display data signal into a low swing differential signal format, and transmits the display data signal to the corresponding first source driver 230 and second source driver 240 by the connecting unit 201, respectively. . The timing controller 292 simultaneously transmits the timing control signal to the gate driver 220, the first source driver 230, and the second source driver 240.
該第一源極驅動器230藉由該連接單元201之第17－32號引腳接收其對應之顯示資料訊號，並分別藉由該連接單元201之第3、8、10、14、15、36及37號引腳接收其對應之電源電壓、起始脈衝訊號、輸出極性控制訊號、反衝電壓補償訊號、資料鎖存脈衝訊號、正極性時鐘訊號及負極性時鐘訊號。該第一源極驅動器230進一步將該顯示資料訊號轉換成對應之資料電壓。The first source driver 230 receives its corresponding display data signal through pins 17-32 of the connection unit 201, and respectively passes through the third, eighth, ten, 14, 15, and 36 of the connection unit 201. And the 37th pin receives its corresponding power supply voltage, start pulse signal, output polarity control signal, kickback voltage compensation signal, data latch pulse signal, positive polarity clock signal and negative polarity clock signal. The first source driver 230 further converts the display data signal into a corresponding data voltage.
該第二源極驅動器240藉由該連接單元201之第42－59號引腳接收其所對應之顯示資料訊號，並分別藉由該連接單元201之第4、9、10、14、15、39及40號引腳接收其對應之電源電壓、起始脈衝訊號、輸出極性控制訊號、反衝電壓補償訊號、資料鎖存脈衝訊號、正極性時鐘訊號及負極性時鐘訊號。該第二源極驅動器240亦進一步將該顯示資料訊號轉換成對應之資料電壓。The second source driver 240 receives the corresponding display data signal by the pins 42-59 of the connection unit 201, and is respectively connected by the fourth, 9, 10, 14, 15 of the connection unit 201. Pins 39 and 40 receive their corresponding power supply voltage, start pulse signal, output polarity control signal, kickback voltage compensation signal, data latch pulse signal, positive polarity clock signal and negative polarity clock signal. The second source driver 240 further converts the display data signal into a corresponding data voltage.
該閘極驅動器220藉由該連接單元201之第5號引腳接收電源電壓，並分別藉由該連接單元201之第11、12及13號引腳接收其對應之輸出使能訊號、時鐘訊號及起始脈衝訊號。該閘極驅動器220進一步根據上述訊號產生複數掃描脈衝訊號，並依序施加至該閘極線X1 、X2 、…X2m 。當該掃描脈衝訊號施加至該第i(1i2m)條閘極線Xi 時，與該閘極線Xi 相連接之第i(1i2m)列薄膜電晶體271導通。該第一源極驅動器230及該第二源極驅動器240分別將其內部產生之資料電壓對應輸出至該第i列畫素單元P(i,j) (1j2n)之畫素電極272。同時，該公共電極273接收一公共電壓電路(圖未示)發出之公共電壓，從而使得該畫素電極272與該公共電極273間形成一電場。該電場驅動夾於該畫素電極272與該公共電極273間之液晶分子發生旋轉，控制光線通過量以顯示畫面。The gate driver 220 receives the power supply voltage through the fifth pin of the connection unit 201, and receives the corresponding output enable signal and clock signal through the pins 11 and 12 of the connection unit 201, respectively. And the starting pulse signal. The gate driver 220 further generates a plurality of scan pulse signals according to the signals, and sequentially applies the gate lines X 1 , X 2 , . . . , X 2m . When the scan pulse signal is applied to the i-th (1) i The first i 2m) Article gate line X i, is connected to the gate line of X i (1 i The 2m) column thin film transistor 271 is turned on. The first source driver 230 and the second source driver 240 respectively output corresponding data voltages generated therein to the i-th pixel unit P (i, j) (1 ) j 2n) of the pixel electrode 272. At the same time, the common electrode 273 receives a common voltage from a common voltage circuit (not shown), so that an electric field is formed between the pixel electrode 272 and the common electrode 273. The electric field drives the liquid crystal molecules sandwiched between the pixel electrode 272 and the common electrode 273 to rotate, and controls the light throughput to display a picture.
由上可見，該液晶顯示裝置200中，該內部介面電路280之連接單元201僅引入少量之接地引腳。具體而言，其將先前技術液晶顯示裝置100之內部介面電路180中相鄰差分對所對應引腳間之接地引腳去除，而僅保留用於傳輸時序控制訊號之引腳間所需要之接地引腳。由於該顯示資料訊號係以低擺幅差分低壓訊號之格式進行訊號傳輸，且低擺幅差分低壓訊號每一差分對之正負極性訊號之電壓擺幅均較小(典型值分別為±200mV)，因而其在傳輸過程中可能產生之差模噪聲較小。具體而言，在該內部介面電路280中，雖然該顯示資料訊號在傳輸過程中每一差分對之正負極性訊號在鄰近差分對之電磁干擾下亦會產生一定幅度之不一致，然由於該顯示資料訊號係轉換成低擺幅差分低壓訊號格式再進行傳輸，因此上述電磁干擾之不一致幅度較小，通常並不影響訊號之傳輸。本實施例經實驗證明，該較小之差模噪聲並不會對該低擺幅差分訊號格式之顯示資料訊號之傳輸效果造成影響。As can be seen from the above, in the liquid crystal display device 200, the connection unit 201 of the internal interface circuit 280 introduces only a small number of ground pins. Specifically, it removes the ground pin between the pins corresponding to adjacent differential pairs in the internal interface circuit 180 of the prior art liquid crystal display device 100, and only needs the ground required between the pins for transmitting the timing control signals. Pin. Since the display data signal is transmitted in a low swing differential low voltage signal format, and the voltage swing of the positive and negative polarity signals of each differential pair of the low swing differential low voltage signal is small (typically ±200 mV, respectively), Therefore, the differential mode noise that may be generated during transmission is small. Specifically, in the internal interface circuit 280, although the positive and negative polarity signals of each differential pair during the transmission of the display data signal may have a certain amplitude inconsistency under the electromagnetic interference of the adjacent differential pair, the display data is The signal is converted into a low-swing differential low-voltage signal format for transmission, so the above-mentioned electromagnetic interference has a small inconsistency and usually does not affect the transmission of the signal. The experimental example proves that the smaller differential mode noise does not affect the transmission effect of the display data signal of the low swing differential signal format.
請參閱圖4，其係本發明之液晶顯示裝置200之內部介面電路280傳輸之資料訊號實際驗證結果之波形圖。該波形圖係表示第27及28號引腳所測得之訊號波形，也即表示該第一源極驅動器230所對應之6位綠基色二進制訊號第三個差分對之訊號波形。該波形圖係藉由TEK TDS7404型示波器之差分探頭於該液晶顯示裝置200以60Hz之掃描頻率顯示解析度為1280×1204之Dot On/Off畫面下測得，其包括一第一曲線401、一第二曲線402及一第三曲線403。其中該第一曲線401係該6位綠基色二進制訊號第三個差分對之正極性訊號G2P－1之電壓曲線，該第二曲線402係其負極性訊號G2N－1之電壓曲線，該第三曲線403係該6位綠基色訊號第三個差分對之差模電壓曲線。在該實驗中，藉由該第三曲線403實際測得該差模電壓值為424mV。由於通常低擺幅差分訊號之差模電壓值(即其正負極性訊號之電壓擺幅之差，典型值為400mV)只要不小於200mV就可滿足傳輸要求，因此，雖然該6位綠基色二進制訊號第三個差分對所對應之引腳間沒有引入接地引腳進行電氣隔離，然實驗證明其傳輸效果實際上並不會受到影響。也就是說，該6位綠基色二進制訊號第三個差分對之正極性訊號G2P－1及負極性訊號G2N－1在傳輸過程中，其差模電壓之實際值由於受到噪聲干擾而偏離理想值(即上述典型值)之程度係在允許之範圍內，因此該6位綠基色二進制訊號第三個差分對之傳輸效果並不會受到影響。Please refer to FIG. 4 , which is a waveform diagram of actual verification results of data signals transmitted by the internal interface circuit 280 of the liquid crystal display device 200 of the present invention. The waveform diagram shows the signal waveform measured by the pins 27 and 28, that is, the signal waveform of the third differential pair of the 6-bit green primary binary signal corresponding to the first source driver 230. The waveform is measured by the differential probe of the TEK TDS7404 oscilloscope on the Dot On/Off screen of the liquid crystal display device 200 with a resolution of 1280×1204 at a scanning frequency of 60 Hz, and includes a first curve 401 and a The second curve 402 and a third curve 403. The first curve 401 is a voltage curve of the positive polarity signal G2P-1 of the third differential pair of the 6-bit green primary color binary signal, and the second curve 402 is a voltage curve of the negative polarity signal G2N-1, the third Curve 403 is the differential mode voltage curve of the third differential pair of the 6-bit green primary color signal. In this experiment, the differential mode voltage value was actually measured by the third curve 403 to be 424 mV. Since the differential mode voltage value of the normally low-swing differential signal (ie, the difference between the voltage swings of the positive and negative polarity signals, typically 400 mV) can satisfy the transmission requirement as long as it is not less than 200 mV, therefore, although the 6-bit green primary color binary signal The ground pin is not introduced between the pins corresponding to the third differential pair for electrical isolation. However, the experiment proves that the transmission effect is not affected. That is to say, in the transmission process, the positive value of the third differential pair of the 6-bit green primary binary signal G2P-1 and the negative polarity signal G2N-1 are deviated from the ideal value due to noise interference. The degree of the above-mentioned typical value is within the allowable range, so the transmission effect of the third differential pair of the 6-bit green primary binary signal is not affected.
請參閱表3，其係該液晶顯示裝置200之內部介面電路280傳輸之資料訊號所測得之差模電壓值。Please refer to Table 3, which is the differential mode voltage value measured by the data signal transmitted by the internal interface circuit 280 of the liquid crystal display device 200.
由表3可見，該液晶顯示裝置200之內部介面電路280所傳輸之顯示資料訊號之所有差模電壓值均大於200mV，也就是說，該內部介面電路280可滿足低擺幅差分訊號之傳輸要求，其傳輸效果並不會因為去除相鄰差分對所對應之接地引腳而受到影響。It can be seen from Table 3 that all differential mode voltage values of the display data signals transmitted by the internal interface circuit 280 of the liquid crystal display device 200 are greater than 200 mV, that is, the internal interface circuit 280 can meet the transmission requirements of the low swing differential signals. The transmission effect is not affected by removing the ground pin corresponding to the adjacent differential pair.
綜上所述，本發明之液晶顯示裝置200於其內部介面電路280之連接單元201中，用於傳輸該第一源極驅動器230及該第二源極驅動器240所對應之低擺幅差分訊號之資料引腳分別依次設置，將每對資料引腳之間用於進行電氣隔離之接地引腳被去除。經實驗證明，上述接地引腳之去除並不會對該內部介面電路280之處傳輸效果造成影響。也就是說，先前技術之液晶顯示裝置100中，基於傳輸低壓差分訊號格式之介面電路發展而來之傳輸低擺幅差分訊號之內部介面電路180中，相鄰差分對所對應之訊號引腳間分別採用一接地引腳進行電氣隔離係目前業界之一技術偏見。本發明之液晶顯示裝置200有效克服上述技術偏見，並帶來以下技術效果。一方面，由於大量接地引腳被取消，該液晶顯示裝置200之內部介面電路280中，該連接單元201之引腳得到更加有效之利用，因而其尺寸較小成本較低，因而可降低該液晶顯示裝置200之成本。另一方面，由於該連接單元201總面積較小，該內部介面電路280中與該連接單元201對應之印製電路板及資料傳輸線之尺寸同樣可有效減小，由此可進一步降低該內部介面電路280及該液晶顯示裝置200之成本。In summary, the liquid crystal display device 200 of the present invention is configured to transmit the low swing differential signal corresponding to the first source driver 230 and the second source driver 240 in the connection unit 201 of the internal interface circuit 280. The data pins are sequentially set, and the ground pins for electrically isolating between each pair of data pins are removed. It has been experimentally proved that the removal of the above ground pin does not affect the transmission effect of the internal interface circuit 280. That is to say, in the prior art liquid crystal display device 100, the internal interface circuit 180 for transmitting a low-swing differential signal based on the interface circuit for transmitting the low-voltage differential signal format is developed, and the signal pins corresponding to the adjacent differential pairs are The use of a grounding pin for electrical isolation is currently one of the industry's technical biases. The liquid crystal display device 200 of the present invention effectively overcomes the above-mentioned technical bias and brings about the following technical effects. On the one hand, since a large number of ground pins are eliminated, the pins of the connection unit 201 are more effectively utilized in the internal interface circuit 280 of the liquid crystal display device 200, so that the size thereof is smaller and the cost is lower, so that the liquid crystal can be lowered. The cost of the display device 200. On the other hand, since the total area of the connecting unit 201 is small, the size of the printed circuit board and the data transmission line corresponding to the connecting unit 201 in the internal interface circuit 280 can also be effectively reduced, thereby further reducing the internal interface. The cost of the circuit 280 and the liquid crystal display device 200.
本發明之液晶顯示裝置200並不侷限於以上實施方式所描述。如，該控制電路290還可進一步包括一縮放控制器(Scaler)對資料訊號進行縮放控制，且該時序控制器292直接集成於該縮放控制器內部。又如，該內部介面電路280中，該六十引腳之連接單元201還可採用一對三十引腳之連接單元代替等。The liquid crystal display device 200 of the present invention is not limited to the above embodiment. For example, the control circuit 290 may further include a scaling controller (Scaler) to perform scaling control on the data signal, and the timing controller 292 is directly integrated inside the scaling controller. For example, in the internal interface circuit 280, the sixty-pin connection unit 201 can also be replaced by a pair of thirty-pin connection units.
請參閱圖5，係本發明液晶顯示裝置第二實施方式之結構示意圖。該液晶顯示裝置500與上述液晶顯示裝置200之結構相似，其區別在於：該液晶顯示裝置500之液晶面板510僅包括一源極驅動器530。該液晶面板510之主動矩陣530內部所有畫素單元均由該源極驅動器530驅動。該液晶顯示裝置500之內部介面電路580包括一連接單元501，其用於傳輸資料訊號及時序訊號至該液晶面板510之閘極驅動器520及源極驅動器530。該連接單元501包括三十六引腳，且各引腳之功能分別如表4所示。表4中，“＊－S”表示與該源極驅動器530對應；“＊－G”表示與該閘極驅動器520對應，且各引腳功能符號與表2所示液晶顯示裝置200之連接單元201各引腳功能相對應。Referring to FIG. 5, it is a schematic structural view of a second embodiment of a liquid crystal display device of the present invention. The liquid crystal display device 500 is similar in structure to the liquid crystal display device 200 described above, except that the liquid crystal panel 510 of the liquid crystal display device 500 includes only one source driver 530. All of the pixel units in the active matrix 530 of the liquid crystal panel 510 are driven by the source driver 530. The internal interface circuit 580 of the liquid crystal display device 500 includes a connection unit 501 for transmitting data signals and timing signals to the gate driver 520 and the source driver 530 of the liquid crystal panel 510. The connection unit 501 includes thirty-six pins, and the functions of the pins are as shown in Table 4. In Table 4, "*-S" indicates that it corresponds to the source driver 530; "*-G" indicates a connection unit corresponding to the gate driver 520, and each pin function symbol is connected to the liquid crystal display device 200 shown in Table 2. 201 pin functions correspond.
由表4可以看出，該內部介面電路580之連接單元501之三十六個引腳中，第15－32號引腳用於傳輸顯示資料訊號，且該第15－32號引腳均連續設置，從而使得該連接單元501之尺寸較小成本較低。另一方面，該液晶顯示裝置500中，該主動矩陣510之所有畫素單元570均由該源極驅動器530進行驅動，從而使得該內部介面電路580之連接單元501僅需採用三十六引腳。因此，該液晶顯示裝置500之成本可進一步降低，且使得該液晶面板510之結構更加緊湊，符合液晶顯示裝置微縮化之產業趨勢。As can be seen from Table 4, among the thirty-six pins of the connection unit 501 of the internal interface circuit 580, pins 15-32 are used for transmitting display data signals, and the pins 15-32 are continuous. The arrangement is such that the size of the connecting unit 501 is smaller and less expensive. On the other hand, in the liquid crystal display device 500, all the pixel units 570 of the active matrix 510 are driven by the source driver 530, so that the connection unit 501 of the internal interface circuit 580 only needs to adopt 36 pins. . Therefore, the cost of the liquid crystal display device 500 can be further reduced, and the structure of the liquid crystal panel 510 is made more compact, conforming to the industrial trend of miniaturization of the liquid crystal display device.
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝之人士，在援依本案發明精神所作之等效修飾或變化，皆應包含於以下申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be equivalently modified or changed in accordance with the spirit of the invention. All should be included in the scope of the following patent application.
200、500‧‧‧液晶顯示裝置200, 500‧‧‧ liquid crystal display device
210、510‧‧‧液晶面板210, 510‧‧‧ LCD panel
220、520‧‧‧閘極驅動器220, 520‧‧ ‧ gate driver
230、240、530‧‧‧源極驅動器230, 240, 530‧‧‧ source drivers
250、550‧‧‧主動矩陣250, 550‧‧ ‧ active matrix
270、570‧‧‧畫素單元270, 570‧‧ ‧ pixel unit
271‧‧‧薄膜電晶體271‧‧‧film transistor
272‧‧‧畫素電極272‧‧‧pixel electrodes
273‧‧‧公共電極273‧‧‧Common electrode
274‧‧‧液晶電容274‧‧‧Liquid Crystal Capacitor
280、580‧‧‧內部介面電路280, 580‧‧‧Internal interface circuit
201、501‧‧‧連接單元201, 501‧‧‧ Connection unit
290‧‧‧控制電路290‧‧‧Control circuit
292‧‧‧時序控制器292‧‧‧Sequence Controller
401‧‧‧第一曲線401‧‧‧ first curve
402‧‧‧第二曲線402‧‧‧second curve
403‧‧‧第三曲線403‧‧‧ third curve
VDD‧‧‧電源電壓VDD‧‧‧Power supply voltage
X1 、X2 、…X2m ‧‧‧閘極線X 1 , X 2 ,...X 2m ‧‧‧ gate line
Y1 、Y2 、…Y2n ‧‧‧資料線Y 1 , Y 2 , ... Y 2n ‧‧‧ data line
圖1係先前技術一種液晶顯示裝置之結構示意圖。1 is a schematic structural view of a liquid crystal display device of the prior art.
圖2係本發明液晶顯示裝置第一實施方式之結構示意圖。2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention.
圖3係圖2所示液晶顯示裝置之內部介面電路之連接單元之電路示意圖。3 is a circuit diagram showing a connection unit of an internal interface circuit of the liquid crystal display device shown in FIG. 2.
圖4係圖2所示液晶顯示裝置之內部介面電路所傳輸之資料訊號之波形圖。4 is a waveform diagram of data signals transmitted by an internal interface circuit of the liquid crystal display device shown in FIG. 2.
圖5係本發明液晶顯示裝置第二實施方式之結構示意圖。Fig. 5 is a schematic view showing the structure of a second embodiment of the liquid crystal display device of the present invention.
液晶顯示裝置．．．200Liquid crystal display device. . . 200
畫素電極．．．272Pixel electrode. . . 272
液晶面板．．．210LCD panel. . . 210
公共電極．．．273Common electrode. . . 273
閘極驅動器．．．220Gate driver. . . 220
液晶電容．．．274Liquid crystal capacitors. . . 274
源極驅動器．．．230、240Source driver. . . 230, 240
內部介面電路．．．280Internal interface circuit. . . 280
主動矩陣．．．250Active matrix. . . 250
連接單元．．．201Connection unit. . . 201
畫素單元．．．270Pixel unit. . . 270
控制電路．．．290Control circuit. . . 290
薄膜電晶體．．．271Thin film transistor. . . 271
時序控制器．．．292Timing controller. . . 292
Claims (29)
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| TW97105350A TWI405169B (en) | 2008-02-15 | 2008-02-15 | Liquid crystal display device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW494384B (en) * | 2000-07-27 | 2002-07-11 | Samsung Electronics Co Ltd | Flat panel display |
| US20020093512A1 (en) * | 2001-01-15 | 2002-07-18 | Hannstar Display Corp. | Programmable interface |
| US20040178976A1 (en) * | 2003-03-12 | 2004-09-16 | Jeon Yong Weon | Bus interface technology |
| CN101071537A (en) * | 2004-03-31 | 2007-11-14 | 恩益禧电子股份有限公司 | Electronic device |
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| TW494384B (en) * | 2000-07-27 | 2002-07-11 | Samsung Electronics Co Ltd | Flat panel display |
| US20020093512A1 (en) * | 2001-01-15 | 2002-07-18 | Hannstar Display Corp. | Programmable interface |
| US20040178976A1 (en) * | 2003-03-12 | 2004-09-16 | Jeon Yong Weon | Bus interface technology |
| CN101071537A (en) * | 2004-03-31 | 2007-11-14 | 恩益禧电子股份有限公司 | Electronic device |
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