TWI404171B - Method for buried bit line and single side bit line contact process and scheme - Google Patents
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本發明係關於一種製作埋藏式位元線與單側位元線接觸窗之方法及其結構，尤指一種製作記憶體之埋藏式位元線與單側位元線接觸窗之方法及其結構。The invention relates to a method for fabricating a buried bit line and a single-sided bit line contact window and a structure thereof, in particular to a method for fabricating a buried bit line and a single-sided bit line contact window of a memory and a structure thereof .
DRAM位元胞(bit cell)係由一金氧半導體(metal-oxide-semiconductor，MOS)電晶體串連至一電容器(capacitor)所構成。電容器一般設計為堆疊於半導體基材表面上的堆疊電容(stack capacitor)或深埋入基材的溝渠電容(trench capacitor)；電晶體則以閘極通道(channel)區域相對於半導體基材原始表面(primary surface)的方位分類，可分為閘極通道電流方向與半導體基材原始表面平行的平面式電晶體裝置，以及閘極通道電流方向與半導體基材原始表面垂直之垂直式電晶體結構二種。The DRAM bit cell is composed of a metal-oxide-semiconductor (MOS) transistor connected in series to a capacitor. The capacitor is generally designed as a stack capacitor stacked on the surface of the semiconductor substrate or a trench capacitor buried deep in the substrate; the transistor is in a gate channel region relative to the original surface of the semiconductor substrate The orientation classification of the primary surface can be divided into a planar transistor device in which the current direction of the gate channel is parallel to the original surface of the semiconductor substrate, and a vertical transistor structure in which the current direction of the gate channel is perpendicular to the original surface of the semiconductor substrate. Kind.
而習知DRAM位元胞之MOS電晶體係由電性連接至閘極的字元線(word line)控制MOS電晶體的開關，並利用電性連接至源極/汲極的位元線(bit line)形成並控制一電流傳輸通路，再經由汲極/源極電性連接至電容器之電極達成DRAM位元胞之儲存或輸出。The MOS transistor system of the conventional DRAM bit cell controls the switch of the MOS transistor by a word line electrically connected to the gate, and utilizes a bit line electrically connected to the source/drain ( Bit line) forms and controls a current transmission path, and then electrically connects to the electrode of the capacitor via the drain/source to achieve storage or output of the DRAM bit cell.
另外，習知DRAM位元胞係為8F2 單元，其中F表示特徵尺寸(feature)，即既定製程之最小實際尺寸，如半導體製程之線寬。隨著各種電子產品朝小型化發展之趨勢，DRAM位元胞的設計也必須符合高積集度、高密度之要求，因此半導體業界係致力於降低DRAM位元胞的尺寸，從8F2 單元至6F2 單元。而利用埋藏式位元線、埋藏式字元線以及垂直式MOS電晶體結構，現今半導體業界已可達成將DRAM位元胞的尺寸降低至4F2 單元的目標。請參閱第1圖，第1圖係為一習知4F2 單元的DRAM陣列之佈局圖案示意圖。根據第1圖，4F2 單元的DRAM陣列100包含有埋藏式位元線110、埋藏式字元線120以及電容器130。在長度方向上，埋藏式字元線120寬度與電容器130佔2F；在寬度方向上，電容器130與埋藏式位元線110寬度佔2F，因此一個DRAM位元胞的面積為2F×2F=4F2 。In addition, the conventional DRAM bit cell system is an 8F 2 cell, where F represents a feature size, that is, the minimum actual size of the custom process, such as the line width of the semiconductor process. With the trend toward miniaturization of various electronic products, the design of DRAM bit cells must also meet the requirements of high integration and high density. Therefore, the semiconductor industry is working to reduce the size of DRAM bit cells, from 8F 2 units to 6F 2 unit. With buried bit lines, buried word lines, and vertical MOS transistor structures, the semiconductor industry today has achieved the goal of reducing the size of DRAM cells to 4F 2 cells. Please refer to FIG. 1 , which is a schematic diagram of a layout pattern of a conventional 4F 2 unit DRAM array. According to FIG. 1, the DRAM array 100 of the 4F 2 cell includes a buried bit line 110, a buried word line 120, and a capacitor 130. In the length direction, the width of the buried word line 120 and the capacitor 130 occupy 2F; in the width direction, the width of the capacitor 130 and the buried bit line 110 occupy 2F, so the area of one DRAM bit cell is 2F×2F=4F 2 .
藉由上述埋藏式位元線110與埋藏式字元線110等埋藏式的電路設計，可減少記憶體位元胞中每個元件接點所佔用的空間，因此埋藏式電路設計不僅可使用於DRAM陣列中，更是廣泛使用於多種記憶體中。但值得注意的是，如第1圖所示之埋藏式位元線110仍需要利用一位元線接觸窗112與MOS電晶體的源極/汲極電性連接，以建構電流傳輸通路。然而，埋藏式位元線110係一深埋在半導體基底中的三維結構，因此如何能在埋藏式位元線110中準確地形成位元線接觸窗112，確保各記憶體如第1圖之DRAM位元胞可被準確地操作，或避免相鄰的記憶體位元胞因位元線接觸窗112製作缺陷而被不正常的開啟，仍為業界持續關注的問題。By using the buried circuit design such as the buried bit line 110 and the buried word line 110, the space occupied by each component contact in the memory cell can be reduced, so that the buried circuit design can be used not only for DRAM. In the array, it is widely used in a variety of memory. However, it is worth noting that the buried bit line 110 as shown in FIG. 1 still needs to be electrically connected to the source/drain of the MOS transistor by using a one-line contact window 112 to construct a current transmission path. However, the buried bit line 110 is a three-dimensional structure buried deep in the semiconductor substrate, so how the bit line contact window 112 can be accurately formed in the buried bit line 110, ensuring that each memory is as shown in FIG. The DRAM bit cell can be operated accurately, or the adjacent memory bit cell is abnormally turned on due to the defect of the bit line contact window 112, which is still a problem of continuous concern in the industry.
因此，本發明之一目的係在於提供一種可在半導體基底中準確地形成單側接觸窗的埋藏式位元線及其製作方法。Accordingly, it is an object of the present invention to provide a buried bit line that can accurately form a one-sided contact window in a semiconductor substrate and a method of fabricating the same.
根據本發明所提供之申請專利範圍，係提供一種埋藏式位元線之製作方法，該方法首先提供一半導體基底，接下來進行一第一蝕刻製程，於該半導體基底內形成複數個第一溝渠(trench)，並於該等第一溝渠之側壁形成一第一保護層。隨後進行一第二蝕刻製程，蝕刻該等第一溝渠底部之半導體基底，形成複數個第二溝渠；並於該等第二溝渠內依序形成一第二保護層與一第三保護層，且該第三保護層之高度小於該第二溝渠之深度。接下來移除部分該第一保護層，而暴露出部分該第一溝渠之側壁，隨後於暴露之該等第一溝渠之側壁形成一第四保護層，再移除第一溝渠內之該第一保護層，於該等第一溝渠內分別形成一開口，並移除該第三保護層。接著透過該開口於該基底內形成一接觸窗，以及於該第一溝渠與該第二溝渠內形成一金屬複合層。According to the patent application scope provided by the present invention, a method for fabricating a buried bit line is provided, which first provides a semiconductor substrate, and then performs a first etching process to form a plurality of first trenches in the semiconductor substrate. (trench), and forming a first protective layer on the sidewalls of the first trenches. a second etching process is performed to etch the semiconductor substrate at the bottom of the first trench to form a plurality of second trenches; and a second protective layer and a third protective layer are sequentially formed in the second trenches, and The height of the third protective layer is less than the depth of the second trench. And then removing a portion of the first protective layer to expose a portion of the sidewall of the first trench, and then forming a fourth protective layer on the sidewall of the exposed first trench, and removing the first layer in the first trench a protective layer, respectively forming an opening in the first trenches and removing the third protective layer. Then, a contact window is formed in the substrate through the opening, and a metal composite layer is formed in the first trench and the second trench.
根據本發明所提供之申請專利範圍，另提供一種埋藏式位元線，包含有一設置於一半導體基底內之溝渠、一設置於該溝渠側壁與底部之第一保護層、一形成於該溝渠側壁上之第一保護層中之開口、一對應於該對開口而形成於該半導體基底內之接觸窗、一形成於該溝渠相對於該開口之側壁上之第二保護層、以及一設置於該溝渠內之金屬複合層。According to the patent application provided by the present invention, a buried bit line includes a trench disposed in a semiconductor substrate, a first protective layer disposed on the sidewall and the bottom of the trench, and a sidewall formed on the trench. An opening in the first protective layer, a contact window formed in the semiconductor substrate corresponding to the pair of openings, a second protective layer formed on the sidewall of the trench relative to the opening, and a a metal composite layer in the trench.
根據本發明所提供之埋藏式位元線及其製作方法，係藉由不同保護層的形成與移除於埋藏式位元線的單側定義出開口形成的位置與大小，繼而透過該開口準確地在半導體基底中形成接觸窗，確保埋藏式位元線與MOS電晶體的電流傳疏通路的建構，並避免相鄰的記憶體位元胞因埋藏式位元線接觸窗製作的缺陷而被不正常的開啟。The buried bit line provided by the present invention and the method for fabricating the same are defined by the formation and removal of different protective layers on one side of the buried bit line to define the position and size of the opening, and then accurately pass through the opening. Forming a contact window in the semiconductor substrate to ensure the construction of the buried channel of the buried bit line and the MOS transistor, and avoiding the defect of the adjacent memory bit cell due to the buried bit line contact window. Normally turned on.
請參閱第2圖至第13圖，第2圖至第13圖係為本發明所提供之埋藏式位元線之製作方法之一第一較佳實施例的製作流程剖面圖。首先需注意本發明所提供之埋藏式位元線製作方法係以DRAM為例示說明，但熟習該項技藝人士應知本發明所提供之製作方法亦不限於其他類型之記憶體如靜態隨機存取記憶體(Static random access memory，SRAM)或快閃記憶體等。如第2圖所示，本發明所提供之方法首先係提供一半導體基底200，隨後對半導體基底200進行一第一蝕刻製程，透過一習知圖案化硬遮罩202於半導體基底200內形成複數個第一溝渠(trench)204。接下來，於半導體基底200上形成一第一保護層206，且第一保護層206係如第2圖所示覆蓋各第一溝渠204之底部與側壁。另外，第一保護層206可包含氮化矽、氮氧化矽或氧化-氮化-氧化(oxide-nitride-oxide，ONO)複合物等與半導體基底200具蝕刻率差異的材料。Please refer to FIG. 2 to FIG. 13 . FIG. 2 to FIG. 13 are cross-sectional views showing a manufacturing process of a first preferred embodiment of a method for fabricating a buried bit line provided by the present invention. It should be noted that the method for fabricating the buried bit line provided by the present invention is exemplified by the DRAM. However, those skilled in the art should be aware that the manufacturing method provided by the present invention is not limited to other types of memory such as static random access. Static random access memory (SRAM) or flash memory. As shown in FIG. 2, the method provided by the present invention first provides a semiconductor substrate 200, and then performs a first etching process on the semiconductor substrate 200 to form a plurality of semiconductor masks 200 through a conventional patterned hard mask 202. A first trench 204. Next, a first protective layer 206 is formed on the semiconductor substrate 200, and the first protective layer 206 covers the bottom and sidewalls of each of the first trenches 204 as shown in FIG. In addition, the first protective layer 206 may include a material having a difference in etching rate from the semiconductor substrate 200, such as tantalum nitride, hafnium oxynitride or an oxide-nitride-oxide (ONO) composite.
請參閱第3圖。進行一第二蝕刻製程，蝕刻部份第一保護層206，並使殘餘之第一保護層206於各第一溝渠204之側壁上形成側壁子(spacer)，接著再藉由圖案化硬遮罩202與側壁子的遮蔽保護，蝕刻第一溝渠204底部之半導體基底200，直至埋藏式位元線預定之深度，而形成複數個第二溝渠208。Please refer to Figure 3. Performing a second etching process, etching a portion of the first protective layer 206, and forming a residual first protective layer 206 on the sidewalls of each of the first trenches 204, and then patterning the hard mask The shielding protection of the 202 and the sidewalls etches the semiconductor substrate 200 at the bottom of the first trench 204 until a predetermined depth of the buried bit line forms a plurality of second trenches 208.
請參閱第4圖與第5圖，接下來係於第二溝渠208內依序形成一第二保護層210與一第三保護層212：例如首先係進行一熱氧化製程，而於第二溝渠208之底部與側壁形成具有氧化矽材料的第二保護層210。由於第一溝渠204之側壁係由第一保護層206所覆蓋，因此僅有裸露出來的第二溝渠208的底部與側壁被氧化反應形成第二保護層210。接下來請參閱第5圖，在形成第二保護層210後，係進行一沈積製程，於第二溝渠208內形成一填滿第二溝渠208的多孔性(porous)氧化矽層或未摻雜多晶矽(undoped-polysilicon)層等蝕刻率不同於第一保護層206的膜層，再藉由一回蝕刻(etching back)製程回蝕刻上述膜層至暴露出第一保護層206，而形成如第5圖所示之第三保護層212，用以於後續製程中保護第二溝渠208底部的半導體基底200。值得注意的是，第三保護層212之高度係小於第二溝渠208之深度；換句話說，第三保護層212之高度以不覆蓋到第一保護層206為準。Referring to FIG. 4 and FIG. 5, a second protective layer 210 and a third protective layer 212 are sequentially formed in the second trench 208: for example, a thermal oxidation process is performed first, and a second trench is formed. The bottom and sidewalls of 208 form a second protective layer 210 having a yttria material. Since the sidewalls of the first trench 204 are covered by the first protective layer 206, only the bottom and sidewalls of the exposed second trench 208 are oxidized to form the second protective layer 210. Next, referring to FIG. 5, after forming the second protective layer 210, a deposition process is performed to form a porous ruthenium oxide layer or undoped in the second trench 208 filling the second trench 208. An etch rate of the undoped-polysilicon layer is different from that of the first protective layer 206, and the etch back is etched back to expose the first protective layer 206 by an etching back process to form a first The third protective layer 212 is shown in FIG. 5 for protecting the semiconductor substrate 200 at the bottom of the second trench 208 in a subsequent process. It should be noted that the height of the third protective layer 212 is smaller than the depth of the second trench 208; in other words, the height of the third protective layer 212 is not covered by the first protective layer 206.
請參閱第6圖與第7圖。待完成第三保護層212之製作後，係於第二溝渠208內的第三保護層212上形成一第一光阻層214，且第一光阻層214係如第6圖所示，覆蓋第二溝渠208內部分的第二保護層210與第一溝渠204內部分的第一保護層206。接下來如第7圖所示，移除未被第一光阻層214覆蓋的第一保護層206，而暴露出第一溝渠204之側壁。隨後移除第一光阻層214。值得注意的是，在移除部分第一保護層206後，剩餘的第一保護層206如第7圖所示，係對稱地設置於各第一溝渠204內相對的兩側壁上。Please refer to Figure 6 and Figure 7. After the third protective layer 212 is formed, a first photoresist layer 214 is formed on the third protective layer 212 in the second trench 208, and the first photoresist layer 214 is covered as shown in FIG. A second protective layer 210 of a portion of the second trench 208 and a first protective layer 206 of a portion of the first trench 204. Next, as shown in FIG. 7, the first protective layer 206 not covered by the first photoresist layer 214 is removed, and the sidewalls of the first trench 204 are exposed. The first photoresist layer 214 is then removed. It should be noted that after removing a portion of the first protective layer 206, the remaining first protective layer 206 is symmetrically disposed on opposite sidewalls of each of the first trenches 204 as shown in FIG.
請參閱第8圖。隨後進行一熱氧化製程，於暴露出來的第一溝渠204側壁形成一包含氧化矽材料的第四保護層216。此時，若第三保護層212包含未摻雜多晶矽，則其表面亦會形成一氧化矽層212a。由此可知，第二溝渠208內係設置有一覆蓋第二溝渠208側壁與底部的第二保護層210與第三保護層212、氧化矽層212a；而第一溝渠204之側壁則由下而上設置有第一保護層206與第四保護層216。第二保護層210、第四保護層216與氧化矽層212a包含有相同的氧化矽材料，其蝕刻率係與設置於兩者中間的第一保護層206不同。Please refer to Figure 8. A thermal oxidation process is then performed to form a fourth protective layer 216 comprising a yttria material on the exposed sidewalls of the first trench 204. At this time, if the third protective layer 212 contains undoped polysilicon, a tantalum oxide layer 212a is also formed on the surface. Therefore, the second trench 208 is provided with a second protective layer 210 and a third protective layer 212 and a ruthenium oxide layer 212a covering the sidewalls and the bottom of the second trench 208; and the sidewall of the first trench 204 is from bottom to top. A first protective layer 206 and a fourth protective layer 216 are provided. The second protective layer 210, the fourth protective layer 216 and the hafnium oxide layer 212a comprise the same hafnium oxide material, and the etching rate is different from the first protective layer 206 disposed between the two.
請參閱第9圖。接下來於第一溝渠204與第二溝渠208內形成一圖案化之第二光阻層218，且第二光阻層218係覆蓋第一溝渠204與第二溝渠208的兩側壁的其中之一，較佳為覆蓋第一溝渠204與第二溝渠208中相同側之單一側壁上的第一保護層206與第四保護層216。另外，為避免第一溝渠204與第二溝渠208的深度造成第二光阻層218顯影的問題，繼而影響第二光阻層218覆蓋單側第一保護層206與第四保護層216的準確性，熟習該項技藝之人士應知第二光阻層218亦可由一多晶矽或硼磷矽玻璃(borophosphosilicate glass，BPSG)(圖未示)等蝕刻率異於第一保護層206與第三保護層216之膜層所取代。多晶矽與BPSG首先係填滿第一溝渠204與第二溝渠208，再對上述膜層進行一圖案化步驟，使得圖案化的多晶矽或BPSG如同第9圖中的第二光阻層218，僅覆蓋第一溝渠204與第二溝渠208中相同側之單一側壁上的第一保護層206與第四保護層216，更確保覆蓋單側第一保護層206與第四保護層216的準確性。Please refer to Figure 9. A patterned second photoresist layer 218 is formed in the first trench 204 and the second trench 208, and the second photoresist layer 218 covers one of the sidewalls of the first trench 204 and the second trench 208. Preferably, the first protective layer 206 and the fourth protective layer 216 are covered on a single sidewall of the same side of the first trench 204 and the second trench 208. In addition, in order to avoid the problem that the depth of the first trench 204 and the second trench 208 causes the second photoresist layer 218 to be developed, the second photoresist layer 218 is affected to cover the first side first protective layer 206 and the fourth protective layer 216. The person skilled in the art should be aware that the second photoresist layer 218 may also have an etch rate different from that of the first protective layer 206 and the third protection by a polycrystalline germanium or borophosphosilicate glass (BPSG) (not shown). The film layer of layer 216 is replaced. The polysilicon and BPSG first fill the first trench 204 and the second trench 208, and then perform a patterning step on the film layer, so that the patterned polysilicon or BPSG is like the second photoresist layer 218 in FIG. The first protective layer 206 and the fourth protective layer 216 on the single sidewall of the same side of the first trench 204 and the second trench 208 further ensure the accuracy of covering the one-sided first protective layer 206 and the fourth protective layer 216.
請參閱第10圖，接下來進行一蝕刻製程，利用第一保護層206蝕刻率不同於第二保護層210、第四保護層216與氧化矽層212a之特點，移除未被第二光阻層218覆蓋的第一保護層206，而於各第一溝渠204內形成一開口222，且開口222係形成於各第一溝渠204的同一側側壁。由第2圖至第10圖可知，在本實施例中，第一溝渠204之深度決定了開口222底部之位置；而第一光阻層214在第一溝渠204內之高度則決定了開口222頂部之位置。換句話說，由第一溝渠之深度204與第一光阻層214在第一溝渠204內之高度係可定義開口222之大小。Referring to FIG. 10, an etching process is performed to remove the second photoresist layer by using the first protective layer 206 with an etch rate different from that of the second protective layer 210, the fourth protective layer 216, and the yttrium oxide layer 212a. The first protective layer 206 is covered by the layer 218, and an opening 222 is formed in each of the first trenches 204, and the opening 222 is formed on the same side wall of each of the first trenches 204. As can be seen from FIG. 2 to FIG. 10, in the present embodiment, the depth of the first trench 204 determines the position of the bottom of the opening 222; and the height of the first photoresist layer 214 within the first trench 204 determines the opening 222. The position of the top. In other words, the height of the opening 222 can be defined by the depth of the first trench 204 and the height of the first photoresist layer 214 within the first trench 204.
請參閱第11圖。接下來，依序移除第二光阻層218、氧化矽層212a與第三保護層212，並於第一溝渠204與第二溝渠208內形成一填滿開口222的含砷層。在本第一較佳實施例中，該含砷層包含一矽砷玻璃(arsenic silicate glass，ASG)層224。Please refer to Figure 11. Next, the second photoresist layer 218, the yttrium oxide layer 212a and the third protective layer 212 are sequentially removed, and an arsenic-containing layer filling the opening 222 is formed in the first trench 204 and the second trench 208. In the first preferred embodiment, the arsenic-containing layer comprises an arsenic silicate glass (ASG) layer 224.
請參閱第12圖。形成ASG層224後，即進行一熱擴散製程，使ASG層224內的砷離子由開口222擴散進入半導體基底200，而形成一對應於開口222的接觸窗226。在形成接觸窗226之後，則去除ASG層224，而暴露出開口222。另外，本第一較佳實施例之一變化型中，接觸窗226亦可利 用氣相摻雜(gas phase doping)而形成於半導體基底200內，使接觸窗226可包含砷等N型摻雜質。此一透過開口222所形成的接觸窗226即用以與後續形成的MOS電晶體的源極/汲極電性連接，確保電流傳疏通路的建構。Please refer to Figure 12. After the ASG layer 224 is formed, a thermal diffusion process is performed to diffuse arsenic ions in the ASG layer 224 from the opening 222 into the semiconductor substrate 200 to form a contact window 226 corresponding to the opening 222. After the contact window 226 is formed, the ASG layer 224 is removed and the opening 222 is exposed. In addition, in a variation of the first preferred embodiment, the contact window 226 may also be advantageous. The gas phase doping is formed in the semiconductor substrate 200 such that the contact window 226 may contain an N-type dopant such as arsenic. The contact window 226 formed through the opening 222 is electrically connected to the source/drain of the subsequently formed MOS transistor to ensure the construction of the current draining path.
接下來請參閱第13圖。在完成接觸窗226的製作後，係於第一溝渠204與第二溝渠208內形成一金屬複合層230，用以作為位元線。金屬複合層230係可包含一填滿開口222的鈦層232、一鎢層236與一設置於鈦層232與鎢層236之間的氮化鈦層234，但熟習該項技藝之人士應知複合金屬層230之材料選擇係不限於此，任何適用的金屬或金屬化合物材料皆可作為金屬複合層230之材料選擇。此外，在形成上述金屬層時，剩餘的第一保護層206、第二保護層210與第四保護層216係用以保護半導體基底200不受金屬污染。最後，再於金屬複合層230上方形成一第五保護層240，填滿第一溝渠204，完成埋藏式位元線250之製作。第五保護層240可為一氧化矽層，但不限於此。Next, please refer to Figure 13. After the fabrication of the contact window 226 is completed, a metal composite layer 230 is formed in the first trench 204 and the second trench 208 for use as a bit line. The metal composite layer 230 can include a titanium layer 232 filling the opening 222, a tungsten layer 236, and a titanium nitride layer 234 disposed between the titanium layer 232 and the tungsten layer 236, but those skilled in the art should be aware of the art. The material selection of the composite metal layer 230 is not limited thereto, and any suitable metal or metal compound material may be selected as the material of the metal composite layer 230. In addition, when the above metal layer is formed, the remaining first protective layer 206, second protective layer 210 and fourth protective layer 216 are used to protect the semiconductor substrate 200 from metal contamination. Finally, a fifth protective layer 240 is formed over the metal composite layer 230 to fill the first trench 204 to complete the fabrication of the buried bit line 250. The fifth protective layer 240 may be a hafnium oxide layer, but is not limited thereto.
另外請參閱第14圖至第15圖。第14圖至第15圖係為本發明所提供之一第二較佳實施例之示意圖。在第二較佳實施例中，由於形成第一保護層206、第二保護層210、第三保護層212、第四保護層216、開口222與含砷層等步驟係同於第一較佳實施例，因此上述步驟係不再贅述，熟習該項技藝之人士係可逕行參閱第2圖至第11圖而得知。本第二較佳實施例與第一較佳實施例不同的是，形成於第一溝渠204與第二溝渠208內且填滿開口222的含砷層係為一含砷多晶矽層。Please also refer to Figures 14 through 15. 14 to 15 are schematic views showing a second preferred embodiment of the present invention. In the second preferred embodiment, the steps of forming the first protective layer 206, the second protective layer 210, the third protective layer 212, the fourth protective layer 216, the opening 222, and the arsenic-containing layer are the same as the first one. For the embodiments, the above steps are not described again, and those skilled in the art can refer to FIGS. 2 to 11 for details. The second preferred embodiment differs from the first preferred embodiment in that the arsenic-containing layer formed in the first trench 204 and the second trench 208 and filling the opening 222 is an arsenic-containing polysilicon layer.
請參閱第14圖。在形成含砷多晶矽層之後，同樣利用一熱擴散製程，使含砷多晶矽層內的砷離子由開口222擴散進入半導體基底200，而形成一對應於開口222的接觸窗226，隨後移除開口222以外的含砷多晶矽層，但開口222內仍有剩餘的含砷多晶矽層225所填滿。接下來於第一溝渠204與第二溝渠208內形成一鈦層(圖未示)，並進行一自對準金屬矽化物製程之步驟，使填滿開口222的含砷多晶矽層225與鈦反應形成一如第14圖所示之金屬矽化物層228。上述金屬矽化物製程係為該為半導體領域中具通常知識者所熟知，故於此亦不再贅述。值得注意的是，由於金屬矽化物層228的形成，係可避免後續形成的埋藏式位元線與MOS電晶體的源極/汲極之間發生尖峰(spiking)現象。Please refer to Figure 14. After forming the arsenic-containing polysilicon layer, the arsenic ions in the arsenic-containing polysilicon layer are diffused into the semiconductor substrate 200 from the opening 222 by a thermal diffusion process to form a contact window 226 corresponding to the opening 222, and then the opening 222 is removed. The arsenic-containing polysilicon layer is not filled, but the remaining arsenic-containing polysilicon layer 225 remains in the opening 222. Next, a titanium layer (not shown) is formed in the first trench 204 and the second trench 208, and a self-aligned metal telluride process is performed to react the arsenic-containing polysilicon layer 225 filling the opening 222 with titanium. A metal telluride layer 228 as shown in Fig. 14 is formed. The above metal telluride process is well known to those of ordinary skill in the semiconductor art and will not be described herein. It is worth noting that due to the formation of the metal telluride layer 228, a spiking phenomenon between the subsequently formed buried bit line and the source/drain of the MOS transistor can be avoided.
請繼續參閱第15圖。在完成金屬矽化物層228的製作後，係於第一溝渠204與第二溝渠208內形成一金屬複合層230，用以作為位元線。金屬複合層230係可包含一氮化鈦層234與鎢層236，但不限於此。同樣地，在形成上述金屬層時，剩餘的第一保護層206、第二保護層210與第四保護層216係用以保護半導體基底200不受金屬污染。最後，再於金屬複合層230上方形成一第五保護層240，填滿第一溝渠204，完成埋藏式位元線250之製作。Please continue to see Figure 15. After the fabrication of the metal telluride layer 228 is completed, a metal composite layer 230 is formed in the first trench 204 and the second trench 208 for use as a bit line. The metal composite layer 230 may include a titanium nitride layer 234 and a tungsten layer 236, but is not limited thereto. Similarly, when the metal layer is formed, the remaining first protective layer 206, second protective layer 210, and fourth protective layer 216 are used to protect the semiconductor substrate 200 from metal contamination. Finally, a fifth protective layer 240 is formed over the metal composite layer 230 to fill the first trench 204 to complete the fabrication of the buried bit line 250.
請重新參閱第13圖與第15圖。根據本發明所提供之埋藏式位元線之製作方法，係提供一種埋藏式位元線250，其包含有一溝渠，而該溝渠係由第一溝渠204與第二溝渠208所構成。埋藏式位元線250更包含一保護層，分別設置於溝渠204/208之側壁與底部。該保護層由前述的第二保護層210與第四保護層216所構成，由於兩者皆為由熱氧化製程所形成的氧化矽材料，且具有相同的蝕刻率，因此可視為同一保護層。保護層210/216可用以在後續製程中保護半導體基底200不受製程傷害或金屬污染。更值得注意的是，根據前述本發明所提供之方法，係藉由不同保護層蝕刻率不同的特性，輕易地藉由蝕刻製程於保護層中定義並形成一開口222。值得注意的是，在溝渠204/208相對於開口222之另一側壁上，埋藏式位元線250更包含一保護層206，保護層206之位置與大小係與開口222之位置及大小相同，且包含有氮化矽、氮氧化矽或氧化-氮化-氧化複合物等蝕刻率不同於保護層210/216之材料。Please refer to Figure 13 and Figure 15 again. According to the method of fabricating the buried bit line provided by the present invention, a buried bit line 250 is provided which includes a trench formed by the first trench 204 and the second trench 208. The buried bit line 250 further includes a protective layer disposed on the sidewalls and the bottom of the trench 204/208, respectively. The protective layer is composed of the second protective layer 210 and the fourth protective layer 216 described above. Since both of them are yttria materials formed by a thermal oxidation process and have the same etch rate, they can be regarded as the same protective layer. The protective layer 210/216 can be used to protect the semiconductor substrate 200 from process damage or metal contamination in subsequent processes. More importantly, according to the method provided by the foregoing invention, an opening 222 is easily defined and formed in the protective layer by an etching process by different characteristics of different protective layer etch rates. It should be noted that, on the other sidewall of the trench 204/208 relative to the opening 222, the buried bit line 250 further includes a protective layer 206. The position and size of the protective layer 206 are the same as the position and size of the opening 222. And a material having an etching rate different from that of the protective layer 210/216, such as tantalum nitride, niobium oxynitride or an oxidation-nitriding-oxidation composite.
對應於開口222之處，係設置有一接觸窗226，包含砷等N型摻雜質，此一透過開口222所形成的接觸窗226即用以與後續形成的MOS電晶體的源極/汲極電性連接，確保電流傳疏通路的建構。埋藏式位元線250更包含一設置於溝渠204/208內之金屬複合層330，其上更包含有一填滿溝渠204/208之保護層240；金屬複合層230係用以作為位元線。值得注意的是，金屬複合層230係可如第13圖所示，填滿開口222。或者，當接觸窗226係藉由含砷多晶矽層熱擴散所形成時，亦可如第15圖所示，藉由一金屬矽化物製程於開口222處形成金屬矽化物層228，由含砷多晶矽層225與金屬矽化物層228填滿開口222。Corresponding to the opening 222, a contact window 226 is disposed, which comprises an N-type dopant such as arsenic. The contact window 226 formed through the opening 222 is used for the source/drain of the subsequently formed MOS transistor. Electrical connection ensures the construction of the current channel. The buried bit line 250 further includes a metal composite layer 330 disposed in the trench 204/208, further comprising a protective layer 240 filling the trench 204/208; the metal composite layer 230 is used as a bit line. It should be noted that the metal composite layer 230 can fill the opening 222 as shown in FIG. Alternatively, when the contact window 226 is formed by thermal diffusion of an arsenic-containing polysilicon layer, as shown in FIG. 15, a metal telluride layer 228 is formed at the opening 222 by a metal telluride process, and the arsenic-containing polysilicon is formed. Layer 225 and metal telluride layer 228 fill opening 222.
綜上所述，本發明所提供之埋藏式位元線及其製作方法，係適用於不同類型的記憶體，其藉由具有不同蝕刻率的保護層的形成與移除定義出開口形成的位置與大小，因而能準確地在半導體基底中形成接觸窗，確保埋藏式位元線與MOS電晶體的電流傳疏通路的建構，繼而避免相鄰的記憶體位元胞因埋藏式位元線接觸窗製作的缺陷而被不正常的開啟。In summary, the buried bit line provided by the present invention and the manufacturing method thereof are applicable to different types of memory, and the position formed by the opening is defined by the formation and removal of the protective layer having different etching rates. And the size, thus accurately forming a contact window in the semiconductor substrate, ensuring the construction of the buried channel of the buried bit line and the MOS transistor, and then avoiding the adjacent memory bit cell due to the buried bit line contact window The defects were created and opened abnormally.
以上所述僅為本發明之第一較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above description is only the first preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．DRAM陣列100. . . DRAM array
110．．．埋藏式位元線110. . . Buried bit line
112．．．位元線接觸窗112. . . Bit line contact window
120．．．埋藏式字元線120. . . Buried word line
130．．．電容器130. . . Capacitor
200．．．半導體基底200. . . Semiconductor substrate
202．．．圖案化硬遮罩202. . . Patterned hard mask
204．．．第一溝渠204. . . First ditches
206．．．第一保護層206. . . First protective layer
208．．．第二溝渠208. . . Second ditches
210．．．第二保護層210. . . Second protective layer
212．．．第三保護層212. . . Third protective layer
212a．．．氧化矽層212a. . . Cerium oxide layer
214．．．第一光阻層214. . . First photoresist layer
216．．．第四保護層216. . . Fourth protective layer
218．．．第二光阻層218. . . Second photoresist layer
222．．．開口222. . . Opening
224．．．ASG層224. . . ASG layer
225．．．含砷多晶矽層225. . . Arsenic-containing polycrystalline layer
226．．．接觸窗226. . . Contact window
228．．．金屬矽化物層228. . . Metal telluride layer
230．．．金屬複合層230. . . Metal composite layer
232．．．鈦層232. . . Titanium layer
234．．．氮化鈦層234. . . Titanium nitride layer
236．．．鎢層236. . . Tungsten layer
240．．．第五保護層240. . . Fifth protective layer
250．．．埋藏式位元線250. . . Buried bit line
第1圖係為一習知4F2 單元的DRAM陣列之佈局圖案示意圖；1 is a schematic diagram of a layout pattern of a conventional 4F 2 unit DRAM array;
第2圖至第13圖係為本發明所提供之一種埋藏式位元線之製作方法之一第一較佳實施例的製作流程剖面圖；2 to 13 are cross-sectional views showing a manufacturing process of a first preferred embodiment of a method for fabricating a buried bit line provided by the present invention;
第14圖至第15圖係為本發明所提供之一第二較佳實施例之示意圖。14 to 15 are schematic views showing a second preferred embodiment of the present invention.
200．．．半導體基底200. . . Semiconductor substrate
202．．．圖案化硬遮罩202. . . Patterned hard mask
204．．．第一溝渠204. . . First ditches
206．．．第一保護層206. . . First protective layer
208．．．第二溝渠208. . . Second ditches
210．．．第二保護層210. . . Second protective layer
216．．．第四保護層216. . . Fourth protective layer
222．．．開口222. . . Opening
226．．．接觸窗226. . . Contact window
230．．．金屬複合層230. . . Metal composite layer
232．．．鈦層232. . . Titanium layer
234．．．氮化鈦層234. . . Titanium nitride layer
236．．．鎢層236. . . Tungsten layer
240．．．第五保護層240. . . Fifth protective layer
250．．．埋藏式位元線250. . . Buried bit line
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|---|---|---|---|---|
| US5219789A (en) * | 1991-04-19 | 1993-06-15 | Sharp Kabushiki Kaisha | Method for forming contact portion of semiconductor device |
| US5233217A (en) * | 1991-05-03 | 1993-08-03 | Crosspoint Solutions | Plug contact with antifuse |
| US20050285175A1 (en) * | 2004-06-23 | 2005-12-29 | International Business Machines Corporation | Vertical SOI Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219789A (en) * | 1991-04-19 | 1993-06-15 | Sharp Kabushiki Kaisha | Method for forming contact portion of semiconductor device |
| US5233217A (en) * | 1991-05-03 | 1993-08-03 | Crosspoint Solutions | Plug contact with antifuse |
| US20050285175A1 (en) * | 2004-06-23 | 2005-12-29 | International Business Machines Corporation | Vertical SOI Device |
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