TWI403596B - Copper alloy wire for semiconductor packaging - Google Patents
Copper alloy wire for semiconductor packaging Download PDFInfo
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- TWI403596B TWI403596B TW101139990A TW101139990A TWI403596B TW I403596 B TWI403596 B TW I403596B TW 101139990 A TW101139990 A TW 101139990A TW 101139990 A TW101139990 A TW 101139990A TW I403596 B TWI403596 B TW I403596B
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C9/00—Alloys based on copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- Engineering & Computer Science (AREA)
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Abstract
Description
本發明係有關於一種半導體封裝用之銅合金線，尤其是指一種可解決傳統銅線氧化反應和鍍鈀銅線皮膜可靠度問題的銅鈀稀合金線，同時具有較佳之常溫與高溫抗氧化功效以及良好之銲接成球性與接合性者。The invention relates to a copper alloy wire for semiconductor packaging, in particular to a copper-palladium-thin alloy wire which can solve the problem of traditional copper wire oxidation reaction and palladium-plated copper wire film reliability, and has better normal temperature and high temperature oxidation resistance. Efficacy and good welding into the ball and joint.
按，習知的電晶體、IC等半導體，或積體電路等組件，其連結電極與外部導線一般係以高純度4N系(純度>99.99mass(質量)%)的黃金與其他微量金屬元素製成的金線作為電性連接之接合線；然而，隨著金價不斷地飆漲，封裝業者對金線的替代品需求更形強烈；因此，在考量材料成本下，有業者採用銅製成的導線，然使用銅導線時，由於封裝用樹脂與導線的熱膨脹係數差異過大，隨著半導體啟動後溫度上升，因熱形成之體積膨脹對形成迴路的銅接合線產生外部應力，特別是對暴露於嚴酷的熱循環條件下的半導體元件，容易使銅接合線發生斷線問題；因此，針對上述缺失，有業者針對封裝用之接合銅線改良，請參閱中華民國發明專利公開第201207129號所揭露之『封裝用之接合銅線及其製造方法』，其中揭露一種封裝用之接合銅線，成分包括有銀(Ag)、添加物、以及銅(Cu)；其中，銀含量係0.1~3wt%；添加物係至少一選自由鎳(Ni)、鉑(Pt)、鈀(Pd)、 錫(Sn)、及金(Au)所組成之群組，且添加物之含量係0.1~3wt%；再者，銅與銀共晶相體積率佔全部體積的0.1~8%，且接合銅線抗拉強度250MPa以上，導電率在70%IACS以上；藉此，不僅使得阻抗和傳統金線相當或甚至更低(>70%IACS)，可達到更佳導電率，且硬度適中並易於銲接，更能進行球型銲接，於耐熱循環之嚴苛條件下亦能使用。According to the conventional semiconductor such as a transistor or an IC, or an integrated circuit, the connecting electrode and the external lead are generally made of high-purity 4N (purity > 99.99 mass%) gold and other trace metal elements. The gold wire is used as the bonding wire for electrical connection; however, as the price of gold continues to soar, the demand for alternatives to the gold wire by the packaging industry is even stronger; therefore, in consideration of the cost of materials, some manufacturers use wires made of copper. However, when a copper wire is used, since the difference in thermal expansion coefficient between the resin for sealing and the wire is too large, as the temperature rises after the semiconductor is started, the volume expansion due to heat generates external stress on the copper bonding wire forming the circuit, especially for exposure to severe stress. In the semiconductor element under the thermal cycle conditions, the copper bonding wire is liable to be disconnected. Therefore, in view of the above-mentioned deficiencies, the manufacturer has improved the bonding copper wire for packaging. Please refer to the disclosure of the Republic of China Patent Publication No. 201207129. A bonding copper wire for packaging and a manufacturing method thereof, wherein a bonding copper wire for packaging is disclosed, the composition comprising silver (Ag), an additive, Copper (a Cu); wherein the content of the silver-based 0.1 ~ 3wt%; at least one additive selected from the group consisting of nickel-based (Ni), platinum (Pt), palladium (Pd), a group consisting of tin (Sn) and gold (Au), and the content of the additive is 0.1 to 3 wt%; further, the volume ratio of copper to silver eutectic phase is 0.1 to 8% of the total volume, and the copper is bonded The tensile strength of the wire is above 250 MPa, and the electrical conductivity is above 70% IACS; thereby not only making the impedance comparable to or lower than the conventional gold wire (>70% IACS), but also achieving better conductivity, moderate hardness and easy soldering. It can be used for ball welding and can be used under the severe conditions of heat cycle.
然，上述之接合銅線雖能滿足成本與銲接的要求，但卻有易氧化、壽命短的缺失，因此有業者藉由一表面塗層，其能為積體電路封裝，提供更佳之引線接合性能；請參閱中華民國發明專利公告第480292號所揭露之『適用於引線接合之鈀表面塗層及形成鈀表面塗層之方法』，其表面塗層係形成於一基板之上，包含一鈀層與一種或多種材料層；該一種或多種材料層係夾在基板與鈀層之間；當至少一種材料之硬度少於250(KHN50)時，該鈀層之硬度少於大約500(KHN50)；其中該鈀層之厚度最好大於0.075微米，以避免氧化物在其下材料層上形成；上述之基板材料可包含有銅或銅合金，藉由鍍鈀銅線來取代金線，不但可以節省約七成的材料成本，而且鍍鈀銅線於被使用時的可靠度(如耐高溫、高濕能力)也能符合要求，不過，卻因鍍鈀銅線的表面硬度偏高，且鍍鈀層厚度不均，造成封裝過程整體產出率差、良率偏低的問題，所以對半導體業者來說，鍍鈀銅線於打線接合封裝技術 上的使用，並無法有效評估線材品質並進一步地提高可靠度之功效；再者，於銅或銅合金鍍上鈀層使得打線接合成球時，易造成鈀層的偏析，進而導致接合界面剝離問題。However, although the above-mentioned bonded copper wire can meet the requirements of cost and soldering, it has the defects of easy oxidation and short life, so that a surface coating can provide a better wire bonding for the integrated circuit package. Performance; please refer to the "Method for Applying Wire Bonded Palladium Surface Coating and Forming Palladium Surface Coating" as disclosed in the Republic of China Invention Patent Publication No. 480292. The surface coating is formed on a substrate containing a palladium. a layer and one or more layers of material; the layer of one or more materials being sandwiched between the substrate and the palladium layer; and when the hardness of the at least one material is less than 250 (KHN50), the hardness of the palladium layer is less than about 500 (KHN50) Wherein the thickness of the palladium layer is preferably greater than 0.075 micrometers to prevent oxide formation on the underlying material layer; the substrate material may comprise copper or a copper alloy, and the palladium-plated copper wire is substituted for the gold wire, not only It saves about 70% of the material cost, and the palladium-plated copper wire can meet the requirements when it is used (such as high temperature resistance and high humidity capacity). However, the surface hardness of the palladium-plated copper wire is high and plated. Palladium layer thickness is not , Encapsulation process resulting in overall yield is poor, the problem of low yield, the semiconductor industry, the palladium to copper wire bonding packaging technology The use of the above is not effective in evaluating the quality of the wire and further improving the reliability. Further, when the palladium layer is plated on the copper or copper alloy to bond the wire into a ball, segregation of the palladium layer is liable to occur, which leads to peeling of the joint interface. problem.
今，發明人即是鑑於上述現有半導體封裝用之接合線在實際實施上仍具有多處之缺失，於是乃一本孜孜不倦之精神，並藉由其豐富之專業知識及多年之實務經驗所輔佐，而加以改善，並據此研創出本發明。Nowadays, the inventor is in view of the fact that the above-mentioned conventional semiconductor package bonding wire still has many defects in practical implementation, so it is a tireless spirit, and with its rich professional knowledge and years of practical experience, Improvements have been made, and the present invention has been developed based on this.
本發明主要目的為提供一種半導體封裝用之銅合金線，尤其是指一種可解決傳統銅線氧化反應和鍍鈀銅線可靠度不佳問題的銅鈀稀合金線，同時具有較佳之常溫與高溫抗氧化功效以及良好之銲接成球性與接合性者。The main object of the present invention is to provide a copper alloy wire for semiconductor packaging, in particular to a copper-palladium-thin alloy wire which can solve the problem of poor reliability of conventional copper wire oxidation and palladium-plated copper wire, and has better normal temperature and high temperature. Antioxidant effect and good welding into the ball and joint.
為了達到上述實施目的，本發明人提出一種半導體封裝用之銅合金線，係由銅合金材質製成，以100%的總組成成份重量百分比計算，該銅合金材質包括有0.01~0.65wt.%的貴金屬(較佳係為鈀)、0.05wt.%以下的稀土元素，以及剩餘重量百分比的銅；藉此，以熔融狀的銅合金製成之鍍鈀稀合金接合線不僅具有較佳之銲接成球性與接合性，可提高線材之品質與可靠度，並一併解決傳統銅或銅合金鍍上鈀層所造成的偏析和歪球，進而導致接合界面剝離的問題。In order to achieve the above-mentioned object, the present inventors propose a copper alloy wire for semiconductor packaging, which is made of a copper alloy material and is calculated by weight percentage of 100% of the total composition, and the copper alloy material includes 0.01 to 0.65 wt.%. a noble metal (preferably palladium), a rare earth element of 0.05 wt.% or less, and a residual weight percentage of copper; whereby a palladium-plated thin alloy bonding wire made of a molten copper alloy not only has better soldering Sphericality and splicability can improve the quality and reliability of the wire, and solve the segregation and smashing caused by the palladium layer on the traditional copper or copper alloy, which leads to the problem of the joint interface peeling.
在本發明的一實施例中，稀土元素可包含有鑭(La)或 鈰(Ce)其中之一，或兩者之組合；藉此，使得本發明之銅合金線不僅可於無塵室中可達到28天無氧化之功效，避免傳統之接合銅線易氧化的缺失，於大氣潔淨環境中其抗氧化性亦達14天以上；此外，本發明之鍍鈀稀合金接合線於175℃環境下，表層可達7天不剝離之功效，具有良好之高溫抗氧化能力。In an embodiment of the invention, the rare earth element may comprise lanthanum (La) or One of cesium (Ce), or a combination of the two; thereby, the copper alloy wire of the present invention can not only achieve 28 days of non-oxidation effect in a clean room, but also avoids the loss of oxidation of the conventional bonded copper wire. In the air clean environment, its oxidation resistance is also more than 14 days; in addition, the palladium-plated thin alloy bonding wire of the invention has the effect of not peeling off for 7 days in the environment of 175 ° C, and has good high temperature oxidation resistance. .
本發明之目的及其結構功能上的優點，將依據以下圖面所示之結構，配合具體實施例予以說明，俾使審查委員能對本發明有更深入且具體之瞭解。The object of the present invention and its structural and functional advantages will be explained in conjunction with the specific embodiments according to the structure shown in the following drawings, so that the reviewing committee can have a more in-depth and specific understanding of the present invention.
首先，本發明之半導體封裝用之銅合金線係適用於印刷電路板之電路、IC封裝、ITO基板、IC卡等之電子工業零件之端子或電路表面；請參閱下表，係為本發明之半導體封裝用之銅合金線組成成分表，如下表所示，以100%的總組成成份重量百分比計算，銅合金材質係包括有0.01~0.65wt.%的貴金屬、0.05wt.%以下的稀土元素，以及剩餘重量百分比的銅；其中，貴金屬較佳係為鈀(Pd)，而稀土元素可包含有鑭(La)或鈰(Ce)其中之一，或兩者之組合，於本實施例係包括有鑭以及鈰兩元素。First, the copper alloy wire for semiconductor package of the present invention is applied to a terminal or a circuit surface of an electronic industrial part such as a circuit of a printed circuit board, an IC package, an ITO substrate, an IC card, etc.; The composition of the composition of the copper alloy wire for semiconductor encapsulation, as shown in the following table, is calculated as 100% of the total composition weight percentage. The copper alloy material includes 0.01 to 0.65 wt.% of precious metal and 0.05 wt.% or less of rare earth element. And a residual weight percentage of copper; wherein the noble metal is preferably palladium (Pd), and the rare earth element may comprise one of lanthanum (La) or cerium (Ce), or a combination of the two, in the present embodiment It includes two elements, 镧 and 铈.
再者，為使 貴審查委員能進一步瞭解本發明之目的、特徵以及所達成之功效，以下茲舉本發明之一種製造步驟實施例，然不限定以該步驟製成銅合金線；本發明並非於銅基材表面以電鍍或化學鍍方式進行塗佈(coating)，而是將上述組成成分之鈀、鑭、鈰以及銅等金屬材料依預設之重量百分比例投置入一熔爐中，以混煉製得一熔融狀的銅合金液體；接著，使銅合金液體經由鑄錠製造(ingot making)、輥軋(press roll)、主抽線(heavy drawing)、細抽線(fine drawing)、表面清洗、烘乾、定型退火(final annealing)、繞線(rewinding)等加工處理，以製成一銅合金線，再予使用在半導體元件的打線接合封裝製程中。Furthermore, in order to enable the reviewing committee to further understand the object, features and effects of the present invention, an embodiment of the manufacturing steps of the present invention is exemplified below, but the copper alloy wire is not limited by this step; Coating the surface of the copper substrate by electroplating or electroless plating, and placing the metal materials such as palladium, ruthenium, iridium, and copper of the above composition into a furnace according to a predetermined weight percentage. The molten copper alloy liquid is obtained by kneading; then, the copper alloy liquid is subjected to ingot making, press roll, heavy drawing, fine drawing, Surface cleaning, drying, final annealing, rewinding, etc., to form a copper alloy wire, which is used in the wire bonding process of semiconductor components.
接著，藉由下述具體實際實施例，可進一步證明本發明之製程可實際應用之範圍，但不意欲以任何形式限制本發明之範圍：下表為銅合金線加入不同比例的鈀金屬以及比較添加稀土元素之氧化情形對照表；由表中可知鈀金屬和稀土元素的添加，對於銅合金線的抗氧化能力是有顯著影響的；舉例而言， 當鈀金屬的含量大於0.52wt.%後，其於室溫下皆可達到28天無氧化之功效，然既使鈀金屬的含量添加至0.75wt.%，175℃高溫7天無氧化之功效仍是無法達到；而當添加稀土元素(0.02wt.%)後，鈀金屬的含量僅需添加至0.25wt.%，於室溫下即可達到28天無氧化之功效，且當鈀金屬的含量於0.65wt.%以上，亦可達到175℃高溫7天無氧化之功效，意即本發明之鍍鈀稀合金接合線其表層可達7天不剝離之功效，具有良好之高溫抗氧化能力。Next, the scope of the process of the present invention can be further proved by the following specific practical examples, but it is not intended to limit the scope of the invention in any form: the following table shows the addition of different proportions of palladium metal to copper alloy wires and comparison A comparison table of oxidation conditions of adding rare earth elements; it is known from the table that the addition of palladium metal and rare earth elements has a significant influence on the oxidation resistance of the copper alloy wire; for example, When the content of palladium metal is more than 0.52wt.%, it can achieve 28 days of non-oxidation at room temperature, but the palladium metal content is added to 0.75wt.%, and the high temperature of 175 °C for 7 days has no oxidation effect. Still can not be reached; and when adding rare earth elements (0.02wt.%), the content of palladium metal only needs to be added to 0.25wt.%, at room temperature can reach 28 days without oxidation effect, and when palladium metal The content is above 0.65wt.%, and can also reach the high temperature of 175 °C for 7 days without oxidation, which means that the palladium-plated thin alloy bonding wire of the invention can have the surface layer up to 7 days without peeling effect, and has good high temperature oxidation resistance. .
請再參閱下表另一具體實施例之比較表，為銅合金線於0.65wt.%的鈀金屬下，比較添加不同比例之稀土元素其成球性對照表；由表中可知當稀土元素之含量大於0.05wt.%後，因冶金均勻性不佳，導致成球性將由正圓球變成 偏心球，因此本發明之鍍鈀稀合金接合線係包含0.05wt.%以下的稀土元素含量。Please refer to the comparison table of another specific embodiment of the following table, for the copper alloy wire under 0.65wt.% of palladium metal, compare the addition of different proportions of rare earth elements to the spheroidal comparison table; from the table, it can be seen that when the rare earth element After the content is more than 0.05wt.%, the sphericity will be changed from a perfect sphere due to poor metallurgical uniformity. The eccentric ball, therefore, the palladium-plated thin alloy bonding wire of the present invention contains a rare earth element content of 0.05 wt.% or less.
再者，請參閱下表另一具體實施例之比較表，為銅合金線於不同比例的鈀金屬以及稀土元素下，量測其熱膨脹係數(COEFFICIENT OF THERMAL EXPANSION，CTE)之比較表；由表中可知於銅合金線中添加有鈀金屬以及稀土元素，可降低銅合金線的熱膨脹係數，有助改善熱疲勞可靠度，以減少結合界面剝離的現象發生。Furthermore, please refer to the comparison table of another specific embodiment of the following table, which is a comparison table of the coefficient of thermal expansion (COEFFICIENT OF THERMAL EXPANSION, CTE) of the copper alloy wire under different proportions of palladium metal and rare earth elements; It can be seen that the addition of palladium metal and rare earth elements to the copper alloy wire can reduce the thermal expansion coefficient of the copper alloy wire, help to improve the thermal fatigue reliability, and reduce the occurrence of joint interface peeling.
最後，請再參閱下表另一具體實施例之比較表，為純銅 線、鍍鈀銅線以及本發明之銅合金線之金屬間化合物(intermetallic compound，IMC)於175℃/2000小時之環境條件下所量測之厚度比較表；可明顯看出於銅合金線中添加有鈀金屬以及稀土元素能降低金屬間化合物層厚度，進而提高Cu/Al界面可靠度。Finally, please refer to the comparison table of another specific embodiment of the following table, which is pure copper. Comparison table of thickness measured by wire, palladium-plated copper wire and intermetallic compound (IMC) of copper alloy wire of the present invention under 175 ° C / 2000 hours; obviously visible in copper alloy wire The addition of palladium metal and rare earth elements can reduce the thickness of the intermetallic compound layer, thereby improving the reliability of the Cu/Al interface.
由上述之實施說明可知，本發明與現有技術相較之下，本發明具有以下優點：It can be seen from the above description that the present invention has the following advantages compared with the prior art:
1.本發明將銅合金線添加鈀金屬以及稀土元素，使得銅合金線之抗氧化功效於無塵室以及大氣潔淨環境中分別達到28天以及14天以上，解決傳統之接合銅線易氧化的缺失，且本發明之鍍鈀稀合金接合線於175℃環境下，表層可達7天不剝離之功效，具有良好之高溫抗氧化能力。1. The invention adds palladium metal and rare earth element to the copper alloy wire, so that the anti-oxidation effect of the copper alloy wire reaches 28 days and 14 days respectively in the clean room and the air clean environment, respectively, and solves the problem that the traditional copper wire is easily oxidized. It is missing, and the palladium-plated thin alloy bonding wire of the invention has the effect of not peeling off for 7 days in the environment of 175 ° C, and has good high temperature oxidation resistance.
2.本發明之鍍鈀稀合金接合線不僅可降低銅合金線的熱膨脹係數，有助改善熱疲勞可靠度，以減少結合界面剝離的現象發生外，亦能降低金屬間化合物層厚度，進而提高界面可靠度。2. The palladium-plated thin alloy bonding wire of the invention not only reduces the thermal expansion coefficient of the copper alloy wire, but also improves the thermal fatigue reliability, reduces the phenomenon of the joint interface peeling, and also reduces the thickness of the intermetallic compound layer, thereby improving Interface reliability.
綜上所述，本發明之半導體封裝用之銅合金線，的確能藉 由上述所揭露之實施例，達到所預期之使用功效，且本發明亦未曾公開於申請前，誠已完全符合專利法之規定與要求。爰依法提出發明專利之申請，懇請惠予審查，並賜准專利，則實感德便。In summary, the copper alloy wire for semiconductor packaging of the present invention can indeed be borrowed From the embodiments disclosed above, the intended use efficiency is achieved, and the present invention has not been disclosed before the application, and the company has fully complied with the requirements and requirements of the patent law.爰Issuing an application for a patent for invention in accordance with the law, and asking for a review, and granting a patent, is truly sensible.
惟，上述所揭之圖示及說明，僅為本發明之較佳實施例，非為限定本發明之保護範圍；大凡熟悉該項技藝之人士，其所依本發明之特徵範疇，所作之其它等效變化或修飾，皆應視為不脫離本發明之設計範疇。The illustrations and descriptions of the present invention are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; those skilled in the art, which are characterized by the scope of the present invention, Equivalent variations or modifications are considered to be within the scope of the design of the invention.
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| Application Number | Priority Date | Filing Date | Title |
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| TW101139990A TWI403596B (en) | 2012-10-29 | 2012-10-29 | Copper alloy wire for semiconductor packaging |
| PH12013000283A PH12013000283A1 (en) | 2012-10-29 | 2013-09-19 | Copper alloy wire for semiconductor packaging |
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| TW101139990A TWI403596B (en) | 2012-10-29 | 2012-10-29 | Copper alloy wire for semiconductor packaging |
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| TWI403596B true TWI403596B (en) | 2013-08-01 |
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| CN104278169B (en) * | 2013-07-12 | 2016-08-31 | 河南理工大学 | A kind of corrosion-resistant bonding brass wire and preparation method thereof |
| CN103805802A (en) * | 2014-01-09 | 2014-05-21 | 东莞市共民实业有限公司 | Copper-silver alloy for ultra-fine copper enameled wire and production process thereof |
| CN104018023A (en) * | 2014-05-06 | 2014-09-03 | 阜阳市光普照明科技有限公司 | Method for preparing copper alloy bonding wire for light-emitting diode (LED) encapsulation |
| JP6056876B2 (en) | 2015-01-07 | 2017-01-11 | 三菱マテリアル株式会社 | Superconducting stabilizer |
| JP6299803B2 (en) | 2016-04-06 | 2018-03-28 | 三菱マテリアル株式会社 | Superconducting wire and superconducting coil |
| JP6299802B2 (en) | 2016-04-06 | 2018-03-28 | 三菱マテリアル株式会社 | Superconducting stabilizer, superconducting wire and superconducting coil |
| TWI640640B (en) * | 2017-09-22 | 2018-11-11 | 香港商駿碼科技（香港）有限公司 | Dual-phase copper alloy wire resistant to repeated cold and heat shocks and manufacturing method thereof |
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| CN101689517A (en) * | 2007-07-24 | 2010-03-31 | 新日铁高新材料株式会社 | Bonding wire for semiconductor device and wire connecting method |
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| CN101689517A (en) * | 2007-07-24 | 2010-03-31 | 新日铁高新材料株式会社 | Bonding wire for semiconductor device and wire connecting method |
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