TWI399840B - Leadframe having isolated inner lead and its fabricating method - Google Patents
Leadframe having isolated inner lead and its fabricating method Download PDFInfo
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- TWI399840B TWI399840B TW097135392A TW97135392A TWI399840B TW I399840 B TWI399840 B TW I399840B TW 097135392 A TW097135392 A TW 097135392A TW 97135392 A TW97135392 A TW 97135392A TW I399840 B TWI399840 B TW I399840B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- Lead Frames For Integrated Circuits (AREA)
Description
本發明係有關於一種晶片封裝型半導體裝置所使用之導線架(leadframe,或稱引線框架)，特別係有關於一種具有獨立內引腳之導線架及其製造方法。The present invention relates to a leadframe (or leadframe) used in a chip package type semiconductor device, and more particularly to a lead frame having independent inner leads and a method of fabricating the same.
按，導線架(leadframe)普遍使用於半導體封裝構造並具有低成本之優勢。晶片承載於導線架上並被樹脂類封膠體密封，可藉由導線架之引腳對外電性溝通。在製造中為了能以模封(molding)技術形成封膠體，導線架之引腳應延伸到模封區之外，以便於被上下模具所夾固。通常導線架係由一金屬板進行蝕刻或沖裁，以製成複數個引腳。Press, leadframes are commonly used in semiconductor package construction and have the advantage of low cost. The wafer is carried on the lead frame and sealed by a resin-based encapsulant, and can be electrically communicated externally by the lead of the lead frame. In order to form the encapsulant in a molding process in the manufacturing process, the lead of the lead frame should extend beyond the molding area to be clamped by the upper and lower molds. Typically, the lead frame is etched or stamped from a metal plate to form a plurality of pins.
因導線架之引腳為同層金屬結構，故排列次序為固定，不利於作腳位調整。故有人提出了兩種導線架上下夾合的技術，或者在晶片主動面上貼上一電路薄膜，或者在黏晶膠帶上額外設置電性轉接元件，如導電塊、轉接引線或梳狀導電條等等，使得由晶片銲墊連接到引腳的傳輸路徑可不需要依序排列，達到腳位調整之功效。然而這種方式是需要額外設置供打線連接之第二導線架、電路薄膜、導電塊、轉接引線或梳狀導電條等內部電性轉接元件在原導線架上或晶片上，除了會增加封裝製程步驟也會增加元件設置厚度導致如銲線等元件外露於封膠體的風險。此外，銲線 的非晶片焊點也會產生打線高度差與位移偏差，需時常作打線製程設定參數的校正調整。Since the leads of the lead frame are of the same layer metal structure, the arrangement order is fixed, which is not suitable for the adjustment of the foot position. Therefore, some techniques have been proposed for the upper and lower clamping of the lead frame, or a circuit film is attached to the active surface of the wafer, or an electrical switching element such as a conductive block, a transfer lead or a comb is additionally disposed on the adhesive tape. Conductive strips and the like, so that the transmission path connected to the pins by the die pads can be arranged in order to achieve the effect of the foot adjustment. However, this method requires an additional internal conductive adapter such as a second lead frame, a circuit film, a conductive block, a transfer lead or a comb-shaped conductive strip for wire bonding, on the original lead frame or on the wafer, except that the package is added. The process steps also increase the thickness of the component settings, causing the risk of components such as solder wires being exposed to the encapsulant. In addition, the wire bonding The non-wafer solder joints also produce the difference in line height and displacement, and it is often necessary to make correction adjustments to the setting parameters of the wire bonding process.
有鑒於此，本發明之主要目的係在於提供一種具有獨立內引腳之導線架及其製造方法，在引腳之同一層結構中具有電性轉接的整合作用，製程中不需要額外設置供打線連接之內部電性轉接元件，故能避免銲線的非晶片焊點會產生打線高度差與位移偏差，並能使獨立內引腳能被電性絕緣地固定在模封區內。In view of this, the main object of the present invention is to provide a lead frame having independent inner leads and a manufacturing method thereof, which have an electrical transfer integration function in the same layer structure of the pins, and no additional setting is required in the process. The internal electrical switching component is connected by wire bonding, so that the non-wafer soldering point of the bonding wire can avoid the wire height difference and the displacement deviation, and the independent inner pin can be electrically insulated and fixed in the die sealing zone.
本發明之次一目的係在於提供一種具有獨立內引腳之導線架及其製造方法，適用於「晶片在引腳上」(COL,Chip－On－Lead)之封裝型態，可達成不增加元件高度之腳位次序的調整，特別可運用於多晶片堆疊之「晶片在引腳上」封裝。A second object of the present invention is to provide a lead frame having independent inner leads and a manufacturing method thereof, which are suitable for a package type of "Chip-On-Lead" (COL, On-Lead), which can be achieved without increasing The adjustment of the order of the component heights can be applied to the "on-wafer" package of multi-wafer stacking.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。依據本發明所揭示之一種具有獨立內引腳之導線架，在該導線架中定義有一模封區以及一在該模封區內之晶片設置區，該導線架係包含複數個引腳、一獨立內引腳、一外引腳、一第一貼片以及一第二貼片。每一引腳係具有一體連接之一在該模封區內之內腳部與一延伸到該模封區之外之外腳部，並且每一內腳部之內端係形成為一第一接指。該獨立內引腳係完全形成在該模封區內並與該些引腳為同層結構，該獨立內引腳之兩端係形成為一第二接指與一第三接指。該外引腳係局 部形成在該模封區內並延伸到該模封區之外，該外引腳係具有一在該模封區內之第四接指，其中至少一之該些內腳部係電性隔離地形成在該獨立內引腳與該外引腳之間，其中該些第一接指與該第二接指係為線性排列，該第三接指與該第四接指係為相鄰近。該第一貼片係貼設於該獨立內引腳與該些內腳部，以電性絕緣地固定該獨立內引腳，該第一貼片係位於該模封區內並靠近該些第一接指與該第二接指。該第二貼片係貼設於該獨立內引腳與該些內腳部，以電性絕緣地固定該獨立內引腳，該第二貼片係位於該模封區內並靠近該第三接指與該第四接指。本發明另揭示一種具有獨立內引腳之導線架之製造方法。當該獨立內引腳在尚未電性隔離之前，可利用一連接條，位於該晶片設置區內並為同材質地一體連接該獨立內引腳至緊鄰該獨立內引腳之其中一之該些內腳部。在貼設第一貼片與第二貼片之後，切除該連接條，以使該獨立內引腳與該緊鄰之內腳部為電性隔離。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a lead frame having an independent inner lead defines a die seal region and a die set region in the die seal region, the lead frame includes a plurality of pins, An independent inner pin, an outer pin, a first patch, and a second patch. Each of the pins has an integral connection within the molding region and a foot extending beyond the molding region, and the inner end of each inner leg is formed as a first Fingers. The independent inner leads are completely formed in the mold sealing region and have the same layer structure as the pins, and the two ends of the independent inner pins are formed as a second finger and a third finger. The outer pin system Forming in the molding region and extending outside the molding region, the outer lead has a fourth finger in the molding region, wherein at least one of the inner legs is electrically isolated The ground is formed between the independent inner pin and the outer lead, wherein the first finger and the second finger are linearly arranged, and the third finger is adjacent to the fourth finger. The first patch is attached to the independent inner lead and the inner leg to electrically fix the independent inner lead, and the first patch is located in the mold sealing area and close to the first One finger and the second finger. The second patch is attached to the independent inner lead and the inner leg portion to electrically fix the independent inner lead, and the second patch is located in the mold sealing area and adjacent to the third The finger is connected to the fourth finger. The invention further discloses a method of manufacturing a lead frame having independent inner leads. Before the independent inner pin is not electrically isolated, a connecting strip is disposed in the wafer setting area and the independent inner pin is integrally connected to the same material to one of the adjacent inner pins. Inside the foot. After the first patch and the second patch are attached, the connecting strip is cut away to electrically isolate the independent inner lead from the immediately adjacent inner leg.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述導線架中，該獨立內引腳在該第一貼片與該第二貼片之間係可具有一第一連接條殘留痕跡。In the lead frame, the independent inner pin may have a residual trace of the first connecting strip between the first patch and the second patch.
在前述導線架中，緊鄰該獨立內引腳之其中一之該些內腳部係可亦具有一第二連接條殘留痕跡，其係與該第一連接條殘留痕跡相對應。In the lead frame, the inner leg portions adjacent to one of the independent inner pins may also have a second connecting strip residual mark corresponding to the residual trace of the first connecting strip.
在前述導線架中，該些第一接指與該第四接指係可位於該晶片設置區之外，該獨立內引腳係延展至一特定長度以穿越該晶片設置區並使該第二接指與該第三接指位於該晶片設置區之外。In the lead frame, the first fingers and the fourth fingers may be located outside the wafer setting area, the independent inner pins are extended to a specific length to traverse the wafer setting area and the second The finger and the third finger are located outside the wafer setting area.
在前述導線架中，該第一貼片與該第二貼片係可更位於該晶片設置區內。In the lead frame, the first patch and the second patch may be located in the wafer setting area.
在前述導線架中，可另包含有複數個短引腳，係較短於該些引腳，並且不延伸至該晶片設置區內。In the lead frame, a plurality of short pins may be further included, which are shorter than the pins and do not extend into the wafer setting area.
在前述導線架中，該第三接指與該第四接指之排列方向係可與該些第一接指與該第二接指之排列方向互為平行，並且該些短引腳之內端係朝向該些第一接指與該第二接指。In the lead frame, the direction in which the third finger and the fourth finger are arranged may be parallel to the direction in which the first finger and the second finger are arranged, and the short pins are The end faces the first finger and the second finger.
在前述導線架中，該第三接指與該第四接指之排列方向係可與該些第一接指與該第二接指之排列方向互為垂直。In the lead frame, the direction in which the third finger and the fourth finger are arranged may be perpendicular to the direction in which the first finger and the second finger are arranged.
在前述導線架中，該些引腳之該些外腳部係可分散在該模封區之兩相對平行側邊。In the lead frame, the outer legs of the pins may be dispersed on two opposite parallel sides of the molding zone.
在前述導線架中，可另包含有複數個側支撐墊，係排列在該些引腳之該些內腳部之兩側。In the lead frame, a plurality of side support pads may be further disposed on both sides of the inner legs of the pins.
在前述導線架中，該些側支撐墊係可具有複數個模流通孔。In the lead frame described above, the side support pads may have a plurality of die flow holes.
在前述導線架中，該第四接指係可往內延伸至該晶片設置區內。In the lead frame described above, the fourth finger can extend inwardly into the wafer setting area.
在前述導線架中，該第二貼片係可更貼設於該第四 接指。In the lead frame, the second patch can be further attached to the fourth Fingers.
在前述導線架中，該些內腳部在該晶片設置區內之一特定區段係可寬度放大以形成為複數個第一鎖墊。In the lead frame, the inner leg portion may be enlarged in width in a specific section of the wafer setting region to form a plurality of first lock pads.
在前述導線架中，該獨立內引腳在該第一晶片下方之一特定區段係可寬度放大以形成為一第二鎖墊。In the lead frame, the independent inner pin is widened in a specific section below the first wafer to form a second lock pad.
在前述導線架中，該些第一鎖墊與該第二鎖墊係可為線性排列。In the lead frame, the first lock pad and the second lock pad may be linearly arranged.
在前述導線架中，可另包含有一T形壩，其係形成於該模封區內但形成在該晶片設置區之外。In the lead frame, a T-shaped dam may be further included in the mold region but formed outside the wafer setting region.
由以上技術方案可以看出，本發明之具有獨立內引腳之導線架及其製造方法，有以下優點與功效：一、藉由模封區內獨立內引腳與引腳為同層結構以及其兩端位置關係以及複數個貼片的貼設，使得導線架在引腳之同一層結構中具有電性轉接的整合作用，製程中不需要額外設置供打線連接之內部電性轉接元件，並能避免銲線的非晶片焊點會產生打線高度差與位移偏差。此外，更能使獨立內引腳能被電性絕緣地固定在模封區內。It can be seen from the above technical solution that the lead frame with independent inner leads of the present invention and the manufacturing method thereof have the following advantages and effects: 1. The independent inner pins and pins are in the same layer structure in the molding region and The positional relationship between the two ends and the affixing of the plurality of patches enable the lead frame to have an electrical transfer integration function in the same layer structure of the pins, and no additional internal electrical switching elements for wire bonding are required in the process. And can avoid the wire height difference and displacement deviation of the non-wafer solder joint of the wire. In addition, the independent inner pins can be electrically insulated and fixed in the mold sealing area.
二、藉由獨立內引腳之延展直到穿越晶片設置區並使其兩端接指位於晶片設置區之外，以適用於「晶片在引腳上」(COL)之封裝型態，可達成不增加元件高度之腳位次序的調整，特別可運用於多晶片堆疊之「晶片在引腳上」封裝。Second, by extending the independent internal pins until the wafer setting area is passed and the two ends of the fingers are located outside the wafer setting area, so as to apply to the "on-chip" (COL) package type, The adjustment of the order of the component heights is particularly applicable to the "on-wafer" package of multi-wafer stacking.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件，且所顯示之元件並非以實際實施之數目、形狀、尺寸比例繪製，某些尺寸比例與其他相關尺寸比例已經被修飾放大或是簡化，以提供更清楚的描述，實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components in this case, and the components shown are not drawn in the actual implementation of the number, shape, size ratio, some size ratios and other related size ratios have been modified or simplified to provide a clearer description, the actual implementation The number, shape, and size ratios are an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種具有獨立內引腳之導線架舉例說明於第1圖之平面示意圖。在該導線架100中定義有一模封區101以及一在該模封區101內之晶片設置區102，該晶片設置區102係用以設置一晶片210(如第6圖所示)，該模封區101係供一封膠體240之形成(如第6圖所示)，利用該模封區101大於該晶片設置區102，以使該封膠體240能順利密封該晶片210或更多晶片。該導線架100係包含複數個引腳110、一獨立內引腳120、一外引腳130、一第一貼片141以及一第二貼片142。其中，第2圖係為該導線架100剖切該些引腳110的截面示意圖，第3圖係為該導線架100剖切該獨立內引腳120與該外引腳130的截面示意圖。其中該些引腳110、該獨立內引腳120與該外引腳130係為同一層相同金屬材料，其材質可為銅、鐵或其合金。該第一貼片141與該第二貼片142係為電性絕緣的黏著貼片，其材質可為聚亞醯胺，例如Kapton膠帶。In accordance with a first embodiment of the present invention, a leadframe having independent internal leads is illustrated in a plan view of FIG. A die seal area 101 is defined in the lead frame 100 and a wafer setting area 102 in the mold sealing area 101. The wafer setting area 102 is used to set a wafer 210 (as shown in FIG. 6). The sealing zone 101 is formed by forming a colloid 240 (as shown in FIG. 6), and the molding area 101 is larger than the wafer setting area 102, so that the encapsulant 240 can smoothly seal the wafer 210 or more. The lead frame 100 includes a plurality of pins 110, a separate inner pin 120, an outer lead 130, a first patch 141, and a second patch 142. 2 is a schematic cross-sectional view of the lead frame 100 for cutting the pins 110, and FIG. 3 is a schematic cross-sectional view of the lead frame 100 for cutting the independent inner pin 120 and the outer lead 130. The pins 110, the independent inner leads 120 and the outer leads 130 are the same metal material of the same layer, and the material thereof may be copper, iron or an alloy thereof. The first patch 141 and the second patch 142 are electrically insulated adhesive patches, and the material thereof may be polyamidamine, such as Kapton. tape.
該些引腳110係具有傳統導線架之引腳結構，每一引腳110係具有一體連接之一在該模封區101內之內腳部111與一延伸到該模封區101之外之外腳部112，並且每一內腳部111之內端係形成為一第一接指113。故延伸到該模封區101之外之該些外腳部112可被上下模具夾合並可對外電性導通。The pins 110 have a lead structure of a conventional lead frame, and each of the pins 110 has an integral connection between the leg portion 111 and a portion extending outside the die seal region 101. The outer leg portion 112 and the inner end of each inner leg portion 111 are formed as a first finger 113. Therefore, the outer leg portions 112 extending beyond the mold sealing region 101 can be combined by the upper and lower molds to be electrically conductive.
該獨立內引腳120係完全形成在該模封區101內，故僅作為供打線連接之內部電性轉接元件，並且該獨立內引腳120係與該些引腳110為同層結構，故無習知另外設置之必要。該獨立內引腳120之兩端係形成為一第二接指121與一第三接指122。其中，「完全形成在該模封區101內」則包含該第二接指121與該第三接指122亦在該模封區101內。通常該獨立內引腳120係可較短於相鄰近引腳110之內腳部111。The independent inner pin 120 is completely formed in the mold sealing region 101, and therefore serves only as an internal electrical switching component for wire bonding, and the independent inner pin 120 is in the same layer structure as the pins 110. Therefore, there is no need for additional settings. The two ends of the independent inner pin 120 are formed as a second finger 121 and a third finger 122. The "completely formed in the mold sealing area 101" includes the second connecting finger 121 and the third connecting finger 122 also in the molding area 101. Typically, the individual inner pins 120 can be shorter than the inner legs 111 adjacent the pins 110.
該外引腳130係局部形成在該模封區101內並延伸到該模封區101之外，該外引腳130係具有一在該模封區101內之第四接指131，以供內部電性連接至該獨立內引腳120並提供對外電性導通。通常該外引腳130係可較長於相鄰近引腳110之外腳部112。The outer lead 130 is partially formed in the mold sealing area 101 and extends outside the mold sealing area 101. The outer lead 130 has a fourth finger 131 in the mold sealing area 101 for The internal electrical connection is electrically connected to the independent inner pin 120 and provides external electrical conduction. Typically, the outer pin 130 can be longer than the foot 112 adjacent the pin 110.
在該些內腳部111中之至少一內腳部(特別標示為111’)係電性隔離地形成在該獨立內引腳120與該外引腳130之間(如第1及3圖所示)，其中該些第一接指113與該第二接指121係為線性排列，以供與晶片電性連接之打線接合。該第三接指122與該第四接指131係為相 鄰近(如第1圖所示)。At least one of the inner leg portions 111 (specifically designated as 111') is electrically isolated between the independent inner pin 120 and the outer lead 130 (as shown in FIGS. 1 and 3) The first finger 113 and the second finger 121 are linearly arranged for wire bonding with the wafer. The third finger 122 and the fourth finger 131 are phased Proximity (as shown in Figure 1).
該第一貼片141係貼設於該獨立內引腳120與該些內腳部111，以電性絕緣地固定該獨立內引腳120，該第一貼片141係位於該模封區101內並靠近該些第一接指113與該第二接指121(如第1圖所示)。The first chip 141 is attached to the inner inner lead 120 and the inner leg portion 111 to electrically fix the independent inner lead 120. The first patch 141 is located in the mold sealing area 101. And close to the first finger 113 and the second finger 121 (as shown in FIG. 1).
該第二貼片142係貼設於該獨立內引腳120與該些內腳部111，以電性絕緣地固定該獨立內引腳120，該第二貼片142係位於該模封區101內並靠近該第三接指122與該第四接指131(如第1圖所示)。因此，在半導體封裝製程中，無法被上下模具夾合之該獨立內引腳120係能被電性絕緣地固定在該模封區101內。該第二貼片142之長度係可較短於該第一貼片141。The second chip 142 is disposed on the independent inner pin 120 and the inner leg portion 111 to electrically fix the independent inner pin 120. The second patch 142 is located in the die seal region 101. The inner finger is adjacent to the third finger 122 and the fourth finger 131 (as shown in FIG. 1). Therefore, in the semiconductor packaging process, the individual inner leads 120 that cannot be sandwiched by the upper and lower molds can be electrically insulated and fixed in the mold sealing region 101. The length of the second patch 142 can be shorter than the first patch 141.
因此，該獨立內引腳120、該些引腳110與該外引腳130為同層金屬結構，利用該獨立內引腳120兩端之第二接指121與第三接指122的位置關係以及第一貼片141與第二貼片142的貼設，使得該導線架100在該些引腳110之同一層結構中具有電性轉接的整合作用，製程中不需要額外設置供打線連接之內部電性轉接元件，並能避免銲線的非晶片焊點會產生打線高度差與位移偏差。Therefore, the independent inner leads 120, the pins 110 and the outer leads 130 are in the same layer metal structure, and the positional relationship between the second fingers 121 and the third fingers 122 at the two ends of the independent inner pins 120 is utilized. And the mounting of the first patch 141 and the second patch 142, so that the lead frame 100 has an electrical transfer integration function in the same layer structure of the pins 110, and no additional connection is required in the process for the wire bonding. The internal electrical switching component can avoid the wire height difference and displacement deviation of the non-wafer solder joint of the bonding wire.
再如第1圖所示，更具體地，該獨立內引腳120在該第一貼片141與該第二貼片142之間係可具有一第一連接條殘留痕跡151。緊鄰該獨立內引腳120之其中一之該些內腳部111係可亦具有一第二連接條殘留痕跡 152，其係與該第一連接條殘留痕跡151相對應。這是因為在該第一貼片141與該第二貼片142貼附至該些引腳110與該獨立內引腳120之前，該獨立內引腳120係可一體連接到相鄰之其中一引腳110之內腳部111’(如第4圖所示)。As shown in FIG. 1 , more specifically, the independent inner lead 120 may have a first connecting strip residual trace 151 between the first patch 141 and the second patch 142 . The inner leg portions 111 of one of the independent inner pins 120 may also have a trace of the second connecting strip. 152, which corresponds to the first connecting strip residue trace 151. This is because the independent inner pin 120 can be integrally connected to one of the adjacent ones before the first patch 141 and the second patch 142 are attached to the pins 110 and the independent inner leads 120. The foot 111' within the pin 110 (as shown in Figure 4).
較佳地，該導線架100可適用於「晶片在引腳上」(COL)之封裝型態。再如第1圖所示，該些第一接指113與該第四接指131係可位於該晶片設置區102之外，該獨立內引腳120係延展至一特定長度以穿越該晶片設置區102並使該第二接指121與該第三接指122位於該晶片設置區102之外。因此，晶片之背面係可同時設置於該些引腳110與該獨立內引腳120，並且不覆蓋該些第一接指113、該第二接指121、該第三接指122與該第四接指131，並且該些第一接指113與該第二接指121為第一接指群組，該第三接指122與該第四接指131為排列方向不同之第二接指群組。在本實施例中，第二接指群組(包含該第三接指122與該第四接指131)之排列方向係可與第一接指群組(包含該些第一接指113與該第二接指121)之排列方向互為平行。尤佳地，該第一貼片141與該第二貼片142係可更位於該晶片設置區102內，不會佔據該模封區101在該晶片設置區102之外有限的接指配置空間。在一較佳實施例中，再如第1圖所示，該第四接指131係可往內延伸至該晶片設置區102內，使該第四接指131亦具有承載晶片之作用。該第二 貼片142係可更貼設於該第四接指131。此外，該導線架100係可另包含有複數個側支撐墊170，係排列在該些引腳110之該些內腳部111之兩側，該些側支撐墊170之至少一部位或絕大部份係形成於該晶片設置區102內，以增加晶片承載效果。而該些側支撐墊170係可具有複數個模流通孔171，有助於一封膠體之填入，以增加被封膠體結合之強度。Preferably, the leadframe 100 is adaptable to a "wafer on pin" (COL) package type. As shown in FIG. 1 , the first fingers 113 and the fourth fingers 131 are located outside the wafer setting area 102 , and the independent inner pins 120 are extended to a specific length to traverse the wafer. The area 102 and the second finger 121 and the third finger 122 are located outside the wafer setting area 102. Therefore, the back side of the chip can be simultaneously disposed on the pins 110 and the independent inner pins 120, and does not cover the first fingers 113, the second fingers 121, the third fingers 122, and the first The fourth finger 131 and the second finger 121 are the first finger group, and the third finger 122 and the fourth finger 131 are second fingers different in arrangement direction. Group. In this embodiment, the arrangement direction of the second finger group (including the third finger 122 and the fourth finger 131) and the first finger group (including the first fingers 113 and The arrangement direction of the second fingers 121) is parallel to each other. More preferably, the first patch 141 and the second patch 142 are located in the wafer setting area 102, and do not occupy a limited finger arrangement space of the molding area 101 outside the wafer setting area 102. . In a preferred embodiment, as shown in FIG. 1, the fourth finger 131 can extend inwardly into the wafer setting area 102, so that the fourth finger 131 also functions as a carrier. The second The patch 142 can be further attached to the fourth finger 131. In addition, the lead frame 100 can further include a plurality of side support pads 170 disposed on opposite sides of the inner leg portions 111 of the pins 110, and at least one portion of the side support pads 170 or Portions are formed in the wafer setting area 102 to increase the wafer carrying effect. The side support pads 170 can have a plurality of mold flow holes 171 to facilitate the filling of a gel to increase the strength of the seal body.
在本實施例中，該導線架100係可另包含有複數個短引腳160，係較短於該些引腳110，並且不延伸至該晶片設置區102內，故不作為晶片承載。並且該些短引腳160之內端161係朝向該些第一接指113與該第二接指121，故能形成在一打線區域內，以增加引腳數量。In this embodiment, the lead frame 100 can further include a plurality of short pins 160 that are shorter than the pins 110 and do not extend into the wafer setting area 102 and are not carried as wafers. The inner ends 161 of the short pins 160 are directed toward the first fingers 113 and the second fingers 121, so that they can be formed in a wire bonding region to increase the number of pins.
關於該導線架100之鎖固增進功效，尚可採取以下幾點技術手段達成。該些內腳部111在該晶片設置區102內之一特定區段係可寬度放大以形成為複數個第一鎖墊114。該獨立內引腳120在該第一晶片下方之一特定區段係可寬度放大以形成為一第二鎖墊123。該些第一鎖墊114與該第二鎖墊123係可為線性排列，故可以避免該獨立內引腳120與該些內腳部111在封膠體內產生剝離或滑移。此外，該導線架100係可另包含有一T形壩181或182，其係形成於該模封區101之兩側內但形成在該晶片設置區102之外，每一T形壩181或182連接有一空白外腳部，以避免空白外腳部的剝離或滑移。Regarding the locking enhancement effect of the lead frame 100, the following technical means can be achieved. The inner leg portion 111 can be enlarged in width in a particular section of the wafer setting area 102 to form a plurality of first lock pads 114. The individual inner pin 120 can be width-amplified in a specific section below the first wafer to form a second lock pad 123. The first locking pad 114 and the second locking pad 123 can be linearly arranged, so that the independent inner pin 120 and the inner leg portion 111 can be prevented from being peeled off or slipped in the sealing body. In addition, the lead frame 100 may further include a T-shaped dam 181 or 182 formed on both sides of the molding region 101 but formed outside the wafer setting region 102, each T-shaped dam 181 or 182. A blank outer leg is attached to avoid peeling or slipping of the blank outer leg.
第4與5圖係繪示上述導線架100在製造過程中之局部平面示意圖。首先，利用蝕刻或沖壓技術使一金屬板形成為一如第4圖所示之導線架半成品，其主架構已大致形成，包含有該些引腳110、一尚未電性隔離之獨立內引腳120、一外引腳130以及一連接條150。該獨立內引腳120係完全形成在該模封區101內並與該些引腳110為同層結構。該連接條150係位於該晶片設置區102內並為同材質地一體連接該獨立內引腳120至緊鄰該獨立內引腳120之其中一之該些內腳部111或111’。故能在貼片貼附之前，預先確定該獨立內引腳120之相對位置並且不會位移。如第5圖所示，之後，貼設一第一貼片141與一第二貼片142於該獨立內引腳120與該些內腳部111，其中該第一貼片141係位於該模封區101內並靠近該些第一接指113與該第二接指121，該第二貼片142係位於該模封區101內並靠近該第三接指122與該第四接指131。最後，切除該連接條150，以使該獨立內引腳120與該緊鄰之內腳部111為電性隔離。如第1圖所示，通常在該連接條150切除之後，該獨立內引腳120在該第一貼片141與該第二貼片142之間係可具有一第一連接條殘留痕跡151，並且緊鄰該獨立內引腳120之其中一之該些內腳部111係亦具有一第二連接條殘留痕跡152，其係與該第一連接條殘留痕跡151相對應。4 and 5 are partial plan views showing the lead frame 100 described above during the manufacturing process. First, a metal plate is formed into a semi-finished product of the lead frame as shown in FIG. 4 by etching or stamping technology, and the main structure thereof is substantially formed, and the pins 110 and an independent inner pin that are not electrically isolated are included. 120, an outer pin 130 and a connecting strip 150. The individual inner leads 120 are completely formed in the mold region 101 and have the same layer structure as the pins 110. The connecting strip 150 is located in the wafer setting area 102 and integrally connects the independent inner pin 120 to the inner leg portion 111 or 111' adjacent to the one of the independent inner pins 120. Therefore, the relative position of the independent inner pin 120 can be predetermined and not displaced before the patch is attached. As shown in FIG. 5, a first patch 141 and a second patch 142 are attached to the independent inner lead 120 and the inner leg portion 111, wherein the first patch 141 is located in the mold. In the sealing area 101, adjacent to the first connecting finger 113 and the second connecting finger 121, the second patch 142 is located in the molding area 101 and adjacent to the third connecting finger 122 and the fourth connecting finger 131. . Finally, the connecting strip 150 is cut away to electrically isolate the independent inner lead 120 from the immediately adjacent inner leg portion 111. As shown in FIG. 1 , the independent inner lead 120 may have a first connecting strip residual trace 151 between the first patch 141 and the second patch 142 after the connecting strip 150 is cut off. And the inner leg portions 111 of the one of the independent inner pins 120 also have a second connecting strip residual mark 152 corresponding to the first connecting strip residual trace 151.
如第6圖所示，該導線架100可運用於一「晶片在 引腳上」封裝構造，特別是該封裝構造為多晶片堆疊。一第一晶片210對準於該晶片設置區102而使其背面設置於該獨立內引腳120上，依第1圖中該晶片設置區102之形狀可推知，該第一晶片210亦設置於該些引腳110上。並利用複數個第一銲線221電性連接該第一晶片210之複數個第一銲墊211至該導線架100，例如可以連接到該些引腳110之第一接指113、該獨立內引腳120之第二接指121以及該短引腳160之內端161。至少一跳接銲線230可遠離上述形成有該些第一銲線221之打線區，能電性連接該獨立內引腳120之第三接指122與該外引腳130之第四接指131而跨過在其間引腳之內腳部111’，達成不增加元件高度之腳位次序的調整，並且不會增加供打線內部電性轉接元件的設置步驟與厚度。一第二晶片250可更疊設於該第一晶片210，並以複數個第二銲線222電性連接該第二晶片250之複數個第二銲墊251至該導線架100。當該第一晶片210與該第二晶片250為階梯狀堆疊時，該跳接銲線230可被隱藏在該第二晶片250之突出部位之下方。此外，一封膠體240係可形成於該模封區101內，以密封該些晶片210、250、該些引腳之內腳部111’、該獨立內引腳120、該些銲線221、222與該跳接銲線230，其中該獨立內引腳120係被完全密封，不會延伸到該封膠體240之側邊。As shown in Figure 6, the leadframe 100 can be used in a "wafer in "on-pin" package construction, in particular the package is constructed as a multi-wafer stack. A first wafer 210 is disposed on the wafer setting region 102 and has a back surface disposed on the independent inner pin 120. According to the shape of the wafer setting region 102 in FIG. 1, the first wafer 210 is also disposed on the first wafer 210. The pins 110 are on. And electrically connecting the plurality of first pads 211 of the first wafer 210 to the lead frame 100 by using a plurality of first bonding wires 221, for example, may be connected to the first fingers 113 of the pins 110, the independent The second finger 121 of the pin 120 and the inner end 161 of the short pin 160. The at least one jumper wire 230 can be remote from the wire bonding region where the first bonding wires 221 are formed, and the third finger 122 of the independent inner pin 120 and the fourth finger of the outer pin 130 can be electrically connected. 131, across the foot portion 111' between the pins therebetween, achieves an adjustment of the order of the feet without increasing the height of the element, and does not increase the setting steps and thickness for the internal electrical switching element of the wire. A second wafer 250 can be stacked on the first wafer 210 and electrically connected to the plurality of second pads 251 of the second wafer 250 to the lead frame 100 by a plurality of second bonding wires 222. When the first wafer 210 and the second wafer 250 are stacked in a stepwise manner, the jumper wire 230 may be hidden under the protruding portion of the second wafer 250. In addition, a glue body 240 can be formed in the mold sealing area 101 to seal the wafers 210, 250, the inner leg portions 111' of the pins, the independent inner pins 120, the bonding wires 221, 222 and the jumper bond wire 230, wherein the separate inner pin 120 is completely sealed and does not extend to the side of the sealant 240.
依據本發明之第二具體實施例，另一種具有獨立內 引腳之導線架100舉例說明於第7圖之平面示意圖與第8圖之在貼設貼片之前之局部平面示意圖。在該導線架100中定義有一模封區101以及一在該模封區101內之晶片設置區102，該導線架100係包含複數個引腳110、一獨立內引腳120、一外引腳130、一第一貼片141以及一第二貼片142。According to a second embodiment of the invention, the other has an independent The lead frame 100 of the pin is illustrated in a plan view of FIG. 7 and a partial plan view of the figure 8 before the patch is attached. A die seal region 101 and a wafer mounting region 102 in the die seal region 101 are defined in the lead frame 100. The lead frame 100 includes a plurality of pins 110, an independent inner pin 120, and an outer pin. 130, a first patch 141 and a second patch 142.
每一引腳110係具有一體連接之一在該模封區101內之內腳部111與一延伸到該模封區101之外之外腳部112，並且每一內腳部111之內端係形成為一第一接指113。該獨立內引腳120係完全形成在該模封區101內並與該些引腳110為同層結構，該獨立內引腳120之兩端係形成為一第二接指121與一第三接指122。該外引腳130係局部形成在該模封區101內並延伸到該模封區101之外，該外引腳130係具有一在該模封區101內之第四接指131，該些內腳部111之至少一內腳部111’係電性隔離地形成在該獨立內引腳120與該外引腳130之間，其中該些第一接指113與該第二接指121係為線性排列，該第三接指122與該第四接指131係為相鄰近。在本實施例中，該第三接指122與該第四接指131之排列方向係可與該些第一接指113與該第二接指121之排列方向互為垂直。該些引腳110之該些外腳部112係可分散在該模封區101之兩相對平行側邊。依照此一架構可以省略短引腳，以增加引腳對晶片之支撐效果。此外，該第一貼片141與該第二貼片142係貼設於該獨立 內引腳120與該些內腳部111並位於該模封區101內，以電性絕緣地固定該獨立內引腳120。其中，該第一貼片141係靠近該些第一接指113與該第二接指121。該第二貼片142係靠近該第三接指122與該第四接指131。Each of the pins 110 has an inner portion 111 in the molding region 101 and a foot portion 112 extending beyond the molding region 101, and the inner end of each inner leg portion 111 It is formed as a first finger 113. The independent inner lead 120 is completely formed in the mold sealing area 101 and has the same layer structure as the pins 110. The two ends of the independent inner lead 120 are formed as a second finger 121 and a third end. Finger 122. The outer lead 130 is partially formed in the mold sealing area 101 and extends outside the mold sealing area 101. The outer lead 130 has a fourth finger 131 in the mold sealing area 101. The at least one inner leg portion 111 ′ of the inner leg portion 111 is electrically isolated between the independent inner pin 120 and the outer pin 130 , wherein the first finger 113 and the second finger 121 are For linear alignment, the third finger 122 is adjacent to the fourth finger 131. In this embodiment, the arrangement direction of the third finger 122 and the fourth finger 131 may be perpendicular to the arrangement direction of the first finger 113 and the second finger 121. The outer leg portions 112 of the pins 110 are dispersed on two opposite parallel sides of the molding region 101. According to this architecture, short pins can be omitted to increase the pin-to-wafer support. In addition, the first patch 141 and the second patch 142 are attached to the independent The inner lead 120 and the inner leg portion 111 are located in the mold sealing region 101 to electrically fix the independent inner lead 120. The first patch 141 is adjacent to the first finger 113 and the second finger 121. The second patch 142 is adjacent to the third finger 122 and the fourth finger 131.
如第7圖所示，該獨立內引腳120係具有一第一連接條殘留痕跡151。而緊鄰該獨立內引腳120之其中一之該些內腳部111’係亦具有一第二連接條殘留痕跡152，其係與該第一連接條殘留痕跡151相對應。如第8圖所示，在貼設該第一貼片141與該第二貼片142之前，該獨立內引腳120係藉由至少一連接條150以與緊鄰之內腳部111’或111一體連接。在移除該連接條150之後便產生第一連接條殘留痕跡151與第二連接條殘留痕跡152。因此，該獨立內引腳120係能與該些引腳110形成在同一層導線架結構中並能被電性絕緣地固定在該模封區101內，不需要被模具夾合。As shown in FIG. 7, the independent inner pin 120 has a first connecting strip residual trace 151. The inner leg portions 111' adjacent to one of the individual inner pins 120 also have a second connecting strip residual mark 152 corresponding to the first connecting strip residual trace 151. As shown in FIG. 8, before the first patch 141 and the second patch 142 are attached, the independent inner pin 120 is connected to the inner leg portion 111' or 111 by at least one connecting strip 150. One connection. After the connecting strip 150 is removed, a first connecting strip residual trace 151 and a second connecting strip residual trace 152 are produced. Therefore, the independent inner leads 120 can be formed in the same layer of lead frame structure as the pins 110 and can be electrically insulated in the mold sealing region 101 without being clamped by the mold.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，本發明技術方案範圍當依所附申請專利範圍為準。任何熟悉本專業的技術人員可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention.
100‧‧‧導線架100‧‧‧ lead frame
101‧‧‧模封區101‧‧‧Molded area
102‧‧‧晶片設置區102‧‧‧ wafer setup area
110‧‧‧引腳110‧‧‧ pin
111‧‧‧內腳部111‧‧‧foot
111’‧‧‧內腳部111’‧‧‧foot
112‧‧‧外腳部112‧‧‧Outer foot
113‧‧‧第一接指113‧‧‧First finger
114‧‧‧第一鎖墊114‧‧‧First lock pad
120‧‧‧獨立內引腳120‧‧‧Independent internal pins
121‧‧‧第二接指121‧‧‧second finger
122‧‧‧第三接指122‧‧‧ Third finger
123‧‧‧第二鎖墊123‧‧‧Second lock pad
130‧‧‧外引腳130‧‧‧External pin
131‧‧‧第四接指131‧‧‧fourth finger
141‧‧‧第一貼片141‧‧‧First patch
142‧‧‧第二貼片142‧‧‧Second patch
150‧‧‧連接條150‧‧‧Connecting strip
151‧‧‧第一連接條殘留痕跡151‧‧‧Residual traces of the first connecting strip
152‧‧‧第二連接條殘留痕跡152‧‧‧Second joint strip residue trace
160‧‧‧短引腳160‧‧‧ Short pin
161‧‧‧內端161‧‧‧ inner end
170‧‧‧側支撐墊170‧‧‧ side support pads
171‧‧‧模流通孔171‧‧‧Molded holes
181‧‧‧T形壩181‧‧‧T-shaped dam
182‧‧‧T形壩182‧‧‧T-shaped dam
210‧‧‧第一晶片210‧‧‧First chip
211‧‧‧第一銲墊211‧‧‧First pad
221‧‧‧第一銲線221‧‧‧First wire bond
222‧‧‧第二銲線222‧‧‧second welding line
230‧‧‧跳接銲線230‧‧‧jumper wire
240‧‧‧封膠體240‧‧‧ Sealant
250‧‧‧第二晶片250‧‧‧second chip
251‧‧‧第二銲墊251‧‧‧Second pad
第1圖：為依據本發明第一具體實施例的一種具有獨立 內引腳之導線架之局部平面示意圖。Figure 1: An independent embodiment of the first embodiment of the present invention A partial plan view of the lead frame of the inner lead.
第2圖：為依據本發明第一具體實施例的導線架剖切引腳的截面示意圖。Fig. 2 is a schematic cross-sectional view showing a lead-out pin of a lead frame according to a first embodiment of the present invention.
第3圖：為依據本發明第一具體實施例的導線架剖切獨立內引腳與外引腳的截面示意圖。Fig. 3 is a cross-sectional view showing the independent inner and outer pins of the lead frame according to the first embodiment of the present invention.
第4圖：為依據本發明第一具體實施例的導線架在貼設貼片之前的局部平面示意圖。Fig. 4 is a partial plan view showing the lead frame according to the first embodiment of the present invention before the patch is attached.
第5圖：為依據本發明第一具體實施例的導線架在貼設貼片之後的局部平面示意圖。Fig. 5 is a partial plan view showing the lead frame according to the first embodiment of the present invention after the patch is attached.
第6圖：繪示一種半導體封裝構造使用本發明第一具體實施例的導線架包含剖切獨立內引腳與外引腳的截面示意圖。FIG. 6 is a cross-sectional view showing a semiconductor package structure using a lead frame according to a first embodiment of the present invention, including cut-away independent inner and outer leads.
第7圖：為依據本發明第二具體實施例的另一種具有獨立內引腳之導線架之局部平面示意圖。Figure 7 is a partial plan view showing another lead frame having independent inner leads in accordance with a second embodiment of the present invention.
第8圖：為依據本發明第二具體實施例的導線架在貼設貼片前之局部平面示意圖。Figure 8 is a partial plan view showing the lead frame according to the second embodiment of the present invention before the patch is attached.
100‧‧‧導線架100‧‧‧ lead frame
101‧‧‧模封區101‧‧‧Molded area
102‧‧‧晶片設置區102‧‧‧ wafer setup area
110‧‧‧引腳110‧‧‧ pin
111‧‧‧內腳部111‧‧‧foot
111’‧‧‧內腳部111’‧‧‧foot
112‧‧‧外腳部112‧‧‧Outer foot
113‧‧‧第一接指113‧‧‧First finger
114‧‧‧第一鎖墊114‧‧‧First lock pad
120‧‧‧獨立內引腳120‧‧‧Independent internal pins
121‧‧‧第二接指121‧‧‧second finger
122‧‧‧第三接指122‧‧‧ Third finger
123‧‧‧第二鎖墊123‧‧‧Second lock pad
130‧‧‧外引腳130‧‧‧External pin
131‧‧‧第四接指131‧‧‧fourth finger
141‧‧‧第一貼片141‧‧‧First patch
142‧‧‧第二貼片142‧‧‧Second patch
151‧‧‧第一連接條殘留痕跡151‧‧‧Residual traces of the first connecting strip
152‧‧‧第二連接條殘留痕跡152‧‧‧Second joint strip residue trace
160‧‧‧短引腳160‧‧‧ Short pin
161‧‧‧內端161‧‧‧ inner end
170‧‧‧側支撐墊170‧‧‧ side support pads
171‧‧‧模流通孔171‧‧‧Molded holes
181‧‧‧T形壩181‧‧‧T-shaped dam
182‧‧‧T形壩182‧‧‧T-shaped dam
Claims (25)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097135392A TWI399840B (en) | 2008-09-15 | 2008-09-15 | Leadframe having isolated inner lead and its fabricating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097135392A TWI399840B (en) | 2008-09-15 | 2008-09-15 | Leadframe having isolated inner lead and its fabricating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201011882A TW201011882A (en) | 2010-03-16 |
| TWI399840B true TWI399840B (en) | 2013-06-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW097135392A TWI399840B (en) | 2008-09-15 | 2008-09-15 | Leadframe having isolated inner lead and its fabricating method |
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| TW (1) | TWI399840B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337521B1 (en) * | 1999-09-22 | 2002-01-08 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US20050236698A1 (en) * | 2004-04-27 | 2005-10-27 | Isao Ozawa | Semiconductor device in which semiconductor chip is mounted on lead frame |
| TW200539414A (en) * | 2004-05-24 | 2005-12-01 | Advanced Semiconductor Eng | Leadless leadframe with an improved die pad for mold locking |
-
2008
- 2008-09-15 TW TW097135392A patent/TWI399840B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337521B1 (en) * | 1999-09-22 | 2002-01-08 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US20050236698A1 (en) * | 2004-04-27 | 2005-10-27 | Isao Ozawa | Semiconductor device in which semiconductor chip is mounted on lead frame |
| TW200539414A (en) * | 2004-05-24 | 2005-12-01 | Advanced Semiconductor Eng | Leadless leadframe with an improved die pad for mold locking |
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|---|---|
| TW201011882A (en) | 2010-03-16 |
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