TWI398845B

TWI398845B - Shift register

Info

Publication number: TWI398845B
Application number: TW97137284A
Authority: TW
Inventors: Tsung Ting Tsai; Yung Chih Chen
Original assignee: Au Optronics Corp
Priority date: 2008-09-26
Filing date: 2008-09-26
Publication date: 2013-06-11
Also published as: TW201013626A

Description

移位暫存器Shift register

本發明涉及一種位移暫存器，尤其是指一種能降低因偏壓效應產生漏電流之位移暫存器。The invention relates to a displacement register, in particular to a displacement register capable of reducing leakage current caused by a bias effect.

功能先進的顯示器已漸成為現今消費電子產品的重要特色，其中液晶顯示器已經逐漸為各種電子設備如電視、行動電話、個人數位助理(PDA)、數位相機、電腦螢幕或筆記型電腦螢幕所廣泛應用。低溫多晶矽(Low Temperature Poly-Silicon，LTPS)液晶顯示器是目前消費性產品開發的主流，主要應用於高度整合特性與高畫質顯示器。Advanced display has become an important feature of today's consumer electronics products. LCD monitors have been widely used in a variety of electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens. . Low Temperature Poly-Silicon (LTPS) liquid crystal displays are currently the mainstream of consumer product development, and are mainly used in highly integrated features and high-quality displays.

請參閱第1圖，第1圖係先前技術之液晶顯示器10之功能方塊圖。液晶顯示器10包含一液晶顯示面板12、一閘極驅動器(gate driver)14以及源極驅動器(source driver)16。液晶顯示面板12包含複數個像素(pixel)，而每一個像素包含三個分別代表紅綠藍(RGB)三原色的像素單元20構成。以一個1024×768解析度的液晶顯示面板12來說，共需要1024×768×3個像素單元20組合而成。閘極驅動器14輸出掃描訊號使得每一列的電晶體22依序開啟，同時源極驅動器16則輸出對應的資料訊號至一整列的像素單元20使其充電到各自所需的電壓，以顯示不同的灰階。當同一列充電完畢後，閘極驅動器14便將該列的掃描訊號關閉，然後閘極驅動器14再輸出掃描訊號將下一列的電晶體22打開，再由源極驅動器16對下一列的像素單元20進行充放電。如此依序下去，直到液晶顯示面板12的所有像素單元20 都充電完成，再從第一列開始充電。Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art liquid crystal display 10. The liquid crystal display 10 includes a liquid crystal display panel 12, a gate driver 14, and a source driver 16. The liquid crystal display panel 12 includes a plurality of pixels, and each of the pixels includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB). For a liquid crystal display panel 12 having a resolution of 1024×768, a total of 1024×768×3 pixel units 20 are required to be combined. The gate driver 14 outputs a scan signal so that the transistors 22 of each column are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different Grayscale. After the same column is charged, the gate driver 14 turns off the scan signal of the column, and then the gate driver 14 outputs the scan signal to turn on the transistor 22 of the next column, and then the source driver 16 pairs the pixel unit of the next column. 20 charge and discharge. So in sequence, until all the pixel units 20 of the liquid crystal display panel 12 All charging is completed, and charging starts from the first column.

在目前的液晶顯示面板設計中，閘極驅動器14等效上係為移位暫存器(shift register)，其目的即每隔一固定間隔輸出掃描訊號至液晶顯示面板12。以一個1024×768解析度以及60Hz的更新頻率的液晶顯示面板12為例，每一個畫面的顯示時間約為1/60=16.67ms。所以每一個掃描訊號的脈波週期約為16.67ms/768=21.7μs。而源極驅動器16則在這21.7μs的時間內，將像素單元20充放電到所需的電壓，以顯示出相對應的灰階。In the current liquid crystal display panel design, the gate driver 14 is equivalently a shift register, and the purpose is to output a scan signal to the liquid crystal display panel 12 at regular intervals. Taking a liquid crystal display panel 12 having a resolution of 1024 x 768 and an update frequency of 60 Hz as an example, the display time of each picture is about 1/60 = 16.67 ms. Therefore, the pulse period of each scanning signal is about 16.67 ms / 768 = 21.7 μs. The source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 μs period to display the corresponding gray scale.

請參閱第2圖以及第3圖，第2圖係先前技術之移位暫存器之移位暫存單元的電路圖，第3圖係電晶體的源-閘極電壓差V_GS 與漏電流Id的關係圖。第2圖所示係美國專利公開第2008/0056431號揭露的移位暫存器。當電晶體403、413關閉時，雖然閘-源極電壓差V_GS 等於0，但是從第3圖可以發覺，實際上仍會有些許的漏電流產生，而使得節點N5的電壓有漏電的疑慮。如此一來，每一級移位暫存單元都會因為漏電的影響使得輸出訊號脈衝的波形越來越低而影響顯示品質。對於使用於非晶矽薄膜製程技術製造的高解析度液晶顯示面板的閘極驅動器14而言，製程的元件均勻性與穩定性有著極大的變異特性。所以在點亮液晶顯示面板12後，常常會因為閘極驅動器14內部電晶體的偏壓(stress)問題而造成液晶顯示面板12的表現發生異常。Please refer to FIG. 2 and FIG. 3, FIG. 2 is a circuit diagram of a shift register unit of the prior art shift register, and FIG. 3 is a source-gate voltage difference V _GS and a drain current Id of the transistor. Diagram of the relationship. Figure 2 shows a shift register disclosed in U.S. Patent Publication No. 2008/0056431. When the transistors 403, 413 are turned off, although the gate-source voltage difference V _GS is equal to 0, it can be seen from Fig. 3 that there is still a slight leakage current, and the voltage of the node N5 has a leakage. . In this way, each stage of the shift register unit will cause the waveform of the output signal pulse to be lower and lower due to the influence of the leakage, thereby affecting the display quality. For the gate driver 14 of the high-resolution liquid crystal display panel manufactured by the amorphous germanium film process technology, the uniformity and stability of the components of the process have great variability. Therefore, after the liquid crystal display panel 12 is lit, the performance of the liquid crystal display panel 12 is often abnormal due to the stress of the internal transistor of the gate driver 14.

因此，本發明之主要目的在於提供一種能改善因偏壓效應產生漏電流的移位暫存器，在不同製程條件下仍然可以順利輸出波形，以解決上述先前技術的問題。Therefore, the main object of the present invention is to provide an improvement in leakage current due to a bias effect. The shift register can still smoothly output waveforms under different process conditions to solve the above problems of the prior art.

依據本發明之上述目的，本發明提供一種移位暫存器，其包含複數個以串聯方式連接的移位暫存單元。每一移位暫存單元包含提昇電路、第一時脈下拉模組以及第二時脈下拉模組。提昇電路包含第一電晶體、第二電晶體和第三電晶體。第一電晶體的汲極、閘極和源極分別耦接於該第一時脈訊號、第一節點以及驅動訊號端。第二電晶體的汲極、閘極和源極分別耦接於該第一時脈訊號、第一節點以及一輸出訊號端。第三電晶體的汲極和閘極耦接於前一級移位暫存單元之一驅動訊號端，其源極耦接於該第一節點。第一時脈下拉模組包含第四電晶體、第五電晶體、第六電晶體、第七電晶體和第一驅動電路。第四電晶體的汲極、閘極以及源極分別耦接至該提升電路之該第一節點、第二節點及輸出節點。第五電晶體的汲極、閘極和源極分別耦接至該輸出節點、該第二節點及第一電源電壓。第六電晶體的汲極、閘極和源極分別耦接至該驅動訊號端、該第二節點以及該第一電源電壓。第七電晶體的汲極、閘極和源極分別耦接至該第二節點、該輸出節點及該第一電源電壓。In accordance with the above objects of the present invention, the present invention provides a shift register comprising a plurality of shift register units connected in series. Each shift register unit includes a boost circuit, a first clock pull-down module, and a second clock pull-down module. The boost circuit includes a first transistor, a second transistor, and a third transistor. The drain, the gate and the source of the first transistor are respectively coupled to the first clock signal, the first node, and the driving signal end. The drain, the gate and the source of the second transistor are respectively coupled to the first clock signal, the first node and an output signal terminal. The drain and the gate of the third transistor are coupled to one of the driving signal terminals of the previous stage shift register unit, and the source thereof is coupled to the first node. The first clock pull-down module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first driving circuit. The drain, the gate and the source of the fourth transistor are respectively coupled to the first node, the second node and the output node of the boosting circuit. The drain, the gate and the source of the fifth transistor are respectively coupled to the output node, the second node, and the first power voltage. The drain, the gate and the source of the sixth transistor are respectively coupled to the driving signal terminal, the second node, and the first power voltage. The drain, the gate and the source of the seventh transistor are respectively coupled to the second node, the output node, and the first power voltage.

第二時脈下拉模組包含第八電晶體、第九電晶體、第十電晶體以及第二驅動電路。第八電晶體的汲極、閘極和源極分別耦接至該第一節點、一第三節點及前一級移位暫存單元之驅動訊號端。第九電晶體，其汲極、閘極和源極分別耦接至該輸出節點、該第二時脈訊號及該第一電源電壓。第十電晶體的汲極、閘極和源極分別耦接至給該驅動訊號端、該第二時脈訊號及該第一電源電壓。此外，該第一時脈訊號與該第二時脈訊號之相位相差180度。該第一電源電壓之電壓準位係低於該第一時脈訊號或是該第二時脈訊號之最低電壓準位。The second clock pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, and a second driving circuit. The drain, the gate and the source of the eighth transistor are respectively coupled to the driving signal terminals of the first node, a third node and the shifting temporary storage unit of the previous stage. The ninth transistor has a drain, a gate and a source coupled to the output node, the second clock signal and the first power voltage. The drain, the gate and the source of the tenth transistor are respectively coupled to the driving signal terminal and the second clock signal And the first supply voltage. In addition, the phase of the first clock signal and the second clock signal are different by 180 degrees. The voltage level of the first power voltage is lower than the first clock signal or the lowest voltage level of the second clock signal.

依據本發明之一實施例，該第一驅動電路包含第十一電晶體、第十二電晶體和第十三電晶體。該第十一電晶體的汲極與閘極耦接至該第一時脈訊號，其源極耦接至一第四節點。該第十二電晶體的汲極耦接至該第四節點，其閘極與源極皆耦接至一第二時脈訊號。該第十三電晶體的汲極、閘極和源極分別耦接至該第一時脈訊號，該第四節點及該第二節點。該第二驅動電路包含第十四電晶體、第十五電晶體和第十五電晶體。該第十四電晶體的汲極與閘極耦接至該第二時脈訊號，其源極耦接至該第一節點。該第十五電晶體的汲極耦接至該第五節點，閘極與源極係耦接至該第一時脈訊號。該第十五電晶體的汲極、閘極和源極分別耦接至該第二時脈訊號、該第五節點及該第三節點。According to an embodiment of the invention, the first driving circuit comprises an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The drain and the gate of the eleventh transistor are coupled to the first clock signal, and the source thereof is coupled to a fourth node. The drain of the twelfth transistor is coupled to the fourth node, and the gate and the source are coupled to a second clock signal. The drain, the gate and the source of the thirteenth transistor are respectively coupled to the first clock signal, the fourth node and the second node. The second driving circuit includes a fourteenth transistor, a fifteenth transistor, and a fifteenth transistor. The drain and the gate of the fourteenth transistor are coupled to the second clock signal, and the source thereof is coupled to the first node. The drain of the fifteenth transistor is coupled to the fifth node, and the gate and the source are coupled to the first clock signal. The drain, the gate and the source of the fifteenth transistor are respectively coupled to the second clock signal, the fifth node and the third node.

在另一實施例中，該第二驅動電路另包含一第十七電晶體，其汲極、閘極及源極分別耦接至該第三節點、前一級移位暫存單元之一驅動訊號端和該第一電源電壓。In another embodiment, the second driving circuit further includes a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the driving signal of the third node and the previous stage shift register unit. And the first supply voltage.

在又一實施例中。該第一驅動電路包含第十一電晶體，其汲極、閘極及源極分別耦接至該第一時脈訊號、一第二電源電壓以及該第二節點。該第二驅動電路包含第十二電晶體，其汲極、閘極及源極分別耦接至該第二時脈訊號、該第二電源電壓以及該第三節點。In yet another embodiment. The first driving circuit includes an eleventh transistor, and the drain, the gate and the source are respectively coupled to the first clock signal, a second power voltage, and the second node. The second driving circuit includes a twelfth transistor, and the drain, the gate and the source are respectively coupled to the second clock signal, the second power voltage, and the third node.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more apparent and understood.

請參閱第4圖，第4圖係本發明之移位暫存器之第一實施例之移位暫存單元100(n)之電路圖。本實施例之移位暫存器可應用於液晶顯示器之閘極驅動器。移位暫存器包含複數個串接(cascade-connected)之移位暫存單元100(n)。移位暫存單元100(n)用來依據第一時脈訊號CK、第二時脈訊號XCK以及每一移位暫存單元100(n)之前一個移位暫存單元100(n-1)之驅動訊號端ST(n-1)的驅動訊號脈衝自每一移位暫存單元100(n)之輸出端OUT(n)和驅動訊號端ST(n)分別輸出掃描訊號脈衝以及驅動訊號脈衝。當第一級移位暫存單元100(1)自驅動訊號端ST(0)接收到觸發起始脈衝Vst之後，移位暫存單元100(1)就會隔一系統時脈(clock cycle)產生輸出訊號脈衝ST(1)，接下來，每一移位暫存單元100(n)係依據第一時脈訊號CK、第二時脈訊號XCK以及每一移位暫存單元100(n)之前一個移位暫存單元100(n-1)於驅動訊號端ST(n-1)輸出的驅動訊號脈衝，以每隔一系統時脈的方式於每一移位暫存單元100(n)的輸出端OUT(n)輸出一輸出訊號脈衝，該輸出訊號脈衝即掃瞄訊號脈衝，用來開啟對應的像素電晶體。第一時脈訊號CK與第二時脈訊號XCK之相位相差180度。Please refer to FIG. 4, which is a circuit diagram of the shift register unit 100(n) of the first embodiment of the shift register of the present invention. The shift register of this embodiment can be applied to a gate driver of a liquid crystal display. The shift register includes a plurality of cascade-connected shift register units 100(n). The shift register unit 100(n) is configured to use the first clock signal CK, the second clock signal XCK, and a shift register unit 100(n-1) before each shift register unit 100(n). The driving signal pulse of the driving signal terminal ST(n-1) outputs the scanning signal pulse and the driving signal pulse from the output terminal OUT(n) and the driving signal terminal ST(n) of each shift register unit 100(n), respectively. . After the first stage shift register unit 100(1) receives the trigger start pulse Vst from the drive signal terminal ST(0), the shift register unit 100(1) is separated by a system clock cycle. An output signal pulse ST(1) is generated. Next, each shift register unit 100(n) is based on the first clock signal CK, the second clock signal XCK, and each shift register unit 100(n). The driving signal pulse outputted by the previous shift register unit 100(n-1) at the driving signal terminal ST(n-1) is applied to each shift register unit 100(n) every other system clock. The output terminal OUT(n) outputs an output signal pulse, which is a scan signal pulse, which is used to turn on the corresponding pixel transistor. The phase of the first clock signal CK and the second clock signal XCK are 180 degrees out of phase.

每一移位暫存單元100(n)包含提升電路(pull-up circuit)102、第一時脈下拉模組(pull-down module)104以及第二時脈下拉模組106。提升電路102耦接於第一時脈訊號CK，用來於輸出端OUT(n)提供輸出訊號脈衝。提升模組102包含第一電晶體T1、第二電晶體T2以及第三電晶體T3。電晶體T1的汲極、閘極和源極分別耦接於第一時脈訊號CK、第一節點Q以及驅動訊號端ST(n)。電晶體T2的汲極、閘極和源極分別耦接於第一時脈訊號CK、第一節點Q以及輸出訊號端ST(n)。電晶體T3的汲極和閘極耦接於前一級移位暫存單元100(n-1)之驅動訊號端ST(n-1)，其源極耦接於第一節點Q1。在本發明中，時脈訊號CK、XCK的低電壓準位V_L ，係小於直流電源電壓V_SS 的電壓準位，舉例來說，時脈訊號CK、XCK的低電壓準位V_L 可以是-12V，而直流電源電壓V_SS 的電壓準位可以為-9V。Each shift register unit 100(n) includes a pull-up circuit 102, a first clock pull-down module 104, and a second clock pull-down module 106. The boosting circuit 102 is coupled to the first clock signal CK for providing an output signal pulse at the output terminal OUT(n). The lifting module 102 includes a first transistor T1, a second transistor T2, and a third transistor T3. The drain, the gate and the source of the transistor T1 are respectively coupled to the first clock signal CK, the first node Q, and the driving signal terminal ST(n). The drain, the gate and the source of the transistor T2 are respectively coupled to the first clock signal CK, the first node Q, and the output signal terminal ST(n). The drain and the gate of the transistor T3 are coupled to the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1), and the source thereof is coupled to the first node Q1. In the present invention, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . For example, the low voltage level V _{L of the} clock signals CK and XCK may be -12V, and the voltage level of the DC power supply voltage V _SS can be -9V.

第一時脈下拉模組104用來於接收第一時脈訊號CK，導通第一時脈下拉模組104，其包含第四電晶體T4、第五電晶體T5、第六電晶體T6、第七電晶體T7以及第一驅動電路110。電晶體T4的汲極、閘極以及源極分別耦接至第一節點Q、第二節點K及輸出節點OUT(n)。第五電晶體T5的汲極、閘極和源極分別耦接至輸出節點OUT(n)、第二節點K及第一電源電壓V_SS 。電晶體T6的汲極、閘極和源極分別耦接至驅動訊號端ST(n)、第二節點K以及第一電源電壓V_SS 。電晶體T7的汲極、閘極和源極分別耦接至第二節點K、輸出節點OUT(n)及第一電源電壓V_SS 。第一驅動電路110包含第十一電晶體T11、第十二電晶體T12以及第十三電晶體T13。電晶體T11的汲極與閘極耦接至第一時脈訊號CK，其源極耦接至第四節點S。電晶體T12的汲極耦接至第四節點S，其閘極與源極皆耦接至第二時脈訊號XCK。電晶體T13的汲極、閘極和源極分別耦接至第一時脈訊號CK、第四節點S及第二節點K。The first clock pull-down module 104 is configured to receive the first clock signal CK, and turn on the first clock pull-down module 104, which includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, Seven transistors T7 and a first driving circuit 110. The drain, the gate and the source of the transistor T4 are respectively coupled to the first node Q, the second node K, and the output node OUT(n). The drain, the gate and the source of the fifth transistor T5 are respectively coupled to the output node OUT(n), the second node K, and the first power voltage V _SS . The drain, the gate and the source of the transistor T6 are respectively coupled to the driving signal terminal ST(n), the second node K, and the first power voltage V _SS . The drain, the gate and the source of the transistor T7 are respectively coupled to the second node K, the output node OUT(n) and the first power voltage V _SS . The first driving circuit 110 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The drain and the gate of the transistor T11 are coupled to the first clock signal CK, and the source thereof is coupled to the fourth node S. The gate of the transistor T12 is coupled to the fourth node S, and the gate and the source are coupled to the second clock signal XCK. The drain, the gate and the source of the transistor T13 are respectively coupled to the first clock signal CK, the fourth node S and the second node K.

第二時脈下拉模組106用來於接收第二時脈訊號XCK，導通第二時脈下拉模組106，其包含第八電晶體T8、第九電晶體T9、第十電晶體T10以及第二驅動電路112。電晶體T8的汲極、閘極和源極分別耦接至第一節點Q、第三節點P及前一級移位暫存單元100(n-1)之驅動訊號端ST(n-1)。第九電晶體T9的汲極、閘極和源極分別耦接至輸出節點OUT(n)、第二時脈訊號XCK及第一電源電壓V_SS 。電晶體T10的汲極、閘極和源極分別耦接至給驅動訊號端ST(n)、第二時脈訊號XCK及第一電源電壓V_SS 。第二驅動電路112耦接於電晶體T8之閘極，用來下拉第一節點Q之電壓。第二驅動電路112包含第十四電晶體T14、第十五電晶體T15、第十六電晶體T16以及第十七電晶體T17。電晶體T14的汲極與閘極均耦接至第二時脈訊號XCK，其源極耦接至第一節點(N)。電晶體T15的汲極耦接至第五節點N，其閘極與源極係耦接至第一時脈訊號CK。電晶體T16的汲極、閘極和源極分別耦接至第二時脈訊號XCK、第五節點N及第三節點P。電晶體T17的其汲極、閘極及源極分別耦接至第三節點P、前一級移位暫存單元100(n-1)之驅動訊號端ST(n-1)和第一電源電壓V_SS 。The second clock pull-down module 106 is configured to receive the second clock signal XCK, and turn on the second clock pull-down module 106, which includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a Two drive circuit 112. The drain, the gate and the source of the transistor T8 are respectively coupled to the first node Q, the third node P, and the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1). The drain, the gate and the source of the ninth transistor T9 are respectively coupled to the output node OUT(n), the second clock signal XCK, and the first power voltage V _SS . The drain, the gate and the source of the transistor T10 are respectively coupled to the driving signal terminal ST(n), the second clock signal XCK and the first power voltage V _SS . The second driving circuit 112 is coupled to the gate of the transistor T8 for pulling down the voltage of the first node Q. The second driving circuit 112 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The drain and the gate of the transistor T14 are both coupled to the second clock signal XCK, and the source thereof is coupled to the first node (N). The gate of the transistor T15 is coupled to the fifth node N, and the gate and the source are coupled to the first clock signal CK. The drain, the gate and the source of the transistor T16 are respectively coupled to the second clock signal XCK, the fifth node N and the third node P. The drain, the gate and the source of the transistor T17 are respectively coupled to the third node P, the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1), and the first power voltage. V _SS .

請同時參考第4圖以及第5圖，第5圖係第4圖之各訊號以及節點之時序圖。在時段t0-t1期間，第一時脈訊號CK處於低電壓準位，第二時脈訊號XCK處於高電壓準位。來自前一級移位暫存單元100(n-1)的驅動訊號端ST(n-1)的羅動訊號亦處於高電壓準位，使得電晶體T3會開啟(turn on)導通。此時節點Q的電位開始被拉高。在此同時，第一驅動電路110在節點K輸出的電壓準位是低電壓準位V_L ，所以電晶體T4、T5、T6係關閉。但第二驅動電路112在節點P的輸出則為高電壓準位V_H ，所以電晶體T9、T10分別開啟導通低電壓準位V_SS 至輸出端OUT(n)和驅動訊號端ST(n)。電晶體T8開啟導通高電壓準位V_H 至節點Q。Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a timing chart of each signal and node of FIG. During the period t0-t1, the first clock signal CK is at a low voltage level, and the second clock signal XCK is at a high voltage level. The pinning signal from the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1) is also at a high voltage level, so that the transistor T3 turns on. At this time, the potential of the node Q starts to be pulled high. At the same time, the voltage level output by the first driving circuit 110 at the node K is the low voltage level V _L , so the transistors T4, T5, and T6 are turned off. However, the output of the second driving circuit 112 at the node P is the high voltage level V _H , so the transistors T9 and T10 respectively turn on the low voltage level V _SS to the output terminal OUT(n) and the driving signal terminal ST(n). . The transistor T8 turns on the high voltage level V _H to the node Q.

請法意，由於關閉不導通的電晶體T4、T5、T6的閘極電位等於V_L ，其恰好就是第一時脈訊號CK的最低電壓準位，而其源極的電位等於電源電壓V_SS ，所以此時電晶體T4、T5、T6的閘-源極壓差Vgs低於0V。舉例來說，時脈訊號CK的低電壓準位V_L 若是-12V，而直流電源電壓V_SS 的電壓準位為-9V，則此時電晶體T4、T5、T6的閘-源極壓差Vgs等於-3V。請參閱第3圖，電晶體的閘-源極壓差Vgs在-3V時，漏電流Id的值遠小於閘-源極壓差Vgs在0V的漏電流值。亦言之，節點Q的電壓因電晶體T4的漏電流減少而下降的量更小，所以電晶體T1、T2控制的驅動訊號端ST(n)和輸出端OUT(n)的輸出的波形可以正常運作。Please be careful, because the gate potential of the closed non-conducting transistors T4, T5, T6 is equal to V _L , which is exactly the lowest voltage level of the first clock signal CK, and the potential of the source is equal to the power supply voltage V _SS Therefore, at this time, the gate-source voltage difference Vgs of the transistors T4, T5, and T6 is lower than 0V. For example, if the low voltage level V _{L of the} clock signal CK is -12V, and the voltage level of the DC power supply voltage V _SS is -9V, then the gate-source voltage difference of the transistors T4, T5, and T6 is at this time. Vgs is equal to -3V. Referring to Fig. 3, when the gate-source voltage difference Vgs of the transistor is -3V, the value of the drain current Id is much smaller than the value of the drain-source voltage difference Vgs at 0V. In other words, the voltage of the node Q decreases by the decrease of the leakage current of the transistor T4, so the waveforms of the output of the driving signal terminal ST(n) and the output terminal OUT(n) controlled by the transistors T1 and T2 can be working normally.

在時段t1-t2期間，第一時脈訊號CK處於高電壓準位V_H ，使得第一驅動電路110在節點K輸出的電壓準位是高電壓準位V_H ，所以電晶體T4、T5、T6係開啟導通。同時，第二時脈訊號XCK與前一級移位暫存單元100(n-1)的驅動訊號端ST(n-1)的驅動訊號處於低電壓準位V_L ，此時節點P的電位處於低電壓準位V_L ，所以電晶體T8、T9、T10係關閉不導通。但是，節點Q的電位會因為浮動(floating)之故，且因電容效應而隨著第一時脈訊號CK的上昇由準位V₂ 跳升至準位V₁ 。當節點Q的電位跳升至準位V₁ 之後，電晶體T1和T2會被開啟導通第一時脈訊號CK，導致輸出端OUT(n)和驅動訊號端ST(n)輸出高電壓準位。During the period t1-t2, the first clock signal CK is at the high voltage level V _H , so that the voltage level output by the first driving circuit 110 at the node K is the high voltage level V _H , so the transistors T4, T5, The T6 system turns on. At the same time, the driving signal of the driving signal terminal ST(n-1) of the second clock signal XCK and the previous stage shift register unit 100(n-1) is at the low voltage level V _L , and the potential of the node P is at this time. The low voltage level V _L , so the transistors T8, T9, T10 are closed and non-conducting. However, the potential of the node Q may float due to the floating effect, and jumps from the level V ₂ to the level V ₁ as the first clock signal CK rises due to the capacitive effect. When the potential of the node Q jumped level V _1, transistors T1 and T2 are turned ON when the first clock signal CK, resulting in the output terminal OUT (n) and the drive signal terminal ST (n) outputs a high voltage level .

請法意關閉不導通的電晶體T8、T9、T10，由於其閘極的電位等於V_L ，其恰好就是第二時脈訊號XCK的最低電壓準位，而其源極的電位等於電源電壓V_SS 。所以此時電晶體T8、T9、T10的閘-源極壓差Vgs低於0V，舉例來說，時脈訊號CK、XCK的低電壓準位V_L 若是-12V，而直流電源電壓V_SS 的電壓準位為-9V，則此時電晶體T8、T9、T10的閘-源極壓差Vgs等於-3V。請參閱第3圖，電晶體的閘-源極壓差Vgs在-3V時，漏電流Id的值遠小於閘-源極壓差Vgs在0V的漏電流值亦言之，節點Q的電壓因電晶體T8的漏電流減少而下降的量更小，所以輸出的波形可以正常運作。Please turn off the non-conducting transistors T8, T9, T10. Since the potential of the gate is equal to V _L , it is exactly the lowest voltage level of the second clock signal XCK, and the potential of the source is equal to the power supply voltage V. _SS . Therefore, the gate-source voltage difference Vgs of the transistors T8, T9, and T10 is lower than 0V. For example, if the low voltage level V _{L of the} clock signals CK and XCK is -12V, and the DC power supply voltage V _SS When the voltage level is -9V, the gate-source voltage difference Vgs of the transistors T8, T9, and T10 is equal to -3V. Referring to Fig. 3, when the gate-source voltage difference Vgs of the transistor is -3V, the value of the drain current Id is much smaller than the value of the gate-source voltage difference Vgs at 0V, and the voltage of the node Q is The leakage current of the transistor T8 is reduced and the amount of decrease is smaller, so the output waveform can operate normally.

在時段t2-t3時，第一時脈訊號CK處於低電壓準位，第二時脈訊號XCK處於高電壓準位。來自前一級移位暫存單元100(n-1)的驅動訊號端ST(n-1)的驅動訊號亦處於低電壓準位，使得電晶體T3會關閉。在此同時，第一驅動電路110在節點K輸出的電壓準位是低電壓準位V_L ，所以電晶體T4、T5、T6係關閉。但第二驅動電路112在節點P的輸出則為高電壓準位V_H ，所以電晶體T9、T10分別開啟導通低電壓準位V_SS 至輸出端OUT(n)和驅動訊號端ST(n)。電晶體T8開啟將節點Q的電位下拉至V_SS 。本實施例之移位暫存器可應用於液晶顯示器之閘極驅動器。During the period t2-t3, the first clock signal CK is at a low voltage level, and the second clock signal XCK is at a high voltage level. The driving signal from the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1) is also at a low voltage level, so that the transistor T3 is turned off. At the same time, the voltage level output by the first driving circuit 110 at the node K is the low voltage level V _L , so the transistors T4, T5, and T6 are turned off. However, the output of the second driving circuit 112 at the node P is the high voltage level V _H , so the transistors T9 and T10 respectively turn on the low voltage level V _SS to the output terminal OUT(n) and the driving signal terminal ST(n). . Transistor T8 turns on to pull the potential of node Q down to V _SS . The shift register of this embodiment can be applied to a gate driver of a liquid crystal display.

請參閱第6圖，第6圖係本發明之移位暫存器之第二實施例之移位暫存單元200(n)之電路圖。每一移位暫存單元200(n)包含一提升電路(pull-up circuit)102、一第一時脈下拉模組(pull-down module)104以及一第二時脈下拉模組206。本實施例之移位暫存單元200(n)的提升電路102與第一時脈下拉模組104的電路結構與第4圖所示之移位暫存單元100(n)相同，而第二時脈下拉模組206的電晶體T8、T9、T10的電路結構與第4圖所示之移位暫存單元100(n)相同，故在此不另贅述其運作。第二驅動電路212包含第十四電晶體T14、第十五電晶體T15以及第十六電晶體T16。電晶體T14的汲極與閘極耦接至第二時脈訊號XCK，其源極耦接至第一節點(N)。電晶體T15的汲極耦接至第五節點N，其閘極與源極係耦接至第一時脈訊號CK。電晶體T16的汲極、閘極和源極分別耦接至第二時脈訊號XCK、第五節點N及第三節點P。第6圖所示之第二驅動電路212與第4圖所示之第二驅動電路112皆是耦接於電晶體T8之閘極，並用來於接收第二時脈訊號XCK時，開啟電晶體T8。在本實施例中，時脈訊號CK、XCK的低電壓準位V_L ，係小於直流電源電壓V_SS 的電壓準位。移位暫存單元200(n)的運作與移位暫存單元100(n)類似，其對應各節點的輸出電壓變化時序圖與第5圖一致。在此不另贅述。Please refer to FIG. 6. FIG. 6 is a circuit diagram of the shift register unit 200(n) of the second embodiment of the shift register of the present invention. Each shift register unit 200(n) includes a pull-up circuit 102, a first clock pull-down module 104, and a second clock pull-down module 206. The circuit structure of the boost circuit 102 and the first clock pull-down module 104 of the shift register unit 200(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the second The circuit configuration of the transistors T8, T9, and T10 of the clock pull-down module 206 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The second driving circuit 212 includes a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The drain and the gate of the transistor T14 are coupled to the second clock signal XCK, and the source thereof is coupled to the first node (N). The gate of the transistor T15 is coupled to the fifth node N, and the gate and the source are coupled to the first clock signal CK. The drain, the gate and the source of the transistor T16 are respectively coupled to the second clock signal XCK, the fifth node N and the third node P. The second driving circuit 212 shown in FIG. 6 and the second driving circuit 112 shown in FIG. 4 are all coupled to the gate of the transistor T8 and used to turn on the transistor when receiving the second clock signal XCK. T8. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 200(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

請參閱第7圖，第7圖係本發明之移位暫存器之第三實施例之移位暫存單元300(n)之電路圖。每一移位暫存單元300(n)包含一提升電路(pull-up circuit)102、一第一時脈下拉模組(pull-down module)304以及一第二時脈下拉模組306。本實施例之移位暫存單元300(n)的提升電路102與第4圖所示之移位暫存單元100(n)相同，第一時脈下拉電路304的電晶體T4-T7，和第二時脈下拉模組306的電晶體T8-T10的電路結構與第4圖所示之移位暫存單元100(n)相同，故在此不另贅述其運作。第一驅動電路310包含一第十一電晶體T11，其汲極、閘極及源極分別耦接至第一時脈訊號CK、第二直流電源電壓V_DD 以及第二節點K。第7圖所示之第一驅動電路310與第4圖所示之第一驅動電路110皆是耦接於電晶體T4之閘極，並用來於接收第一時脈訊號CK時，開啟電晶體T4。而第二驅動電路312包含一第十二電晶體T12，其汲極、閘極及源極分別耦接至第二時脈訊號XCK、第二電源電壓V_DD 以及第三節點P。第7圖所示之第二驅動電路312與第4圖所示之第二驅動電路112皆是耦接於電晶體T8之閘極，並用來於接收第二時脈訊號XCK時，開啟電晶體T8。在本實施例中，時脈訊號CK、XCK的低電壓準位V_L ，係小於直流電源電壓V_SS 的電壓準位。移位暫存單元300(n)的運作與移位暫存單元100(n)類似，其對應各節點的輸出電壓變化時序圖與第5圖一致。在此不另贅述。Please refer to FIG. 7. FIG. 7 is a circuit diagram of the shift register unit 300(n) of the third embodiment of the shift register of the present invention. Each shift register unit 300(n) includes a pull-up circuit 102, a first clock pull-down module 304, and a second clock pull-down module 306. The lifting circuit 102 of the shift register unit 300(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the transistors T4-T7 of the first clock pull-down circuit 304, and The circuit structure of the transistors T8-T10 of the second clock pull-down module 306 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The first driving circuit 310 includes an eleventh transistor T11, and the drain, the gate and the source are respectively coupled to the first clock signal CK, the second DC power voltage V _DD and the second node K. The first driving circuit 310 shown in FIG. 7 and the first driving circuit 110 shown in FIG. 4 are all coupled to the gate of the transistor T4, and are used to turn on the transistor when receiving the first clock signal CK. T4. The second driving circuit 312 includes a twelfth transistor T12, and the drain, the gate and the source are respectively coupled to the second clock signal XCK, the second power voltage V _DD and the third node P. The second driving circuit 312 shown in FIG. 7 and the second driving circuit 112 shown in FIG. 4 are all coupled to the gate of the transistor T8, and are used to turn on the transistor when receiving the second clock signal XCK. T8. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 300(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

請參閱第8圖，第8圖係本發明之移位暫存器之第四實施例之移位暫存單元400(n)之電路圖。每一移位暫存單元400(n)包含一提升電路(pull-up circuit)102、一第一時脈下拉模組(pull-down module)404以及一第二時脈下拉模組406。本實施例之移位暫存單元400(n)的提升電路102與第4圖所示之移位暫存單元100(n)相同，第一時脈下拉電路404的電晶體T4-T7和第二時脈下拉模組406的電晶體T8-T10的電路結構與第4圖所示之移位暫存單元100(n)相同，故在此不另贅述其運作。第一羅動電路410包含第十一電晶體T11，其汲極、閘極及源極分別耦接至第一時脈訊號CK、第二直流電源電壓V_DD 以及第二節點K。第8圖所示之第一驅動電路410與第4圖所示之第一驅動電路110皆是耦接於電晶體T4之閘極，並用來於接收第一時脈訊號CK時，開啟電晶體T4。本實施例的第二驅動電路412實質上是用來第二時脈訊號XCK的時脈產生器，使得電晶體T8的汲極和源極直接耦接至第二時脈訊號XCK，也就是說，電晶體T8的閘極耦接於節點P，而節點P直接耦接於第二時脈訊號XCK，而不再連接其它實體電路。電晶體 T8於接收第二時脈訊號XCK時會開啟導通。在本實施例中，時脈訊號CK、XCK的低電壓準位V_L ，係小於直流電源電壓V_SS 的電壓準位。移位暫存單元400(n)的運作與移位暫存單元100(n)類似，其對應各節點的輸出電壓變化時序圖與第5圖一致。在此不另贅述。Please refer to FIG. 8. FIG. 8 is a circuit diagram of the shift register unit 400(n) of the fourth embodiment of the shift register of the present invention. Each shift register unit 400(n) includes a pull-up circuit 102, a first clock pull-down module 404, and a second clock pull-down module 406. The boosting circuit 102 of the shift register unit 400(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the transistors T4-T7 and the first of the first clock pull-down circuit 404. The circuit structure of the transistors T8-T10 of the two-clock pull-down module 406 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The first oscillating circuit 410 includes an eleventh transistor T11, and the drain, the gate and the source are respectively coupled to the first clock signal CK, the second DC power voltage V _DD and the second node K. The first driving circuit 410 shown in FIG. 8 and the first driving circuit 110 shown in FIG. 4 are all coupled to the gate of the transistor T4, and are used to turn on the transistor when receiving the first clock signal CK. T4. The second driving circuit 412 of the embodiment is substantially a clock generator for the second clock signal XCK, so that the drain and the source of the transistor T8 are directly coupled to the second clock signal XCK, that is, The gate of the transistor T8 is coupled to the node P, and the node P is directly coupled to the second clock signal XCK, and is no longer connected to other physical circuits. The transistor T8 turns on when it receives the second clock signal XCK. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 400(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

相較於先前技術，本發明之移位暫存器在每一級移位暫存單元中，利用時脈訊號CK、XCK的低電壓準位V_L 係小於直流電源電壓V_SS 的電壓準位的特性，使得電晶體T4、T8在關閉的時候，閘-源極壓差Vgs低於0V。因為電晶體的閘-源極壓差Vgs在低於0V時，漏電流的值遠小於閘-源極壓差Vgs在0V的漏電流值。所以節點Q的電壓因電晶體T4、T8的漏電流變小而下降的量更小這麼一來，用來依據節點Q的電壓控制驅動訊號端ST(n)和輸出端OUT(n)的電晶體T1、T2的輸出波形可大幅改善。即使電晶體因製程差異而導致漏電流在閘-源極壓差Vgs在0V時略有差異，但是只要將閘-源極壓差Vgs降至-3V甚至更低，漏電流的降幅甚至可超過100倍，因此電晶體因製程差異而導致漏電流的差異與之相比，更顯得微不足道。Compared to the prior art, the present invention shift register in each stage in the shift register unit, utilizing the clock signal CK, XCK low voltage level V _L is less than the DC supply voltage line V _SS voltage level of the The characteristics are such that when the transistors T4 and T8 are turned off, the gate-source voltage difference Vgs is lower than 0V. Since the gate-source voltage difference Vgs of the transistor is below 0V, the value of the leakage current is much smaller than the value of the drain current of the gate-source voltage difference Vgs at 0V. Therefore, the voltage of the node Q is reduced by the leakage current of the transistors T4 and T8 being smaller, so as to control the power of the driving signal terminal ST(n) and the output terminal OUT(n) according to the voltage of the node Q. The output waveforms of the crystals T1 and T2 can be greatly improved. Even if the transistor has a slight difference in the gate-source voltage difference Vgs at 0V due to process variations, as long as the gate-source voltage difference Vgs is reduced to -3V or lower, the leakage current can even exceed 100 times, so the difference in leakage current caused by the difference in process of the transistor is even more insignificant.

雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與修改，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be variously modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧液晶顯示器10‧‧‧LCD display

12‧‧‧液晶顯示面板12‧‧‧LCD panel

14‧‧‧閘極驅動器14‧‧‧ Gate Driver

16‧‧‧源極驅動器16‧‧‧Source Driver

20‧‧‧像素單元20‧‧‧ pixel unit

22‧‧‧電晶體22‧‧‧Optoelectronics

100(n)‧‧‧移位暫存單元100(n)‧‧‧Shift register unit

200(n)‧‧‧移位暫存單元200(n)‧‧‧Shift register unit

300(n)‧‧‧移位暫存單元300(n)‧‧‧Shift register unit

400(n)‧‧‧移位暫存單元400(n)‧‧‧Shift register unit

T1-T17‧‧‧電晶體T1-T17‧‧‧O crystal

102‧‧‧提升電路102‧‧‧Upgrading circuit

104、204‧‧‧第一時脈下拉模組104, 204‧‧‧ first clock pull-down module

106‧‧‧第二時脈下拉模組106‧‧‧Second clock pull-down module

110、310‧‧‧第一驅動電路110, 310‧‧‧ first drive circuit

112、212‧‧‧第二驅動電路112, 212‧‧‧second drive circuit

410‧‧‧第一驅動電路410‧‧‧First drive circuit

312、412‧‧‧第二驅動電路312, 412‧‧‧ second drive circuit

CK‧‧‧第一時脈訊號CK‧‧‧ first clock signal

XCK‧‧‧第二時脈訊號XCK‧‧‧ second clock signal

P、Q、K‧‧‧節點P, Q, K‧‧‧ nodes

N、S‧‧‧節點N, S‧‧‧ nodes

OUT(n)‧‧‧輸出端OUT(n)‧‧‧ output

ST(n)、ST(n-1)‧‧‧驅動訊號端ST(n), ST(n-1)‧‧‧ drive signal end

C1、C2‧‧‧電容C1, C2‧‧‧ capacitor

第1圖係先前技術之液晶顯示器之功能方塊圖。Figure 1 is a functional block diagram of a prior art liquid crystal display.

第2圖係先前技術之移位暫存器之移位暫存單元的電路圖。Figure 2 is a circuit diagram of a shift register unit of a prior art shift register.

第3圖係電晶體的源-閘極電壓差與漏電流的關係圖。Figure 3 is a plot of source-gate voltage difference versus leakage current for a transistor.

第4圖係本發明之移位暫存器之第一實施例之移位暫存單元之電路圖。Figure 4 is a circuit diagram of a shift register unit of the first embodiment of the shift register of the present invention.

第5圖係第4圖之各訊號以及節點之時序圖。Figure 5 is a timing diagram of each signal and node of Figure 4.

第6圖係本發明之移位暫存器之第二實施例之移位暫存單元之電路圖。Figure 6 is a circuit diagram of a shift register unit of the second embodiment of the shift register of the present invention.

第7圖係本發明之移位暫存器之第三實施例之移位暫存單元之電路圖。Figure 7 is a circuit diagram of a shift register unit of the third embodiment of the shift register of the present invention.

第8圖係本發明之移位暫存器之第四實施例之移位暫存單元之電路圖。Figure 8 is a circuit diagram of a shift register unit of a fourth embodiment of the shift register of the present invention.

100(n)‧‧‧移位暫存單元100(n)‧‧‧Shift register unit

C1、C2‧‧‧電容C1, C2‧‧‧ capacitor

T1-T17‧‧‧電晶體T1-T17‧‧‧O crystal

102‧‧‧提升電路102‧‧‧Upgrading circuit

104‧‧‧第一時脈下拉模組104‧‧‧First clock pull-down module

106‧‧‧第二時脈下拉模組106‧‧‧Second clock pull-down module

110‧‧‧第一驅動電路110‧‧‧First drive circuit

112‧‧‧第二驅動電路112‧‧‧Second drive circuit

CK‧‧‧第一時脈訊號CK‧‧‧ first clock signal

XCK‧‧‧第二時脈訊號XCK‧‧‧ second clock signal

P、Q、K‧‧‧節點P, Q, K‧‧‧ nodes

N、S‧‧‧節點N, S‧‧‧ nodes

OUT(n)‧‧‧輸出端OUT(n)‧‧‧ output

ST(n)、ST(n-1)‧‧‧驅動訊號端ST(n), ST(n-1)‧‧‧ drive signal end

Claims

一種移位暫存器，其包含：複數個移位暫存單元，該複數個移位暫存單元係以串聯的方式耦接，每一移位暫存單元係用來依據一第一時脈訊號、一第二時脈訊號以及該每一移位暫存單元之前一個移位暫存單元之一驅動訊號脈衝輸出該每一移位暫存單元之輸出訊號脈衝，每一移位暫存單元包含：一提升模組(pull-up module)，用來依據該第一時脈訊號，提供該輸出訊號，其包含：一第一電晶體，其汲極、閘極和源極分別耦接於該第一時脈訊號、一第一節點以及一驅動訊號端；一第二電晶體，其汲極、閘極和源極分別耦接於該第一時脈訊號、該第一節點以及一輸出訊號端；一第三電晶體，其汲極和閘極耦接於前一級移位暫存單元之一驅動訊號端，其源極耦接於該第一節點；一第一時脈下拉模組(pull-down module)，用來於接收該第一時脈訊號，導通該第一時脈下拉模組，其包含：一第四電晶體，其汲極、閘極以及源極分別耦接至該提升電路之該第一節點、一第二節點及一輸出節點；一第五電晶體，其汲極、閘極和源極分別耦接至該輸出節點、該第二節點及一第一電源電壓；一第六電晶體，其汲極、閘極和源極分別耦接至該驅動訊號端、該第二節點以及該第一電源電壓；一第七電晶體，其汲極、閘極和源極分別耦接至該第二節點、該輸出節點及該第一電源電壓；以及一第一驅動電路，耦接於該第四電晶體之閘極，用來於接收該第一時脈訊號時，開啟該第四電晶體；一第二時脈下拉模組，用來於接收該第二時脈訊號，導通該第二時脈下拉模組，其包含：一第八電晶體，其汲極、閘極和源極分別耦接至該第一節點、一第三節點及前一級移位暫存單元之一驅動訊號端；一第九電晶體，其汲極、閘極和源極分別耦接至該輸出節點、該第二時脈訊號及該第一電源電壓；一第十電晶體，其汲極、閘極和源極分別耦接至給該驅動訊號端、該第二時脈訊號及該第一電源電壓；以及一第二驅動電路，耦接於該第八電晶體之閘極，用來於接收該第二時脈訊號時，開啟該第八電晶體，其中該第一時脈訊號或是該第二時脈訊號之最低電壓準位係低於該第一電源電壓之電壓準位，該第一時脈下拉模組與該第二時脈下拉模組係交互作動。 A shift register includes: a plurality of shift temporary storage units, wherein the plurality of shift temporary storage units are coupled in series, and each shift temporary storage unit is configured to use a first clock a signal, a second clock signal, and one of the shift register units of each of the shift register units drive a signal pulse to output an output signal pulse of each shift register unit, each shift register unit The method includes: a pull-up module, configured to provide the output signal according to the first clock signal, comprising: a first transistor, wherein the drain, the gate and the source are respectively coupled to The first clock signal, a first node, and a driving signal end; a second transistor having a drain, a gate and a source coupled to the first clock signal, the first node, and an output a third transistor having a drain and a gate coupled to a driving signal terminal of the previous stage shift register unit, the source of which is coupled to the first node; and a first clock pull-down module (pull-down module), configured to receive the first clock signal, and turn on the first clock pulldown The module includes: a fourth transistor having a drain, a gate, and a source coupled to the first node, a second node, and an output node of the boosting circuit; and a fifth transistor; The drain, the gate and the source are respectively coupled to the output node, the second node and a first power voltage; and a sixth transistor has a drain, a gate and a source coupled to the driving signal end respectively , a second node and the first power supply voltage; a seventh transistor having a drain, a gate and a source coupled to the second node, the output node and the first power supply voltage, respectively; and a first driving circuit a second transistor connected to the gate of the fourth transistor for receiving the first clock signal; a second clock pull-down module for receiving the second clock The signal, the second clock pull-down module is turned on, comprising: an eighth transistor, wherein the drain, the gate and the source are respectively coupled to the first node, the third node, and the previous stage shift register One of the cells drives a signal terminal; a ninth transistor having a drain, a gate and a source coupled to the output node, the second clock signal and the first power supply voltage, respectively; a tenth transistor; The drain, the gate and the source are respectively coupled to the driving signal terminal, the second clock signal and the first power voltage; and a second driving circuit coupled to the gate of the eighth transistor, When the second clock signal is received, the eighth transistor is turned on, wherein the first clock signal is The second is the lowest voltage level of the clock signal line is lower than the voltage level of the first power supply voltage, the first pull-down clock module is actuated when the second line module is interacting with the drop-down pulse.

如申請專利範圍第1項所述之移位暫存器，其中該第一驅動電路包含：一第十一電晶體，其汲極與閘極耦接至該第一時脈訊號，其源極耦接至一第四節點；一第十二電晶體，其汲極耦接至該第四節點，其閘極與源極皆耦接至一第二時脈訊號；一第十三電晶體，其汲極、閘極和源極分別耦接至該第一時脈訊號，該第四節點及該第二節點。 The shift register according to claim 1, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain and the gate are coupled to the first clock signal, and the source thereof Coupled to a fourth node; a twelfth transistor having a drain coupled to the fourth node, a gate and a source coupled to a second clock signal; a thirteenth transistor having a drain, a gate and a source The poles are respectively coupled to the first clock signal, the fourth node and the second node.

如申請專利範圍第2項所述之移位暫存器，其中該第二驅動電路包含：一第十四電晶體，其汲極與閘極耦接至該第二時脈訊號，其源極耦接至該第一節點；一第十五電晶體，其汲極耦接至該第五節點，閘極與源極係耦接至該第一時脈訊號；以及一第十六電晶體，其汲極、閘極和源極分別耦接至該第二時脈訊號、該第五節點及該第三節點。 The shift register according to claim 2, wherein the second driving circuit comprises: a fourteenth transistor, wherein the drain and the gate are coupled to the second clock signal, and the source thereof Coupling to the first node; a fifteenth transistor, the drain is coupled to the fifth node, the gate and the source are coupled to the first clock signal; and a sixteenth transistor, The drain, the gate and the source are respectively coupled to the second clock signal, the fifth node and the third node.

如申請專利範圍第3項所述之移位暫存器，其中該第二驅動電路另包含：一第十七電晶體，其汲極、閘極及源極分別耦接至該第三節點、前一級移位暫存單元之一驅動訊號端和該第一電源電壓。 The shift register according to claim 3, wherein the second driving circuit further comprises: a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the third node, One of the previous stage shift register units drives the signal terminal and the first power supply voltage.

如申請專利範圍第1項所述之移位暫存器，其中該第一驅動電路包含：一第十一電晶體，其汲極、閘極及源極分別耦接至該第一時脈訊號、一第二電源電壓以及該第二節點。 The shift register according to claim 1, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain, the gate and the source are respectively coupled to the first clock signal a second supply voltage and the second node.

如申請專利範圍第5項所述之移位暫存器，其中該第二驅動電路包含：一第十二電晶體，其汲極、閘極及源極分別耦接至該第二時脈訊號、該第二電源電壓以及該第三節點。 The shift register according to claim 5, wherein the second driving circuit comprises: a twelfth transistor, wherein the drain, the gate and the source are respectively coupled to the second clock signal The second power voltage and the third node.

如申請專利範圍第5項所述之移位暫存器，其中該第三節點耦接於該第二時脈訊號。 The shift register according to claim 5, wherein the third node is coupled to the first Two-clock signal.

如申請專利範圍第1項所述之移位暫存器，其中該第一時脈訊號與該第二時脈訊號之相位相差180度。 The shift register of claim 1, wherein the first clock signal and the second clock signal are 180 degrees out of phase.

如申請專利範圍第1項所述之移位暫存器，其係應用於一液晶顯示器。 The shift register as described in claim 1 is applied to a liquid crystal display.

一種移位暫存單元，其包含：一提升模組(pull-up module)，用來依據一第一時脈訊號，提供該輸出訊號，其包含：一第一電晶體，其汲極、閘極和源極分別耦接於該第一時脈訊號、一第一節點以及一驅動訊號端，一第二電晶體，其汲極、閘極和源極分別耦接於該第一時脈訊號、該第一節點以及一輸出訊號端；一第三電晶體，其汲極和閘極耦接於前一級移位暫存單元之一驅動訊號端，其源極耦接於該第一節點；一第一時脈下拉模組，用來於接收該第一時脈訊號，導通該第一時脈下拉模組，其包含：一第四電晶體，其汲極、閘極以及源極分別耦接至該提升電路之該第一節點、一第二節點及一輸出節點；一第五電晶體，其汲極、閘極和源極分別耦接至該輸出節點、該第二節點及一第一電源電壓；一第六電晶體，其汲極、閘極和源極分別耦接至該驅動訊號端、該第二節點以及該第一電源電壓；一第七電晶體，其汲極、閘極和源極分別耦接至該第二節點、該輸出節點及該第一電源電壓；以及一第一驅動電路，耦接於該第四電晶體之閘極，用來於接收該第一時脈訊號時，開啟該第四電晶體；一第二時脈下拉模組，用來於接收一第二時脈訊號，導通該第二時脈下拉模組，其包含：一第八電晶體，其汲極、閘極和源極分別耦接至該第一節點、一第三節點及前一級移位暫存單元之一驅動訊號端；一第九電晶體，其汲極、閘極和源極分別耦接至該輸出節點、該第二時脈訊號及該第一電源電壓；一第十電晶體，其汲極、閘極和源極分別耦接至給該驅動訊號端、該第二時脈訊號及該第一電源電壓；以及一第二驅動電路，耦接於該第八電晶體之閘極，用來於接收該第二時脈訊號時，開啟該第八電晶體，其中該第一時脈訊號或是該第二時脈訊號之最低電壓準位係低於該第一電源電壓之電壓準位，該第一時脈下拉模組與該第二時脈下拉模組係交互作動。 A shift register unit includes: a pull-up module for providing the output signal according to a first clock signal, comprising: a first transistor, a drain, a gate The pole and the source are respectively coupled to the first clock signal, a first node, and a driving signal terminal, and a second transistor has a drain, a gate and a source coupled to the first clock signal respectively a first transistor and an output signal terminal; a third transistor having a drain and a gate coupled to one of the driving signal terminals of the previous stage shift register unit, the source of which is coupled to the first node; a first clock pull-down module is configured to receive the first clock signal and turn on the first clock pull-down module, comprising: a fourth transistor, the drain, the gate and the source are respectively coupled Connected to the first node, a second node, and an output node of the boosting circuit; a fifth transistor having a drain, a gate, and a source coupled to the output node, the second node, and a first a power supply voltage; a sixth transistor, wherein the drain, the gate and the source are respectively coupled to the driving signal terminal, The second node and the first power voltage; a seventh transistor, the drain, the gate and the source are respectively coupled to the second node, the output node and the first power voltage; and a first driving circuit coupled to the fourth transistor a gate for opening the fourth transistor when receiving the first clock signal; a second clock pull-down module for receiving a second clock signal, turning on the second clock pull-down mode The group includes: an eighth transistor having a drain, a gate and a source coupled to the first node, a third node, and a driving signal terminal of the first stage shift register unit; a transistor, the drain, the gate and the source are respectively coupled to the output node, the second clock signal and the first power voltage; and a tenth transistor, the drain, the gate and the source are respectively coupled Connecting to the driving signal terminal, the second clock signal and the first power voltage; and a second driving circuit coupled to the gate of the eighth transistor for receiving the second clock signal Turning on the eighth transistor, wherein the first clock signal or the lowest voltage of the second clock signal Lower than the bit line voltage level of the first power supply voltage, the first pull-down clock module is actuated when the second line module is interacting with the drop-down pulse.

如申請專利範圍第10項所述之移位暫存單元，其中該第一驅動電路包含：一第十一電晶體，其汲極與閘極耦接至該第一時脈訊號，其源極耦接至一第四節點；一第十二電晶體，其汲極耦接至該第四節點，其閘極與源極皆耦接至一第二時脈訊號；一第十三電晶體，其汲極、閘極和源極分別耦接至該第一時脈訊號，該第四節點及該第二節點。 The shift register unit of claim 10, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain and the gate are coupled to the first clock signal, and the source thereof Coupled to a fourth node; a twelfth transistor having a drain coupled to the fourth node, a gate and a source coupled to a second clock signal; a thirteenth transistor having a drain, a gate and a source The poles are respectively coupled to the first clock signal, the fourth node and the second node.

如申請專利範圍第11項所述之移位暫存單元，其中該第二驅動電路包含：一第十四電晶體，其汲極與閘極耦接至該第二時脈訊號，其源極耦接至該第一節點；一第十五電晶體，其汲極耦接至該第五節點，閘極與源極係耦接至該第一時脈訊號；以及一第十六電晶體，其汲極、閘極和源極分別耦接至該第二時脈訊號、該第五節點及該第三節點。 The shift register unit of claim 11, wherein the second driving circuit comprises: a fourteenth transistor, wherein the drain and the gate are coupled to the second clock signal, and the source thereof Coupling to the first node; a fifteenth transistor, the drain is coupled to the fifth node, the gate and the source are coupled to the first clock signal; and a sixteenth transistor, The drain, the gate and the source are respectively coupled to the second clock signal, the fifth node and the third node.

如申請專利範圍第12項所述之移位暫存單元，其中該第二驅動電路另包含：一第十七電晶體，其汲極、閘極及源極分別耦接至該第三節點、前一級移位暫存單元之一驅動訊號端和該第二電源電壓。 The shift register unit of claim 12, wherein the second drive circuit further comprises: a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the third node, One of the previous stage shift register units drives the signal terminal and the second power supply voltage.

如申請專利範圍第10項所述之移位暫存單元，其中該第一驅動電路包含：一第十一電晶體，其汲極、閘極及源極分別耦接至該第一時脈訊號、一第二電源電壓以及該第二節點。 The shifting temporary storage unit of claim 10, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain, the gate and the source are respectively coupled to the first clock signal a second supply voltage and the second node.

如申請專利範圍第14項所述之移位暫存單元，其中該第二驅動電路包含：一第十二電晶體，其汲極、閘極及源極分別耦接至該第二時脈訊號、該第二電源電壓以及該第三節點。 The shift register unit of claim 14, wherein the second drive circuit package The circuit includes a twelfth transistor, and the drain, the gate and the source are respectively coupled to the second clock signal, the second power voltage, and the third node.

如申請專利範圍第14項所述之移位暫存單元，其中該第三節點耦接於該第二時脈訊號。 The shift register unit of claim 14, wherein the third node is coupled to the second clock signal.

如申請專利範圍第10項所述之移位暫存單元，其中該第一時脈訊號與該第二時脈訊號之相位相差180度。The shift register unit of claim 10, wherein the phase of the first clock signal and the second clock signal are different by 180 degrees.