TWI396273B - Light-emitting device package having a testing pad and testing method thereof - Google Patents
Light-emitting device package having a testing pad and testing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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Abstract
Description
本發明是有關於一種串聯發光二極體測試方法及測試基板。The invention relates to a series light emitting diode testing method and a test substrate.
隨著半導體技術的進步，發光二極體(light-emitting diode,LED)所能達到的功率越來越大，並且所發出的光強度越來越高。除此之外，發光二極體更具有省電、使用壽命長、環保、啟動快速、體積小...等優點。因此，發光二極體已被廣泛地應用於照明設備、交通號誌、顯示器、光學滑鼠...等產品，同時更有逐漸取代傳統螢光燈管的趨勢。With the advancement of semiconductor technology, the power that light-emitting diodes (LEDs) can achieve is getting larger and larger, and the intensity of light emitted is getting higher and higher. In addition, the light-emitting diode has the advantages of power saving, long service life, environmental protection, fast startup, small size, and the like. Therefore, the light-emitting diode has been widely used in lighting equipment, traffic signs, displays, optical mice, etc., and at the same time has gradually replaced the trend of traditional fluorescent tubes.
然而，在發光二極體逐漸取代其他照明元件，市場佔有率逐漸變大的同時，卻在品管的部份浮現了新的問題。請參考圖1，圖1為習知技術中測試多晶串聯電路時所使用之一測試基板10的示意圖。如圖1所示，習知測試方法是利用一測試基板10，測試基板10包含一陶瓷基板12、一用低溫共燒陶瓷技術(LTCC)製作的外框14及一玻璃基板(未顯示)。在陶瓷基板12的上表面，設置有複數個銲墊16a、16b、16c、16d、16e、16f、16g，以供容置發光二極體晶片18a、18b、18c、18d、18e、18f之用，各發光二極體晶片18a、18b、18c、18d、18e、18f之間透過打線而互相串聯。銲墊16的材料係為導電材料，且銲墊16a、16b、16c、16d、16e、16f、16g在製作時，形狀並非全然為四方形，而是將大多數做成以狹長部位連接的兩個四方形。However, while the LEDs are gradually replacing other lighting components, the market share has gradually increased, but new problems have emerged in the quality control. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a test substrate 10 used in testing a polycrystalline series circuit in the prior art. As shown in FIG. 1, the conventional test method utilizes a test substrate 10 comprising a ceramic substrate 12, an outer frame 14 made of low temperature co-fired ceramic technology (LTCC), and a glass substrate (not shown). On the upper surface of the ceramic substrate 12, a plurality of pads 16a, 16b, 16c, 16d, 16e, 16f, 16g are provided for accommodating the LED chips 18a, 18b, 18c, 18d, 18e, 18f. The light-emitting diode chips 18a, 18b, 18c, 18d, 18e, and 18f are connected in series to each other by wire bonding. The material of the pad 16 is a conductive material, and the pads 16a, 16b, 16c, 16d, 16e, 16f, 16g are not completely square in shape at the time of fabrication, but are mostly made of two connected by narrow portions. Four squares.
在串接發光二極體晶片18a、18b、18c、18d、18e、18f時，通常是將發光二極體晶片18a、18b、18c、18d、18e、18f的正極固定至銲墊16a、16b、16c、16d、16e、16f、16g，使正極的導電材料與銲墊16a、16b、16c、16d、16e、16f的材料互熔，再將負極打線連接至銲墊16b、16c、16d、16e、16f、16g。而負極的數量依照晶片的功率，並不限定為一個，圖中是以兩個為例。此時，由於發光二極體晶片18a的正極電連接至銲墊16a，發光二極體晶片18a的負極經由金線22a電連接至銲墊16b，銲墊16b又電連接至發光二極體晶片18b的正極，發光二極體晶片18b的負極再經由金線22b電連接至銲墊16c，便將發光二極體晶片18a、18b串聯在一起。同理，發光二極體晶片18c、18d、18e、18f也是經由銲墊16c、16d、16e、16f、16g及金線22c、22d、22e、22f而互相串聯在一起，最後形成一個由發光二極體晶片18a、18b、18c、18d、18e、18f串聯起來的多晶串聯電路30，圖2為利用圖1之配置方式之多晶串聯電路30的等效電路圖。When the LED chips 18a, 18b, 18c, 18d, 18e, and 18f are connected in series, the positive electrodes of the LED chips 18a, 18b, 18c, 18d, 18e, and 18f are usually fixed to the pads 16a and 16b, 16c, 16d, 16e, 16f, 16g, the conductive material of the positive electrode and the materials of the pads 16a, 16b, 16c, 16d, 16e, 16f are mutually fused, and the negative electrode is wire-bonded to the pads 16b, 16c, 16d, 16e, 16f, 16g. The number of the negative electrodes is not limited to one according to the power of the wafer, and two are exemplified in the figure. At this time, since the positive electrode of the light emitting diode chip 18a is electrically connected to the pad 16a, the negative electrode of the light emitting diode chip 18a is electrically connected to the pad 16b via the gold wire 22a, and the pad 16b is electrically connected to the light emitting diode chip. The positive electrode of 18b, the negative electrode of the light-emitting diode chip 18b is electrically connected to the pad 16c via the gold wire 22b, and the light-emitting diode chips 18a, 18b are connected in series. Similarly, the LED chips 18c, 18d, 18e, and 18f are also connected in series via the pads 16c, 16d, 16e, 16f, and 16g and the gold wires 22c, 22d, 22e, and 22f, and finally form a light-emitting diode. The polycrystalline series circuit 30 in which the polar body wafers 18a, 18b, 18c, 18d, 18e, and 18f are connected in series, and FIG. 2 is an equivalent circuit diagram of the polycrystalline series circuit 30 using the arrangement of FIG.
由於上述多晶串聯電路30中所有的發光二極體晶片18a、18b、18c、18d、18e、18f都已經串聯在一起，因此唯一的測試方法就是直接測量頭尾兩端，通常的作法是將整個多晶串聯電路30的正極(與銲墊16a等電位)以及負極(與銲墊16g等電位)拉至測試基板10的下表面(未顯示)，以方便測量。但如此一來，即使測量出來的數據沒有問題，也因為無法直接測試單顆晶片而不能確定個別晶片的實際狀況。對應用端的客戶而言，不僅沒有保障，也容易造成他們的品質問題。Since all of the LED arrays 18a, 18b, 18c, 18d, 18e, and 18f in the polycrystalline series circuit 30 are already connected in series, the only test method is to directly measure the ends of the head and the tail. The usual practice is to The positive electrode of the entire polycrystalline series circuit 30 (equipotential to the pad 16a) and the negative electrode (potential with the pad 16g) are pulled to the lower surface (not shown) of the test substrate 10 to facilitate measurement. However, even if the measured data is not problematic, the actual condition of the individual wafers cannot be determined because the single wafer cannot be directly tested. For the client of the application side, not only is there no guarantee, but it is also easy to cause their quality problems.
習知技術中亦有利用測試設備來做測試，然而，這樣的作法還是有其缺點及限制。因為，在實施這樣的測試時，必需先將設備的各針腳(Pin)分別與設於測試基板背面的各晶片之正、負電極相接觸，然後再將從設備延伸出的各電源線之一端的電源插頭依需要插至測試設備電源的正、負極，以供電至各針腳執行測試。當多顆晶片設置於一測試基板之內時，因為測試基板背面的晶片正、負電極面積相對較小，針腳與它們之間的固定及接觸相對困難，且遇有串聯狀況時，通常作法是仍供應頭尾兩晶片獨立電源，再利用中間晶片的電源線互相串接，利用各電源線的搭接以造成多顆晶片的等效串聯，不僅需準備兩個以上獨立電源，操作上也並不便利。Test equipment has also been used for testing in the prior art. However, such an approach has its drawbacks and limitations. Because, in carrying out such a test, it is necessary to first contact each pin (Pin) of the device with the positive and negative electrodes of each wafer disposed on the back surface of the test substrate, and then one end of each power line extending from the device. The power plug is inserted into the positive and negative poles of the test equipment power supply as needed to supply power to each pin to perform the test. When a plurality of wafers are disposed in a test substrate, since the positive and negative electrode areas of the wafer on the back surface of the test substrate are relatively small, the fixing and contact between the pins and the pins are relatively difficult, and in the case of a series connection, the usual practice is The two power supply lines of the head and the tail are still supplied, and the power lines of the intermediate chips are connected in series, and the overlapping of the power lines is used to cause the equivalent series connection of the plurality of chips, and not only two independent power sources are required to be prepared, but also the operation is also Not convenient.
因此，如何能發展出一種測試方法及搭配的測試裝置，不僅可以在多晶串聯電路中任意測試個別晶片，即時反映出問題來，在操作上又簡易快速，同時也不需要頻繁的切換開關及複雜的電路設計，便成了一個非常重要的課題。Therefore, how to develop a test method and a matching test device can not only test individual wafers in a polycrystalline series circuit, but also reflect the problem in an instant, and is simple and fast in operation, and does not require frequent switching switches and Complex circuit design has become a very important topic.
本發明提供一種測試方法，適於測試具有測試墊之發光二極體封裝，可任意測試多晶串聯電路中的個別晶片。The present invention provides a test method suitable for testing a light emitting diode package having a test pad, which can optionally test individual wafers in a polycrystalline series circuit.
本發明提供一種具有測試墊之發光二極體封裝，可快速測試多晶串聯電路中的個別晶片。The invention provides a light emitting diode package with a test pad for quickly testing individual wafers in a polycrystalline series circuit.
本發明之一實施例中提出一種具有測試墊之發光二極體封裝，其包含一第一基板、一外框以及一第二基板。外框設置於第一基板之一上表面，第二基板設置於外框之上，與第一基板以及外框形成一密閉空間，且外框以及第二基板暴露出部分之上表面。測試基板另包含一第一至第N銲墊、一第一至第N-1晶片以及一第一至第N測試墊。第一至第N銲墊設置於上表面且位於密閉空間之內，第一至第N-1晶片之至少一第一電極分別被固定至第一至第N-1銲墊，第一至第N-1晶片之至少一第二電極分別被打線連接至第二至第N銲墊，第一至第N測試墊設置於被暴露出來之上表面，且第一至第N測試墊分別電連接於第一至第N銲墊。One embodiment of the present invention provides a light emitting diode package having a test pad, including a first substrate, an outer frame, and a second substrate. The outer frame is disposed on an upper surface of the first substrate, and the second substrate is disposed on the outer frame to form a sealed space with the first substrate and the outer frame, and the outer frame and the second substrate expose a portion of the upper surface. The test substrate further includes a first to Nth pad, a first to N-1th wafer, and a first to Nth test pad. The first to Nth pads are disposed on the upper surface and are located in the sealed space, and the at least one first electrode of the first to N-1th wafers are respectively fixed to the first to N-1 pads, first to first At least one second electrode of the N-1 wafer is wire-bonded to the second to Nth pads, respectively, the first to Nth test pads are disposed on the exposed upper surface, and the first to Nth test pads are respectively electrically connected On the first to Nth pads.
在本發明之一實施例中，第一基板係包含一陶瓷基板或是一矽基板。In an embodiment of the invention, the first substrate comprises a ceramic substrate or a germanium substrate.
在本發明之一實施例中，外框係為一利用低溫共燒陶瓷技術(LTCC)製作的外框。In one embodiment of the invention, the outer frame is an outer frame made using low temperature co-fired ceramic technology (LTCC).
在本發明之一實施例中，晶片係為一發光二極體晶片。In one embodiment of the invention, the wafer is a light emitting diode wafer.
在本發明之一實施例中，第二基板係為一玻璃基板。In an embodiment of the invention, the second substrate is a glass substrate.
在本發明之一實施例中，第一電極係為正極，第二電極係為負極。In an embodiment of the invention, the first electrode is a positive electrode and the second electrode is a negative electrode.
在本發明之一實施例中，第一電極係為負極，該第二電極係為正極。In one embodiment of the invention, the first electrode is a negative electrode and the second electrode is a positive electrode.
本發明之又一實施例中提出一種具有測試墊之發光二極體封裝，其包含一基板以及一透鏡。透鏡設置於基板之上，與基板形成一密閉空間，且透鏡暴露出部分之基板。測試基板另包含一第一至第N銲墊、一第一至第N-1晶片以及一第一至第N測試墊。第一至第N銲墊設置於基板之上且位於密閉空間之內，第一至第N-1晶片之至少一第一電極分別被固定至第一至第N-1銲墊，第一至第N-1晶片之至少一第二電極分別被打線連接至第二至第N銲墊，第一至第N測試墊設置於被暴露出來之基板之上，且第一至第N測試墊分別電連接於第一至第N銲墊。In another embodiment of the present invention, a light emitting diode package having a test pad is provided, comprising a substrate and a lens. The lens is disposed on the substrate to form a sealed space with the substrate, and the lens exposes a portion of the substrate. The test substrate further includes a first to Nth pad, a first to N-1th wafer, and a first to Nth test pad. The first to Nth pads are disposed on the substrate and located in the sealed space, and the at least one first electrode of the first to N-1th wafers are respectively fixed to the first to N-1 pads, first to At least one second electrode of the N-1th wafer is wire-bonded to the second to Nth pads, respectively, and the first to Nth test pads are disposed on the exposed substrate, and the first to Nth test pads are respectively Electrically connected to the first to Nth pads.
在本發明之一實施例中，基板係包含一陶瓷基板或是一矽基板。In an embodiment of the invention, the substrate comprises a ceramic substrate or a germanium substrate.
在本發明之一實施例中，測試基板另包含一外框，設置於基板與透鏡之間。In an embodiment of the invention, the test substrate further includes an outer frame disposed between the substrate and the lens.
在本發明之一實施例中，外框係為一利用低溫共燒陶瓷技術(LTCC)製作的外框。In one embodiment of the invention, the outer frame is an outer frame fabricated using low temperature co-fired ceramic technology (LTCC).
在本發明之一實施例中，透鏡係包含一ㄇ形透鏡或是一碗形透鏡。In one embodiment of the invention, the lens system comprises a dome lens or a bowl lens.
在本發明之一實施例中，晶片係為一發光二極體晶片。In one embodiment of the invention, the wafer is a light emitting diode wafer.
在本發明之一實施例中，第一電極係為正極，第二電極係為負極。In an embodiment of the invention, the first electrode is a positive electrode and the second electrode is a negative electrode.
在本發明之一實施例中，第一電極係為負極，該第二電極係為正極。In one embodiment of the invention, the first electrode is a negative electrode and the second electrode is a positive electrode.
在本發明之又一實施例中提出一種測試方法，適於測試具有測試墊之發光二極體封裝，其包含提供一測試基板，測試基板包含有一第一基板、一外框以及一第二基板。外框設置於第一基板之一上表面，第二基板設置於外框之上，與第一基板以及外框形成一密閉空間，且外框以及第二基板暴露出部分之上表面。測試基板另包含一第一至第N銲墊、一第一至第N-1晶片以及一第一至第N測試墊。第一至第N銲墊設置於上表面且位於密閉空間之內，第一至第N-1晶片之至少一第一電極分別被固定至第一至第N-1銲墊，第一至第N-1晶片之至少一第二電極分別被打線連接至第二至第N銲墊，第一至第N測試墊設置於被暴露出來之上表面，且第一至第N測試墊分別電連接於第一至第N銲墊。測試多晶串聯電路之方法另包含提供一電源，以及利用二電連接至電源之測試探針分別電連接於第N-1測試墊及第N測試墊，以測量第N-1晶片之電性。In another embodiment of the present invention, a test method is provided, which is suitable for testing a light emitting diode package having a test pad, comprising: providing a test substrate, the test substrate comprising a first substrate, an outer frame and a second substrate . The outer frame is disposed on an upper surface of the first substrate, and the second substrate is disposed on the outer frame to form a sealed space with the first substrate and the outer frame, and the outer frame and the second substrate expose a portion of the upper surface. The test substrate further includes a first to Nth pad, a first to N-1th wafer, and a first to Nth test pad. The first to Nth pads are disposed on the upper surface and are located in the sealed space, and the at least one first electrode of the first to N-1th wafers are respectively fixed to the first to N-1 pads, first to first At least one second electrode of the N-1 wafer is wire-bonded to the second to Nth pads, respectively, the first to Nth test pads are disposed on the exposed upper surface, and the first to Nth test pads are respectively electrically connected On the first to Nth pads. The method for testing a polycrystalline series circuit further includes providing a power source and electrically connecting to the N-1 test pad and the Nth test pad by using two test leads electrically connected to the power source to measure the electrical property of the N-1th chip. .
在本發明之一實施例中，晶片係為一發光二極體晶片。In one embodiment of the invention, the wafer is a light emitting diode wafer.
在本發明之一實施例中，第一電極係為正極，第二電極係為負極。In an embodiment of the invention, the first electrode is a positive electrode and the second electrode is a negative electrode.
在本發明之一實施例中，第一電極係為負極，該第二電極係為正極。In one embodiment of the invention, the first electrode is a negative electrode and the second electrode is a positive electrode.
在本發明之又一實施例中提出一種測試方法，適於測試具有測試墊之發光二極體封裝，其包含提供一測試基板，測試基板含有一基板以及一透鏡。透鏡設置於基板之上，與基板形成一密閉空間，且透鏡暴露出部分之基板。測試基板另包含一第一至第N銲墊、一第一至第N-1晶片以及一第一至第N測試墊。第一至第N銲墊設置於基板之上且位於密閉空間之內，第一至第N-1晶片之至少一第一電極分別被固定至第一至第N-1銲墊，第一至第N-1晶片之至少一第二電極分別被打線連接至第二至第N銲墊，第一至第N測試墊設置於被暴露出來之基板之上，且第一至第N測試墊分別電連接於第一至第N銲墊。測試多晶串聯電路之方法另包含提供一電源，以及利用二電連接至電源之測試探針分別電連接於第N-1測試墊及第N測試墊，以測量第N-1晶片之電性。In yet another embodiment of the present invention, a test method is provided for testing a light emitting diode package having a test pad, comprising providing a test substrate comprising a substrate and a lens. The lens is disposed on the substrate to form a sealed space with the substrate, and the lens exposes a portion of the substrate. The test substrate further includes a first to Nth pad, a first to N-1th wafer, and a first to Nth test pad. The first to Nth pads are disposed on the substrate and located in the sealed space, and the at least one first electrode of the first to N-1th wafers are respectively fixed to the first to N-1 pads, first to At least one second electrode of the N-1th wafer is wire-bonded to the second to Nth pads, respectively, and the first to Nth test pads are disposed on the exposed substrate, and the first to Nth test pads are respectively Electrically connected to the first to Nth pads. The method for testing a polycrystalline series circuit further includes providing a power source and electrically connecting to the N-1 test pad and the Nth test pad by using two test leads electrically connected to the power source to measure the electrical property of the N-1th chip. .
在本發明之一實施例中，晶片係為一發光二極體晶片。In one embodiment of the invention, the wafer is a light emitting diode wafer.
在本發明之一實施例中，第一電極係為正極，第二電極係為負極。In an embodiment of the invention, the first electrode is a positive electrode and the second electrode is a negative electrode.
在本發明之一實施例中，第一電極係為負極，該第二電極係為正極。In one embodiment of the invention, the first electrode is a negative electrode and the second electrode is a positive electrode.
在本發明之測試方法中，不必在元件尺寸日益縮小的情況下，還要勉強設計設備的各針腳，使其與測試基板背面的各個晶片的正、負電極能妥善接觸。同時因為不必要進行電源線的相互搭接才能造成多顆晶片的等效串聯，只需要準備單個獨立電源，操作上方便省時，又不必擔心因為搭接所產生的不預期短路情形。此外，本發明方法可以在多晶串聯電路中任意測試個別晶片，即時反映出個別問題，並且也不需要頻繁的切換開關及複雜的電路設計。In the test method of the present invention, it is not necessary to design the pins of the device to be properly contacted with the positive and negative electrodes of the respective wafers on the back surface of the test substrate without the ever-shrinking component size. At the same time, because it is not necessary to make the interconnection of the power lines to cause the equivalent series connection of multiple wafers, only a single independent power source needs to be prepared, which is convenient and time-saving in operation, and there is no need to worry about the unexpected short circuit caused by the overlap. In addition, the method of the present invention can arbitrarily test individual wafers in a polycrystalline series circuit, reflecting individual problems in real time, and also does not require frequent switching switches and complicated circuit designs.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
請參考圖3，圖3為本發明之一實施例中一測試基板100的上視圖。如圖3所示，測試基板100包含一陶瓷基板102、一用低溫共燒陶瓷技術(LTCC)製作的外框104及一玻璃基板(未顯示)。在陶瓷基板102的上表面103，設置有複數個銲墊106a、106b、106c、106d、106e，以供容置發光二極體晶片108a、108b、108c、108d之用，在陶瓷基板102的上表面103，另設置有複數個測試墊112a、112b、112c、112d、112e，以供點測之用，而各發光二極體晶片108a、108b、108c、108d之間係透過打線而互相串聯。Please refer to FIG. 3. FIG. 3 is a top view of a test substrate 100 according to an embodiment of the present invention. As shown in FIG. 3, the test substrate 100 includes a ceramic substrate 102, an outer frame 104 made of low temperature co-fired ceramic technology (LTCC), and a glass substrate (not shown). On the upper surface 103 of the ceramic substrate 102, a plurality of pads 106a, 106b, 106c, 106d, 106e are provided for accommodating the LED chips 108a, 108b, 108c, and 108d on the ceramic substrate 102. The surface 103 is further provided with a plurality of test pads 112a, 112b, 112c, 112d, 112e for spotting, and each of the LED chips 108a, 108b, 108c, and 108d is connected in series with each other through a wire.
銲墊106a、106b、106c、106d、106e的材料係為導電材料，且銲墊106a、106b、106c、106d、106e在製作時，形狀並非全然為四方形，而是將大多數做成以狹長部位連接的兩個四方形。測試墊112a、112b、112c、112d、112e係分別電連接至銲墊106a、106b、106c、106d、106e，所以相對應之兩者應具有相同的電位。事實上，銲墊106a、106b、106c、106d、106e及測試墊112a、112b、112c、112d、112e可為相同的材料，並以相同的製程所形成，例如：利用鋼板塗佈後再燒結，或是鍍金屬材之後再蝕刻，而鍍的種類可以包含電鍍、無電鍍、濺鍍、化學氣相沉積、物理氣相沉積等。The material of the pads 106a, 106b, 106c, 106d, 106e is a conductive material, and the pads 106a, 106b, 106c, 106d, 106e are not completely square in shape at the time of fabrication, but are made mostly in a narrow shape. Two squares connected to the part. The test pads 112a, 112b, 112c, 112d, 112e are electrically connected to the pads 106a, 106b, 106c, 106d, 106e, respectively, so that the corresponding two should have the same potential. In fact, the pads 106a, 106b, 106c, 106d, 106e and the test pads 112a, 112b, 112c, 112d, 112e may be of the same material and formed by the same process, for example, after coating with a steel plate and then sintering, It can be etched after metal plating, and the type of plating can include electroplating, electroless plating, sputtering, chemical vapor deposition, physical vapor deposition, and the like.
在串聯發光二極體晶片108a、108b、108c、108d時，通常是將發光二極體晶片108a、108b、108c、108d的正極固定至銲墊106a、106b、106c、106d，再將負極打線電連接至銲墊106b、106c、106d、106e。而負極的數量依照晶片的功率，並不限定為一個，圖3中是以兩個為例。此時，由於發光二極體晶片108a的正極電連接至銲墊106a，發光二極體晶片108a的負極經由金線114a電連接至銲墊106b，銲墊106b又電連接至發光二極體晶片108b的正極，發光二極體晶片108b的負極再經由金線114b電連接至銲墊106c，便將發光二極體晶片108a、108b串聯在一起。同理，發光二極體晶片108c、108d也是經由銲墊106c、106d、106e及金線114c、114d而互相串聯在一起，最後形成一個由發光二極體晶片108a、108b、108c、108d串聯起來的多晶串聯電路130，圖4為利用圖3之配置方式之多晶串聯電路130的等效電路圖。但是與習知技術不同的是，由於測試墊112a、112b、112c、112d、112e係分別電連接至銲墊106a、106b、106c、106d、106e，所以測試墊112a係與發光二極體晶片108a之正極等電位，在等效電路圖上是以節點A來表示；測試墊112b係與發光二極體晶片108a之負極及發光二極體晶片108b之正極等電位，在等效電路圖上是以節點B來表示；測試墊112c係與發光二極體晶片108b之負極及發光二極體晶片108c之正極等電位，在等效電路圖上是以節點C來表示；測試墊112d係與發光二極體晶片108c之負極與發光二極體晶片108d之正極等電位，在等效電路圖上是以節點D來表示；測試墊112e係與發光二極體晶片108d之負極等電位，在等效電路圖上是以節點E來表示。請參考圖5，圖5為圖3之測試基板100的背面示意圖。整個多晶串聯電路130的正極(與節點A等電位)被拉至測試基板100之一下表面132的正電極134，負極(與節點B等電位)被拉至下表面132的負電極136，下表面132上另設置有一導熱層138，用以將發光二極體晶片108a、108b、108c、108d所發出的熱導出。When the LED chips 108a, 108b, 108c, and 108d are connected in series, the positive electrodes of the LED chips 108a, 108b, 108c, and 108d are usually fixed to the pads 106a, 106b, 106c, and 106d, and the negative electrode is electrically connected. Connected to pads 106b, 106c, 106d, 106e. The number of the negative electrodes is not limited to one according to the power of the wafer, and two of them are exemplified in FIG. At this time, since the positive electrode of the light-emitting diode wafer 108a is electrically connected to the pad 106a, the negative electrode of the light-emitting diode wafer 108a is electrically connected to the pad 106b via the gold wire 114a, and the pad 106b is electrically connected to the light-emitting diode chip. The positive electrode of 108b, the negative electrode of the light-emitting diode wafer 108b is electrically connected to the pad 106c via the gold wire 114b, and the light-emitting diode wafers 108a, 108b are connected in series. Similarly, the LED chips 108c, 108d are also connected in series via the pads 106c, 106d, 106e and the gold wires 114c, 114d, and finally a series of LEDs 108a, 108b, 108c, 108d are connected in series. The polycrystalline series circuit 130, FIG. 4 is an equivalent circuit diagram of the polycrystalline series circuit 130 using the arrangement of FIG. However, unlike the prior art, since the test pads 112a, 112b, 112c, 112d, 112e are electrically connected to the pads 106a, 106b, 106c, 106d, 106e, respectively, the test pad 112a is connected to the LED wafer 108a. The positive potential of the positive electrode is represented by a node A on the equivalent circuit diagram; the test pad 112b is equipotential to the positive electrode of the light-emitting diode wafer 108a and the positive electrode of the light-emitting diode wafer 108b, and is a node on the equivalent circuit diagram. B is shown; the test pad 112c is equipotential to the anode of the LED wafer 108b and the anode of the LED wafer 108c, and is represented by a node C on the equivalent circuit diagram; the test pad 112d is connected to the LED The negative electrode of the wafer 108c and the positive electrode of the light-emitting diode wafer 108d are equipotential, and are represented by a node D on the equivalent circuit diagram; the test pad 112e is equipotential to the negative electrode of the light-emitting diode wafer 108d, and is equivalent to the equivalent circuit diagram. It is represented by node E. Please refer to FIG. 5. FIG. 5 is a schematic rear view of the test substrate 100 of FIG. The positive electrode of the entire polycrystalline series circuit 130 (equipotential to node A) is pulled to the positive electrode 134 of the lower surface 132 of one of the test substrates 100, and the negative electrode (equipotential to the node B) is pulled to the negative electrode 136 of the lower surface 132, under A heat conducting layer 138 is further disposed on the surface 132 for discharging heat emitted by the LED chips 108a, 108b, 108c, and 108d.
是以，當測試時，只要將探針142點在測試墊112a、112b之上，就可以直接測試發光二極體晶片108a的電氣特性。同理，若要測試發光二極體晶片108b，就只要將將探針142點在測試墊112b、112c之上；若要測試發光二極體晶片108c，就只要將探針142點在測試墊112c、112d之上；若要測試發光二極體晶片108d，就只要將探針142點在測試墊112d、112e之上。而此處的電氣特性，除了正向電壓(VF )、正向電流之外(IF )，尚包含逆向電壓(VR )、逆向電流(IR )，完全視加在各測試墊112a、112b、112c、112d、112e上的電壓極性而定。當然，如果想要測試整個多晶串聯電路130的電氣特性，也可以直接將探針142點在測試墊112a、112e，或是將探針142點在下表面132的正電極134與負電極136，所得到的結果也會與習知測試方式相同。Therefore, when testing, the electrical characteristics of the LED wafer 108a can be directly tested by simply spotting the probe 142 over the test pads 112a, 112b. Similarly, if the LED array 108b is to be tested, the probe 142 will be placed on the test pads 112b, 112c; to test the LED wafer 108c, the probe 142 is placed on the test pad. Above 112c, 112d; to test the LED array 108d, the probe 142 is placed over the test pads 112d, 112e. The electrical characteristics here, in addition to the forward voltage (V F ) and the forward current (I F ), also include the reverse voltage (V R ) and the reverse current (I R ), which are added to each test pad 112a. The polarity of the voltage on 112b, 112c, 112d, 112e depends on the polarity. Of course, if it is desired to test the electrical characteristics of the entire polycrystalline series circuit 130, the probe 142 may be directly spotted on the test pads 112a, 112e, or the probe 142 may be spotted on the positive electrode 134 and the negative electrode 136 of the lower surface 132, The results obtained will also be the same as in the conventional test.
請參考圖6，圖6為圖3之測試基板100沿6-6’剖線的剖面示意圖。如圖6所示，陶瓷基板102位於最下方，用低溫共燒陶瓷技術製作的外框104設置於陶瓷基板102之上，而玻璃基板144覆蓋於外框104之上，以將發光二極體晶片(未顯示)封閉在密閉的空間內，進而保護其不受環境因素的傷害。請一併參考圖3，外框104並非圍繞整個陶瓷基板102的周邊，玻璃基板144的覆蓋範圍也未超過外框104，使陶瓷基板102上表面103的部份邊緣被暴露出來。而被暴露出來的部分，正好用以設置有複數個測試墊112a、112b、112c、112d、112e，以方便點測之用。Please refer to FIG. 6. FIG. 6 is a cross-sectional view of the test substrate 100 of FIG. 3 taken along line 6-6'. As shown in FIG. 6, the ceramic substrate 102 is located at the bottom, and the outer frame 104 made by the low-temperature co-fired ceramic technology is disposed on the ceramic substrate 102, and the glass substrate 144 is overlaid on the outer frame 104 to expose the light-emitting diode. The wafer (not shown) is enclosed in a confined space to protect it from environmental factors. Referring to FIG. 3 together, the outer frame 104 does not surround the entire periphery of the ceramic substrate 102. The coverage of the glass substrate 144 does not exceed the outer frame 104, so that a part of the edge of the upper surface 103 of the ceramic substrate 102 is exposed. The exposed portion is just used to set a plurality of test pads 112a, 112b, 112c, 112d, 112e for convenient spotting.
本發明方法是利用元件上的佈局方式，來達到簡便測試的目的。換言之，只要測試基板100的佈局完成，並依照佈局來製作出測試基板100，就可以隨時測試個別晶片或是整串晶片。與傳統方法中，需要精密設計測試針腳以與測試基板背面各晶片之正、負電極相容相較，可說是簡單很多。同時，本發明方法不需要利用測試設備端的電線搭接，或是特別的電路設計就能運作，與習知技術的概念完全不同。不僅可以免除繁複的電路設計，也不需要在測試過程中重複操作切換開關。另外，本發明測試方法是直接點測於靠近晶片正、負極的節點，可以很直接及真實地反映出個別晶片電性不良的情形，進而快速鎖定可能造成不良的缺陷種類，以期迅速解決品質問題。並且本發明方法無需考慮因做換線、搭接等動作，所產生的不預期之短路問題，而當短路發生時，無疑地將造成測試結果的不正確，進而影響產線的運作。The method of the invention utilizes the layout on the component to achieve the purpose of simple testing. In other words, as long as the layout of the test substrate 100 is completed and the test substrate 100 is fabricated in accordance with the layout, the individual wafers or the entire wafer can be tested at any time. Compared with the conventional method, it is much simpler to design the test pins to be compatible with the positive and negative electrodes of the wafers on the back side of the test substrate. At the same time, the method of the present invention does not require the use of wire laps at the test equipment end, or a special circuit design to operate, which is completely different from the concept of the prior art. Not only can the complicated circuit design be eliminated, but also the switch must be repeatedly operated during the test. In addition, the test method of the present invention directly measures the nodes near the positive and negative electrodes of the wafer, and can directly and truly reflect the poor electrical condition of the individual wafers, thereby quickly locking the types of defects that may cause defects, so as to quickly solve the quality problem. . Moreover, the method of the present invention does not need to consider the unexpected short circuit problem caused by the action of changing lines, laps, etc., and when the short circuit occurs, the test result is undoubtedly caused to be incorrect, thereby affecting the operation of the production line.
然而，上述所揭露之實施例並非唯一的實施方式，事實上，任何設計，只要能讓發光二極體晶片108a、108b、108c、108d被容置在銲墊106a、106b、106c、106d、106e上，並順利打線串聯，之後再利用陶瓷基板102上表面103所暴露出來的邊緣部份，將圖4中A、B、C、D、E節點的電位拉到測試墊112a、112b、112c、112d、112e上，都在本發明的範圍之內。銲墊106a、106b、106c、106d、106e的形狀、排列秩序及排列方式可以有各種變化，測試墊112a、112b、112c、112d、112e的形狀、排列秩序及排列方式也可以有各種變化，只要在佈局及製程上做得到的，都可以達到本發明的目的。此外，本發明方法並不限於將發光二極體晶片108a、108b、108c、108d的正極固定至銲墊106a、106b、106c、106d，再將負極打線電連接至銲墊106b、106c、106d、106e，製作上亦有可能是將負極固定至銲墊，再將正極打線連接至銲墊以形成等效串聯，同理，於此情形中正極的數量依照晶片的功率，並不限定為一個。除此之外，陶瓷基板102亦可被其他材質之基板置換，例如矽基板。However, the embodiments disclosed above are not the only embodiments. In fact, any design is provided so that the LED wafers 108a, 108b, 108c, 108d can be accommodated in the pads 106a, 106b, 106c, 106d, 106e. Up, and smoothly connect the wires in series, and then use the edge portions exposed by the upper surface 103 of the ceramic substrate 102 to pull the potentials of the A, B, C, D, and E nodes in FIG. 4 to the test pads 112a, 112b, 112c, Both 112d and 112e are within the scope of the present invention. The shape, arrangement order and arrangement of the pads 106a, 106b, 106c, 106d, 106e can be variously changed. The shape, arrangement order and arrangement of the test pads 112a, 112b, 112c, 112d, 112e can also be variously changed, as long as The objects of the present invention can be achieved by making the layout and the process. In addition, the method of the present invention is not limited to fixing the positive electrodes of the LED wafers 108a, 108b, 108c, and 108d to the pads 106a, 106b, 106c, and 106d, and electrically connecting the negative electrodes to the pads 106b, 106c, and 106d, 106e, it is also possible to fix the negative electrode to the bonding pad and then connect the positive electrode wire to the bonding pad to form an equivalent series. Similarly, the number of positive electrodes in this case is not limited to one according to the power of the wafer. In addition, the ceramic substrate 102 may be replaced by a substrate of another material, such as a germanium substrate.
請參考圖7，圖7為本發明另一實施例中一測試基板200的剖面示意圖。如圖7所示，測試基板200係包含有一基板202以及一透鏡206，透鏡206係設置於基板202之一上表面203，且透鏡206與基板202形成一密閉空間，以將發光二極體晶片(未顯示)封閉在密閉的空間內，進而保護其不受環境因素的傷害。基板202係包含有一陶瓷基板或是一矽基板，於圖7中透鏡206係為一ㄇ型透鏡，但事實上，透鏡206可能為各種形狀。請參考圖8，圖8為本發明再一實施例中一測試基板300的剖面示意圖。如圖8所示，測試基板300係包含有一基板302、一外框304以及一透鏡306，外框304係設置於基板302之一上表面303，透鏡306係設置於外框304之上，並藉此與基板302形成一密閉空間，以將發光二極體晶片(未顯示)封閉在密閉的空間內，進而保護其不受環境因素的傷害。基板302係包含有一陶瓷基板或是一矽基板，於圖8中透鏡306係為一碗型透鏡，但事實上，透鏡306可能為各種形狀。Please refer to FIG. 7. FIG. 7 is a cross-sectional view of a test substrate 200 according to another embodiment of the present invention. As shown in FIG. 7, the test substrate 200 includes a substrate 202 and a lens 206. The lens 206 is disposed on an upper surface 203 of the substrate 202, and the lens 206 forms a sealed space with the substrate 202 to expose the LED. (not shown) enclosed in a confined space to protect it from environmental factors. The substrate 202 comprises a ceramic substrate or a substrate. In Figure 7, the lens 206 is a 透镜-type lens, but in fact, the lens 206 may be of various shapes. Please refer to FIG. 8. FIG. 8 is a cross-sectional view of a test substrate 300 according to still another embodiment of the present invention. As shown in FIG. 8 , the test substrate 300 includes a substrate 302 , an outer frame 304 , and a lens 306 . The outer frame 304 is disposed on an upper surface 303 of the substrate 302 , and the lens 306 is disposed on the outer frame 304 . Thereby, a sealed space is formed with the substrate 302 to enclose the light-emitting diode wafer (not shown) in a sealed space, thereby protecting it from environmental factors. The substrate 302 comprises a ceramic substrate or a substrate. In Figure 8, the lens 306 is a bowl lens, but in fact, the lens 306 may be of various shapes.
綜上所述，在本發明之實施例之測試方法及測試基板中，不必在元件尺寸日益縮小的情況下，還要勉強設計設備的各針腳，使其與測試基板背面的各個晶片的正、負電極妥善接觸。同時因為不必要進行電源線的相互搭接才能造成多顆晶片的等效串聯，只需要準備單個獨立電源，操作上方便省時，又不必擔心因為搭接所產生的不預期短路情形。此外，本發明方法可以在多晶串聯電路中任意測試個別晶片，即時反映出個別問題，並且也不需要頻繁的切換開關及複雜的電路設計。In summary, in the test method and the test substrate of the embodiment of the present invention, it is not necessary to design the pins of the device to be positive with the respective wafers on the back surface of the test substrate, in the case where the component size is increasingly reduced. The negative electrode is in proper contact. At the same time, because it is not necessary to make the interconnection of the power lines to cause the equivalent series connection of multiple wafers, only a single independent power source needs to be prepared, which is convenient and time-saving in operation, and there is no need to worry about the unexpected short circuit caused by the overlap. In addition, the method of the present invention can arbitrarily test individual wafers in a polycrystalline series circuit, reflecting individual problems in real time, and also does not require frequent switching switches and complicated circuit designs.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10、100、200、300．．．測試基板10, 100, 200, 300. . . Test substrate
12、102、202、302．．．陶瓷基板12, 102, 202, 302. . . Ceramic substrate
103、203、303．．．上表面103, 203, 303. . . Upper surface
14、104、304．．．外框14, 104, 304. . . Outer frame
16a、16b、16c、16d、16e、16f、16g、106a、106b、106c、106d、106e．．．銲墊16a, 16b, 16c, 16d, 16e, 16f, 16g, 106a, 106b, 106c, 106d, 106e. . . Solder pad
18a、18b、18c、18d、18e、18f、108a、108b、108c、108d．．．發光二極體晶片18a, 18b, 18c, 18d, 18e, 18f, 108a, 108b, 108c, 108d. . . Light-emitting diode chip
22a、22b、22c、22d、22e、22f、114a、114b、114c、114d．．．金線22a, 22b, 22c, 22d, 22e, 22f, 114a, 114b, 114c, 114d. . . Gold Line
30、130．．．多晶串聯電路30, 130. . . Polycrystalline series circuit
112a、112b、112c、112d．．．測試墊112a, 112b, 112c, 112d. . . Test pad
132．．．下表面132. . . lower surface
134．．．正電極134. . . Positive electrode
136．．．負電極136. . . Negative electrode
138．．．導熱層138. . . Thermal layer
142．．．探針142. . . Probe
144．．．玻璃基板144. . . glass substrate
206、306．．．透鏡206, 306. . . lens
圖1為習知技術中測試多晶串聯電路時所使用之一測試基板的示意圖。FIG. 1 is a schematic diagram of a test substrate used in testing a polycrystalline series circuit in the prior art.
圖2為利用圖1之配置方式之多晶串聯電路的等效電路圖。2 is an equivalent circuit diagram of a polycrystalline series circuit using the configuration of FIG. 1.
圖3為本發明之一實施例中一測試基板的上視圖。3 is a top plan view of a test substrate in accordance with an embodiment of the present invention.
圖4為利用圖3之配置方式之多晶串聯電路的等效電路圖。4 is an equivalent circuit diagram of a polycrystalline series circuit using the arrangement of FIG.
圖5為圖3之測試基板的背面示意圖。FIG. 5 is a schematic rear view of the test substrate of FIG. 3. FIG.
圖6為圖3之測試基板沿6-6’剖線的剖面示意圖。Figure 6 is a cross-sectional view of the test substrate of Figure 3 taken along line 6-6'.
圖7為本發明另一實施例中一測試基板的剖面示意圖。FIG. 7 is a cross-sectional view showing a test substrate according to another embodiment of the present invention.
圖8為本發明再一實施例中一測試基板的剖面示意圖。FIG. 8 is a cross-sectional view showing a test substrate according to still another embodiment of the present invention.
100．．．測試基板100. . . Test substrate
102．．．陶瓷基板102. . . Ceramic substrate
103．．．上表面103. . . Upper surface
104．．．外框104. . . Outer frame
106a、106b、106c、106d、106e．．．銲墊106a, 106b, 106c, 106d, 106e. . . Solder pad
108a、108b、108c、108d．．．發光二極體晶片108a, 108b, 108c, 108d. . . Light-emitting diode chip
112a、112b、112c、112d．．．測試墊112a, 112b, 112c, 112d. . . Test pad
114a、114b、114c、114d．．．金線114a, 114b, 114c, 114d. . . Gold Line
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