TWI393350B - I/o buffer - Google Patents

I/o buffer Download PDF

Info

Publication number
TWI393350B
TWI393350B TW98128812A TW98128812A TWI393350B TW I393350 B TWI393350 B TW I393350B TW 98128812 A TW98128812 A TW 98128812A TW 98128812 A TW98128812 A TW 98128812A TW I393350 B TWI393350 B TW I393350B
Authority
TW
Taiwan
Prior art keywords
voltage
gate
gate voltage
wafer
module
Prior art date
Application number
TW98128812A
Other languages
Chinese (zh)
Other versions
TW201108614A (en
Inventor
Chua Chin Wang
Ron Chi Kuo
Jen Wei Liu
Original Assignee
Univ Nat Sun Yat Sen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Sun Yat Sen filed Critical Univ Nat Sun Yat Sen
Priority to TW98128812A priority Critical patent/TWI393350B/en
Publication of TW201108614A publication Critical patent/TW201108614A/en
Application granted granted Critical
Publication of TWI393350B publication Critical patent/TWI393350B/en

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Description

輸出入緩衝器電路裝置Output buffer circuit device

本發明是有關於一種電路裝置，特別是指一種輸出入緩衝器電路裝置。The present invention relates to a circuit arrangement, and more particularly to an output-in buffer circuit arrangement.

在隨著製程技術不斷的演進，為了降低功率損耗，IC之電源供應電壓(VDD)也越來越低。當在系統中使用不同製程及不同供應電壓的晶片時，若使用傳統輸出入單元(input/output cell，I/O cell)，當作晶片與晶片之間的界面來傳輸訊號，會產生閘極氧化層可靠度(gate-oxide reliability)與漏電流(leakage current)等許多的問題。所以為了滿足不同電壓界面的使用，需使用混和電壓共容輸出入單元(mixed-voltage-tolerant I/O cell)。As process technology continues to evolve, the power supply voltage (VDD) of ICs is getting lower and lower in order to reduce power loss. When using different processes and different supply voltages in the system, if a traditional input/output cell (I/O cell) is used as the interface between the chip and the chip to transmit signals, a gate will be generated. There are many problems such as gate-oxide reliability and leakage current. Therefore, in order to meet the use of different voltage interfaces, a mixed-voltage-tolerant I/O cell is required.

先前技術中，混合電壓共容輸出入單元均無法傳送較高或較低電壓準位訊號(如本國專利第1230507號，或是美國專利第6333663號與第5828231號)。若使用堆疊式N型電晶體(stacked NMOS)技巧或N型電晶體阻隔技術(NMOS-blocking)，雖然能解決混合電壓共容輸出入單元接收到2×VDD高壓訊號時元件可靠度的問題，但卻只能提供電壓準位為VDD的輸出訊號，而無法提供高電壓2×VDD的輸出訊號，甚至低電壓0.5×VDD的輸出訊號，所以無法達到真正的全雙向。而N型電晶體阻隔技術雖能接收3×VDD之訊號，但仍無法傳送大範圍的訊號輸出。In the prior art, the mixed voltage common-capacity input and output unit cannot transmit higher or lower voltage level signals (such as national patent No. 1230507, or US Patent No. 6333663 and No. 5582231). If a stacked N-type transistor (stacked NMOS) technique or an N-type transistor blocking technique (NMOS-blocking) is used, although the problem of component reliability when the mixed voltage common-capacitance input/output unit receives the 2×VDD high-voltage signal can be solved, However, it can only provide an output signal with a voltage level of VDD, and cannot provide a high-voltage 2×VDD output signal or even a low-voltage 0.5×VDD output signal, so that true full bidirectional cannot be achieved. While the N-type transistor blocking technology can receive the signal of 3×VDD, it still cannot transmit a wide range of signal output.

因此，本發明之目的，即在提供一種可解決閘極氧化層過壓問題及漏電流路徑，並能接收與傳送三倍之外部電壓訊號之輸出入緩衝器電路裝置。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an output-in and buffer circuit device which can solve the overvoltage problem of the gate oxide layer and the leakage current path and can receive and transmit three times the external voltage signal.

於是，本發明之輸出入緩衝器電路裝置，是與一外部電壓、至少一個晶片焊接點，及一個核心電路電連接，以分別在一傳輸模式及一接收模式下傳送及接收複數個不同電壓準位之數位訊號，該輸出入緩衝器電路裝置包含：一預先驅動單元、一電壓偵測單元、一動態閘極偏壓產生單元、一輸出級單元、一輸入級單元，及一第一浮動N型井單元。Therefore, the input/output buffer circuit device of the present invention is electrically connected to an external voltage, at least one wafer soldering point, and a core circuit for transmitting and receiving a plurality of different voltage levels in a transmission mode and a reception mode, respectively. The bit-input signal device includes: a pre-drive unit, a voltage detecting unit, a dynamic gate bias generating unit, an output stage unit, an input stage unit, and a first floating N Well unit.

該預先驅動單元是接收該核心電路所產生的電壓訊號，並產生一第一控制訊號。該電壓偵測單元是與該晶片焊接點電連接，以偵測存在於該晶片焊接點上的電壓，並產生一對應之直流偏壓；該動態閘極偏壓產生單元具有：一外部電壓偵測模組，用以判斷該外部電壓目前之電壓值，並產生一對應之判斷訊號；一第一閘極電壓產生模組，是與該預先驅動單元及該外部電壓偵測模組電連接，並接收該第一控制訊號及該判斷訊號，並轉換為適當的第一閘極電壓；一第二閘極電壓產生模組，用以接收該第一閘極電壓，並將其轉換為一第二閘極電壓後輸出；一第三閘極電壓產生模組，用以接收該第二閘極電壓與該直流偏壓，並根據該判斷訊號及該核心電路的控制，以產生相對應的第三閘極電壓，其中，該第三閘極電壓產生模組在接收模式下是使該第二閘極電 壓及該第三閘極電壓相互隔絕，同時使該第三閘極電壓追隨存在於該晶片焊接點上的電壓，而在傳輸模式下是使該第三閘極電壓追隨該第二閘極電壓；及一第四閘極電壓產生模組，是根據該判斷訊號的值來產生一第四閘極電壓。The pre-drive unit receives the voltage signal generated by the core circuit and generates a first control signal. The voltage detecting unit is electrically connected to the solder joint of the wafer to detect a voltage existing on the solder joint of the wafer and generate a corresponding DC bias; the dynamic gate bias generating unit has: an external voltage detect The measurement module is configured to determine a current voltage value of the external voltage and generate a corresponding determination signal; a first gate voltage generation module is electrically connected to the pre-drive unit and the external voltage detection module, And receiving the first control signal and the determination signal, and converting to an appropriate first gate voltage; a second gate voltage generating module for receiving the first gate voltage and converting it into a first a second gate voltage output module; a third gate voltage generating module for receiving the second gate voltage and the DC bias voltage, and according to the determination signal and the control of the core circuit, to generate a corresponding a three-gate voltage, wherein the third gate voltage generating module is configured to make the second gate electrically The voltage and the third gate voltage are isolated from each other while causing the third gate voltage to follow the voltage present at the solder joint of the wafer, and in the transmission mode, the third gate voltage follows the second gate voltage And a fourth gate voltage generating module for generating a fourth gate voltage according to the value of the determining signal.

該輸出級單元是與該外部電壓電連接，並於傳輸模式下接收該第一、第二、第三、第四閘極電壓，且將其轉換為適合於該晶片焊接點之電壓準位的數位訊號，並輸出至該晶片焊接點。The output stage unit is electrically connected to the external voltage, and receives the first, second, third, and fourth gate voltages in a transmission mode, and converts the voltage into a voltage level suitable for the solder joint of the wafer. A digital signal is output to the wafer solder joint.

該輸入級單元是與該晶片焊接點電連接，並於接收模式下用以接收自該晶片焊接點之不同電壓準位之訊號，並將其轉換成適合於該核心電路之邏輯數位訊號後輸至該核心電路。The input stage unit is electrically connected to the solder joint of the wafer, and receives signals of different voltage levels from the solder joint of the wafer in a receiving mode, and converts the signal into a logic digital signal suitable for the core circuit. To the core circuit.

該第一浮動N型井單元是用以提供輸出級單元與前述晶片焊接點偵測電路適當的電壓準位。The first floating N-well unit is configured to provide an appropriate voltage level of the output stage unit and the aforementioned wafer solder joint detecting circuit.

本發明之功效在於，利用該第三閘極電壓產生模組用以接收該第二閘極電壓與該直流偏壓，並根據該判斷訊號及該核心電路的控制，以產生相對應的第三閘極電壓，並在接收模式下驅使該第二閘極電壓及第三閘極電壓相互隔絕，同時使該第三閘極電壓追隨存在於該晶片焊接點上的電壓，進而可在不產生閘極氧化層過壓及漏電流路徑的情況下接收與傳送三倍之外部電壓之訊號。The third gate voltage generating module is configured to receive the second gate voltage and the DC bias voltage, and generate a corresponding third according to the determining signal and the control of the core circuit. a gate voltage, and in the receiving mode, driving the second gate voltage and the third gate voltage to be isolated from each other, and simultaneously causing the third gate voltage to follow a voltage existing on the solder joint of the wafer, thereby preventing the gate from being generated A signal that receives and transmits three times the external voltage in the case of a pole oxide overvoltage and leakage current path.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一個較佳實施例的詳細說明中，將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

參閱圖1，本發明之輸出入緩衝器電路裝置之較佳實施例，是與一外部電壓VDDIO、至少一個晶片焊接點200，及一個核心電路100電連接，以分別在一傳輸模式及一接收模式下傳送及接收複數個不同電壓準位之數位訊號，該輸出入緩衝器電路裝置包含：一預先驅動單元1、一電壓偵測單元2、一動態閘極偏壓產生單元3、一輸出級單元4、一輸入級單元5，及一第一浮動N型井單元6。Referring to FIG. 1, a preferred embodiment of the input-output buffer circuit device of the present invention is electrically coupled to an external voltage VDDIO, at least one wafer bonding pad 200, and a core circuit 100 for receiving in a transmission mode and a receiving circuit, respectively. And transmitting and receiving a plurality of digital signals of different voltage levels, wherein the output buffer circuit device comprises: a pre-drive unit 1, a voltage detecting unit 2, a dynamic gate bias generating unit 3, and an output stage The unit 4, an input stage unit 5, and a first floating N-type well unit 6.

為了作大範圍之不同電壓介面的應用，該輸出級單元4所使用之外部電壓VDDIO，是使得本發明之輸出入緩衝器可傳送與接收5/3.3/2.5/1.8/1.2/0.9V等不同電壓準位的電壓值，而該核心電路100之電位供應電壓VDD則為1.8V。For a wide range of different voltage interface applications, the external voltage VDDIO used by the output stage unit 4 is such that the output-in buffer of the present invention can be transmitted and received differently than 5/3.3/2.5/1.8/1.2/0.9V. The voltage value of the voltage level, and the potential supply voltage VDD of the core circuit 100 is 1.8V.

該預先驅動單元(Pre-driver circuit)1是與該核心電路100電連接，並接收核心電路100所產生的電壓訊號OE、第三控制訊號Dout，以設定該輸出入緩衝電路的一操作模式，使得輸出入緩衝電路操作在傳送模式或接收模式。The pre-driver circuit 1 is electrically connected to the core circuit 100, and receives the voltage signal OE and the third control signal Dout generated by the core circuit 100 to set an operation mode of the output buffer circuit. The output buffer circuit is operated in a transmission mode or a reception mode.

該電壓偵測單元2是與該晶片焊接點200電連接，以偵測存在於該晶片焊接點200上的電壓，並產生對應之直流偏壓。The voltage detecting unit 2 is electrically connected to the wafer bonding pad 200 to detect a voltage present on the wafer bonding pad 200 and generate a corresponding DC bias voltage.

參閱圖2，該動態閘極偏壓產生單元3具有一外部電壓偵測模組31、一低功率偏壓模組36、一第一閘極電壓產生模組32、一第二閘極電壓產生模組33、一第三閘極電壓產生模組34，及一第四閘極電壓產生模組35。Referring to FIG. 2, the dynamic gate bias generating unit 3 has an external voltage detecting module 31, a low power bias module 36, a first gate voltage generating module 32, and a second gate voltage generating unit. The module 33, a third gate voltage generating module 34, and a fourth gate voltage generating module 35.

配合參閱圖3，該外部電壓偵測模組31是用以判斷該外部電壓VDDIO目前之電壓值，並產生一對應之判斷訊號，在本實施例中，該外部電壓偵測模組31包括一P型電晶體串接偏壓模組311、與該P型電晶體串接偏壓模組311電連接的四個溫度計碼產生器TR0~TR3(Thermometer code generator)，及一與該四溫度計碼產生器電連接的溫度計碼與單擊碼轉換器312(Thermometer code to one-hot code transformer)。其中，該P型電晶體串接偏壓模組311係以11個二極體接法的PMOS電晶體串聯當作一直流偏壓電路，使其門檻電壓總和大於該外部電壓VDDIO的操作電壓，而降低靜態功率消耗。Referring to FIG. 3, the external voltage detecting module 31 is configured to determine the current voltage value of the external voltage VDDIO, and generate a corresponding determination signal. In this embodiment, the external voltage detecting module 31 includes a a P-type transistor serial connection bias module 311, four thermometer code generators TR0~TR3 (Thermometer code generator) electrically connected to the P-type transistor serial connection bias module 311, and one and the four thermometer codes The thermometer code is connected to the code converter 312 (Thermometer code to one-hot code transformer). The P-type transistor serial connection bias module 311 is a series of PMOS transistors connected by 11 diodes as a DC bias circuit, so that the sum of the threshold voltages is greater than the operating voltage of the external voltage VDDIO. And reduce static power consumption.

當該外部電壓VDDIO由高電壓模式轉換為低電壓模式時，其輸出電壓VX1~VX11也會逐次下降，而其所輸出之電壓VX4、VX5、VX7、VX8、VX10分別輸出至該四溫度計碼產生器TR0~TR3，而溫度計碼產生器TR0、TR1所輸入的電壓VX4、VX5在該外部電壓VDDIO操作在高電壓模式時，會出現大於1.8V的電壓，因此必須在輸入的PMOS電晶體閘極加上一NMOS保護電路，以避免高電壓造成PMOS的閘極氧化層過壓。反之，溫度計碼產生器TR3、TR4則不需要NMOS保護電路。藉此，利用PMOS和NMOS不會被同時導通而產生直流漏電路徑，可以有效地降低靜態功率消耗，比直接使用一反相器來偵測上述之VX系列電壓來得省電。因此，溫度計碼產生器TR0~TR3可依照不同之該外部電壓VDDIO的操作模式下產生相對應的溫度計碼VD0~VD3。When the external voltage VDDIO is switched from the high voltage mode to the low voltage mode, the output voltages VX1 V VX11 are also sequentially decreased, and the output voltages VX4, VX5, VX7, VX8, and VX10 are respectively output to the four thermometer codes. TR0~TR3, and the voltages VX4 and VX5 input by the thermometer code generators TR0 and TR1 will generate a voltage greater than 1.8V when the external voltage VDDIO is operated in the high voltage mode, so the PMOS transistor gate must be input. An NMOS protection circuit is added to avoid high voltages causing overvoltage of the PMOS gate oxide layer. Conversely, the thermometer code generators TR3, TR4 do not require an NMOS protection circuit. Thereby, the PMOS and the NMOS are not simultaneously turned on to generate a DC leakage path, which can effectively reduce the static power consumption, and save power by directly using an inverter to detect the VX series voltage. Therefore, the thermometer code generators TR0~TR3 can generate corresponding thermometer codes VD0~VD3 according to different operation modes of the external voltage VDDIO.

在此要注意的是，在本實施例中，該外部電壓偵測模組31利用該P型電晶體串接偏壓模組311所產生的偏壓來偵測目前使用的外部電壓，並產生VD50、VD33、VD25、VD18等四個控制電壓，以作為該判斷訊號，其中VD50為邏輯1時，表示外部電壓VDDIO=5.0V。VD33為邏輯1時，表示外部電壓VDDIO=3.3V。VD25為邏輯1時，表示外部電壓VDDIO=2.5V。VD18為邏輯1時，表示外部電壓。It should be noted that, in this embodiment, the external voltage detecting module 31 uses the bias voltage generated by the P-type transistor serial connection bias module 311 to detect the external voltage currently used, and generates Four control voltages, such as VD50, VD33, VD25, and VD18, are used as the determination signal. When VD50 is logic 1, it indicates that the external voltage VDDIO=5.0V. When VD33 is logic 1, it indicates that the external voltage VDDIO = 3.3V. When VD25 is logic 1, it indicates that the external voltage VDDIO = 2.5V. When VD18 is logic 1, it indicates external voltage .

回顧圖1、2，並配合參閱圖4，該第一閘極電壓產生模組32是與該預先驅動單元1及該外部電壓偵測模組31電連接，並接收該第一控制訊號UP及該判斷訊號，並轉換為適當的第一閘極電壓Vg1。Referring to FIG. 1 and FIG. 2, and referring to FIG. 4, the first gate voltage generating module 32 is electrically connected to the pre-driving unit 1 and the external voltage detecting module 31, and receives the first control signal UP and The determination signal is converted to an appropriate first gate voltage Vg1.

在本實施例中，該第一閘極電壓產生模組32係以由一個電壓準位轉換器(Voltage level converter)所構成，以輸出反相之該第一閘極電壓Vg1及訊號QB。基本的電壓準位轉換電路是由二顆交叉耦合(Cross-coupled)的PMOS電晶體分別串接二顆用來放電的NMOS電晶體所組成，其中該等NMOS電晶體的閘極控制電壓為反相的訊號。圖4中編號為MN101~MN106以及MP103~MP106的電晶體為同一組的放電電晶體，主要操作在該外部電壓VDDIO為5.0V時，由訊號UP50和其反相訊號所控制。當該外部電壓VDDIO為5.0V時，由於VD50為1.8V，而VD33、VD25、VD18為0V，因此UP50和其反相訊號即受該第一控制訊號UP而控制，其餘控制訊號UPL、UP18及其反相訊號皆為0V。而此時V33為3.3V，因此當該第一控制訊號UP為1.8V時，UP50為1.8V，訊號QB通過編號為MP103、MN101、MP105、MN103、MN105的電晶體而放電，直到約3.3V，而該第一閘極電壓Vg1則經由編號為MP102的電晶體拉到與該外部電壓VDDIO等同的電位(5.0V)。其中編號為MN101~MN104、MP105和MP106的電晶體是為了防止其它的電晶體受到5.0V的高電壓破壞，產生閘極氧化層過壓的問題，其中V43為4.3V。In this embodiment, the first gate voltage generating module 32 is configured by a voltage level converter to output the inverted first gate voltage Vg1 and the signal QB. The basic voltage level conversion circuit is composed of two cross-coupled PMOS transistors respectively connected in series with two NMOS transistors for discharging, wherein the gate control voltage of the NMOS transistors is reversed. Phase signal. The transistors numbered MN101~MN106 and MP103~MP106 in Fig. 4 are the same group of discharge transistors, and the main operation is controlled by the signal UP50 and its inverted signal when the external voltage VDDIO is 5.0V. When the external voltage VDDIO is 5.0V, since the VD50 is 1.8V, and the VD33, VD25, and VD18 are 0V, the UP50 and its inverted signal are controlled by the first control signal UP, and the remaining control signals UPL, UP18 and The inverted signals are all 0V. At this time, V33 is 3.3V, so when the first control signal UP is 1.8V, the UP50 is 1.8V, and the signal QB is discharged by the transistors numbered MP103, MN101, MP105, MN103, MN105 until about 3.3V. The first gate voltage Vg1 is pulled to a potential (5.0 V) equivalent to the external voltage VDDIO via the transistor numbered MP102. The transistors numbered MN101~MN104, MP105 and MP106 are used to prevent other transistors from being damaged by the high voltage of 5.0V, which causes the overvoltage of the gate oxide layer, wherein V43 is 4.3V.

編號為MN107~MN110、MP107和MP108的電晶體為第二組放電的電晶體，操作在該外部電壓VDDIO為3.3V和2.5V時，由訊號UPL和其反相訊號所控制。當外部電壓VDDIO為3.3V時，因為VD33為1.8V，若此時該第一控制訊號UP為1.8V，則訊號UPL亦為1.8V，因此訊號QB經由編號為MN107、MP107、MN109的電晶體放電。因為此時電壓V11為1.1V，訊號QB會被放電到約1.5V(1.1V+|Vtp|)的電壓。而該第一閘極電壓Vg1則由編號為PM102的電晶體充電到3.3V。同樣地，當該外部電壓VDDIO為2.5V時，VD25為1.8V，因此圖7中的NMOS電晶體即會被導通，進而將V10接地，使得V11電壓為0.39V。因此該第一閘極電壓Vg1和訊號QB隨著該第一控制訊號UP的變化，形成在0.7V(=0.39V+|Vtp|)和2.5V之間變動的電壓。其中編號為MN107和MN108之電晶體的閘極接到V33，V33在該外部電壓VDDIO為5.0V時偏壓在3.3V，因此編號為MN107和MN108的電晶體可用來保護其它的電晶體，以免產生閘極氧化層過壓的問題。The transistors numbered MN107~MN110, MP107 and MP108 are the second group of discharged transistors. The operation is controlled by the signal UPL and its inverted signal when the external voltage VDDIO is 3.3V and 2.5V. When the external voltage VDDIO is 3.3V, since VD33 is 1.8V, if the first control signal UP is 1.8V at this time, the signal UPL is also 1.8V, so the signal QB passes through the transistors numbered MN107, MP107, MN109. Discharge. Since the voltage V11 is 1.1V at this time, the signal QB is discharged to a voltage of about 1.5V (1.1V+|Vtp|). The first gate voltage Vg1 is charged to 3.3V by the transistor numbered PM102. Similarly, when the external voltage VDDIO is 2.5V, VD25 is 1.8V, so the NMOS transistor in FIG. 7 is turned on, and V10 is grounded so that the V11 voltage is 0.39V. Therefore, the first gate voltage Vg1 and the signal QB form a voltage varying between 0.7V (=0.39V+|Vtp|) and 2.5V as the first control signal UP changes. The gates of the transistors numbered MN107 and MN108 are connected to V33, and V33 is biased at 3.3V when the external voltage VDDIO is 5.0V, so the transistors numbered MN107 and MN108 can be used to protect other transistors. The problem of overvoltage of the gate oxide layer is generated.

編號為MN111~MN116的電晶體為第三組放電用的電晶體，其主要操作在外部電壓VDDIO為1.8/1.2/0.9V時，此時VD18為1.8V，因此UP18會隨著該第一控制訊號UP而變化。由於整個放電路徑上沒有任何PMOS電晶體，因此該第一閘極電壓Vg1和訊號QB會是在0V和1.8/1.2/0.9V之間變化的訊號。同樣地，編號為MN111~MN114的電晶體是作為避免電晶體之閘極氧化層產生過壓的保護電晶體。The transistors numbered MN111~MN116 are the third group of transistors for discharge. The main operation is when the external voltage VDDIO is 1.8/1.2/0.9V. At this time, VD18 is 1.8V, so UP18 will follow the first control. The signal changes and changes. Since there is no PMOS transistor on the entire discharge path, the first gate voltage Vg1 and the signal QB will be signals varying between 0V and 1.8/1.2/0.9V. Similarly, the transistors numbered MN111~MN114 act as protective transistors that avoid overvoltages in the gate oxide layer of the transistor.

回顧圖1，並配合參閱圖5，該第二閘極電壓產生模組33是用以接收該第一閘極電壓Vg1，並將其轉換為一第二閘極電壓Vg2後輸出。在本實施例中，係以編號為MN201、MN201、MP201~MP203的電晶體所組成的開關，以產生所需要的電壓。當在傳輸模式下且該外部電壓VDDIO大於1.8V時，該第一閘極電壓Vg1會在該外部電壓VDDIO和該外部電壓VDDIO減去VDD(VDDIO-VDD)的電壓之間變化，當該第一閘極電壓Vg1等於該外部電壓VDDIO時，是為了關閉電晶體Po1(見圖1)，而當該第一閘極電壓Vg1等於VDDIO-VDD，是為了導通電晶體Po1同時保護電晶體Po1不造成閘極氧化層過壓。此時使用編號為MN201之電晶體的NMOS箝制技術由該第一閘極電壓Vg1來產生Vg2。當該第一閘極電壓Vg1等於該外部電壓VDDIO且大於VDD時，編號為MN201的電晶體可以使通過的電壓為VX2(4.12 V)-Vtn，略大於VDDIO-VDD的電壓值。若外部電壓VDDIO等於5.0 V，訊號OE50為1.8 V，因此VX2-Vtn≒VDDIO-VDD=3.2 V可以經由編號為MP201的電晶體傳到該第二閘極電壓Vg2，且此時訊號OE50為1.8 V，編號為MP201的電晶體不會產生任何過壓的問題。若外部電壓VDDIO為3.3 V或2.5 V，則VX2-Vtn=VDDIO-VDD=1.5 V或0.7 V，此時訊號OE18為1.8V且訊號OE50等於0 V，因此VX2-Vtn可經由編號為MN202和MP201的電晶體傳到該第二閘極電壓Vg2。同時，VX2>VX2-Vtn，因此編號為MP202和MP203的電晶體不會導通。Referring to FIG. 1 and referring to FIG. 5, the second gate voltage generating module 33 is configured to receive the first gate voltage Vg1 and convert it into a second gate voltage Vg2 for output. In the present embodiment, switches composed of transistors numbered MN201, MN201, MP201~MP203 are used to generate the required voltage. When in the transmission mode and the external voltage VDDIO is greater than 1.8V, the first gate voltage Vg1 varies between the external voltage VDDIO and the external voltage VDDIO minus the voltage of VDD (VDDIO-VDD), when the first When the gate voltage Vg1 is equal to the external voltage VDDIO, it is for turning off the transistor Po1 (see FIG. 1), and when the first gate voltage Vg1 is equal to VDDIO-VDD, it is for guiding the transistor Po1 while protecting the transistor Po1. Causes overvoltage of the gate oxide layer. At this time, the NMOS clamping technique using the transistor numbered MN201 generates Vg2 from the first gate voltage Vg1. When the first gate voltage Vg1 is equal to the external voltage VDDIO and greater than VDD, the transistor numbered MN201 can pass the voltage to VX2 (4.12 V) - Vtn, which is slightly larger than the voltage value of VDDIO-VDD. If the external voltage VDDIO is equal to 5.0 V and the signal OE50 is 1.8 V, VX2-Vtn ≒ VDDIO-VDD=3.2 V can be transmitted to the second gate voltage Vg2 via the transistor numbered MP201, and the signal OE50 is 1.8. V, the transistor numbered MP201 does not cause any overvoltage problems. If the external voltage VDDIO is 3.3 V or 2.5 V, then VX2-Vtn=VDDIO-VDD=1.5 V or 0.7 V. At this time, the signal OE18 is 1.8V and the signal OE50 is equal to 0 V, so VX2-Vtn can be numbered MN202 and The transistor of the MP201 is passed to the second gate voltage Vg2. At the same time, VX2>VX2-Vtn, so the transistors numbered MP202 and MP203 will not turn on.

當在接收模式且該外部電壓VDDIO1.8 V時，VX2-Vtn會小於1.8 V，此時VD18的反相訊號為0 V，因此訊號OE18為0 V。且訊號OE50為1.8 V，編號為MN202和MP201的電晶體則關閉使得VX2-Vtn無法通過。同時因為VX2<1.8 V，所以1.8 V會通過編號為MP202和MP203的電晶體而輸出到該第二閘極電壓Vg2。When in receive mode and the external voltage VDDIO At 1.8 V, VX2-Vtn will be less than 1.8 V. At this time, the inverted signal of VD18 is 0 V, so the signal OE18 is 0 V. And the signal OE50 is 1.8 V, and the transistors numbered MN202 and MP201 are turned off so that VX2-Vtn cannot pass. At the same time, since VX2 < 1.8 V, 1.8 V is output to the second gate voltage Vg2 through the transistors numbered MP202 and MP203.

另外要注意的是，該第二閘極電壓產生模組33更具有一第三浮動N型井電路331，可以比較1.8 V和該第二閘極電壓Vg2兩者之電壓值，而使輸出訊號Vwell_vg2為前述兩者之較大者。其目的是在避免PMOS電晶體的寄生二極體被啟動而產生漏電流路徑，會產生多餘的功率消耗，也會造成電壓準位不如預期。若該第二閘極電壓Vg2大於1.8 V，電晶體MP205的閘極電壓為該第二閘極電壓Vg2，因此電晶體MP205會關閉。而該第二閘極電壓Vg2則經由電 晶體MP206輸出到Vwell_vg2。相反地，若該第二閘極電壓Vg2小於1.8 V，則電晶體MP206關閉，電晶體MP205的閘極電壓值則偏壓在該第二閘極電壓Vg2，其是小於1.8 V，因此1.8 V會通過電晶體MP205輸出到Vwell_vg2。In addition, the second gate voltage generating module 33 further has a third floating N-well circuit 331 for comparing the voltage values of both the 1.8 V and the second gate voltage Vg2 to output signals. Vwell_vg2 is the larger of the two. The purpose is to avoid the leakage current path when the parasitic diode of the PMOS transistor is activated, which will generate excessive power consumption and cause the voltage level to be lower than expected. If the second gate voltage Vg2 is greater than 1.8 V, the gate voltage of the transistor MP205 is the second gate voltage Vg2, so the transistor MP205 is turned off. And the second gate voltage Vg2 is via electricity The crystal MP206 is output to Vwell_vg2. Conversely, if the second gate voltage Vg2 is less than 1.8 V, the transistor MP206 is turned off, and the gate voltage value of the transistor MP205 is biased at the second gate voltage Vg2, which is less than 1.8 V, thus 1.8 V. It will be output to Vwell_vg2 through transistor MP205.

回顧圖1、2，並配合參閱圖6，該第三閘極電壓產生模組34是用以接收該第二閘極電壓Vg2與該直流偏壓，並根據該判斷訊號及該核心電路100的控制，以產生相對應的第三閘極電壓Vg3，其中，第三閘極電壓產生模組34在接收模式下是使該第二閘極電壓Vg2及第三閘極電壓Vg3相互隔絕，同時使該第三閘極電壓Vg3追隨存在於該晶片焊接點200上的電壓，而在傳輸模式下是使該第三閘極電壓Vg3追隨該第二閘極電壓Vg2。Referring to FIG. 1 and FIG. 2, and referring to FIG. 6, the third gate voltage generating module 34 is configured to receive the second gate voltage Vg2 and the DC bias voltage, and according to the determining signal and the core circuit 100. Controlling to generate a corresponding third gate voltage Vg3, wherein the third gate voltage generating module 34 in the receiving mode isolates the second gate voltage Vg2 and the third gate voltage Vg3 from each other while making The third gate voltage Vg3 follows the voltage present on the wafer pad 200, and in the transmission mode, the third gate voltage Vg3 follows the second gate voltage Vg2.

在本實施例中，當在接收模式下且該外部電壓VDDIO等於1.8/1.2/0.9 V，以及該直流偏壓等於5.0 V時，訊號QB=0 V、該第二閘極電壓Vg2=1.8 V且Vg4=3.2 V，此時點neta會被電晶體MN311箝在約3.2 V，點neta與第四閘極電壓Vg4經由一第二浮動N型井電路一342產生出點netb的電壓，約為3.2 V，因此該晶片焊接點200的電壓會經由電晶體MP318傳輸到該第三閘極電壓Vg3，以關閉電晶體Po3(見圖1)，避免產生漏電流路徑。同時點net_bias<1.8 V，該第二浮動N型井電路二343可使點nety=1.8 V以關閉電晶體MN301；Vwell_cont=3.2 V且Vwell_vg2=1.8 V，該第二浮動N型井電路344使點netw=3.2 V，以關閉電晶體MP301；又晶片焊接點200的電壓可經由電晶 體MP304與MP305傳至點netx以關閉電晶體MP302，Vwell_out=5.0 V、Vwell_cont=3.2 V使點netz=3.2 V以關閉電晶體MN302；該第二閘極電壓Vg2與第三閘極電壓Vg3被電晶體MN301、MP301和MN302、MP302隔開，因此點netu為浮接(floating)，此時電晶體MP312將點netz(3.2 V)傳至點netu，使電晶體MN301、MP301、MN302與MP302之間不會有過壓問題。In this embodiment, when in the receiving mode and the external voltage VDDIO is equal to 1.8/1.2/0.9 V, and the DC bias voltage is equal to 5.0 V, the signal QB=0 V, the second gate voltage Vg2=1.8 V And Vg4=3.2 V, at this time, the point neta is clamped by the transistor MN311 at about 3.2 V, and the point neta and the fourth gate voltage Vg4 generate a point netb voltage via a second floating N-well circuit 342, which is about 3.2. V, therefore the voltage of the wafer solder joint 200 is transmitted to the third gate voltage Vg3 via the transistor MP318 to turn off the transistor Po3 (see FIG. 1) to avoid a leakage current path. At the same time, net_bias<1.8 V, the second floating N-well circuit 343 can make the point nety=1.8 V to turn off the transistor MN301; Vwell_cont=3.2 V and Vwell_vg2=1.8 V, the second floating N-well circuit 344 makes Point netw=3.2 V to turn off the transistor MP301; the voltage of the wafer solder joint 200 can pass through the electro-crystal The body MP304 and MP305 are transmitted to the point netx to turn off the transistor MP302, Vwell_out=5.0 V, Vwell_cont=3.2 V, the point netz=3.2 V to turn off the transistor MN302; the second gate voltage Vg2 and the third gate voltage Vg3 are The transistors MN301, MP301 and MN302, MP302 are separated, so the point netu is floating. At this time, the transistor MP312 transmits the point netz (3.2 V) to the point netu, so that the transistors MN301, MP301, MN302 and MP302 are There will be no overvoltage problems.

當VPAD=0 V時，點nety依然保持1.8 V，且因為Vwell_cont降至1.8 V，點netw也降為1.8 V，因此該第二閘極電壓Vg2與第三閘極電壓Vg3保持隔絕，也就是該第三閘極電壓Vg3是浮接的，且將會維持在5.0 V，這個高電壓會造成電晶體Po3的閘極氧化層產生過壓的情形。為了避免這個現象，加上了電晶體MN303、MN304、MN305和邊緣偵測模組341(edge detector)。在接收模式時，該邊緣偵測模組341會偵測來自該核心電路100之第二控制訊號DIN的負緣，在負緣發生的時候輸出一個0 V的脈衝訊號Vpulse，這個0 V的脈衝Vpulse將該第三閘極電壓Vg3由5.0 V放電到1.8 V之後隨即恢復1.8 V的電壓，等待下次的負緣產生才會發生作用。因此，電晶體Po3的閘極氧化層過壓問題可以被避免。當VPAD=3.3/2.5 V時，點neta約為1.8 V，Vg4=1.8 V，經由該第二浮動N型井電路342使點netb產生1.8 V，該晶片焊接點200之電壓經由電晶體MP318傳至該第三閘極電壓Vg3，以關閉輸出級電路的Po3，避免產生漏電流路徑。又該晶片焊接點200的電壓可經 由電晶體MP304與MP305傳至點netx以關閉電晶體MP302，Vwell_out=3.3/2.5 V、Vwell_cont=1.8 V，使點netz=1.8 V以關閉電晶體MN302來隔絕第二閘極電壓Vg2與第三閘極電壓Vg3。When VPAD=0 V, the point nety remains at 1.8 V, and since Vwell_cont drops to 1.8 V, the point netw also drops to 1.8 V, so the second gate voltage Vg2 is kept isolated from the third gate voltage Vg3, that is, The third gate voltage Vg3 is floating and will be maintained at 5.0 V. This high voltage causes an overvoltage condition in the gate oxide layer of the transistor Po3. In order to avoid this phenomenon, transistors MN303, MN304, MN305 and edge detector 341 are added. In the receiving mode, the edge detection module 341 detects the negative edge of the second control signal DIN from the core circuit 100, and outputs a 0 V pulse signal Vpulse when the negative edge occurs, the 0 V pulse. Vpulse will discharge the voltage of 1.8 V after discharging the third gate voltage Vg3 from 5.0 V to 1.8 V, and wait for the next negative edge generation to take effect. Therefore, the overvoltage problem of the gate oxide of the transistor Po3 can be avoided. When VPAD=3.3/2.5 V, the point neta is about 1.8 V, Vg4=1.8 V, and the point netb generates 1.8 V via the second floating N-well circuit 342, and the voltage of the wafer bonding pad 200 is transmitted via the transistor MP318. To the third gate voltage Vg3, the Po3 of the output stage circuit is turned off to avoid a leakage current path. The voltage of the wafer solder joint 200 can be Passing transistor MP304 and MP305 to point netx to turn off transistor MP302, Vwell_out=3.3/2.5 V, Vwell_cont=1.8 V, making point netz=1.8 V to turn off transistor MN302 to isolate second gate voltage Vg2 and third Gate voltage Vg3.

在傳輸模式下，當該外部電壓VDDIO=5.0 V且傳輸邏輯1時，該第二閘極電壓Vg2=3.2 V，Vwell_vg2=3.2 V且Vwell_cont=3.2 V，使得點netw=3.2 V；又點net_bias產生約2.5 V，經由第二浮動N型井電路343使得點nety為2.5 V，因此該第二閘極電壓Vg2被電晶體MN301和MP301隔絕，但Vwell_out=5.0 V，Vwell_cont=3.2 V的電壓可經由電晶體MN310和MP312傳至點netu，此時電晶體MP303會導通使點netx=1.8 V，而點netu=3.2 V的電壓可傳至該第三閘極電壓Vg3以防止電晶體Po3的閘極氧化層產生過壓的情形。In the transmission mode, when the external voltage VDDIO = 5.0 V and the transmission logic 1, the second gate voltage Vg2 = 3.2 V, Vwell_vg2 = 3.2 V and Vwell_cont = 3.2 V, so that the point netw = 3.2 V; point net_bias Producing about 2.5 V, the point nety is 2.5 V via the second floating N-well circuit 343, so the second gate voltage Vg2 is isolated by the transistors MN301 and MP301, but Vwell_out=5.0 V, Vwell_cont=3.2 V Passing through the transistors MN310 and MP312 to the point netu, at this time, the transistor MP303 is turned on to make the point netx=1.8 V, and the voltage of the point netu=3.2 V can be transmitted to the third gate voltage Vg3 to prevent the gate of the transistor Po3. The extreme oxide layer creates an overpressure condition.

在傳輸邏輯0時，該第二閘極電壓Vg2=3.2 V、點netw=3.2 V、點nety=2.5 V，該第二閘極電壓Vg2依然與該第三閘極電壓Vg3隔絕，且Vwell_out=1.8 V，Vwell_cont=1.8 V，因此點netz之電壓約為1.8 V，電晶體MP312被關閉，第三閘極電壓Vg3發生與接收模式時相同的浮接問題，第三閘極電壓Vg3被維持在3.2 V，造成電晶體Po3的閘極氧化層產生過壓的情形。為了避免這個現象，當傳輸模式下外部電壓VDDIO=5.0 V時，該邊緣偵測模組341亦要啟動，偵測來自該核心電路100之第三控制訊號Dout的負緣並輸出一短暫0 V的脈衝訊號，將第三閘極電壓Vg3放電至1.8 V以下避免電晶體Po3的閘極氧化層產生過壓的情形。When the logic 0 is transmitted, the second gate voltage Vg2=3.2 V, the point netw=3.2 V, the point nety=2.5 V, the second gate voltage Vg2 is still isolated from the third gate voltage Vg3, and Vwell_out= 1.8 V, Vwell_cont = 1.8 V, so the voltage of the point netz is about 1.8 V, the transistor MP312 is turned off, the third gate voltage Vg3 has the same floating connection problem as in the receiving mode, and the third gate voltage Vg3 is maintained at 3.2 V, causing overvoltage in the gate oxide layer of transistor Po3. In order to avoid this phenomenon, when the external voltage VDDIO=5.0 V in the transmission mode, the edge detection module 341 is also activated to detect the negative edge of the third control signal Dout from the core circuit 100 and output a short 0 V. The pulse signal discharges the third gate voltage Vg3 to less than 1.8 V to avoid overvoltage in the gate oxide layer of the transistor Po3.

當傳輸模式之外部電壓VDDIO=3.3 V且傳輸邏輯1時，該第二閘極電壓Vg2=1.5 V，點net_bias產生約2.1 V，經由第二浮動N型井電路343使得點nety為2.1 V，Vwell_out=3.3 V，Vwell_cont=1.8 V可經由電晶體MN310傳至點netz，該第二閘極電壓Vg2=1.5 V可經由電晶體MN301和MN302傳至該第三閘極電壓Vg3，此時電晶體MN304關閉(VD2只有在外部電壓VDDIO=5.0 V時為0)可防止邊緣偵測模組341往該第三閘極電壓Vg3的方向漏電。When the external voltage of the transmission mode VDDIO=3.3 V and the transmission logic 1 is transmitted, the second gate voltage Vg2=1.5 V, the point net_bias generates about 2.1 V, and the point nety is 2.1 V via the second floating N-well circuit 343. Vwell_out=3.3 V, Vwell_cont=1.8 V can be transmitted to the point netz via the transistor MN310, and the second gate voltage Vg2=1.5 V can be transmitted to the third gate voltage Vg3 via the transistors MN301 and MN302, at this time, the transistor The MN304 is turned off (VD2 is 0 only when the external voltage VDDIO=5.0 V) to prevent the edge detecting module 341 from leaking in the direction of the third gate voltage Vg3.

當傳輸模式之外部電壓VDDIO=2.5 V且傳輸邏輯1時，該第二閘極電壓Vg2=0.7 V，點net_bias產生小於1.8 V的電壓，經由該第二浮動N型井電路343使得點nety為1.8 V，Vwell_out=2.5 V，Vwell_cont=1.8 V可經由電晶體MN310傳至點netz，該第二閘極電壓Vg2=0.7 V可經由電晶體MN301和MN302傳至該第三閘極電壓Vg3，此時電晶體MN304關閉可防止該邊緣偵測模組341往該第三閘極電壓Vg3的方向漏電。When the external voltage of the transmission mode VDDIO=2.5 V and the transmission logic 1 is transmitted, the second gate voltage Vg2=0.7 V, the point net_bias generates a voltage less than 1.8 V, and the point nety is made via the second floating N-well circuit 343 1.8 V, Vwell_out=2.5 V, Vwell_cont=1.8 V can be transmitted to the point netz via the transistor MN310, and the second gate voltage Vg2=0.7 V can be transmitted to the third gate voltage Vg3 via the transistors MN301 and MN302, When the transistor MN304 is turned off, the edge detecting module 341 is prevented from leaking in the direction of the third gate voltage Vg3.

當傳輸模式之外部電壓VDDIO=1.8/1.2/0.9 V且傳輸邏輯1時，該第二閘極電壓Vg2=1.8/1.2/0.9 V，點net_bias小於1.8 V的電壓是經由第二浮動N型井電路343使得點nety為1.8 V，Vwell_out=1.8 V，Vwell_cont=1.8 V可使點netz之電壓約為1.8 V，該第二閘極電壓Vg2=1.8/1.2/0.9 V可經由電晶體MN301和MN302傳至第三閘極電壓Vg3，此時電晶體MN304關閉，可防止該邊緣偵測模 組341往第三閘極電壓Vg3的方向漏電。When the external voltage of the transfer mode is VDDIO=1.8/1.2/0.9 V and the logic 1 is transmitted, the second gate voltage Vg2=1.8/1.2/0.9 V, and the voltage of the point net_bias less than 1.8 V is via the second floating N-well. Circuit 343 causes point nety to be 1.8 V, Vwell_out = 1.8 V, Vwell_cont = 1.8 V to cause the voltage of point netz to be approximately 1.8 V, and the second gate voltage Vg2 = 1.8/1.2/0.9 V via transistors MN301 and MN302 Passing to the third gate voltage Vg3, when the transistor MN304 is turned off, the edge detection mode can be prevented The group 341 leaks toward the third gate voltage Vg3.

在傳輸模式傳輸邏輯1時，訊號QB可經由電晶體MP313和MP314傳至點neta，第二浮動N型井電路342使點netb等於外部電壓VDDIO，因此電晶體MP318會關閉，以防止該晶片焊接點200的電壓傳至該第三閘極電壓Vg3；傳輸邏輯0時則點netb為1.8 V，晶片焊接點200的電壓亦不會影響該第三閘極電壓Vg3。In transmission mode transmission logic 1, signal QB can be transmitted to point neta via transistors MP313 and MP314, and second floating N-well circuit 342 causes point netb to be equal to external voltage VDDIO, so transistor MP318 is turned off to prevent soldering of the wafer. The voltage at point 200 is transmitted to the third gate voltage Vg3; when the logic 0 is transmitted, the point netb is 1.8 V, and the voltage at the wafer bonding pad 200 does not affect the third gate voltage Vg3.

回顧圖1、2，並配合參閱圖7，該第四閘極電壓產生模組35是根據該判斷訊號的值來產生一第四閘極電壓Vg4，其主要功能係當該晶片焊接點200的電壓為5.0 V時，必須升高到3.2 V，而當晶片焊接點200的電壓為3.3 V以下時，則保持在1.8 V，以免造成任何電晶體的閘極氧化層過壓。在本實施例中，當晶片焊接點200的電壓為5.0 V時，使用箝制NMOS技術的電晶體MN401會使通過的電壓為VY4-Vtn，大約等於3.2 V，VY4是由該電壓偵測模組產生。VY4-Vtn可以通過電晶體MP401而傳送到該第四閘極電壓Vg4，因為VY3>VY4-Vtn導致電晶體MP402為關閉，因此第四閘極電壓Vg4=VY4-Vtn=3.2 V。當晶片焊接點200的電壓為3.3/2.5/1.8/1.2/0.9/0 V時，VY4-Vtn<1.8 V，因此電晶體MP401會被關閉，因為VY3小於1.8 V，第四閘極電壓Vg4可以經由電晶體MP402而偏壓在1.8 V。而電晶體MP401和MP402的N-well必需接到標示為Vg4的節點，以避免其寄生二極體被導通而產生漏電流。Referring to FIG. 1 and FIG. 2, and referring to FIG. 7, the fourth gate voltage generating module 35 generates a fourth gate voltage Vg4 according to the value of the determining signal, and its main function is when the wafer solder joint 200 is When the voltage is 5.0 V, it must be raised to 3.2 V. When the voltage of the wafer solder joint 200 is 3.3 V or less, it is kept at 1.8 V to avoid overvoltage of the gate oxide of any transistor. In the present embodiment, when the voltage of the wafer bonding pad 200 is 5.0 V, the transistor MN401 using the clamped NMOS technology will pass the voltage VY4-Vtn, which is approximately equal to 3.2 V, and the VY4 is the voltage detecting module. produce. VY4-Vtn can be transferred to the fourth gate voltage Vg4 through the transistor MP401 because VY3>VY4-Vtn causes the transistor MP402 to be turned off, so the fourth gate voltage Vg4=VY4-Vtn=3.2 V. When the voltage of the wafer bonding pad 200 is 3.3/2.5/1.8/1.2/0.9/0 V, VY4-Vtn<1.8 V, so the transistor MP401 will be turned off, because VY3 is less than 1.8 V, and the fourth gate voltage Vg4 can be The bias voltage is 1.8 V via transistor MP402. The N-well of the transistors MP401 and MP402 must be connected to the node labeled Vg4 to prevent the parasitic diode from being turned on to generate leakage current.

回顧圖2，並配合參閱圖8，該低功率偏壓模組36是用以提供適當的電壓準位耦合給該外部電壓偵測模組31、第一閘極電壓產生模組32、第二閘極電壓產生模組33，及第三閘極電壓產生模組34使用。在本實施例中，該低功率偏壓模組36是使用二極體連接方式的PMOS電晶體串連而成。為了降低靜態功率的消耗，串聯的PMOS電晶體之門檻電壓(Threshold voltage)總和必須小於最大之外部電壓VDDIO的電壓值(5.0V)。如此一來，該等PMOS電晶體會操作在次臨界區，靜態電流也可以降低。其中，V11輸出到該第一閘極電壓產生模組32當作一直流偏壓，為了讓V11的輸出電壓可以同時符合外部電壓VDDIO操作在3.3V以及2.5V的電壓準位需求，使用一NMOS電晶體當作短路控制器。當外部電壓VDDIO=2.5V時，VD25為1.8V，使得該NMOS電晶體導通而將V10直接接地，V11也因此可以降到更低的電壓準位，以符合第一閘極電壓產生模組32的需求。Referring to FIG. 2, and referring to FIG. 8, the low power bias module 36 is configured to provide an appropriate voltage level coupling to the external voltage detecting module 31, the first gate voltage generating module 32, and the second. The gate voltage generating module 33 and the third gate voltage generating module 34 are used. In this embodiment, the low power bias module 36 is formed by connecting PMOS transistors in a diode connection manner. In order to reduce the static power consumption, the sum of the threshold voltages of the series PMOS transistors must be less than the voltage value of the maximum external voltage VDDIO (5.0V). As a result, the PMOS transistors operate in the subcritical region and the quiescent current can be reduced. Wherein, the V11 output to the first gate voltage generating module 32 is regarded as a DC bias, and an NMOS is used in order to allow the output voltage of V11 to simultaneously meet the external voltage VDDIO operation at a voltage level of 3.3V and 2.5V. The transistor acts as a short circuit controller. When the external voltage VDDIO=2.5V, VD25 is 1.8V, so that the NMOS transistor is turned on and V10 is directly grounded, and V11 can therefore be lowered to a lower voltage level to conform to the first gate voltage generating module 32. Demand.

回顧圖1，該輸出級單元4是與該外部電壓VDDIO電連接，並於傳輸模式下接收該第一、第二、第三、第四閘極電壓Vg1~Vg4，且將其轉換為適合於該晶片焊接點200之電壓準位的數位訊號，並輸出至該晶片焊接點200。該輸入級單元5是與該晶片焊接點200電連接，並於接收模式下用以接收自該晶片焊接點200之不同電壓準位之訊號，並將其轉換成適合於該核心電路100之邏輯數位訊號後輸至該核心電路100。Referring back to FIG. 1, the output stage unit 4 is electrically connected to the external voltage VDDIO, and receives the first, second, third, and fourth gate voltages Vg1 to Vg4 in a transmission mode, and converts it into a suitable one. The wafer is soldered to a voltage signal of the voltage level of the dot 200 and output to the wafer solder joint 200. The input stage unit 5 is electrically connected to the wafer pad 200 and receives signals of different voltage levels from the wafer pad 200 in the receiving mode and converts it into logic suitable for the core circuit 100. The digital signal is then transmitted to the core circuit 100.

回顧圖1，並配合參閱圖9，該第一浮動N型井單元6是用以提供輸出級單元4與前述晶片焊接點200偵測電路適當的電壓準位，在本實施例中，該第一浮動N型井單元6是偵測該晶片焊接點200的電壓，其架構主要包含二個傳統的浮動N井電路61、62。當晶片焊接點200的電壓大於1.8V時，輸出一等於晶片焊接點200的電壓的Vwell_out電壓，以避免PMOS電晶體的寄生二極體被導通而產生漏電流路徑，其餘時候輸出1.8V的電壓。當晶片焊接點200的電壓等於5.0V時，箝制NMOS電晶體MN503可以通過VY2-Vtn=3.2V的電壓，在通過N井電路62的浮動N井之後，即可輸出VY2-Vtn的電壓到Vwell_cont。而N井電路61則可以輸出在晶片焊接點200及Vwell_cont兩者其中較大的電壓Vwell_out。因此，當晶片焊接點200之電壓=5.0V時，Vwell_cont=3.2V，而Vwell_out=5.0V，且由於N井電路62的輔助提供了3.2V的Vwell_cont訊號，可以保護N井電路61的電晶體閘極氧化層發生過壓的情形。而當晶片焊接點200之電壓時，Vwell_cont可以輸出1.8V的電壓給N井電路61使用。此時N井電路61則如同傳統的浮動N-well般操作，可以輸出晶片焊接點200之電壓與1.8V兩者其中較大的電壓Vwell_out。Referring to FIG. 1 and referring to FIG. 9, the first floating N-well unit 6 is configured to provide an appropriate voltage level of the output stage unit 4 and the wafer soldering point detecting circuit 200. In this embodiment, the first A floating N-well unit 6 is for detecting the voltage of the wafer solder joint 200, and its structure mainly comprises two conventional floating N-well circuits 61, 62. When the voltage of the wafer bonding pad 200 is greater than 1.8V, a Vwell_out voltage equal to the voltage of the wafer bonding pad 200 is output to prevent the parasitic diode of the PMOS transistor from being turned on to generate a leakage current path, and the remaining voltage is 1.8V. . When the voltage of the wafer bonding pad 200 is equal to 5.0V, the clamped NMOS transistor MN503 can pass the voltage of VY2-Vtn=3.2V, and after passing through the floating N well of the N-well circuit 62, the voltage of VY2-Vtn can be output to Vwell_cont. . The N-well circuit 61 can output a larger voltage Vwell_out among the wafer pads 200 and Vwell_cont. Therefore, when the voltage of the wafer bonding pad 200 = 5.0 V, Vwell_cont = 3.2 V, and Vwell_out = 5.0 V, and the Vwell_cont signal of 3.2 V is provided by the assistance of the N-well circuit 62, the transistor of the N-well circuit 61 can be protected. The overvoltage of the gate oxide layer. And when the wafer solder joint 200 voltage When Vwell_cont can output a voltage of 1.8V to the N-well circuit 61. At this time, the N-well circuit 61 operates as a conventional floating N-well, and can output a voltage of the wafer pad 200 and a larger voltage Vwell_out of both 1.8V.

綜上所述，本發明之輸出入緩衝器電路裝置，利用該第三閘極電壓產生模組34的電路設計，使其可在接收模式下驅使對應之電晶體關閉，使該第二閘極電壓Vg2及第三閘極電壓Vg3相互隔絕以減少電性訊號的相互干擾，同時使該第三閘極電壓Vg3追隨存在於該晶片焊接點200上的電壓，並有效藉由對應之電晶體的保護以避免閘極氧化層過壓以及封鎖可能之漏電流路徑，以在不產生閘極氧化層過壓及漏電流路徑的情況下接收與傳送三倍之外部電壓VDDIO之訊號，進而達到大範圍電壓之輸入/輸出的優勢，並提供有效之電晶體閘極保護及防止漏電流的情況發生，故確實能達到本發明之目的。In summary, the input/output buffer circuit device of the present invention utilizes the circuit design of the third gate voltage generating module 34 to drive the corresponding transistor to be turned off in the receiving mode to make the second gate The voltage Vg2 and the third gate voltage Vg3 are isolated from each other to reduce mutual interference of the electrical signals, and the third gate voltage Vg3 is followed by the voltage present on the solder joint 200 of the wafer, and is effectively utilized by the corresponding transistor. Protection to avoid overvoltage of the gate oxide layer and block possible leakage current path to receive and transmit three times the external voltage VDDIO signal without generating a gate oxide overvoltage and leakage current path, thereby achieving a wide range The advantages of voltage input/output, and the provision of effective transistor gate protection and leakage current prevention, can indeed achieve the object of the present invention.

惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

1．．．預先驅動單元1. . . Pre-drive unit

2．．．電壓偵測單元2. . . Voltage detection unit

3．．．動態閘極偏壓產生單元3. . . Dynamic gate bias generation unit

31．．．外部電壓偵測模組31. . . External voltage detection module

311．．．P型電晶體串接偏壓模組311. . . P-type transistor serial connection bias module

TR0~3．．．溫度計碼產生器TR0~3. . . Thermometer code generator

312．．．溫度計碼與單擊碼轉換器312. . . Thermometer code and click code converter

32．．．第一閘極電壓產生模組32. . . First gate voltage generating module

33．．．第二閘極電壓產生模組33. . . Second gate voltage generating module

331．．．第三浮動N型井電路331. . . Third floating N-well circuit

34．．．第三閘極電壓產生模組34. . . Third gate voltage generating module

341．．．邊緣偵測模組341. . . Edge detection module

342~5．．．第二浮動N型井電路342~5. . . Second floating N-well circuit

35．．．第四閘極電壓產生模組35. . . Fourth gate voltage generating module

36．．．低功率偏壓模組36. . . Low power bias module

4．．．輸出級單元4. . . Output stage unit

5．．．輸入級單元5. . . Input stage unit

6．．．第一浮動N型井單元6. . . First floating N-well unit

61~2．．．N井電路61~2. . . N well circuit

100．．．核心電路100. . . Core circuit

200．．．晶片焊接點200. . . Wafer solder joint

VDDIO．．．外部電壓VDDIO. . . External voltage

VDD．．．電位供應電壓VDD. . . Potential supply voltage

Vg1．．．第一閘極電壓Vg1. . . First gate voltage

Vg2．．．第二閘極電壓Vg2. . . Second gate voltage

Vg3．．．第三閘極電壓Vg3. . . Third gate voltage

Vg4．．．第四閘極電壓Vg4. . . Fourth gate voltage

UP．．．第一控制訊號UP. . . First control signal

DIN．．．第二控制訊號DIN. . . Second control signal

Dout．．．第三控制訊號Dout. . . Third control signal

Vpulse．．．脈衝訊號Vpulse. . . Pulse signal

VX1~11．．．電壓VX1~11. . . Voltage

VD0~3．．．溫度計碼VD0~3. . . Thermometer code

圖1是一電路架構示意圖，說明本發明輸出入緩衝器電路裝置之較佳實施例；1 is a schematic diagram of a circuit architecture illustrating a preferred embodiment of the output-in buffer circuit device of the present invention;

圖2是一系統架構示意圖，說明該較佳實施例之之動態閘極偏壓產生器電路架構圖；2 is a schematic diagram of a system architecture, illustrating a circuit diagram of a dynamic gate bias generator of the preferred embodiment;

圖3是一電路圖，說明該較佳實施例之一外部電壓偵測模組；3 is a circuit diagram illustrating an external voltage detecting module of the preferred embodiment;

圖4是一電路圖，說明該較佳實施例之一第一閘極電壓產生模組；4 is a circuit diagram illustrating a first gate voltage generating module of the preferred embodiment;

圖5是一電路圖，說明該較佳實施例之一第二閘極電壓產生模組；Figure 5 is a circuit diagram showing a second gate voltage generating module of the preferred embodiment;

圖6是一電路圖，說明該較佳實施例之一第三閘極電壓產生模組；6 is a circuit diagram illustrating a third gate voltage generating module of the preferred embodiment;

圖7是一電路圖，說明該較佳實施例之一第四閘極電壓產生模組；Figure 7 is a circuit diagram showing a fourth gate voltage generating module of the preferred embodiment;

圖8是一電路圖，說明該較佳實施例之一低功率偏壓模組；及Figure 8 is a circuit diagram showing a low power bias module of the preferred embodiment; and

圖9是一電路圖，說明該較佳實施例之一第一浮動N型井單元。Figure 9 is a circuit diagram illustrating a first floating N-well unit of the preferred embodiment.

341．．．邊緣偵測模組341. . . Edge detection module

342~5．．．第二浮動N型井電路342~5. . . Second floating N-well circuit

VDDIO．．．外部電壓VDDIO. . . External voltage

VDD．．．電位供應電壓VDD. . . Potential supply voltage

Vg2．．．第二閘極電壓Vg2. . . Second gate voltage

Vg3．．．第三閘極電壓Vg3. . . Third gate voltage

Vg4．．．第四閘極電壓Vg4. . . Fourth gate voltage

DIN．．．第二控制訊號DIN. . . Second control signal

Dout．．．第三控制訊號Dout. . . Third control signal

Vpulse．．．脈衝訊號Vpulse. . . Pulse signal

Claims (4)

一種輸出入緩衝器電路裝置，是與一外部電壓、至少一個晶片焊接點，及一個核心電路電連接，以分別在一傳輸模式及一接收模式下傳送及接收複數個不同電壓準位之數位訊號，該輸出入緩衝器電路裝置包含：一預先驅動單元，是接收該核心電路所產生的電壓訊號，並產生一第一控制訊號；一電壓偵測單元，是與該晶片焊接點電連接，以偵測該晶片焊接點上的電壓，並產生一對應之直流偏壓；一動態閘極偏壓產生單元，其具有：一外部電壓偵測模組，用以判斷該外部電壓目前之電壓值，並產生一對應之判斷訊號；一第一閘極電壓產生模組，是與該預先驅動單元及該外部電壓偵測模組電連接，並接收該第一控制訊號及該判斷訊號，以產生一第一閘極電壓；一第二閘極電壓產生模組，用以接收該第一閘極電壓，並將其轉換為一第二閘極電壓後輸出；一第三閘極電壓產生模組，用以接收該第二閘極電壓與該直流偏壓，並根據該判斷訊號及該核心電路的控制，以產生相對應的第三閘極電壓，其中，該第三閘極電壓產生模組在接收模式下是使該第二閘極電壓及該第三閘極電壓相互隔絕，同時使該第三閘極電壓追隨該晶片焊接點的電壓，而在傳輸模式下是使該第三閘極電壓追隨該第二閘極電壓； 及一第四閘極電壓產生模組，是根據該判斷訊號的值來產生一第四閘極電壓；一輸出級單元，是與該外部電壓電連接，並於傳輸模式下接收該第一、第二、第三、第四閘極電壓，並將其轉換為適合於該晶片焊接點之電壓準位的數位訊號後輸出至該晶片焊接點；一輸入級單元，是與該晶片焊接點電連接，並於接收模式下用以接收自該晶片焊接點之不同電壓準位之訊號，並將其轉換成適合於該核心電路之邏輯數位訊號後輸至該核心電路；及一第一浮動N型井單元，用以提供該輸出級單元與該晶片焊接點偵測電路適當的電壓準位。 An input-input buffer circuit device is electrically connected to an external voltage, at least one wafer soldering point, and a core circuit for transmitting and receiving a plurality of digital signals of different voltage levels in a transmission mode and a receiving mode, respectively. The input/output buffer circuit device includes: a pre-drive unit that receives the voltage signal generated by the core circuit and generates a first control signal; and a voltage detecting unit electrically connected to the solder joint of the wafer to Detecting a voltage on the solder joint of the wafer and generating a corresponding DC bias voltage; a dynamic gate bias generating unit having: an external voltage detecting module for determining a current voltage value of the external voltage, And generating a corresponding determination signal; a first gate voltage generating module is electrically connected to the pre-drive unit and the external voltage detecting module, and receives the first control signal and the determining signal to generate a a first gate voltage generating module, configured to receive the first gate voltage and convert it into a second gate voltage and output the same; a three-gate voltage generating module for receiving the second gate voltage and the DC bias voltage, and generating a corresponding third gate voltage according to the determining signal and the control of the core circuit, wherein the The three-gate voltage generating module in the receiving mode is configured to isolate the second gate voltage and the third gate voltage from each other while causing the third gate voltage to follow the voltage of the solder joint of the wafer, and in the transmission mode The third gate voltage is caused to follow the second gate voltage; And a fourth gate voltage generating module, configured to generate a fourth gate voltage according to the value of the determining signal; an output stage unit electrically connected to the external voltage and receiving the first in the transmission mode The second, third, and fourth gate voltages are converted into digital signals suitable for the voltage level of the solder joints of the wafer and output to the wafer solder joint; an input stage unit is soldered to the wafer Connecting and receiving signals from different voltage levels of the solder joints in the receiving mode and converting them into logic digital signals suitable for the core circuit, and then inputting to the core circuit; and a first floating N The well unit is configured to provide an appropriate voltage level of the output stage unit and the wafer solder joint detecting circuit. 依據申請專利範圍第1項所述之輸出入緩衝器電路裝置，其中，該動態閘極偏壓產生單元之該第三閘極電壓產生模組更具有一邊緣偵測模組，該邊緣偵測電路是用以偵測源自於該核心電路之一第二控制訊號及第三控制訊號的預設特徵，並在偵測到該預設特徵時輸出一個脈衝訊號，以驅使該第三閘極電壓產生模組降低該第三閘極電壓。 According to the input/output buffer circuit device of claim 1, wherein the third gate voltage generating module of the dynamic gate bias generating unit further has an edge detecting module, the edge detecting The circuit is configured to detect a preset feature originating from the second control signal and the third control signal of the core circuit, and output a pulse signal to drive the third gate when the preset feature is detected The voltage generating module reduces the third gate voltage. 依據申請專利範圍第2項所述之輸出入緩衝器電路裝置，其中，該動態閘極偏壓產生單元之該第三閘極電壓產生模組更具有一第二浮動N型井電路，其是產生一N井電壓，該N井電壓的值與該第二閘極電壓與該第三閘極 電壓兩者其中之較大者相同，以防止寄生二極體的順偏而產生漏電。 According to the input/output snubber circuit device of claim 2, the third gate voltage generating module of the dynamic gate bias generating unit further has a second floating N-well circuit, which is Generating an N-well voltage, the value of the N-well voltage and the second gate voltage and the third gate The larger of the two voltages is the same to prevent leakage of parasitic diodes. 依據申請專利範圍第3項所述之輸出入緩衝器電路裝置，其中，該動態閘極偏壓產生單元更具有一低功率偏壓模組，用以提供適當的電壓準位耦合給該外部電壓偵測模組、該第一閘極電壓產生模組、該第二閘極電壓產生模組，及該第三閘極電壓產生模組使用。 The input/output snubber circuit device of claim 3, wherein the dynamic thyristor bias generating unit further has a low power bias module for providing an appropriate voltage level coupling to the external voltage. The detecting module, the first gate voltage generating module, the second gate voltage generating module, and the third gate voltage generating module are used.
TW98128812A 2009-08-27 2009-08-27 I/o buffer TWI393350B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW98128812A TWI393350B (en) 2009-08-27 2009-08-27 I/o buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98128812A TWI393350B (en) 2009-08-27 2009-08-27 I/o buffer

Publications (2)

Publication Number Publication Date
TW201108614A TW201108614A (en) 2011-03-01
TWI393350B true TWI393350B (en) 2013-04-11

Family

ID=44835659

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98128812A TWI393350B (en) 2009-08-27 2009-08-27 I/o buffer

Country Status (1)

Country Link
TW (1) TWI393350B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI580142B (en) * 2016-04-13 2017-04-21 Advanced Analog Technology Inc Output stage circuit of integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW510081B (en) * 2001-11-14 2002-11-11 Via Tech Inc Input/output buffer circuit with variable conductance
TW200901626A (en) * 2007-06-28 2009-01-01 Amazing Microelectronic Corp Mixed-voltage I/O buffer to limit hot-carrier degradation
TW200919966A (en) * 2007-10-24 2009-05-01 Univ Nat Sun Yat Sen Output buffer circuit, low-power bias circuit thereof, and input buffer circuit
US20090206875A1 (en) * 2008-02-15 2009-08-20 Spectralinear, Inc. Programmable io architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW510081B (en) * 2001-11-14 2002-11-11 Via Tech Inc Input/output buffer circuit with variable conductance
TW200901626A (en) * 2007-06-28 2009-01-01 Amazing Microelectronic Corp Mixed-voltage I/O buffer to limit hot-carrier degradation
TW200919966A (en) * 2007-10-24 2009-05-01 Univ Nat Sun Yat Sen Output buffer circuit, low-power bias circuit thereof, and input buffer circuit
US20090206875A1 (en) * 2008-02-15 2009-08-20 Spectralinear, Inc. Programmable io architecture

Also Published As

Publication number Publication date
TW201108614A (en) 2011-03-01

Similar Documents

Publication Publication Date Title
US8212590B2 (en) Mixed-voltage I/O buffer
TWI381638B (en) Mixed-voltage tolerant i/o buffer and output buffer circuit thereof
US6487687B1 (en) Voltage level shifter with testable cascode devices
US5629634A (en) Low-power, tristate, off-chip driver circuit
US7701278B2 (en) Drive circuit with a TOP level shifter for transmission of an input signal, and method for transmission
US6040708A (en) Output buffer having quasi-failsafe operation
CN101420224B (en) Output buffer circuit
KR20180040958A (en) High voltage output driver with low voltage device
EP2188893B1 (en) Voltage tolerant floating n-well circuit
CN102208909A (en) Level shift circuit
US20100127751A1 (en) Level shifter adaptive for use in a power-saving operation mode
US7532034B2 (en) Mixed voltage input/output buffer having low-voltage design
US8629705B2 (en) Low voltage signaling
EP3251150B1 (en) Self-sensing reverse current protection switch
TWI393350B (en) I/o buffer
Wang et al. 0.9 V to 5 V bidirectional mixed-voltage I/O buffer with an ESD protection output stage
US10056897B1 (en) Power-on control circuit with state-recovery mechanism and operating circuit utilizing the same
CN114744605B (en) IO transmitter, chip and electronic equipment
US11215648B1 (en) Voltage on-off detector and electronic device including the same
US8207775B2 (en) VOL up-shifting level shifters
CN1841930B (en) Integrated circuit
JP2009213109A (en) Input/output circuit
CN107592107B (en) Driver based on low-voltage CMOS (complementary metal oxide semiconductor) process
CN110417402A (en) Anti- suspension joint circuit
Wang et al. A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees