TWI392070B - Package substrate having semiconductor component embedded therein and fabrication method thereof - Google Patents
Package substrate having semiconductor component embedded therein and fabrication method thereof Download PDFInfo
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- TWI392070B TWI392070B TW097116430A TW97116430A TWI392070B TW I392070 B TWI392070 B TW I392070B TW 097116430 A TW097116430 A TW 097116430A TW 97116430 A TW97116430 A TW 97116430A TW I392070 B TWI392070 B TW I392070B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Microelectronics & Electronic Packaging (AREA)
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Description
本發明係有關於一種半導體結構及製法，尤指一種半導體元件暨嵌埋有半導體元件之封裝基板及其製法。The invention relates to a semiconductor structure and a manufacturing method, in particular to a semiconductor component and a package substrate embedded with a semiconductor component and a manufacturing method thereof.
隨著半導體封裝技術的演進，除了傳統打線式(Wire bonding)半導體封裝技術以外，目前半導體裝置(Semiconductor device)已開發出不同的封裝型態，例如直接在一封裝基板(package substrate)中嵌埋並電性整合一係如具有積體電路之半導體晶片，此種半導體裝置可縮減整體體積大小及厚度，並提昇電性功能，而此封裝結構遂逐漸成為一種封裝的主流。With the evolution of semiconductor packaging technology, in addition to the conventional wire bonding semiconductor packaging technology, semiconductor devices have been developed in different package types, such as directly embedded in a package substrate. And electrically integrated with a semiconductor wafer having an integrated circuit, the semiconductor device can reduce the overall size and thickness, and enhance the electrical function, and the package structure gradually becomes a mainstream of the package.
請參閱第1A至1L圖美國專利第6586276號所揭示之習知嵌埋有半導體晶片之封裝基板之製法；如第1A圖所示，係提供一具有複數電極墊101之晶圓10；如第1B圖所示，於該晶圓10上形成鈍化層11；如第1C圖所示，於該鈍化層11中形成有第一開孔110，以露出該電極墊101；如第1D圖所示，於該鈍化層11及該電極墊101之表面覆蓋一黏著層12；如第1E圖所示，再於該黏著層12之表面形成一保護層13；如第1F圖所示，接著切割該晶圓10以形成複數半導體晶片10a；如第1G圖所示，提供一具有開口140之基板本體14，將該半導體晶片10a置於該基板本體14之開口140中，並以結合材料15形成於該基板本體14之開口140與半導體晶片10a之間的間隙 中，以將該半導體晶片10a固定於該開口140中；如第1H圖所示，於該半導體晶片10a之保護層13、結合材料15及該基板本體14上形成一導電層16；如第1I圖所示，接著於該導電層16上形成阻層17，並於對應該些電極墊101之位置形成有阻層開口170；如第1J圖所示，於該阻層開口170中之導電層16上電鍍形成擴充墊(Expanded Pad)18；如第1K圖所示，移除該阻層17及其所覆蓋之導電層16、保護層13與黏著層12，以露出該擴充墊18及鈍化層11，其中該擴充墊18係大於該電極墊101，以利於後續壓合介電層，再形成線路層時之對位；如第1L圖所示，復於該擴充墊18、鈍化層11及基板本體14上形成增層結構19，該增層結構19係包括有至少一介電層191、疊置於該介電層上之線路層192，以及形成於該介電層中並電性連接該擴充墊18之導電盲孔193，且於該增層結構19表面具有複數電性連接該線路層192之電性接觸墊194，又於該增層結構19上形成絕緣保護層195，該絕緣保護層195形成有複數個絕緣保護層開孔1950以對應露出該電性接觸墊194。Please refer to the method for manufacturing a semiconductor wafer-embedded package substrate disclosed in US Pat. No. 6,586,276, which is incorporated herein by reference. FIG. 1A shows a wafer 10 having a plurality of electrode pads 101; As shown in FIG. 1B, a passivation layer 11 is formed on the wafer 10; as shown in FIG. 1C, a first opening 110 is formed in the passivation layer 11 to expose the electrode pad 101; as shown in FIG. 1D The surface of the passivation layer 11 and the electrode pad 101 is covered with an adhesive layer 12; as shown in FIG. 1E, a protective layer 13 is formed on the surface of the adhesive layer 12; as shown in FIG. The wafer 10 is formed to form a plurality of semiconductor wafers 10a; as shown in FIG. 1G, a substrate body 14 having an opening 140 is provided, the semiconductor wafer 10a is placed in the opening 140 of the substrate body 14, and formed by the bonding material 15 a gap between the opening 140 of the substrate body 14 and the semiconductor wafer 10a The semiconductor wafer 10a is fixed in the opening 140; as shown in FIG. 1H, a conductive layer 16 is formed on the protective layer 13, the bonding material 15 and the substrate body 14 of the semiconductor wafer 10a; As shown in the figure, a resist layer 17 is formed on the conductive layer 16, and a resist opening 170 is formed at a position corresponding to the electrode pads 101; as shown in FIG. 1J, the conductive layer in the resist opening 170 16 is plated to form an Expanded Pad 18; as shown in FIG. 1K, the resist layer 17 and the conductive layer 16, the protective layer 13 and the adhesive layer 12 are removed to expose the expansion pad 18 and passivation. The layer 11, wherein the expansion pad 18 is larger than the electrode pad 101 to facilitate subsequent bonding of the dielectric layer and the alignment of the circuit layer; as shown in FIG. 1L, the expansion pad 18 and the passivation layer 11 are applied. And forming a build-up structure 19 on the substrate body 14. The build-up structure 19 includes at least one dielectric layer 191, a circuit layer 192 stacked on the dielectric layer, and formed in the dielectric layer and electrically Connecting the conductive blind holes 193 of the expansion pad 18, and having a plurality of electrical connections to the circuit layer 19 on the surface of the build-up structure 19 An electrical contact pad 194 is further formed on the build-up structure 19 to form an insulating protective layer 195. The insulating protective layer 195 is formed with a plurality of insulating protective layer openings 1950 to correspondingly expose the electrical contact pads 194.
由上可知，習知嵌埋有半導體晶片之封裝基板之製法中，需要於該鈍化層11及該電極墊101上先形成黏著層12，再於該黏著層12上形成保護層13，之後才將該晶圓10切割形成複數半導體晶片10a；之後將該半導體晶片10a以結合材料15固定於該基板本體14之開口140中，接著再於該黏著層12及保護層13上形成擴充墊18，之 後才於該形成有擴充墊18之半導體晶片10a、結合材料15及基板本體14上形成增層結構19之介電層191；即該半導體晶片10a必須以結合材料15先固定於該基板本體14之開口140中，因而增加製程複雜度；之後再於該半導體晶片10a之電極墊101上形成擴充墊18，方可進行後續之增層結構19，以藉由該擴充墊18避免在增層結構19之介電層191形成開孔時導致該半導體晶片10a之電極墊101受損，如此於製作擴充墊18之製程步驟將導致增加製程步驟、時間及生產成本，且該包括擴充墊18及導電盲孔193之電性連接結構亦為一複雜之結構。As can be seen from the above, in the method of fabricating a package substrate in which a semiconductor wafer is embedded, it is necessary to form an adhesive layer 12 on the passivation layer 11 and the electrode pad 101, and then form a protective layer 13 on the adhesive layer 12. The wafer 10 is cut into a plurality of semiconductor wafers 10a; the semiconductor wafer 10a is then fixed in the opening 140 of the substrate body 14 with a bonding material 15, and then the expansion pad 18 is formed on the adhesive layer 12 and the protective layer 13. It The dielectric layer 191 of the build-up structure 19 is formed on the semiconductor wafer 10a, the bonding material 15 and the substrate body 14 on which the expansion pad 18 is formed; that is, the semiconductor wafer 10a must be first fixed to the substrate body 14 by the bonding material 15. In the opening 140, the process complexity is increased; then the expansion pad 18 is formed on the electrode pad 101 of the semiconductor wafer 10a, so that the subsequent build-up structure 19 can be performed to avoid the build-up structure by the expansion pad 18. When the dielectric layer 191 of 19 is formed into an opening, the electrode pad 101 of the semiconductor wafer 10a is damaged. Thus, the manufacturing process of manufacturing the expansion pad 18 will result in an increase in process steps, time and production cost, and the expansion pad 18 and the conductive layer are included. The electrical connection structure of the blind via 193 is also a complicated structure.
因此，鑒於上述之問題，如何避免習知技術中加工成本高且浪費時間與結構複雜等問題，實已成目前亟欲解決的課題。Therefore, in view of the above problems, how to avoid the problems of high processing cost and wasted time and complicated structure in the prior art has become a problem that is currently being solved.
鑒於上述習知技術之缺失，本發明之一目的係提供一種半導體元件暨嵌埋有半導體元件之封裝基板及其製法，能簡化半導體元件結構並節省製程步驟。In view of the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide a semiconductor device and a package substrate embedded with the semiconductor device and a method of fabricating the same, which can simplify the structure of the semiconductor device and save the process steps.
本發明之又一目的係提供一種半導體元件暨嵌埋有半導體元件之封裝基板及其製法，能將導電盲孔直接電性連接半導體晶片之電極墊。Another object of the present invention is to provide a semiconductor device and a package substrate embedded with a semiconductor device and a method for fabricating the same, which can electrically connect the conductive blind vias directly to the electrode pads of the semiconductor wafer.
為達上述目的及其他目的，本發明揭露一種半導體元件，係包括：半導體晶片，係具有相對應之作用面及非作用面，於該作用面上具有複數電極墊；鈍化層，係設於該作用面及電極墊上；以及金屬墊，係設於該鈍化層上，並 對應該電極墊。To achieve the above and other objects, the present invention discloses a semiconductor device comprising: a semiconductor wafer having a corresponding active surface and a non-active surface, the active surface having a plurality of electrode pads; and a passivation layer disposed thereon a working surface and an electrode pad; and a metal pad is disposed on the passivation layer, and Corresponding to the electrode pads.
依上述結構，該鈍化層係由具有開孔以露出該電極墊之第一鈍化層及形成於該第一鈍化層上並覆蓋該電極墊之第二鈍化層所組成，其中該第一鈍化層係為氮化矽(Si3 N4 )或二氧化矽(SiO2 )，而該第二鈍化層係為聚醯亞胺(Polyimide)或苯並環丁烯(BCB)。該金屬墊係為銅。According to the above structure, the passivation layer is composed of a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad, wherein the first passivation layer It is made of tantalum nitride (Si 3 N 4 ) or cerium oxide (SiO 2 ), and the second passivation layer is polyimide or benzocyclobutene (BCB). The metal pad is copper.
本發明復提供一種嵌埋有半導體元件之封裝基板，係包括：基板本體，係具有至少一開口；半導體晶片，係固定於該基板本體之開口中，該半導體晶片具有相對應之作用面及非作用面，於該作用面上具有複數電極墊及設於該作用面上之鈍化層，該鈍化層具有對應該電極墊之鈍化層開孔；金屬環，係設於該鈍化層開孔上；第一介電層，係設於該基板本體、鈍化層及金屬環上，並對應該電極墊形成貫穿之介電層開孔，以露出該電極墊；以及第一線路層，係設置於該第一介電層上，並於該介電層開孔及鈍化層開孔中設有第一導電盲孔以電性連接該電極墊，且該第一導電盲孔接觸該金屬環。The present invention further provides a package substrate embedded with a semiconductor component, comprising: a substrate body having at least one opening; and a semiconductor wafer fixed in an opening of the substrate body, the semiconductor wafer having a corresponding active surface and a non- The active surface has a plurality of electrode pads and a passivation layer disposed on the active surface, the passivation layer has a passivation layer opening corresponding to the electrode pad; and a metal ring is disposed on the opening of the passivation layer; The first dielectric layer is disposed on the substrate body, the passivation layer and the metal ring, and the dielectric pad is formed with an opening through the dielectric layer to expose the electrode pad; and the first circuit layer is disposed on the substrate layer A first conductive via hole is disposed in the dielectric layer opening and the opening of the passivation layer to electrically connect the electrode pad, and the first conductive blind hole contacts the metal ring.
依上述之結構，該鈍化層係由具有開孔以露出該電極墊之第一鈍化層及形成於該第一鈍化層上並覆蓋該電極墊之第二鈍化層所組成，其中該第一鈍化層係為氮化矽(Si3 N4 )或二氧化矽(SiO2 )，而該第二鈍化層係為聚醯亞胺(Polyimide)或苯並環丁烯(BCB)。According to the above structure, the passivation layer is composed of a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad, wherein the first passivation The layer is tantalum nitride (Si 3 N 4 ) or hafnium oxide (SiO 2 ), and the second passivation layer is polyimide or benzocyclobutene (BCB).
該第一介電層及第一線路層上設有增層結構，該增層結構係包括有至少一第二介電層、疊置於該第二介電層上 之第二線路層、以及複數設於該第二介電層中並電性連接該第一線路層及第二線路層之第二導電盲孔，並於該增層結構上具有電性連接該第二線路層之電性接觸墊，又於該增層結構上設有絕緣保護層，且該絕緣保護層中具有複數絕緣保護層開孔，以對應露出該電性接觸墊。The first dielectric layer and the first circuit layer are provided with a build-up structure, and the build-up structure includes at least one second dielectric layer stacked on the second dielectric layer. a second circuit layer, and a plurality of second conductive blind holes disposed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and electrically connected to the build-up structure The electrical contact pad of the second circuit layer is further provided with an insulating protective layer on the layered structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electrical contact pads.
本發明再提供一種嵌埋有半導體元件之封裝基板製法，係包括：提供一具有相對應之作用面及非作用面之晶圓，於該作用面上具有複數電極墊及形成於該作用面上之鈍化層，且於該鈍化層上設有相對應該電極墊處之金屬墊；切割該晶圓以形成複數半導體晶片；提供一具有開口之基板本體，並將該半導體晶片容設於該開口中；於該基板本體及半導體晶片上形成第一介電層，並使該第一介電層填入該基板本體之開口與半導體晶片之間的間隙中，以將該半導體晶片固定於該開口中；以雷射於該第一介電層中形成相對應該金屬墊之介電層開孔，並露出該金屬墊之部份表面；移除該介電層開孔中之金屬墊及鈍化層，以形成鈍化層開孔並露出該電極墊，並使該金屬墊形成一金屬環；於該第一介電層上形成有第一線路層，該第一線路層具有複數形成於該介電層開孔及鈍化層開孔中之第一導電盲孔，以電性連接該電極墊，且該第一導電盲孔接觸該金屬環；以及移除該阻層及其所覆蓋之導電層。The invention further provides a method for manufacturing a package substrate embedded with a semiconductor component, comprising: providing a wafer having a corresponding active surface and a non-active surface, wherein the active surface has a plurality of electrode pads formed on the active surface a passivation layer, and a metal pad corresponding to the electrode pad is disposed on the passivation layer; the wafer is cut to form a plurality of semiconductor wafers; a substrate body having an opening is provided, and the semiconductor wafer is received in the opening Forming a first dielectric layer on the substrate body and the semiconductor wafer, and filling the first dielectric layer into a gap between the opening of the substrate body and the semiconductor wafer to fix the semiconductor wafer in the opening Forming a dielectric layer opening corresponding to the metal pad in the first dielectric layer, and exposing a portion of the surface of the metal pad; removing the metal pad and the passivation layer in the opening of the dielectric layer, Forming a passivation layer opening and exposing the electrode pad, and forming the metal pad to form a metal ring; forming a first circuit layer on the first dielectric layer, the first circuit layer having a plurality of layers formed on the dielectric layer open Openings of the passivation layer and first conductive vias to electrically connected to the electrode pad, and the first conductive vias contacting the metal ring; and removing the resist layer and the conductive layer is covered.
依上述製法，該金屬墊係為金屬層蝕刻或物理濺鍍形成；該鈍化層係由具有開孔以露出該電極墊之第一鈍化層及形成於該第一鈍化層上並覆蓋該電極墊之第二鈍化 層所組成，其中該第一鈍化層係為氮化矽(Si3 N4 )或二氧化矽(SiO2 )，而該第二鈍化層係為聚醯亞胺(Polyimide)或苯並環丁烯(BCB)；該雷射係為二氧化碳雷射。According to the above method, the metal pad is formed by metal layer etching or physical sputtering; the passivation layer is formed by a first passivation layer having an opening to expose the electrode pad and formed on the first passivation layer and covering the electrode pad a second passivation layer, wherein the first passivation layer is tantalum nitride (Si 3 N 4 ) or cerium oxide (SiO 2 ), and the second passivation layer is polyimide (Polyimide) or Benzocyclobutene (BCB); the laser system is a carbon dioxide laser.
該晶圓之作用面上形成鈍化層之製法，係包括：於該晶圓上形成第一鈍化層，並於該第一鈍化層中形成開孔以露出該電極墊；於該電極墊、第一鈍化層及其開孔上形成第二鈍化層；以及於該第二鈍化層上對應該電極墊之位置形成該金屬墊。Forming a passivation layer on the active surface of the wafer, comprising: forming a first passivation layer on the wafer, and forming an opening in the first passivation layer to expose the electrode pad; and the electrode pad, Forming a second passivation layer on a passivation layer and an opening thereof; and forming the metal pad on a position corresponding to the electrode pad on the second passivation layer.
該介電層開孔中之金屬墊及鈍化層係同步移除，或先移除該金屬墊，再移除該鈍化層。The metal pad and the passivation layer in the opening of the dielectric layer are removed synchronously, or the metal pad is removed first, and then the passivation layer is removed.
該第一線路層及第一導電盲孔之製法，係包括：於該電極墊上、鈍化層開孔、第一介電層及其介電層開孔表面形成有導電層；於該導電層上形成有阻層，該阻層中形成有複數阻層開口，以露出該第一介電層上之導電層部份表面、介電層開孔與鈍化層開孔中導電層；以及於該阻層開口中之導電層上電鍍形成該第一線路層，且於該阻層開口、介電層開孔及鈍化層開孔中形成該第一導電盲孔，以電性連接該電極墊。The first circuit layer and the first conductive via hole are formed on the electrode pad, the passivation layer opening, the first dielectric layer and the opening surface of the dielectric layer are formed with a conductive layer; on the conductive layer Forming a resist layer, wherein the resist layer is formed with a plurality of resist layer openings to expose a surface of the conductive layer portion on the first dielectric layer, a dielectric layer opening and a conductive layer in the opening of the passivation layer; and The first circuit layer is formed by electroplating on the conductive layer in the layer opening, and the first conductive blind hole is formed in the opening of the resist layer, the opening of the dielectric layer and the opening of the passivation layer to electrically connect the electrode pad.
該第一介電層及第一線路層上形成增層結構，該增層結構係包括有至少一第二介電層、疊置於該第二介電層上之第二線路層、以及複數形成於該第二介電層中並電性連接該第一線路層及第二線路層之第二導電盲孔，並於該增層結構上具有電性連接該第二線路層之電性接觸墊，又於 該增層結構上形成有絕緣保護層，且該絕緣保護層中具有複數絕緣保護層開孔，以對應露出該電性接觸墊。Forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure comprising at least one second dielectric layer, a second circuit layer stacked on the second dielectric layer, and a plurality a second conductive via hole formed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and electrically connected to the second circuit layer on the build-up structure Pad, again An insulating protective layer is formed on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electrical contact pads.
因此，本發明之半導體元件暨嵌埋有半導體元件之封裝基板及其製法，係將具有設於鈍化層上並相對該電極墊之金屬墊的晶圓切割成複數半導體晶片，將該半導體晶片設置於該基板本體之開口中，再以第一介電層形成於該半導體晶片及基板本體上，以將該半導體晶片固定於該基板本體之開口中，俾以免除習知以結合材料固定再形成介電層，而增加製程之缺失；接著，以雷射在第一介電層中形成介電層層開孔，並藉由該金屬墊阻擋以避免貫穿該電極墊，然後再移除該介電層開孔中之金屬墊及鈍化層，以露出該半導體晶片之電極墊，再於該第一介電層上形成第一線路層，並電性連接該電極墊，俾可免除習知必須先製作擴充墊，然後再形成增層結構之缺失，以降低晶圓製程之成本與產品製作之時程；因此，本發明具有保護半導體晶片電極墊、並能直接電性導接及節省製程步驟之效果。Therefore, the semiconductor device of the present invention and the package substrate embedded with the semiconductor device and the method for manufacturing the same are to cut a wafer having a metal pad provided on the passivation layer and opposed to the electrode pad into a plurality of semiconductor wafers, and the semiconductor wafer is disposed Forming a first dielectric layer on the semiconductor wafer and the substrate body in the opening of the substrate body to fix the semiconductor wafer in the opening of the substrate body, so as to prevent the conventional material from being fixed by the bonding material. Dielectric layer, and adding a process defect; then, forming a dielectric layer opening in the first dielectric layer by laser, and blocking by the metal pad to avoid penetrating the electrode pad, and then removing the dielectric layer a metal pad and a passivation layer in the opening of the electric layer to expose the electrode pad of the semiconductor wafer, and then forming a first circuit layer on the first dielectric layer and electrically connecting the electrode pad, thereby eliminating the need for conventional The expansion pad is first formed, and then the missing structure is formed to reduce the cost of the wafer process and the time course of product fabrication; therefore, the invention has the electrode pad for protecting the semiconductor wafer and can be directly charged. And conductively connected to the process step of saving effect.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
請參閱第2A至2D圖及第3A至3H圖，係為本發明半導體元件暨嵌埋有半導體元件之封裝基板及其製法。Please refer to FIGS. 2A to 2D and FIGS. 3A to 3H , which illustrate a semiconductor device of the present invention and a package substrate in which a semiconductor element is embedded and a method of fabricating the same.
請參閱第2A至2D圖，係為晶圓上形成鈍化層及金屬 墊之製法。Please refer to Figures 2A to 2D for forming a passivation layer and metal on the wafer. The method of making the pad.
如第2A圖所示，提供一具有相對應之作用面20a及非作用面20b之晶圓20，於該作用面20a上具有複數電極墊201。As shown in FIG. 2A, a wafer 20 having a corresponding active surface 20a and a non-active surface 20b is provided, and a plurality of electrode pads 201 are provided on the active surface 20a.
如第2B圖所示，於該晶圓20之作用面20a上形成例如為氮化矽(Si3 N4 )或二氧化矽(SiO2 )之第一鈍化層22a，且該第一鈍化層22a形成有開孔220a以露出該電極墊201之部份表面。As shown in FIG. 2B, a first passivation layer 22a such as tantalum nitride (Si 3 N 4 ) or hafnium oxide (SiO 2 ) is formed on the active surface 20a of the wafer 20, and the first passivation layer is formed. 22a is formed with an opening 220a to expose a part of the surface of the electrode pad 201.
如第2C圖所示，於該電極墊201及第一鈍化層22a上形成例如為聚醯亞胺(Polyimide)或苯並環丁烯(BCB)之第二鈍化層22b，使該第一鈍化層22a及第二鈍化層22b組成鈍化層22。As shown in FIG. 2C, a second passivation layer 22b such as polyimide or benzocyclobutene (BCB) is formed on the electrode pad 201 and the first passivation layer 22a to make the first passivation. The layer 22a and the second passivation layer 22b constitute a passivation layer 22.
如第2D圖所示，於該鈍化層22上以金屬層蝕刻或物理濺鍍形成金屬墊23；其中該金屬層蝕刻係先形成一金屬層，再於該金屬層上形成阻層，並於阻層中形成有非對應該電極墊之阻層開口，以露出部份之金屬層，移除未被該阻層所覆蓋之金屬層，最後再移除該阻層，以露出該金屬墊；該物理濺鍍則以一光罩置於該鈍化層上，且該光罩具有對應該電極墊之穿孔，於該穿孔中以物理濺鍍形成該金屬墊，最後移除該光罩以露出該金屬墊。As shown in FIG. 2D, a metal pad 23 is formed on the passivation layer 22 by metal layer etching or physical sputtering; wherein the metal layer is formed by first forming a metal layer, and then forming a resist layer on the metal layer. Forming a resist layer opening corresponding to the electrode pad in the resist layer to expose a portion of the metal layer, removing the metal layer not covered by the resist layer, and finally removing the resist layer to expose the metal pad; The physical sputtering is placed on the passivation layer by a photomask, and the photomask has a perforation corresponding to the electrode pad, the metal pad is formed by physical sputtering in the perforation, and the photomask is finally removed to expose the photomask. Metal pad.
請參閱第3A圖，接著對該晶圓20進行切割以形成複數半導體晶片20’，因此，本發明提供一種半導體元件，包括：半導體晶片20’，係具有相對應之作用面20a及非作用面20b，於該作用面20a上具有複數電極墊201；鈍 化層22，係設於該作用面20a及電極墊201上；以及金屬墊23，係設於該鈍化層22上，並對應該電極墊201。Referring to FIG. 3A, the wafer 20 is then diced to form a plurality of semiconductor wafers 20'. Accordingly, the present invention provides a semiconductor device comprising: a semiconductor wafer 20' having a corresponding active surface 20a and a non-active surface 20b, having a plurality of electrode pads 201 on the active surface 20a; blunt The layer 22 is disposed on the active surface 20a and the electrode pad 201; and the metal pad 23 is disposed on the passivation layer 22 and is disposed on the electrode pad 201.
該鈍化層22係由具有開孔220a以露出該電極墊201之第一鈍化層22a及形成於該第一鈍化層22a上並覆蓋該電極墊201之第二鈍化層22b所組成，其中該第一鈍化層22a係為氮化矽(Si3 N4 )，而該第二鈍化層22b係為聚醯亞胺(Polyimide)。該金屬墊23係為銅。The passivation layer 22 is composed of a first passivation layer 22a having an opening 220a to expose the electrode pad 201 and a second passivation layer 22b formed on the first passivation layer 22a and covering the electrode pad 201. A passivation layer 22a is tantalum nitride (Si 3 N 4 ), and the second passivation layer 22b is polyimide. The metal pad 23 is made of copper.
請參閱第3A至3H圖，係為接續將半導體晶片嵌埋於封裝基板之製法流程剖視圖。Please refer to FIGS. 3A to 3H , which are cross-sectional views showing a process flow for embedding a semiconductor wafer in a package substrate.
如第3A圖所示，提供一係如第2D圖之晶圓20，且該晶圓20經切割以形成複數半導體晶片20’，該半導體晶片20’具有相對應之作用面20a及非作用面20b，於該作用面20a上具有複數電極墊201及形成於該作用面20a上之鈍化層22，且於該鈍化層22上對應該電極墊201設有金屬墊23。As shown in FIG. 3A, a wafer 20 such as FIG. 2D is provided, and the wafer 20 is diced to form a plurality of semiconductor wafers 20' having corresponding active faces 20a and non-active surfaces. 20b, the active surface 20a has a plurality of electrode pads 201 and a passivation layer 22 formed on the active surface 20a, and a metal pad 23 is disposed on the passivation layer 22 corresponding to the electrode pads 201.
如第3B圖所示，提供一具有開口300之基板本體30，於該開口300中容置該半導體晶片20’，且於該半導體晶片20’及基板本體30上形成第一介電層31，該第一介電層31並填入該開口300與半導體晶片20’之間的間隙中，以將該半導體晶片20’固定於該開口300中。As shown in FIG. 3B, a substrate body 30 having an opening 300 is provided, the semiconductor wafer 20' is received in the opening 300, and a first dielectric layer 31 is formed on the semiconductor wafer 20' and the substrate body 30, The first dielectric layer 31 is filled in the gap between the opening 300 and the semiconductor wafer 20' to fix the semiconductor wafer 20' in the opening 300.
如第3C圖所示，利用例如二氧化碳雷射於該第一介電層31中形成介電層開孔310，並露出該金屬墊23之部份表面，藉由該金屬墊23阻擋以避免雷射貫穿該電極墊201。As shown in FIG. 3C, a dielectric layer opening 310 is formed in the first dielectric layer 31 by, for example, a carbon dioxide laser, and a portion of the surface of the metal pad 23 is exposed, and the metal pad 23 is blocked to avoid lightning. The light penetrates through the electrode pad 201.
如第3D圖所示，接著，依序移除該金屬墊23(以微蝕刻方式移除)再移除該鈍化層22，以形成鈍化層開孔220並露出該電極墊201，並使該金屬墊形成一金屬環23’。As shown in FIG. 3D, the metal pad 23 is sequentially removed (removed by micro-etching) and the passivation layer 22 is removed to form a passivation layer opening 220 and expose the electrode pad 201, and the The metal pad forms a metal ring 23'.
如第3E圖所示，於該電極墊201上、鈍化層開孔220、第一介電層31及該介電層開孔310表面形成導電層32，該導電層32主要作為後述電鍍金屬材料所需之電流傳導路徑，其可由金屬、合金或沉積數層金屬層所構成，或可使用導電高分子材料以作為該導電層32；然後，於該導電層32上形成阻層33，該阻層33係為乾膜或液態光阻等光阻層(Photoresist)，其係利用印刷、旋塗或貼合等方式形成於該導電層32表面，再藉由曝光、顯影等方式加以圖案化，使該阻層33中形成有複數阻層開口330，以露出該第一介電層31上之導電層32部份表面，以及介電層開孔310與鈍化層開孔220中之導電層32。As shown in FIG. 3E, a conductive layer 32 is formed on the surface of the electrode pad 201, the passivation layer opening 220, the first dielectric layer 31, and the dielectric layer opening 310. The conductive layer 32 is mainly used as a plating metal material to be described later. a desired current conduction path, which may be composed of a metal, an alloy or a plurality of deposited metal layers, or a conductive polymer material may be used as the conductive layer 32; then, a resist layer 33 is formed on the conductive layer 32, the resistance The layer 33 is a photoresist layer such as a dry film or a liquid photoresist, which is formed on the surface of the conductive layer 32 by printing, spin coating or lamination, and then patterned by exposure, development, or the like. A plurality of resist opening openings 330 are formed in the resist layer 33 to expose a portion of the surface of the conductive layer 32 on the first dielectric layer 31, and the conductive layer 32 in the dielectric layer opening 310 and the passivation layer opening 220. .
如第3F圖所示，藉由該導電層32作為電流傳導路徑，以於該阻層開口330中之導電層32上電鍍形成第一線路層34，且於該阻層開口330、介電層開孔310及鈍化層開孔220中形成第一導電盲孔341，以電性連接該電極墊201，且該第一導電盲孔341接觸該金屬環23’。As shown in FIG. 3F, the conductive layer 32 is used as a current conduction path to form a first wiring layer 34 on the conductive layer 32 in the barrier layer opening 330, and the barrier layer opening 330 and the dielectric layer are formed. A first conductive via hole 341 is formed in the opening 310 and the passivation layer opening 220 to electrically connect the electrode pad 201, and the first conductive blind hole 341 contacts the metal ring 23'.
如第3G圖所示，移除該阻層33及其所覆蓋之導電層32，以露出該第一介電層31及第一線路層34。As shown in FIG. 3G, the resist layer 33 and the conductive layer 32 covered thereon are removed to expose the first dielectric layer 31 and the first wiring layer 34.
如第3H圖所示，最後，於該第一介電層31及第一線路層34上形成增層結構35，該增層結構35係包括有至 少一第二介電層351、疊置於該第二介電層上之第二線路層352、以及複數形成於該第二介電層中並電性連接該第一線路層34及第二線路層352之第二導電盲孔353，並於該增層結構35具有電性連接該第二線路層352之電性接觸墊354，接著於該增層結構35上形成絕緣保護層36，且該絕緣保護層36中具有複數絕緣保護層開孔360，以對應露出該電性接觸墊354。Finally, as shown in FIG. 3H, finally, a build-up structure 35 is formed on the first dielectric layer 31 and the first circuit layer 34, and the build-up structure 35 includes a second dielectric layer 351, a second circuit layer 352 stacked on the second dielectric layer, and a plurality of dielectric layers 252 are electrically formed in the second dielectric layer and electrically connected to the first circuit layer 34 and the second a second conductive via 353 of the circuit layer 352, and an electrical contact pad 354 electrically connected to the second circuit layer 352, and then an insulating protective layer 36 is formed on the build-up structure 35, and The insulating protective layer 36 has a plurality of insulating protective layer openings 360 to correspondingly expose the electrical contact pads 354.
本發明復提供一種嵌埋有半導體元件之封裝基板，係包括：基板本體30，係具有至少一開口300；半導體晶片20’，係固定於該基板本體30之開口300中，該半導體晶片20’具有相對應之作用面20a及非作用面20b，於該作用面20a上具有複數電極墊201及設於該作用面20a上之鈍化層22，該鈍化層22具有對應該電極墊201之鈍化層開孔220；金屬環23’，係設於該鈍化層開孔220上；第一介電層31，係設於該基板本體30、鈍化層22及金屬環23’上，並對應該電極墊201形成貫穿之介電層開孔310，以露出該電極墊201；以及第一線路層34，係設置於該第一介電層31上，並於該介電層開孔310及鈍化層開孔220中設有第一導電盲孔341以電性連接該電極墊201，且該第一導電盲孔341接觸該金屬環23’。The present invention provides a package substrate in which a semiconductor device is embedded, comprising: a substrate body 30 having at least one opening 300; a semiconductor wafer 20' fixed in an opening 300 of the substrate body 30, the semiconductor wafer 20' There is a corresponding active surface 20a and a non-active surface 20b. The active surface 20a has a plurality of electrode pads 201 and a passivation layer 22 disposed on the active surface 20a. The passivation layer 22 has a passivation layer corresponding to the electrode pads 201. The opening 220; the metal ring 23' is disposed on the passivation layer opening 220; the first dielectric layer 31 is disposed on the substrate body 30, the passivation layer 22 and the metal ring 23', and the electrode pad is 201 is formed through the dielectric layer opening 310 to expose the electrode pad 201; and the first circuit layer 34 is disposed on the first dielectric layer 31, and is opened in the dielectric layer opening 310 and the passivation layer A first conductive blind via 341 is disposed in the hole 220 to electrically connect the electrode pad 201, and the first conductive blind via 341 contacts the metal ring 23'.
依上述結構，該鈍化層22係由具有開孔220a以露出該電極墊201之第一鈍化層22a及形成於該第一鈍化層22a上並覆蓋該電極墊201之第二鈍化層22b所組成，其中該第一鈍化層22a係為氮化矽(Si3 N4 )或二氧化矽 (SiO2 )，而該第二鈍化層22b係為聚醯亞胺(Polyimide)或苯並環丁烯(BCB)。According to the above structure, the passivation layer 22 is composed of a first passivation layer 22a having an opening 220a to expose the electrode pad 201 and a second passivation layer 22b formed on the first passivation layer 22a and covering the electrode pad 201. Wherein the first passivation layer 22a is tantalum nitride (Si 3 N 4 ) or hafnium oxide (SiO 2 ), and the second passivation layer 22b is polyimide or benzocyclobutene (BCB).
該第一介電層31及第一線路層34上設有增層結構35，該增層結構35係包括有至少一第二介電層351、疊置於該第二介電層上之第二線路層352、以及複數設於該第二介電層中並電性連接該第二線路層352之第二導電盲孔353，該第二導電盲孔353電性連接至該第一線路層34，並於該增層結構35具有電性連接該第二線路層352之電性接觸墊354，又於該增層結構35上設有絕緣保護層36，且該絕緣保護層36中具有複數絕緣保護層開孔360，以對應露出該電性接觸墊354。The first dielectric layer 31 and the first circuit layer 34 are provided with a build-up structure 35. The build-up structure 35 includes at least one second dielectric layer 351 and a plurality of stacked on the second dielectric layer. a second circuit layer 352, and a plurality of second conductive vias 353 disposed in the second dielectric layer and electrically connected to the second circuit layer 352. The second conductive via 353 is electrically connected to the first circuit layer. 34, and the electrical layer 354 is electrically connected to the second circuit layer 352, and the insulating layer 36 is provided on the layering structure 35, and the insulating layer 36 has a plurality of insulating layers 36. The insulating layer is opened 360 to correspondingly expose the electrical contact pad 354.
因此，本發明之半導體元件暨嵌埋有半導體元件之封裝基板及其製法，係將具有設於鈍化層上並相對該電極墊之金屬墊的晶圓切割成複數半導體晶片，將該半導體晶片設置於該基板本體之開口中，再以第一介電層形成於該半導體晶片及基板本體上，以將該半導體晶片固定於該基板本體之開口中，俾以免除習知以結合材料固定再形成介電層，而增加製程之缺失；接著，以雷射在第一介電層中形成介電層層開孔，並藉由該金屬墊阻擋以避免貫穿該電極墊，然後再移除該介電層開孔中之金屬墊及鈍化層，以露出該半導體晶片之電極墊，再於該第一介電層上形成第一線路層，並於該介電層開孔、鈍化層開孔中形成第一導電盲孔以電性連接該電極墊，俾可免除習知必須先製作擴充墊以保護電極墊，然後再形成增層結構之缺失，以降低晶 圓製程之成本與產品製作之時程；因此，本發明具有保護半導體晶片電極墊、並能直接電性導接及節省製程步驟之效果。Therefore, the semiconductor device of the present invention and the package substrate embedded with the semiconductor device and the method for manufacturing the same are to cut a wafer having a metal pad provided on the passivation layer and opposed to the electrode pad into a plurality of semiconductor wafers, and the semiconductor wafer is disposed Forming a first dielectric layer on the semiconductor wafer and the substrate body in the opening of the substrate body to fix the semiconductor wafer in the opening of the substrate body, so as to prevent the conventional material from being fixed by the bonding material. Dielectric layer, and adding a process defect; then, forming a dielectric layer opening in the first dielectric layer by laser, and blocking by the metal pad to avoid penetrating the electrode pad, and then removing the dielectric layer a metal pad and a passivation layer in the opening of the electrical layer to expose the electrode pad of the semiconductor wafer, and then forming a first circuit layer on the first dielectric layer, and in the opening of the dielectric layer and the opening of the passivation layer Forming a first conductive blind via to electrically connect the electrode pad, the germanium may be omitted to make an expansion pad to protect the electrode pad, and then forming a missing layer structure to reduce the crystal The cost of the round process and the time course of product manufacturing; therefore, the present invention has the effect of protecting the electrode pads of the semiconductor wafer, and being capable of direct electrical conduction and saving process steps.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10、20‧‧‧晶圓10, 20‧‧‧ wafer
101、201‧‧‧電極墊101, 201‧‧‧electrode pads
10a、20’‧‧‧半導體晶片10a, 20’‧‧‧ semiconductor wafer
11、22‧‧‧鈍化層11, 22‧‧‧ Passivation layer
110‧‧‧第一開孔110‧‧‧First opening
12‧‧‧黏著層12‧‧‧Adhesive layer
13‧‧‧保護層13‧‧‧Protective layer
14、30‧‧‧基板本體14, 30‧‧‧ substrate body
140、300‧‧‧開口140, 300‧‧‧ openings
15‧‧‧結合材料15‧‧‧Combined materials
16、32‧‧‧導電層16, 32‧‧‧ conductive layer
17、33‧‧‧阻層17, 33‧‧‧ resistance layer
170、330‧‧‧阻層開口170, 330‧‧‧ barrier opening
18‧‧‧擴充墊18‧‧‧Expansion pad
19、35‧‧‧增層結構19, 35‧‧ ‧ layered structure
191‧‧‧介電層191‧‧‧ dielectric layer
192‧‧‧線路層192‧‧‧circuit layer
193‧‧‧導電盲孔193‧‧‧ Conductive blind holes
194、354‧‧‧電性接觸墊194, 354‧‧‧Electrical contact pads
195、36‧‧‧絕緣保護層195, 36‧‧‧Insulating protective layer
1950、360‧‧‧絕緣保護層開孔1950, 360‧‧‧Insulation protective layer opening
20a‧‧‧作用面20a‧‧‧Action surface
20b‧‧‧非作用面20b‧‧‧Non-active surface
220‧‧‧鈍化層開孔220‧‧‧ Passivation layer opening
220a‧‧‧開孔220a‧‧‧ opening
22a‧‧‧第一鈍化層22a‧‧‧First passivation layer
22b‧‧‧第二鈍化層22b‧‧‧second passivation layer
23‧‧‧金屬墊23‧‧‧Metal pad
23’‧‧‧金屬環23’‧‧‧Metal ring
31‧‧‧第一介電層31‧‧‧First dielectric layer
310‧‧‧介電層開孔310‧‧‧Dielectric layer opening
34‧‧‧第一線路層34‧‧‧First line layer
341‧‧‧第一導電盲孔341‧‧‧First conductive blind hole
351‧‧‧第二介電層351‧‧‧Second dielectric layer
352‧‧‧第二線路層352‧‧‧second circuit layer
353‧‧‧第二導電盲孔353‧‧‧Second conductive blind hole
第1A至1L圖係顯示習知嵌埋有半導體元件之封裝基板製法的剖視示意圖；第2A至2D圖係為本發明中於晶圓作用面上形成鈍化層之製法的剖視示意圖；以及第3A至3H圖係為本發明之嵌埋有半導體元件之封裝基板製法之剖視示意圖。1A to 1L are schematic cross-sectional views showing a conventional method of manufacturing a package substrate in which a semiconductor element is embedded; and FIGS. 2A to 2D are cross-sectional views showing a method of forming a passivation layer on a wafer active surface in the present invention; 3A to 3H are schematic cross-sectional views showing a method of manufacturing a package substrate in which a semiconductor element is embedded in the present invention.
20’‧‧‧半導體晶片20’‧‧‧Semiconductor wafer
201‧‧‧電極墊201‧‧‧electrode pads
30‧‧‧基板本體30‧‧‧Substrate body
31‧‧‧第一介電層31‧‧‧First dielectric layer
34‧‧‧第一線路層34‧‧‧First line layer
341‧‧‧第一導電盲孔341‧‧‧First conductive blind hole
Claims (21)
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