TWI390545B - Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit - Google Patents
Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit Download PDFInfo
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- G—PHYSICS
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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Description
本發明主張2008年4月30日申請之韓國專利申請案第10-2008-0040371號之優先權,該案之全文以引用的方式併入本文中。The present invention claims priority to Korean Patent Application No. 10-2008-0040371, filed on Apr. 30, 2008, which is incorporated herein by reference.
本發明涉及用於在多種半導體積體電路中校準終端電阻值的一校準電路,及更特定言之,涉及一技術以減少在一校準電路中消耗的一電流量。The present invention relates to a calibration circuit for calibrating termination resistance values in a plurality of semiconductor integrated circuits, and more particularly to a technique for reducing the amount of current consumed in a calibration circuit.
不同的半導體裝置,諸如CPU、記憶體、閘陣列等等,其等是作為IC晶片而實現的,被併入不同的電子產品中,諸如個人電腦、伺服器或工作站。在大多數情況下,這些半導體裝置每個都具有一接收電路,其用於經由一輸入襯墊接收自一晶片的外部傳輸的多種信號,及一輸出電路,其用於經由一輸出襯墊提供輸出信號到外部。Different semiconductor devices, such as CPUs, memories, gate arrays, etc., are implemented as IC chips and incorporated into different electronic products, such as personal computers, servers or workstations. In most cases, these semiconductor devices each have a receiving circuit for receiving a plurality of signals transmitted from the outside of a wafer via an input pad, and an output circuit for providing via an output pad Output the signal to the outside.
同時,由於電子產品的操作速率增加,介接於半導體裝置之間之一信號的擺動寬度(就是,邏輯上低信號狀態和邏輯上高信號狀態之間的電壓差)已逐漸減少。這是為了最小化傳遞一信號引入的延遲時間所致。然而,由於信號的擺動寬度減少,外部雜訊的影響增加,且信號的反射係數由於一介面終端內的一阻抗失配也變得嚴重。阻抗失配是由於外部雜訊、電源電壓變化、操作溫度變化、生產過程改變,或等等而產生的。當一阻抗失配存在時,以一高速率傳輸資料是困難的,且自半導體裝置的一輸出終端所 輸出的輸出資料可能是失真的。因此,當一接收方的一半導體裝置經由一輸入終端接收失真的輸出信號時,可能頻繁地引起諸如設定/維持失敗或決定一輸入位準的一錯誤等問題。At the same time, as the operating rate of the electronic product increases, the wobble width of the signal interposed between the semiconductor devices (that is, the voltage difference between the logically low signal state and the logically high signal state) has gradually decreased. This is to minimize the delay time introduced by passing a signal. However, as the swing width of the signal decreases, the influence of external noise increases, and the reflection coefficient of the signal becomes severe due to an impedance mismatch in an interface terminal. Impedance mismatches are caused by external noise, changes in supply voltage, changes in operating temperature, changes in production processes, or the like. When an impedance mismatch exists, it is difficult to transmit data at a high rate, and from an output terminal of the semiconductor device The output data of the output may be distorted. Therefore, when a semiconductor device of a receiving side receives a distorted output signal via an input terminal, problems such as setting/maintenance failure or an error determining an input level may be frequently caused.
特定言之,記憶裝置,其等需要一高操作速率,使用在一積體電路晶片內圍繞一襯墊稱為'晶粒終端上'的一阻抗匹配電路用於解決上述問題。代表性地,在'晶粒終端上'方案下,一源終端是由一輸出電路在一傳輸方執行的,及一並行終端是由一終端電路執行的,該終端電路並行連接至在一接收方連接至輸入襯墊的一接收電路。In particular, memory devices, which require a high operating rate, are used in an integrated circuit wafer to surround a pad called an 'impedance termination circuit' to solve the above problem. Typically, under the 'die termination' scheme, a source terminal is executed by an output circuit on a transmission side, and a parallel terminal is executed by a terminal circuit connected in parallel to a reception. The square is connected to a receiving circuit of the input pad.
ZQ校準指示一程序以產生隨PVT(過程、電壓、溫度)的條件而變化的一校準代碼。終端電阻值(在記憶裝置的情況下,一DC襯墊方的終端電阻值)使用作為ZQ校準的結果產生的校準代碼而調整。(由於校準是使用一ZQ節點就是用於校準的一節點執行的,它稱為'ZQ校準'。)The ZQ calibration indicates a procedure to generate a calibration code that varies with the conditions of the PVT (process, voltage, temperature). The termination resistance value (in the case of a memory device, the terminal resistance value of a DC pad side) is adjusted using a calibration code generated as a result of the ZQ calibration. (Because calibration is performed using a ZQ node that is used for calibration, it is called 'ZQ calibration'.)
在下文中,在一校準電路中用於控制電阻值之一校準代碼的產生將在下面描述。In the following, the generation of a calibration code for controlling the resistance value in a calibration circuit will be described below.
圖1是一校準電路的電路圖,該校準電路用於按照一習知技術控制在一記憶裝置中的一終端電阻值。1 is a circuit diagram of a calibration circuit for controlling a terminal resistance value in a memory device in accordance with a conventional technique.
參照圖1,習知的校準電路經組態為包含一校準單元110,其對應於直接地產生一校準代碼PCODE<0:N>的一部分,及一校準控制單元120用於控制校準單元110的一操作。Referring to FIG. 1, a conventional calibration circuit is configured to include a calibration unit 110 corresponding to a portion directly generating a calibration code PCODE<0:N>, and a calibration control unit 120 for controlling the calibration unit 110. An operation.
校準單元110包含一第一上拉電阻單元111、一第二上拉 電阻單元112、一下拉電阻單元113、比較器114和115、及計數器117和118。校準單元110產生校準代碼PCODE<0:N>和NCODE<0:N>,及校準單元110的操作是否是啟用的且校準單元110的操作時間是由校準控制單元120控制的。The calibration unit 110 includes a first pull-up resistor unit 111 and a second pull-up The resistor unit 112, the pull-up resistor unit 113, the comparators 114 and 115, and the counters 117 and 118. The calibration unit 110 generates calibration codes PCODE<0:N> and NCODE<0:N>, and whether the operation of the calibration unit 110 is enabled and the operation time of the calibration unit 110 is controlled by the calibration control unit 120.
在操作中,比較器114比較一ZQ節點的一電壓和一參考電壓VREF(其一般設定為VDDQ/2)以產生一UP/DOWN信號,該ZQ節點係藉由將一連接到一ZQ襯墊的參考電阻器101(其是晶片的一外部電阻器,一般是240 Ω)與第一上拉電阻單元111連接而產生。In operation, comparator 114 compares a voltage of a ZQ node with a reference voltage VREF (which is typically set to VDDQ/2) to generate an UP/DOWN signal by connecting one to a ZQ pad. The reference resistor 101 (which is an external resistor of the wafer, typically 240 Ω) is connected to the first pull-up resistor unit 111.
計數器117接收UP/DOWN信號以產生一二進制代碼PCODE<0:N>,及使用產生的二進制代碼PCODE<0:N>開啟/關閉並行連接地第一上拉電阻單元111的電阻器以控制電阻值。第一上拉電阻單元111的控制的電阻值又影響ZQ節點的電壓,且上述的操作是重複的。就是,第一上拉電阻單元111被校準(也就是,上拉校準)使得第一上拉電阻單元111的一總電阻值(其一般是240 Ω)等於參考電阻器101的電阻值。The counter 117 receives the UP/DOWN signal to generate a binary code PCODE<0:N>, and turns on/off the resistor of the first pull-up resistor unit 111 connected in parallel using the generated binary code PCODE<0:N> to control the resistance. value. The controlled resistance value of the first pull-up resistor unit 111 in turn affects the voltage of the ZQ node, and the above operations are repeated. That is, the first pull-up resistor unit 111 is calibrated (that is, pulled up) so that a total resistance value of the first pull-up resistor unit 111 (which is generally 240 Ω) is equal to the resistance value of the reference resistor 101.
在上述的上拉校準期間產生的二進制代碼PCODE<0:N>被輸入第二上拉電阻單元112(其輿第一上拉電阻單元111有相同的構造並接收相同的代碼,產生相同的電阻值)以決定第二上拉電阻單元112的一總電阻值。其次,下拉校準操作啟動。與上拉校準的情況相似,下拉校準之執行係使用比較器115和控制器117使得一節點的一電壓等於參考電壓VREF,也就是,下拉電阻單元113的一總電阻值等 於第二上拉電阻單元112的一總電阻值。上拉校準代碼PCODE<0:N>和下拉校準代碼NCODE<0:N>是作為上述校準的結果而產生的,其被輸入半導體記憶裝置的輸出終端(DC襯墊方)的上拉和下拉電阻單元(其和校準單元的上拉和下拉電阻單元的構造相同)以決定終端電阻值。The binary code PCODE<0:N> generated during the above pull-up calibration is input to the second pull-up resistor unit 112 (the first pull-up resistor unit 111 has the same configuration and receives the same code, generating the same resistance Value) to determine a total resistance value of the second pull-up resistor unit 112. Second, the pull-down calibration operation starts. Similar to the case of the pull-up calibration, the pull-down calibration is performed using the comparator 115 and the controller 117 such that a voltage of one node is equal to the reference voltage VREF, that is, a total resistance value of the pull-down resistor unit 113, etc. A total resistance value of the second pull-up resistor unit 112. The pull-up calibration codes PCODE<0:N> and the pull-down calibration codes NCODE<0:N> are generated as a result of the above calibration, which is input to the pull-up and pull-down of the output terminal (DC pad side) of the semiconductor memory device. A resistor unit (which is identical in construction to the pull-up and pull-down resistor units of the calibration unit) to determine the termination resistance value.
也就是說,半導體記憶裝置的資料輸出電路使用由上拉校準代碼和下拉校準代碼決定的終端電阻值終止資料的輸入/輸出節點至一上拉位準(當一'high(高)'資料被輸出時)或下拉位準(當一'low(低)'資料被輸出時)以輸出資料。That is, the data output circuit of the semiconductor memory device terminates the input/output node of the data to a pull-up level using the termination resistance value determined by the pull-up calibration code and the pull-down calibration code (when a 'high' profile is used When outputting) or pull-down level (when a 'low' is output) to output data.
上述校準操作的啟用是由校準控制單元120執行的。當一校準命令啟用時,校準控制單元120控制校準單元110以啟動校準操作。取決於校準操作模式(也就是,ZQInit、ZQOper、ZQCS),校準控制單元120差異性控制校準操作時間。對校準操作模式(也就是,ZQInit、ZQOper、ZQCS)和校準控制單元120詳細的描述將會參考附圖在下文給出。The activation of the above calibration operation is performed by the calibration control unit 120. When a calibration command is enabled, the calibration control unit 120 controls the calibration unit 110 to initiate a calibration operation. Depending on the calibration mode of operation (ie, ZQInit, ZQOper, ZQCS), the calibration control unit 120 differentially controls the calibration operation time. A detailed description of the calibration mode of operation (i.e., ZQInit, ZQOper, ZQCS) and calibration control unit 120 will be given below with reference to the drawings.
圖2依照校準操作模式(也就是,ZQInit、ZQOper、ZQCS)(JEDEC標準)顯示一校準命令(ZQC)真值表和時序參數。Figure 2 shows a calibration command (ZQC) truth table and timing parameters in accordance with the calibration mode of operation (i.e., ZQInit, ZQOper, ZQCS) (JEDEC standard).
校準命令(ZQC)藉由/CS(晶片選擇信號)、/RAS(列位址選通信號)、/CAS(行位址選通信號)、/WE(寫啟用信號)的一組合而被啟用,也就是,諸如在圖2上方顯示的/CS='Low'、/RAS='High'、/CAS='High'、/WE='High'。The calibration command (ZQC) is enabled by a combination of /CS (wafer select signal), /RAS (column address strobe signal), /CAS (row address strobe signal), /WE (write enable signal) That is, /CS='Low', /RAS='High', /CAS='High', /WE='High', such as shown at the top of FIG.
校準被分成一長校準和一短校準,其是藉由在校準命令被啟用之一狀態下A10之邏輯位準係高還是低而決定的。The calibration is divided into a long calibration and a short calibration, which is determined by whether the logic level of A10 is high or low in the state in which the calibration command is enabled.
校準操作時間在圖2的下方顯示。詳細地,長校準包含兩種模式,也就是,在一電力開啟後首先被執行的ZQInit,及ZQOper,其是當記憶裝置操作時藉由自一記憶控制器的一輸入產生的。ZQInit和ZQOper的時間根據時脈分別地是512個循環和256個循環。短校準的操作時間是64個循環。The calibration operation time is shown at the bottom of Figure 2. In detail, the long calibration includes two modes, that is, ZQInit, which is executed first after a power is turned on, and ZQOper, which is generated by an input from a memory controller when the memory device operates. The time of ZQInit and ZQOper is 512 cycles and 256 cycles, respectively, depending on the clock. The short calibration operation time is 64 cycles.
圖3是一方塊圖,其顯示圖1的校準控制單元120的一構造。FIG. 3 is a block diagram showing a configuration of the calibration control unit 120 of FIG. 1.
參照圖3,校準控制單元120經組態為包含一計數單元310和一控制單元320。Referring to FIG. 3, the calibration control unit 120 is configured to include a counting unit 310 and a control unit 320.
計數單元310計數一時脈以輸出一計數代碼CNTR_OUT<0:N>。詳細地,無論一時脈CLK何時被啟用當校準命令ZQC被啟用時計數單元310增加來自其中的一代碼CNTR_OUT<0:N>的一值。The counting unit 310 counts a clock to output a count code CNTR_OUT<0:N>. In detail, regardless of when a clock CLK is enabled, the counting unit 310 increases a value from one of the codes CNTR_OUT<0:N> when the calibration command ZQC is enabled.
控制單元320依照校準操作模式允許校準單元110被啟用直到計數代碼CNTR_OUT<0:N>的值達到一預先確定的值。例如,在短校準(ZQCS被啟用)期間,控制單元320允許校準單元110被啟用直到計數代碼CNTR_OUT<0:N>的值達到64。在長校準校準期間,如果ZQInit被啟用,則控制單元320允許校準單元110被啟用直到計數代碼CNTR_OUT<0:N>的值達到512,及如果ZQOper被啟用,則控制單元320允許校準單元110被啟用直到計數代碼CNTR_OUT<0:N>的值達到256。The control unit 320 allows the calibration unit 110 to be enabled in accordance with the calibration mode of operation until the value of the count code CNTR_OUT<0:N> reaches a predetermined value. For example, during short calibration (ZQCS is enabled), control unit 320 allows calibration unit 110 to be enabled until the value of count code CNTR_OUT<0:N> reaches 64. During long calibration calibration, if ZQInit is enabled, control unit 320 allows calibration unit 110 to be enabled until the value of count code CNTR_OUT<0:N> reaches 512, and if ZQOper is enabled, control unit 320 allows calibration unit 110 to be Enable until the value of the count code CNTR_OUT<0:N> reaches 256.
自控制單元320輸出的啟用信號CAL_OPER允許比較器 114和115在一設定時脈循環期間被啟用使得校準操作是可能的。如果比較器114和115未能執行一比較操作,則其不可能產生校準代碼PCODE<0:N>和NCODE<0:N>。因此,啟用信號CAL_OPER也可稱作為校準單元110的一啟用信號。更新信號UPDATE允許計數器117和118封鎖校準代碼PCODE<0:N>和NCODE<0:N>,及用以防止由於上拉校準代碼PCODE<0:N>和下拉校準代碼NCODE<0:N>之間一延遲差別造成的一短時脈干擾(glitch)。The enable signal CAL_OPER output from the control unit 320 allows the comparator 114 and 115 are enabled during a set clock cycle such that a calibration operation is possible. If the comparators 114 and 115 fail to perform a comparison operation, it is impossible to generate the calibration codes PCODE<0:N> and NCODE<0:N>. Therefore, the enable signal CAL_OPER can also be referred to as an enable signal of the calibration unit 110. The update signal UPDATE allows the counters 117 and 118 to block the calibration codes PCODE<0:N> and NCODE<0:N>, and to prevent the pull-up calibration code NCODE<0:N> due to the pull-up calibration code PCODE<0:N> and pull-down. A short glitch caused by a delay difference.
總的來說,校準控制單元120控制校準單元110使得當校準命令ZQC被啟用時,校準單元110可產生正確的校準代碼PCODE<0:N>和NCODE<0:N>。In general, the calibration control unit 120 controls the calibration unit 110 such that when the calibration command ZQC is enabled, the calibration unit 110 can generate the correct calibration codes PCODE<0:N> and NCODE<0:N>.
圖4是一時序圖,其顯示記憶裝置的校準操作之前和之後的操作。Figure 4 is a timing diagram showing the operation before and after the calibration operation of the memory device.
參照圖4,可證實的是不管是長校準ZQCL或短校準ZQCS,在校準操作之前和之後一預先確定的時間期間,只有一NOP(非操作)命令或一取消選擇(DESELECT)命令自記憶控制器被輸入。Referring to FIG. 4, it can be confirmed that whether it is a long calibration ZQCL or a short calibration ZQCS, only one NOP (non-operation) command or one deselect (DESELECT) command self-memory control during a predetermined time before and after the calibration operation. The device is input.
當記憶裝置執行校準操作時,一資料輸入/輸出接腳DQ匯流排維持一高阻抗(Hi-Z)狀態,且資料是自然地不被輸入或輸出。此是因為只有當一正確的終端電阻值由校準操作決定時其才可能正確地輸入或輸出資料。When the memory device performs the calibration operation, a data input/output pin DQ busbar maintains a high impedance (Hi-Z) state, and the data is naturally not input or output. This is because it is only possible to correctly input or output data when a correct termination resistance value is determined by the calibration operation.
圖5是一原理圖,其顯示一DDR3記憶裝置的不同操作。Figure 5 is a schematic diagram showing the different operations of a DDR3 memory device.
聚焦於圖5中的一框501是必要的。參照圖5,一校準操作只有當一記憶裝置是一閒置狀態時才可被執行。Focusing on a frame 501 in Figure 5 is necessary. Referring to Figure 5, a calibration operation can only be performed when a memory device is in an idle state.
圖1的校準控制單元120接收和計數一時脈以便測量當一校準操作被啟用時的一時間。The calibration control unit 120 of FIG. 1 receives and counts a clock to measure a time when a calibration operation is enabled.
輸入至校準控制單元120中的時脈CLK總是以一切換狀態被輸入。儘管校準控制單元120中的計數單元310當一校準操作不被執行時並不輸出其中的輸出值CNTR_OUT<0:N>,計數單元310仍由於一切換時脈而繼續消耗一不必要的電流。The clock CLK input to the calibration control unit 120 is always input in a switching state. Although the counting unit 310 in the calibration control unit 120 does not output the output value CNTR_OUT<0:N> when a calibration operation is not performed, the counting unit 310 continues to consume an unnecessary current due to a switching clock.
亦即,由於在習知的技術中輸入至校準控制單元120中的時脈總是在切換,造成校準控制單元120不必要地消耗一電流之問題。That is, since the clock input to the calibration control unit 120 is always switching in the prior art, the calibration control unit 120 unnecessarily consumes a current problem.
本發明的實施例針對於提供一半導體記憶裝置,該半導體記憶裝置藉由在校準電路被啟用時選擇性地提供用於測量一時間的一時脈而減少一校準電路中之一電流消耗量。Embodiments of the present invention are directed to providing a semiconductor memory device that reduces a current consumption in a calibration circuit by selectively providing a clock for measuring a time when the calibration circuit is enabled.
按照本發明的一態樣,本發明提供一校準單元,其經組態為產生用於控制一終端電阻值的一校準代碼;一校準控制單元,其經組態為在一預先確定的時脈期間計數一時脈並允許該校準單元被啟用;及一時脈控制單元,其經組態為依照使用校準電路的一半導體裝置的一操作模式選擇性地提供時脈至校準控制單元。According to one aspect of the invention, the present invention provides a calibration unit configured to generate a calibration code for controlling a terminal resistance value; a calibration control unit configured to be at a predetermined clock A clock is counted during the period and the calibration unit is enabled; and a clock control unit configured to selectively provide a clock to the calibration control unit in accordance with an operational mode of a semiconductor device using the calibration circuit.
在下文中,將參考附圖詳細描述按照本發明的一半導體記憶裝置。Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail with reference to the accompanying drawings.
圖6是一電路圖,其指示按照本發明的一實施例的一校 準電路。Figure 6 is a circuit diagram indicating a school in accordance with an embodiment of the present invention Quasi-circuit.
參照圖6,該校準電路經組態為包含一校準單元610、一校準控制單元620、及一時脈控制單元630。Referring to FIG. 6, the calibration circuit is configured to include a calibration unit 610, a calibration control unit 620, and a clock control unit 630.
校準單元610產生一校準代碼PCODE<0:N>用於控制一終端電阻值。校準單元610可輿習知的校準單元(圖1的110)有相同的構造。雖然圖1的校準單元110可產生上拉校準代碼PCODE<0:N>和下拉校準代碼NCODE<0:N>兩者,圖6的校準單元610可自然地經組態為僅產生上拉校準代碼PCODE<0:N>或下拉校準代碼NCODE<0:N>。Calibration unit 610 generates a calibration code PCODE<0:N> for controlling a terminal resistance value. The calibration unit 610 has the same configuration as the conventional calibration unit (110 of Fig. 1). Although the calibration unit 110 of FIG. 1 can generate both pull up calibration codes PCODE<0:N> and pull down calibration codes NCODE<0:N>, the calibration unit 610 of FIG. 6 can naturally be configured to generate only pull up calibrations. Code PCODE<0:N> or pull-down calibration code NCODE<0:N>.
在一記憶裝置的情況下,在校準單元610中產生的一校準代碼PCODE<0:N>或NCODE<0:N>被傳送至一資料輸出電路,以控制一上拉終端電阻值或一下拉終端電阻值,及該資料輸出電路終止一資料輸入/輸出節點(DQ節點)為一上拉或下拉,以輸出一'high'資料或'low資料'至一晶片的一外部。In the case of a memory device, a calibration code PCODE<0:N> or NCODE<0:N> generated in the calibration unit 610 is transmitted to a data output circuit to control a pull-up terminal resistance value or pull-down The terminal resistance value, and the data output circuit terminates a data input/output node (DQ node) as a pull-up or pull-down to output a 'high' data or 'low data' to an external portion of a wafer.
校準控制單元620計數一時脈CLK_2以允許校準單元610在一預先確定的時間期間被啟用。就像習知的校準控制單元(圖1和3的120),校準控制單元620經組態為包含一計數單元310,其計數該時脈CLK_2以輸出一計數代碼CNTR_OUT<0:N>,及一控制單元320,其允許校準單元610依照校準操作模式(ZQInit、ZQOper、ZQCS)被啟用直到計數代碼CNTR_OUT<0:N>的一值達到一常數值(例如,512、256、64)。The calibration control unit 620 counts a clock CLK_2 to allow the calibration unit 610 to be enabled during a predetermined time period. Like the conventional calibration control unit (120 of FIGS. 1 and 3), the calibration control unit 620 is configured to include a counting unit 310 that counts the clock CLK_2 to output a count code CNTR_OUT<0:N>, and A control unit 320 that allows the calibration unit 610 to be enabled in accordance with the calibration mode of operation (ZQInit, ZQOper, ZQCS) until a value of the count code CNTR_OUT<0:N> reaches a constant value (eg, 512, 256, 64).
時脈控制單元630依照使用校準電路的一半導體裝置的 一操作狀態選擇性地提供該時脈CLK_2至校準控制單元620。The clock control unit 630 is in accordance with a semiconductor device using a calibration circuit The operating state selectively provides the clock CLK_2 to the calibration control unit 620.
當使用校準電路的一半導體裝置不執行諸如資料輸入/輸出的一操作時,校準操作被執行。例如,在一記憶裝置的情況下,當記憶裝置如先前在先前技術中描述的是一閒置狀態時校準操作被執行。The calibration operation is performed when a semiconductor device using the calibration circuit does not perform an operation such as data input/output. For example, in the case of a memory device, a calibration operation is performed when the memory device is in an idle state as previously described in the prior art.
時脈控制單元630只有當一半導體裝置可執行校準操作時提供一時脈至校準控制單元620。雖然半導體裝置執行一資料輸入/輸出操作,但校準操作不被執行,且在這樣一周期期間,時脈CLK_2不被提供至校準控制單元620使得校準控制單元620不消耗不必要的電流。The clock control unit 630 provides a clock to the calibration control unit 620 only when a semiconductor device can perform a calibration operation. Although the semiconductor device performs a data input/output operation, the calibration operation is not performed, and during such a period, the clock CLK_2 is not supplied to the calibration control unit 620 such that the calibration control unit 620 does not consume unnecessary current.
圖6顯示時脈控制單元630回應記憶裝置的閒置信號IDLE決定是否提供時脈CLK_2至校準控制單元620。當閒置信號被啟用為'high',時脈控制單元630提供一輸入時脈CLK_1至校準控制單元620而沒有任何改變(CLK_1=CLK_2)。然而,當該閒置信號IDLE被停用為'low'時,時脈控制單元630對校準控制單元620提供只有一常數位準的一信號,也就是,一非切換信號(CLK_2='low')。FIG. 6 shows that the clock control unit 630 determines whether to provide the clock CLK_2 to the calibration control unit 620 in response to the idle signal IDLE of the memory device. When the idle signal is enabled to 'high', the clock control unit 630 provides an input clock CLK_1 to the calibration control unit 620 without any change (CLK_1 = CLK_2). However, when the idle signal IDLE is deactivated to 'low', the clock control unit 630 supplies the calibration control unit 620 with a signal having only one constant level, that is, a non-switching signal (CLK_2='low'). .
圖7是一電路圖,其用於描述圖6的閒置信號IDLE。Figure 7 is a circuit diagram for describing the idle signal IDLE of Figure 6.
該閒置信號IDLE是由組合記憶裝置組的啟動信號(RACT0、1、2、3)而產生的。在圖7中,RACT#信號是每個組的一啟動信號。也就是,RACT0是啟動組0的一信號,RACT1、2、3是分別啟動組1、2及3的信號。The idle signal IDLE is generated by the start signal (RACT0, 1, 2, 3) of the combined memory device group. In Figure 7, the RACT# signal is a start signal for each group. That is, RACT0 is a signal for starting group 0, and RACT 1, 2, and 3 are signals for starting groups 1, 2, and 3, respectively.
當RACT0、1、2、3信號都被停用為'low'時,閒置信號 IDLE被啟用為'high',且當RACT0、1、2、3信號的至少一個被啟用為'high'時,該閒置信號IDLE被停用為'low'。Idle signal when RACT0, 1, 2, 3 signals are deactivated to 'low' IDLE is enabled as 'high', and when at least one of the RACT0, 1, 2, 3 signals is enabled to 'high', the idle signal IDLE is deactivated to 'low'.
亦即,當所有組都未被啟動時,閒置信號IDLE被啟用,因此通知記憶裝置不執行任何操作。That is, when all the groups are not activated, the idle signal IDLE is enabled, so the memory device is notified not to perform any operation.
現在,依照本發明一實施例的一校準操作方法將參考圖6和7被描述。Now, a calibration operation method in accordance with an embodiment of the present invention will be described with reference to FIGS. 6 and 7.
依照本發明的一實施例的校準操作方法包含:依照使用一校準電路的一半導體裝置的一操作模式決定時脈CLK_2的一提供部分及在決定的提供部分期間提供時脈CLK_2;計數提供的時脈CLK_2以決定校準操作的一啟用時間;及在決定的啟用時間期間產生一校準代碼PCODE<0:N>或NCODE<0:N>。A calibration operation method according to an embodiment of the present invention includes: determining a supply portion of the clock CLK_2 according to an operation mode of a semiconductor device using a calibration circuit and providing a clock CLK_2 during the determined supply portion; The pulse CLK_2 determines an enable time of the calibration operation; and generates a calibration code PCODE<0:N> or NCODE<0:N> during the determined enable time.
在此,在校準操作的啟用時間期間時脈CLK_2切換的數量依照校準操作模式而改變。Here, the number of clock CLK_2 switchings during the enable time of the calibration operation changes in accordance with the calibration operation mode.
同樣地,時脈CLK_2的提供部分對應於半導體裝置的閒置狀態。Likewise, the supply portion of the clock CLK_2 corresponds to the idle state of the semiconductor device.
依照上面描述的本發明,用於測量一校準電路之一啟用時間的一時脈被選擇性地輸入進校準電路,因此由於一不必要的時脈切換的一電力消耗可被避免。According to the invention as described above, a clock for measuring the activation time of one of the calibration circuits is selectively input to the calibration circuit, so that a power consumption due to an unnecessary clock switching can be avoided.
雖然本發明已經關於特定的實施例被描述,對熟習此項技術者明顯的是在不脫離本發明在下面的請求項中定義的精神和範疇下,可做出不同的改變和修飾。While the present invention has been described with respect to the specific embodiments, it is apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.
特定言之,雖然上面的實施例顯示和描述用在記憶裝置中的校準電路,對熟習此項技術者明顯的是即使當依照本 發明的實施例之校準電路被應用於半導體裝置而不是記憶裝置時,如果半導體裝置經組態為依照半導體裝置是否在一校準操作狀態而選擇性地提供一時脈,則由校準電路消耗的一電流量可被減少。In particular, although the above embodiments show and describe the calibration circuit used in the memory device, it is apparent to those skilled in the art that even when When the calibration circuit of the embodiment of the invention is applied to a semiconductor device instead of a memory device, if the semiconductor device is configured to selectively provide a clock in accordance with whether the semiconductor device is in a calibration operation state, a current consumed by the calibration circuit The amount can be reduced.
101‧‧‧參考電阻器101‧‧‧Reference resistor
110‧‧‧校準單元110‧‧‧ calibration unit
111‧‧‧第一上拉電阻單元111‧‧‧First pull-up resistor unit
112‧‧‧第二上拉電阻單元112‧‧‧Second pull-up resistor unit
113‧‧‧下拉電阻單元113‧‧‧ Pull-down resistor unit
114‧‧‧比較器114‧‧‧ comparator
115‧‧‧比較器115‧‧‧ Comparator
117‧‧‧計數器117‧‧‧ counter
118‧‧‧計數器118‧‧‧ counter
120‧‧‧校準控制單元120‧‧‧calibration control unit
310‧‧‧計數單元310‧‧‧counting unit
320‧‧‧控制單元320‧‧‧Control unit
610‧‧‧校準單元610‧‧‧calibration unit
620‧‧‧校準控制單元620‧‧‧calibration control unit
630‧‧‧時脈控制單元630‧‧‧clock control unit
圖1是按照一習知技術用於控制一記憶裝置中一終端電阻值的一校準電路的一電路圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a calibration circuit for controlling a terminal resistance value in a memory device in accordance with a conventional technique.
圖2依照校準操作模式(也就是ZQInit、ZQOper、ZQCS)(JEDEC標準)顯示一校準命令(ZQC)真值表和時序參數。Figure 2 shows a calibration command (ZQC) truth table and timing parameters in accordance with the calibration mode of operation (i.e., ZQInit, ZQOper, ZQCS) (JEDEC standard).
圖3是一方塊圖,其顯示圖1中校準控制單元120的一構造。FIG. 3 is a block diagram showing a configuration of the calibration control unit 120 of FIG. 1.
圖4是一時序圖,其顯示記憶裝置的校準操作之前和之後的操作。Figure 4 is a timing diagram showing the operation before and after the calibration operation of the memory device.
圖5是一原理圖,其顯示一DDR3記憶裝置的不同操作。Figure 5 is a schematic diagram showing the different operations of a DDR3 memory device.
圖6是一電路圖,其指示按照本發明的一實施例的一校準電路。Figure 6 is a circuit diagram showing a calibration circuit in accordance with an embodiment of the present invention.
圖7是一電路圖,其用於描述圖6的閒置信號IDLE。Figure 7 is a circuit diagram for describing the idle signal IDLE of Figure 6.
610‧‧‧校準單元610‧‧‧calibration unit
620‧‧‧校準控制單元620‧‧‧calibration control unit
630‧‧‧時脈控制單元630‧‧‧clock control unit
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