TWI390398B - Method and system for monitoring and processing running status of a computer - Google Patents
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Description
本發明涉及一種電腦運行狀態偵測及處理方法和系統。 The invention relates to a computer operating state detection and processing method and system.
當機是用戶在使用電腦過程中最常見、最複雜的故障之一,也是造成企業服務中斷的主要原因之一。所謂當機,通常是指電腦顯示幕幕上有顯示內容,但電腦長時間處於不運行狀態。造成當機的原因很多,有可能是電腦受病毒感染、電腦硬體發生故障、軟體衝突、硬體與軟體衝突等等。 Downtime is one of the most common and complex failures in the process of using a computer, and it is one of the main causes of business interruption. The so-called crash, usually refers to the display content on the computer display screen, but the computer is not running for a long time. There are many reasons for the crash, which may be caused by computer infection, computer hardware failure, software conflict, hardware and software conflicts.
目前電腦系統當機的偵測及處理方式,大部分是由電腦將其本身定時記錄的系統狀態透過網路回報給遠端單位(伺服器或網管人員)處理,該遠端單位則根據接收的數值資料,判斷受其監控的電腦是否正常運作。若發生異常,則該遠端系統透過網路傳送系統重置信號至受監控的電腦系統。 At present, most of the detection and processing methods of computer system crashes are reported by the computer to the remote unit (server or network administrator) through the network, and the remote unit is based on the received Numerical data to determine whether the computer being monitored is functioning properly. If an abnormality occurs, the remote system transmits a system reset signal to the monitored computer system via the network.
上述遠端監控方法涉及複雜的資料交換協定,同時又必須考慮網路的安全性問題,一般必須依賴昂貴的晶片(如BMC(Baseboard Management Controller)控制晶片)與配套的處理軟體,才能避免系統長時間處於當機狀態。 The remote monitoring method involves complex data exchange protocols, and must consider the security of the network. Generally, it must rely on expensive chips (such as BMC (Baseboard Management Controller) control chips) and supporting processing software to avoid system length. The time is in a state of being down.
鑒於以上內容,有必要提供一種電腦運行狀態偵測及處理方法和系統,可有效偵測並處理電腦死機狀態,且能降低電路設計成本。 In view of the above, it is necessary to provide a computer operating state detection and processing method and system, which can effectively detect and deal with the computer crash state, and can reduce the circuit design cost.
一種電腦運行狀態偵測及處理系統,用於偵測電腦是否處於正常運行狀態,並當電腦運行發生異常時,自動重啟電腦。所述電腦包括超級輸入輸出晶片、可編程邏輯元件、南橋晶片及設備驅動程式。所述設備驅動程式用於控制所述超級輸入輸出晶片產生並發送一個狀態偵測開始信號至可編程邏輯元件,並用於控制所述超級輸入輸出晶片產生並發送週期性信號至可編程邏輯元件。所述可編程邏輯元件用於接收超級輸入輸出晶片發送的狀態偵測開始信號,並用於當超過預設時間未收到超級輸入輸出晶片發送的週期性信號時,發送一個重啟信號至南橋晶片。所述的南橋晶片用於在收到可編程邏輯元件發送的重啟信號後,重新啟動電腦。 A computer running state detecting and processing system for detecting whether a computer is in a normal running state, and automatically restarting the computer when an abnormality occurs in the running of the computer. The computer includes a super input and output chip, a programmable logic element, a south bridge chip, and a device driver. The device driver is configured to control the super input and output wafer to generate and send a state detection start signal to the programmable logic device, and to control the super input and output wafer to generate and send a periodic signal to the programmable logic device. The programmable logic component is configured to receive a state detection start signal sent by the super input/output chip, and is configured to send a restart signal to the south bridge chip when the periodic signal sent by the super input/output chip is not received within a preset time. The south bridge chip is used to restart the computer after receiving the restart signal sent by the programmable logic element.
一種電腦運行狀態偵測及處理方法,用於偵測電腦是否處於正常運行狀態,該電腦包括超級輸入輸出晶片、可編程邏輯元件及南橋晶片,該方法包括以下步驟:(A)電腦的設備驅動程式控制所述超級輸入輸出晶片產生並發送一個狀態偵測開始信號至可編程邏輯元件;(B)可編程邏輯元件接收超級輸入輸出晶片發送的偵測開始信號;(C)可編程邏輯元件的計時器開始計時;(D)判斷可編程邏輯元件是否收到超級輸入輸出晶片發送的週期性信號;(E)若未收到所述週期性信號,則判斷計時器計時是否超過預設時間;(F)若計時器計時超過預設時間,則發送重啟信號至南橋晶片;(G)南橋晶片重啟電腦。 A computer running state detecting and processing method for detecting whether a computer is in a normal running state, the computer comprising a super input and output chip, a programmable logic component and a south bridge chip, the method comprising the following steps: (A) a computer device driver The program controls the super input/output chip to generate and send a status detection start signal to the programmable logic element; (B) the programmable logic element receives the detection start signal sent by the super input/output chip; (C) the programmable logic element The timer starts counting; (D) determining whether the programmable logic component receives the periodic signal sent by the super input/output chip; (E) determining whether the timer count exceeds the preset time if the periodic signal is not received; (F) If the timer expires more than the preset time, a restart signal is sent to the south bridge chip; (G) the south bridge chip restarts the computer.
相較於習知技術,本發明可透過超級輸入輸出晶片與可 編程邏輯元件的通信狀況判斷電腦運行是否正常,並當電腦運行發生異常時,自動重啟電腦。 Compared with the prior art, the present invention can pass the super input and output chip and can The communication status of the programming logic component determines whether the computer is operating normally, and automatically restarts the computer when an abnormality occurs in the computer.
如圖1所示,係本發明電腦運行狀態偵測及處理系統較佳實施例的系統架構圖。該系統包括主機10及作業系統20。主機10用於執行作業系統20,其包括超級輸入輸出(super input/output,Super I/O)晶片100、可編程邏輯元件(complex programmable logic device,CPLD)110、南橋晶片120及振蕩器(oscillator)130。作業系統20包括設備驅動程式200,該設備驅動程式200控制Super I/O晶片100。 1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention. The system includes a host 10 and an operating system 20. The host 10 is configured to execute the operating system 20, which includes a super input/output (Super I/O) chip 100, a programmable logic device (CPLD) 110, a south bridge chip 120, and an oscillator (oscillator). ) 130. The operating system 20 includes a device driver 200 that controls the Super I/O wafer 100.
其中,Super I/O晶片100透過三個一般輸入輸出(general purpose input/output,GPIO)介面GPIO#1、GPIO#2、GPIO#3實現與CPLD晶片110的連接及通信,於本實施例中,GPIO#1、GPIO#2、GPIO#3分別配置為輸出、輸入、輸出功能。 The Super I/O chip 100 realizes connection and communication with the CPLD chip 110 through three general purpose input/output (GPIO) interfaces GPIO#1, GPIO#2, and GPIO#3, in this embodiment. GPIO#1, GPIO#2, and GPIO#3 are respectively configured as output, input, and output functions.
CPLD晶片110透過三個分別與GPIO#1、GPIO#2、GPIO#3相連的輸入輸出(input/output,I/O)介面I/O#1、I/O#2、I/O#3實現與Super I/O晶片100的連接與通信,於本實施例中,I/O#1、I/O#2、I/O#3分別配置為輸入、輸出、輸入功能。 The CPLD chip 110 transmits three input/output (I/O) interfaces I/O#1, I/O#2, and I/O#3 connected to GPIO#1, GPIO#2, and GPIO#3, respectively. In connection with the connection and communication with the Super I/O chip 100, in the present embodiment, I/O #1, I/O #2, and I/O #3 are respectively configured as input, output, and input functions.
南橋晶片120透過一個“RESET”接腳(圖中未示出)實現與CPLD晶片110的連接與通信。該“RESET”接腳可用於重啟主機10。 The south bridge wafer 120 is connected and communicated with the CPLD wafer 110 via a "RESET" pin (not shown). This "RESET" pin can be used to restart the host 10.
此外,CPLD晶片110還包括判斷模組111、發送模組112。判斷模組111用於透過Super I/O晶片100與CPLD晶片110的通信狀況判斷電腦主機10運行是否正常;發送模組112用於當主機10運行發生異常時,發送重啟信號至南橋晶片120重啟主機10。本發明所稱的模組是完成一特定功能的電腦程式段,比程式更適合於描述軟體在電腦中的執行過程。 In addition, the CPLD chip 110 further includes a determination module 111 and a transmission module 112. The determining module 111 is configured to determine whether the operation of the host computer 10 is normal through the communication status of the Super I/O chip 100 and the CPLD chip 110. The sending module 112 is configured to send a restart signal to the south bridge wafer 120 when the host 10 runs abnormally. Host 10. The module referred to in the present invention is a computer program segment that performs a specific function, and is more suitable for describing the execution process of the software in the computer than the program.
進一步地,CPLD晶片110還包括計時器113。 Further, the CPLD wafer 110 further includes a timer 113.
振蕩器130提供計時器113的工作頻率。 Oscillator 130 provides the operating frequency of timer 113.
本電腦運行狀態偵測及處理系統工作原理介紹如下:設備驅動程式200控制Super I/O晶片100產生並發送開始偵測信號、週期性信號至CPLD晶片110;CPLD晶片110接收Super I/O晶片100發送的開始偵測信號後觸發計時器113開始從零計時(t=0),判斷模組111判斷CPLD晶片110在預設計時周期內(如t=m period)是否收到Super I/O晶片100發出的週期性信號;若CPLD晶片110在預設計時周期內收到該週期性信號則表明作業系統20運行正常,則發送模組112向Super I/O晶片100發送回復資訊、計時器113重新從零開始計時;若CPLD晶片110未在預設計時周期內收到該週期性信號則表明作業系統20出現異常,則發送模組112發送重啟信號至南橋晶片120,南橋晶片120重新啟動主機10。 The operating principle of the computer running state detection and processing system is as follows: The device driver 200 controls the Super I/O chip 100 to generate and transmit a start detection signal and a periodic signal to the CPLD wafer 110; the CPLD wafer 110 receives the Super I/O chip. After the start detection signal transmitted by 100, the trigger timer 113 starts to count from zero (t=0), and the determination module 111 determines whether the CPLD wafer 110 receives the Super I/O within a preset timing period (eg, t=m period). The periodic signal sent by the chip 100; if the CPLD chip 110 receives the periodic signal within a preset timing period, indicating that the operating system 20 is operating normally, the transmitting module 112 sends a reply message and a timer to the Super I/O chip 100. 113 restarts from zero; if the CPLD wafer 110 does not receive the periodic signal within the preset timing period, indicating that the operating system 20 is abnormal, the transmitting module 112 sends a restart signal to the south bridge wafer 120, and the south bridge wafer 120 is restarted. Host 10.
如圖2所示,係本發明電腦運行狀態偵測及處理方法較佳實施例的流程圖。首先,主機10上電,作業系統20啟動 ,設備驅動程式200控制Super I/O晶片100產生一個狀態偵測開始信號S,並發送該狀態偵測開始信號S至CPLD晶片110(步驟S10)。CPLD晶片110接收Super I/O晶片100發送的狀態偵測開始信號S(步驟S20)。計時器113開始計時t=0(步驟S30)。判斷模組111判斷CPLD晶片110是否收到Super I/O晶片100週期性發送的信號P(以下稱作“週期性信號P”)(步驟S40)。若收到週期性信號P,則發送模組112發送回復信號A至Super I/O晶片100(步驟S50),流程返回步驟S20。若未收到週期性信號P,則判斷模組111判斷計時器113計時是否超過預設時間,如m(m>0)個信號P的周期(步驟S50)。若未超過預設時間,則流程返回步驟S40,若超過預設時間,則發送模組112發送重啟信號R至南橋晶片120(S60)。南橋晶片120重新啟動主機10以重新導入作業系統20(步驟S70)。 2 is a flow chart of a preferred embodiment of a method for detecting and processing a computer operating state according to the present invention. First, the host 10 is powered on, and the operating system 20 is started. The device driver 200 controls the Super I/O chip 100 to generate a state detection start signal S, and transmits the state detection start signal S to the CPLD wafer 110 (step S10). The CPLD wafer 110 receives the state detection start signal S transmitted from the Super I/O wafer 100 (step S20). The timer 113 starts timing t=0 (step S30). The judging module 111 judges whether or not the CPLD wafer 110 receives the signal P (hereinafter referred to as "periodic signal P") periodically transmitted by the Super I/O wafer 100 (step S40). Upon receiving the periodic signal P, the transmitting module 112 transmits the reply signal A to the Super I/O wafer 100 (step S50), and the flow returns to step S20. If the periodic signal P is not received, the determination module 111 determines whether the timer 113 counts for more than a preset time, such as a period of m (m > 0) signals P (step S50). If the preset time has not passed, the flow returns to step S40. If the preset time is exceeded, the transmitting module 112 transmits a restart signal R to the south bridge wafer 120 (S60). The south bridge wafer 120 restarts the host 10 to re-import the operating system 20 (step S70).
如圖3所示,係主機10運行正常時的信號示意圖。當主機10運行正常,亦即作業系統20正常工作時,設備驅動程式200控制Super I/O晶片100產生一個狀態偵測開始信號S,並控制Super I/O晶片100產生週期性信號P。CPLD晶片110每次收到Super I/O發送的信號P即回復一個信號A,當主機10運行正常時,信號A亦為一個週期性信號,僅相對於信號P在時間上有一個延遲。南橋晶片120的“RESET”接腳一直處於高電位。 As shown in FIG. 3, it is a signal diagram when the host 10 is operating normally. When the host 10 is operating normally, that is, the operating system 20 is operating normally, the device driver 200 controls the Super I/O chip 100 to generate a state detection start signal S, and controls the Super I/O wafer 100 to generate a periodic signal P. The CPLD chip 110 returns a signal A every time it receives the signal P sent by the Super I/O. When the host 10 is operating normally, the signal A is also a periodic signal, and there is only a delay in time with respect to the signal P. The "RESET" pin of the south bridge wafer 120 is always at a high potential.
如圖4所示,係主機10運行發生異常時的信號示意圖。當主機10在運行過程中出現異常,亦即作業系統20死機時 ,設備驅動程式200無法正常驅動Super I/O晶片100產生並發送週期性信號P。當CPLD晶片110超過預設時間(如m個信號P的周期)未收到信號P時,CPLD晶片110發送一個重啟信號R至南橋晶片120。南橋晶片120的“RESET”接腳由高電位跳變到低電位,主機10重新啟動。 As shown in FIG. 4, it is a schematic diagram of the signal when the host 10 runs an abnormality. When the host 10 is abnormal during operation, that is, when the operating system 20 is dead The device driver 200 cannot normally drive the Super I/O chip 100 to generate and transmit a periodic signal P. When the CPLD wafer 110 does not receive the signal P for more than a predetermined time (e.g., the period of the m signals P), the CPLD wafer 110 transmits a restart signal R to the south bridge wafer 120. The "RESET" pin of the south bridge wafer 120 transitions from a high potential to a low potential, and the host 10 is restarted.
以上所述僅為本發明之較佳實施例而已,且已達廣泛之使用功效,凡其他未脫離本發明所揭示之精神下所完成之均等變化或修飾,均應包含在下述之申請專利範圍內。 The above is only the preferred embodiment of the present invention, and has been used in a wide range of applications. Any other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Inside.
10‧‧‧主機 10‧‧‧Host
100‧‧‧Super I/O晶片 100‧‧‧Super I/O Chip
110‧‧‧可編程邏輯元件 110‧‧‧Programmable logic components
111‧‧‧判斷模組 111‧‧‧Judgement module
112‧‧‧發送模組 112‧‧‧Transmission module
113‧‧‧計時器 113‧‧‧Timer
120‧‧‧南橋晶片 120‧‧‧Southbridge
130‧‧‧振蕩器 130‧‧‧Oscillator
20‧‧‧作業系統 20‧‧‧ operating system
200‧‧‧設備驅動程式 200‧‧‧Device Driver
圖1係本發明電腦運行狀態偵測及處理系統較佳實施例的系統架構圖。 1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention.
圖2係本發明電腦運行狀態偵測及處理方法較佳實施例的流程圖。 2 is a flow chart of a preferred embodiment of a method for detecting and processing a computer operating state according to the present invention.
圖3係電腦正常運行時的信號示意圖。 Figure 3 is a schematic diagram of the signal when the computer is in normal operation.
圖4係電腦運行發生異常時的信號示意圖。 Figure 4 is a schematic diagram of the signal when the computer is running abnormally.
10‧‧‧主機 10‧‧‧Host
100‧‧‧Super I/O晶片 100‧‧‧Super I/O Chip
110‧‧‧可編程邏輯元件 110‧‧‧Programmable logic components
111‧‧‧判斷模組 111‧‧‧Judgement module
112‧‧‧發送模組 112‧‧‧Transmission module
113‧‧‧計時器 113‧‧‧Timer
120‧‧‧南橋晶片 120‧‧‧Southbridge
130‧‧‧振蕩器 130‧‧‧Oscillator
20‧‧‧作業系統 20‧‧‧ operating system
200‧‧‧設備驅動程式 200‧‧‧Device Driver
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