TWI389394B

TWI389394B - Electric connector and electric assembly

Info

Publication number: TWI389394B
Application number: TW98136684A
Authority: TW
Inventors: Sheng Yuan Lee
Original assignee: Via Tech Inc
Priority date: 2009-07-27
Filing date: 2009-10-29
Publication date: 2013-03-11
Also published as: TW201104963A

Description

電連接器及電子組裝Electrical connector and electronic assembly

本發明是有關於一種電連接器及具有其之電子組裝，且特別是有關於一種適用於通用序列匯流排架構的電連接器及具有其之電子組裝。This invention relates to an electrical connector and electronic assembly therewith, and more particularly to an electrical connector suitable for use in a universal serial busbar architecture and electronic assembly therewith.

通用序列匯流排3.0(Universal Serial Bus 3.0；USB 3.0)是一種從USB 2.0所發展出來的訊號傳輸規格，其傳輸速率可達到5G bps，而傳統USB 2.0的傳輸速率則僅有480M bps。USB 3.0電連接器可相容於USB 2.0電連接器，意即USB 3.0採用了與USB 2.0相同的電連接器結構，並增加了數根用來提供USB 3.0功能的接腳。因此，在基於USB 2.0的電連接器結構下，需要提出USB 3.0電連接器結構，以符合需求。Universal Serial Bus 3.0 (USB 3.0) is a signal transmission specification developed from USB 2.0 with a transfer rate of 5G bps, while traditional USB 2.0 has a transfer rate of only 480M bps. The USB 3.0 electrical connector is compatible with the USB 2.0 electrical connector, meaning that USB 3.0 uses the same electrical connector structure as USB 2.0 and adds several pins for USB 3.0 functionality. Therefore, under the USB 2.0-based electrical connector structure, it is necessary to propose a USB 3.0 electrical connector structure to meet the demand.

本發明提出一種電連接器，適於安裝至一電路板。電路板具有相對的一第一表面及一第二表面。電連接器包括一金屬殼體、一絕緣座體、多個第一接腳及多個第二接腳。絕緣座體連接於金屬殼體。這些第一接腳配置於絕緣座體且銲接至第一表面，其中這些第一接腳包括一對第一差動訊號接腳、一對第二差動訊號接腳及一第一接地接腳。第一接地接腳位於這對第一差動訊號接腳及這對第二差動訊號接腳之間。這些第二接腳配置於絕緣座體且銲接至第二表面，其中這些第二接腳包括一電源接腳、一第二接地接腳及一對第三差動訊號接腳。這對第三差動訊號接腳位於電源接腳及第二接地接腳之間。The present invention provides an electrical connector suitable for mounting to a circuit board. The circuit board has a first surface and a second surface opposite to each other. The electrical connector includes a metal housing, an insulating base, a plurality of first pins, and a plurality of second pins. The insulating base is connected to the metal housing. The first pins are disposed on the insulating body and soldered to the first surface, wherein the first pins comprise a pair of first differential signal pins, a pair of second differential signal pins, and a first ground pin . The first ground pin is located between the pair of first differential signal pins and the pair of second differential signal pins. The second pins are disposed on the insulating body and soldered to the second surface, wherein the second pins comprise a power pin, a second ground pin and a pair of third differential signal pins. The pair of third differential signal pins are located between the power pin and the second ground pin.

本發明提出一種電子組裝，包括一電路板及一電連接器。電路板具有相對的一第一表面及一第二表面。電連接器包括一金屬殼體、一絕緣座體、多個第一接腳及多個第二接腳。絕緣座體連接於金屬殼體。這些第一接腳配置於絕緣座體且銲接至第一表面，其中這些第一接腳包括一對第一差動訊號接腳、一對第二差動訊號接腳及一第一接地接腳。第一接地接腳位於這對第一差動訊號接腳及這對第二差動訊號接腳之間。這些第二接腳配置於絕緣座體且銲接至第二表面，其中這些第二接腳包括一電源接腳、一第二接地接腳及一對第三差動訊號接腳。這對第三差動訊號接腳位於電源接腳及第二接地接腳之間。The invention provides an electronic assembly comprising a circuit board and an electrical connector. The circuit board has a first surface and a second surface opposite to each other. The electrical connector includes a metal housing, an insulating base, a plurality of first pins, and a plurality of second pins. The insulating base is connected to the metal housing. The first pins are disposed on the insulating body and soldered to the first surface, wherein the first pins comprise a pair of first differential signal pins, a pair of second differential signal pins, and a first ground pin . The first ground pin is located between the pair of first differential signal pins and the pair of second differential signal pins. The second pins are disposed on the insulating body and soldered to the second surface, wherein the second pins comprise a power pin, a second ground pin and a pair of third differential signal pins. The pair of third differential signal pins are located between the power pin and the second ground pin.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

本發明所提出的電子組裝及其電連接器可適用於USB 3.0架構，相較於USB 2.0及USB 3.0電連接器，增加了五根接腳，其中四根接腳用於一傳送差動訊號對(transmitting differential signal pair)及一接收差動訊號對(receiving differential signal pair)，而第五根接腳則用於接地功能。特別說明的是，一般配置於裝置端(device)的USB電連接器又有公頭(plug connector)之稱；配置於主機端(host)的USB電連接器又有母頭(Receptacle connector)之稱。以下詳細說明本發明之電連接器。The electronic assembly and the electrical connector thereof provided by the invention can be applied to the USB 3.0 architecture, and five pins are added compared to the USB 2.0 and USB 3.0 electrical connectors, wherein four pins are used for transmitting a differential signal. The transmitting differential signal pair and a receiving differential signal pair, and the fifth pin is used for the grounding function. Specifically, the USB electrical connector generally disposed on the device has a plug connector; the USB electrical connector disposed on the host has a Receptacle connector. Said. The electrical connector of the present invention will be described in detail below.

圖1為本發明一實施例之包含電連接器的電子組裝的立體圖。圖2為圖1之電子組裝的部分構件立體圖。請參考圖1及圖2，本實施例的電子組裝100包括一電路板110(僅繪示電路板110之局部)及一電連接器120，其中電連接器120例如是配置於裝置端，又有公頭之稱。電連接器120包括一金屬殼體122、一連接於金屬殼體122的絕緣座體124、多個配置於絕緣座體124的第一接腳126及多個配置於絕緣座體124的第二接腳128。1 is a perspective view of an electronic assembly including an electrical connector in accordance with an embodiment of the present invention. 2 is a perspective view of a portion of the electronic assembly of FIG. 1. Referring to FIG. 1 and FIG. 2 , the electronic assembly 100 of the present embodiment includes a circuit board 110 (only a part of the circuit board 110 is shown) and an electrical connector 120 , wherein the electrical connector 120 is disposed on the device end, for example. There is a name for the public. The electrical connector 120 includes a metal housing 122 , an insulating base 124 connected to the metal housing 122 , a plurality of first pins 126 disposed on the insulating base 124 , and a plurality of second disposed on the insulating base 124 . Pin 128.

第一接腳126包括一對第一差動訊號接腳126a、一對第二差動訊號接腳126b及一第一接地接腳126c，其中第一接地接腳126c位於這對第一差動訊號接腳126a及這對第二差動訊號接腳126b之間。第二接腳128包括一電源接腳128a、一第二接地接腳128b及一對第三差動訊號接腳128c，其中這對第三差動訊號接腳128c位於電源接腳128a及第二接地接腳128b之間。The first pin 126 includes a pair of first differential signal pins 126a, a pair of second differential signal pins 126b, and a first ground pin 126c, wherein the first ground pins 126c are located in the pair of first differentials The signal pin 126a and the pair of second differential signal pins 126b. The second pin 128 includes a power pin 128a, a second ground pin 128b and a pair of third differential pin pins 128c. The pair of third differential pin pins 128c are located at the power pin 128a and the second pin. Between ground pins 128b.

在本實施例中，這對第一差動訊號接腳126a為USB 3.0架構中的一對傳送(Transmitting)差動訊號接腳T_x ⁺ 及T_x ^- ，第二差動訊號接腳126b為USB 3.0架構中的一對接收(Receiving)差動訊號接腳R_x ⁺ 及R_x ^- ，而第三差動訊號接腳128c為USB 3.0架構中支援USB 1.0架構或USB 2.0架構的一對傳送/接收差動訊號接腳D⁺ 及D^- 。In this embodiment, the pair of first differential signal pins 126a are a pair of Transmitting differential signal pins T _x ⁺ and T _x ^- in the USB 3.0 architecture, and the second differential signal pins 126b are A pair of receiving differential signal pins R _x ⁺ and R _x ^- in the USB 3.0 architecture, and a third differential signal pin 128c for transmitting a pair of USB 1.0 architecture or USB 2.0 architecture in the USB 3.0 architecture / Receive differential signal pins D ⁺ and D ^- .

圖3為圖1之電子組裝於另一視角的立體圖。圖4為圖3之電子組裝的部分構件立體圖。圖5為圖1之電子組裝於又一視角的立體圖。圖6為圖5之電子組裝的部分構件立體圖。請參考圖3至圖6，電路板110具有相對的一第一表面110a(標示於圖3及圖4)及一第二表面110b(標示於圖5及圖6)，這些第一接腳126銲接至電路板110的第一表面110a，且這些第二接腳128銲接至電路板110的第二表面110b。3 is a perspective view of the electronic assembly of FIG. 1 assembled from another perspective. 4 is a perspective view of a portion of the electronic assembly of FIG. 3. Figure 5 is a perspective view of the electronic assembly of Figure 1 assembled in yet another perspective. Figure 6 is a perspective view of a portion of the assembly of the electronic assembly of Figure 5. Referring to FIG. 3 to FIG. 6 , the circuit board 110 has a first surface 110 a (shown in FIGS. 3 and 4 ) and a second surface 110 b (shown in FIGS. 5 and 6 ). The first pins 126 . Solder to the first surface 110a of the circuit board 110, and the second pins 128 are soldered to the second surface 110b of the circuit board 110.

圖7為圖1之電子組裝的部分構件剖視圖。請參考圖7，在本實施例中，電子組裝100更包括一安裝至第一表面110a的控制晶片130，其中控制晶片130例如是用來控制記憶體(如反及閘快閃記憶體(NAND Flash))(未繪示)的存取。此外，電路板110包括一配置於第一表面110a的第一線路112及一配置於第二表面110b的第二線路114；在本實施例中，假設第一線路112和第二線路114位於不同剖面，故圖7中第二線路114以虛線繪示。控制晶片130銲接至第一線路112。這些第一接腳126銲接至第一線路112，並經由第一線路112而電性連接至控制晶片130。這些第二接腳128銲接至第二線路114，並經由第二線路114而電性連接至控制晶片130。Figure 7 is a cross-sectional view of a portion of the electronic assembly of Figure 1. Referring to FIG. 7, in the embodiment, the electronic assembly 100 further includes a control wafer 130 mounted to the first surface 110a, wherein the control wafer 130 is used, for example, to control memory (eg, anti-gate flash memory (NAND) Flash)) (not shown) access. In addition, the circuit board 110 includes a first line 112 disposed on the first surface 110a and a second line 114 disposed on the second surface 110b. In this embodiment, it is assumed that the first line 112 and the second line 114 are different. The cross section, so the second line 114 in Figure 7 is shown in dashed lines. Control wafer 130 is soldered to first line 112. The first pins 126 are soldered to the first line 112 and electrically connected to the control wafer 130 via the first line 112. These second pins 128 are soldered to the second line 114 and electrically connected to the control wafer 130 via the second line 114.

在本實施例中，電路板110更包括多個導電孔(conductive via)116(僅繪示出一個)，而這些導電孔116將第二線路114連接至第一線路112。因此，這些第二接腳128可依序經由第二線路114、這些導電孔116及第一線路112而電性連接至控制晶片130。In the present embodiment, the circuit board 110 further includes a plurality of conductive vias 116 (only one is shown), and the conductive vias 116 connect the second line 114 to the first line 112. Therefore, the second pins 128 can be electrically connected to the control wafer 130 via the second line 114 , the conductive holes 116 , and the first line 112 .

值得注意的是，在本實施例中，連接至第一接腳126的第一線路112與連接至第二接腳128的第二線路114分別配置於電路板110的第一表面112及第二表面114，因此第一線路112與第二線路114之間具有較大的距離，以降低訊號干擾的機率。此外，電路板110的第一表面110a僅配置第一接腳126，因此第一差動訊號接腳126a及第二差動訊號接腳126b之間可具有較大的距離(如圖4所繪示)以降低兩者之間的耦合性質，進而維持訊號傳輸品質。It should be noted that, in this embodiment, the first line 112 connected to the first pin 126 and the second line 114 connected to the second pin 128 are respectively disposed on the first surface 112 and the second surface of the circuit board 110. The surface 114, therefore, has a greater distance between the first line 112 and the second line 114 to reduce the chance of signal interference. In addition, the first surface 110a of the circuit board 110 is only configured with the first pin 126, so that the first differential signal pin 126a and the second differential signal pin 126b can have a larger distance (as shown in FIG. 4). Show) to reduce the coupling between the two, thereby maintaining signal transmission quality.

圖8為圖1之電子組裝的局部俯視示意圖。請參考圖8，本實施例的第一接腳126在第一表面110a的正投影與第二接腳128在第一表面110a的正投影不重疊，意即第一接腳126及第二接腳128是以交錯的方式配置於電路板110。值得一提的是，圖8僅為本案之一種實施方式，並非用以限制本發明。在其他實施例中，第一接腳126在第一表面110a的正投影與第二接腳128在第一表面110a的正投影有可能會有部份重疊(未繪示)。8 is a partial top plan view of the electronic assembly of FIG. 1. Referring to FIG. 8, the front projection of the first pin 126 of the embodiment on the first surface 110a does not overlap with the orthographic projection of the second pin 128 on the first surface 110a, that is, the first pin 126 and the second connection. The legs 128 are disposed on the circuit board 110 in a staggered manner. It is to be noted that FIG. 8 is only one embodiment of the present invention and is not intended to limit the present invention. In other embodiments, the orthographic projection of the first pin 126 on the first surface 110a and the orthographic projection of the second pin 128 on the first surface 110a may partially overlap (not shown).

請再參考圖7，本實施例的電路板110更包括兩個參考平面(reference plane)118及115。參考平面118及115位於第一線路112及第二線路114之間，而可藉其屏蔽效果來降低第一線路112與第二線路114彼此間的訊號干擾。在本實施例中，參考平面118例如為接地平面(ground plane)而參考平面115例如為電源平面(power plane)。第一接地接腳126c(繪示於圖2)及第二接地接腳128b(繪示於圖2)可分別透過導電孔117(圖7僅繪示出一個)電性連接於參考平面118，而電源接腳128a(繪示於圖2)可透過導電孔119電性連接於參考平面115。此外，在另一實施例中，電源接腳128a亦可電性連接至其他與電源相關的元件上(未繪示)。Referring to FIG. 7 again, the circuit board 110 of the present embodiment further includes two reference planes 118 and 115. The reference planes 118 and 115 are located between the first line 112 and the second line 114, and the signal interference between the first line 112 and the second line 114 can be reduced by the shielding effect. In the present embodiment, the reference plane 118 is, for example, a ground plane and the reference plane 115 is, for example, a power plane. The first grounding pin 126c (shown in FIG. 2) and the second grounding pin 128b (shown in FIG. 2) are electrically connected to the reference plane 118 through the conductive holes 117 (only one is shown in FIG. 7). The power pin 128a (shown in FIG. 2 ) is electrically connected to the reference plane 115 through the conductive hole 119 . In addition, in another embodiment, the power pin 128a can also be electrically connected to other power-related components (not shown).

綜上所述，本發明將這些第一接腳及這些第二接腳分別配置於電路板相對的第一表面及第二表面，因此位於第一表面且連接這些第一接腳的第一線路與位於第一表面且連接這些第二接腳的第二線路之間可具有較大的距離，以降低第一線路及第二線路之間的訊號相互干擾(crosstalk)。此外，本發明在電路板的第一表面上僅配置這些第一接腳，因此這些第一接腳所包括的這對第一差動訊號接腳及這對第二差動訊號接腳之間可具有較大的距離，以降低兩者之間的耦合性質，進而維持訊號傳輸品質。另外，電路板更可具有位於第一線路及第二線路之間的參考平面，以藉其屏蔽效果進一步來降低第一線路與第二線路彼此間的訊號干擾。In summary, the first pin and the second pin are respectively disposed on the opposite first surface and the second surface of the circuit board, so that the first line connecting the first pins is located on the first surface. There may be a greater distance between the second line located on the first surface and connected to the second pins to reduce signal crosstalk between the first line and the second line. In addition, the present invention only configures the first pins on the first surface of the circuit board, so that the first differential pins included between the first differential pins and the pair of second differential signal pins It can have a large distance to reduce the coupling property between the two, thereby maintaining the signal transmission quality. In addition, the circuit board may further have a reference plane between the first line and the second line to further reduce signal interference between the first line and the second line by virtue of the shielding effect.

雖然本發明巳以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described above by way of example, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100．．．電子組裝100. . . Electronic assembly

110．．．電路板110. . . Circuit board

110a．．．第一表面110a. . . First surface

110b．．．第二表面110b. . . Second surface

112．．．第一線路112. . . First line

114．．．第二線路114. . . Second line

115、118．．．參考平面115, 118. . . Reference plane

116、117、119．．．導電孔116, 117, 119. . . Conductive hole

120．．．電連接器120. . . Electrical connector

122．．．金屬殼體122. . . Metal housing

124．．．絕緣座體124. . . Insulated body

126．．．第一接腳126. . . First pin

126a．．．第一差動訊號接腳126a. . . First differential signal pin

126b．．．第二差動訊號接腳126b. . . Second differential signal pin

126c．．．第一接地接腳126c. . . First grounding pin

128．．．第二接腳128. . . Second pin

128a．．．電源接腳128a. . . Power pin

128b．．．第二接地接腳128b. . . Second grounding pin

128c．．．第三差動訊號接腳128c. . . Third differential signal pin

130．．．控制晶片130. . . Control chip

圖1為本發明一實施例之包含電連器的電子組裝的立體圖。1 is a perspective view of an electronic assembly including an electrical connector in accordance with an embodiment of the present invention.

圖2為圖1之電子組裝的部分構件立體圖。2 is a perspective view of a portion of the electronic assembly of FIG. 1.

圖3為圖1之電子組裝於另一視角的立體圖。3 is a perspective view of the electronic assembly of FIG. 1 assembled from another perspective.

圖4為圖3之電子組裝的部分構件立體圖。4 is a perspective view of a portion of the electronic assembly of FIG. 3.

圖5為圖1之電子組裝於又一視角的立體圖。Figure 5 is a perspective view of the electronic assembly of Figure 1 assembled in yet another perspective.

圖6為圖5之電子組裝的部分構件立體圖。Figure 6 is a perspective view of a portion of the assembly of the electronic assembly of Figure 5.

圖7為圖1之電子組裝的部分構件剖視圖。Figure 7 is a cross-sectional view of a portion of the electronic assembly of Figure 1.

圖8為圖4之電子組裝的局部俯視示意圖。8 is a partial top plan view of the electronic assembly of FIG. 4.

110．．．電路板110. . . Circuit board

110a．．．第一表面110a. . . First surface

110b．．．第二表面110b. . . Second surface

112．．．第一線路112. . . First line

114．．．第二線路114. . . Second line

115、118．．．參考平面115, 118. . . Reference plane

116、117、119．．．導電孔116, 117, 119. . . Conductive hole

126．．．第一接腳126. . . First pin

128．．．第二接腳128. . . Second pin

130．．．控制晶片130. . . Control chip

Claims

一種電連接器，適於安裝至一電路板，該電路板具有相對的一第一表面及一第二表面，該電路板包括一第一線路及一第二線路，該第一線路配置於該第一表面，該第二線路配置於該第二表面，該電連接器包括：一金屬殼體；一絕緣座體，連接於該金屬殼體；多個第一接腳，配置於該絕緣座體且適於銲接至該第一表面，其中該些第一接腳包括：一對第一差動訊號接腳；一對第二差動訊號接腳；一第一接地接腳，位於該對第一差動訊號接腳及該對第二差動訊號接腳之間，其中該些第一接腳中的該對第一差動訊號接腳與該對第二差動訊號接腳銲接至該第一線路；以及多個第二接腳，配置於該絕緣座體且適於銲接至該第二表面，其中該些第二接腳包括：一電源接腳；一第二接地接腳；以及一對第三差動訊號接腳，位於該電源接腳及該第二接地接腳之間，其中該些第二接腳中的該對第三差動訊號接腳銲接至該第二線路。 An electrical connector adapted to be mounted to a circuit board having a first surface and a second surface, the circuit board including a first line and a second line, the first line being disposed a first surface, the second line is disposed on the second surface, the electrical connector includes: a metal housing; an insulating base connected to the metal housing; and a plurality of first pins disposed on the insulating seat And adapted to be soldered to the first surface, wherein the first pins comprise: a pair of first differential signal pins; a pair of second differential signal pins; and a first ground pin located at the pair Between the first differential signal pin and the pair of second differential signal pins, wherein the pair of first differential signal pins of the first pins and the pair of second differential signal pins are soldered to The second circuit is disposed on the insulative housing and is adapted to be soldered to the second surface, wherein the second pins comprise: a power pin; a second ground pin; And a pair of third differential signal pins located between the power pin and the second ground pin, The third differential pair of the plurality of signal pin welded to the second pin in the second line.

如申請專利範圍第1項所述之電連接器，其中該對第一差動訊號接腳為通用序列匯流排3.0架構中的一對傳送差動訊號接腳T_x ⁺ 及T_x ^- ，且該對第二差動訊號接腳為USB 3.0架構中的一對接收差動訊號接腳R_x ⁺ 及R_x ^- 。The electrical connector of claim 1, wherein the pair of first differential signal pins are a pair of transmitting differential signal pins T _x ⁺ and T _x ^- in a universal serial bus 3.0 architecture, and The pair of second differential signal pins are a pair of receiving differential signal pins R _x ⁺ and R _x ^- in the USB 3.0 architecture.

如申請專利範圍第1項所述之電子組裝，其中該對第三差動訊號接腳為USB 3.0架構中支援USB 1.0架構或USB 2.0架構的一對傳送/接收差動訊號接腳D⁺ 及D^- 。The electronic assembly of claim 1, wherein the pair of third differential signal pins are a pair of transmit/receive differential signal pins D ⁺ supporting a USB 1.0 architecture or a USB 2.0 architecture in the USB 3.0 architecture. D ^- .

如申請專利範圍第1項所述之電連接器，其中該些第一接腳在該第一表面的正投影與該些第二接腳在該第一表面的正投影不重疊。 The electrical connector of claim 1, wherein the orthographic projection of the first pins on the first surface does not overlap the orthographic projection of the second pins on the first surface.

一種電子組裝，包括：一電路板，具有相對的一第一表面及一第二表面，其中該電路板包括：一第一線路，配置於該第一表面；以及一第二線路，配置於該第二表面；以及一電連接器，包括：一金屬殼體；一絕緣座體，連接於該金屬殼體；多個第一接腳，配置於該絕緣座體且銲接至該第一表面，其中該些第一接腳包括：一對第一差動訊號接腳；一對第二差動訊號接腳；一第一接地接腳，位於該對第一差動訊號接腳及該對第二差動訊號接腳之間，其中該些第一接腳中的該對第一差動訊號接腳與該對第二差動訊號接腳銲接至該第一線路；多個第二接腳，配置於該絕緣座體且銲接至該第二表面，其中該些第二接腳包括：一電源接腳；一第二接地接腳；以及一對第三差動訊號接腳，位於該電源接腳及該第二接地接腳之間，其中該些第二接腳中的該對第三差動訊號接腳銲接至該第二線路。 An electronic assembly comprising: a circuit board having an opposite first surface and a second surface, wherein the circuit board comprises: a first line disposed on the first surface; and a second line disposed on the a second surface; and an electrical connector, comprising: a metal housing; an insulating base coupled to the metal housing; a plurality of first pins disposed on the insulating housing and soldered to the first surface, The first pins include: a pair of first differential signal pins; a pair of second differential signal pins; a first ground pin located at the pair of first differential signal pins and the pair Between the two differential signal pins, wherein the pair of first differential signals in the first pins a pin and the pair of second differential signal pins are soldered to the first line; a plurality of second pins are disposed on the insulating body and soldered to the second surface, wherein the second pins comprise: a power pin; a second ground pin; and a pair of third differential signal pins located between the power pin and the second ground pin, wherein the pair of the second pins The differential signal pin is soldered to the second line.

如申請專利範圍第5項所述之電子組裝，其中該對第一差動訊號接腳為通用序列匯流排3.0架構中的一對傳送差動訊號接腳T_x ⁺ 及T_x ^- ，且該對第二差動訊號接腳為USB 3.0架構中的一對接收差動訊號接腳R_x ⁺ 及R_x ^- 。The electronic assembly of claim 5, wherein the pair of first differential signal pins are a pair of transmission differential signal pins T _x ⁺ and T _x ^- in the general sequence bus bar 3.0 architecture, and The second differential signal pin is a pair of receiving differential signal pins R _x ⁺ and R _x ^- in the USB 3.0 architecture.

如申請專利範圍第5項所述之電子組裝，其中該對第三差動訊號接腳為USB 3.0架構中支援USB 1.0架構或USB 2.0架構的一對傳送/接收差動訊號接腳D⁺ 及D^- 。The electronic assembly of claim 5, wherein the pair of third differential signal pins are a pair of transmit/receive differential signal pins D ⁺ supporting a USB 1.0 architecture or a USB 2.0 architecture in the USB 3.0 architecture. D ^- .

如申請專利範圍第5項所述之電子組裝，其中該些第一接腳在該第一表面的正投影與該些第二接腳在該第一表面的正投影不重疊。 The electronic assembly of claim 5, wherein the orthographic projection of the first pins on the first surface does not overlap the orthographic projection of the second pins on the first surface.

如申請專利範圍第5項所述之電子組裝，更包括：一控制晶片，安裝至該第一表面。 The electronic assembly of claim 5, further comprising: a control wafer mounted to the first surface.

如申請專利範圍第9項所述之電子組裝，其中該些第一接腳中的該對第一差動訊號接腳與該對第二差動訊號接腳經由該第一線路電性連接至該控制晶片，該些第二接腳中的該第三差動訊號接腳經由該第二線路電性連接至該控制晶片。 The electronic assembly of claim 9, wherein the pair of first differential signal pins and the pair of second differential signals of the first pins The first pin is electrically connected to the control chip via the first line, and the third differential signal pin of the second pins is electrically connected to the control chip via the second line.

如申請專利範圍第10項所述之電子組裝，其中該電路板更包括：多個導電孔，將該第二線路連接至第一線路，以使該些第二接腳依序經由該第二線路、該些導電孔及該第一線路而電性連接至該控制晶片。 The electronic assembly of claim 10, wherein the circuit board further comprises: a plurality of conductive holes, the second line is connected to the first line, so that the second pins are sequentially passed through the second The circuit, the conductive holes and the first line are electrically connected to the control wafer.

如申請專利範圍第10項所述之電子組裝，其中該電路板更包括：一參考平面，位於該第一線路及該第二線路之間。 The electronic assembly of claim 10, wherein the circuit board further comprises: a reference plane located between the first line and the second line.

如申請專利範圍第12項所述之電子組裝，其中該參考平面為一接地平面，且該第一接地接腳及該第二接地接腳電性連接於該接地平面。 The electronic assembly of claim 12, wherein the reference plane is a ground plane, and the first grounding pin and the second grounding pin are electrically connected to the ground plane.

如申請專利範圍第12項所述之電子組裝，其中該參考平面為一電源平面，且該電源接腳電性連接於該電源平面。The electronic assembly of claim 12, wherein the reference plane is a power plane, and the power pin is electrically connected to the power plane.