TWI389310B - 形成自行校準電晶體之方法及用於其之結構 - Google Patents

形成自行校準電晶體之方法及用於其之結構 Download PDF

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TWI389310B
TWI389310B TW095130660A TW95130660A TWI389310B TW I389310 B TWI389310 B TW I389310B TW 095130660 A TW095130660 A TW 095130660A TW 95130660 A TW95130660 A TW 95130660A TW I389310 B TWI389310 B TW I389310B
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Gordon M Grivna
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Description

形成自行校準電晶體之方法及用於其之結構
本發明大體上係關於電子器件，且更特定言之，係關於形成半導體元件之方法及其結構。
先前，半導體工業利用各種方法及結構以形成高效能雙極電晶體。為獲得更高效能，重要之舉在於最小化基極接點之尺寸，以降低寄生電容。另外，需要能夠藉由使用光微影縮放技術來縮小電晶體之尺寸。形成高效能雙極電晶體之先前方法通常依賴於槽蝕刻技術，該等技術一般難以控制，且從製造角度來看係高成本的。於2005年1月20日公開之發明者Freeman等人之美國專利公開案第2005/0012180號揭示了此雙極電晶體之一個實例。用於形成高效能雙極電晶體之方法經由介電質蝕刻窄槽，並使用該等窄槽作為遮罩以形成該電晶體之其他部分。此等先前雙極電晶體結構亦使用多個氧化物或光阻插塞以交替界定發射極開口之外部邊緣及內部邊緣。使用插塞來界定開口需要多個處理步驟，並限制了待塞入之開口的尺寸。
因此，需要一種形成雙極電晶體之方法，該方法可容易地在大小尺寸之間進行縮放，不利用槽處理或插塞技術，且降低製造成本。
圖1說明一雙極電晶體10之放大橫截面部分。如下文將進一步可見，電晶體10可藉由使用光微影技術而縮放至更小或更大尺寸。電晶體10係一雙極電晶體，其具有一摻雜區域38、一摻雜區域39及一摻雜區域44，該摻雜區域38與該摻雜區域39形成電晶體10之一基極，該摻雜區域44形成一發射極。導體18及導體連接34經形成以提供一至該基極之電連接。
圖2說明根據製作電晶體10之方法之一實施例的處於一製造階段之電晶體10的放大橫截面部分。電晶體10係形成於一具有一頂部表面12之半導體基板11上。在較佳實施例中，電晶體10係形成於一半導體基板11上之PNP雙極電晶體，該半導體基板11包括一高摻雜P型塊體基板，在該塊體基板上形成一低摻雜P型磊晶層或可能一低摻雜P型槽以容納電晶體10。因為此等P型元件可能不存在於所有實施例中，所以未作說明。通常，一場氧化層13形成於基板11之靠近電晶體10之外部邊緣之表面12上。一層二氧化矽或氧化物16係形成於表面12之由場氧化層13圍繞之一部分上。氧化物16一般為熱氧化物。一第一保護層17經形成以覆蓋氧化物16。導體18係形成於保護層17之一部分上，且上覆於氧化物16。此後，另一保護層19經形成以覆蓋導體18。用於保護層17與19之材料係一與用於蝕刻導體18之操作相比具有降低之蝕刻速率之材料。在較佳實施例中，導體18係摻雜多晶矽以形成良好電導體，且層17及19係氮化矽。諸如二氧化矽或氧化物之層間介電質20係形成於層19之至少一部分上，且較佳地，上覆於整個導體18。如下文將進一步可見，氧化物16、層17及19、導體18及介電質20之厚度均可影響電晶體10之某些元件之尺寸。
圖3說明根據製作電晶體10之方法之一實施例的處於形成介電質20之後的一後續製造階段之電晶體10的放大橫截面部分。一遮罩23經塗佈至介電質20且經圖案化以形成一上覆於表面12之一部分的開口，電晶體10之基極及發射極將形成於該處。介電質20之曝露部分及層19之下伏部分經移除，從而形成一開口24，通過該開口24將形成電晶體10之作用部分及其電接點。用於蝕刻穿過介電質20之操作亦移除位於開口24內之層19之部分。通常，係使用反應性離子蝕刻(RIE)以移除介電質20及層19之部分。在較佳實施例中，導體18之多晶矽係此操作之蝕刻終止物。
圖4說明根據製作電晶體10之方法之實施例的處於一後續階段之電晶體10。移除導體18之曝露於開口24內之部分。在較佳實施例中，用於移除導體18之摻雜多晶矽之曝露部分的過程在導體18與層17之氮化矽二者之間具有選擇性，因此層17形成此操作之蝕刻終止物。此後，如虛線所示，移除遮罩23。開口24曝露出介電質20之側壁、導體18之側壁及層19、17之側壁。多晶矽隔片26係沿介電質20、導體18、及層19及17之此等側壁而形成。隔片26一般由多晶矽之等形毯覆式沈積形成，該多晶矽係沿介電質20之頂部沈積，且在開口24內沿介電質20、導體18、及層19、17之側壁沈積並沈積於層17之曝露表面上。此後，利用各向異性蝕刻來移除多晶矽，且留下多晶矽之一部分以作為隔片26。
圖5說明根據製作電晶體10之方法之一實施例的處於一後續階段之電晶體10。隔片26經氧化以在形成隔片26處形成保護隔片28。通常，利用濕式氧化法來將隔片26形成為隔片28。隔片26(圖4)及隔片28之寬度非常小，以免妨礙電晶體10之基極及發射極之後續形成。在較佳實施例中，隔片26向開口24中延伸約五十(50)奈米，且所得隔片28向開口24中延伸約六十五(65)奈米。此後，自在開口24內且自導體18下之第一距離31移除層17。當移除層17之後，自大約與層17相同之區域移除層16之曝露部分。在此等操作期間，保護隔片28保護介電質20、導體18及層19之側壁。層17及16之移除底切導體18，以形成一下伏於導體18之凹座29，該凹座29曝露出導體18之具有一底部表面30之突出部分。在較佳實施例中，層17之部分藉由在磷酸中進行濕式氮化蝕刻大約六十(60)分鐘而被移除，該蝕刻用於形成大約十(10)奈米之距離31。在此較佳實施例中，氧化物16之部分係由一基於HF之濕式蝕刻而移除，該濕式蝕刻蝕刻氧化物且對於層17及導體18具有選擇性。層16之移除亦自隔片28移除一類似量，其使得隔片28變得更薄，而使得該等側壁大體上垂直於表面12。如下文將進一步可見，距離31係重要的且輔助最小化電晶體10之外質或非作用基極之寬度。
圖6說明根據製作電晶體10之方法之一實施例的進一步階段。一導體連接34經形成於凹座29中，並經利用以將導體18互連至非作用基極，該非作用基極隨後將形成為摻雜區域38。連接34一般係藉由在介電質20上、隔片28上、凹座29中及沿表面12之曝露於開口24內之部分施加一等形層摻雜多晶矽而形成。該等形多晶矽經沈積為具有一不小於凹座29深度之一半的厚度。一各向異性蝕刻經使用以移除多晶矽而留下填充凹座29且下伏於導體18及隔片28二者之多晶矽之一部分作為連接34。較佳地，該多晶矽等形層經形成為具有一約為五十(50)奈米之厚度。此後，穿過開口24氧化電晶體10，以沿隔片28之側壁、連接34之側壁及表面12之曝露部分形成一二氧化矽層或氧化物層35。較佳地，氧化物層35經形成為具有一約為七十(70)奈米之厚度。在較佳實施例中，使用一熱氧化循環，其亦將摻雜劑自導體18驅逐至連接34中並至基板11中，以在第一表面12上形成電晶體10之基極之外質部分作為摻雜區域38。此確保在連接34與區域38之間形成一電阻非常低之電連接。該裝置之作用基極區係藉由穿過開口24摻雜表面12之一部分以在表面12上形成摻雜區域39而形成的。較佳地，區域39係藉由經由氧化物層35將摻雜劑植入基板11中而形成的。在較佳實施例中，使用能量為30 KeV之約為2.5E13之硼植入物。
圖7說明根據製作電晶體10之方法之一實施例的另一後續階段。在較佳實施例中，約三百(300)奈米之未摻雜多晶矽係沈積於開口24內，接著進行一各向異性蝕刻以留下沿層35之側壁及沿層35底部之一部分延伸之多晶矽填充物41。此後，藉由諸如濕式氧化蝕刻或反應性離子蝕刻而移除沿層35底部之層35之曝露部分，以留下層35之剩餘部分作為校準隔片36。
往回參看圖1，發射極係形成為表面12之部分上之摻雜區域44，其由隔片36及填充物41曝露。摻雜區域44亦為淺薄的，並向區域39中延伸一短距離。為了形成區域44，開口24之剩餘部分由導體43填充，該導體43亦將作為形成區域44之摻雜源。導體43一般由與區域39之摻雜類型相反之摻雜類型所摻雜。在較佳實施例中，導體43係由磷摻雜之多晶矽。將導體43用作摻雜源有助於控制區域44之深度。在此較佳實施例中，快速高熱退火經使用以自導體43驅逐摻雜劑，其將區域44摻雜為具有一不大於層39之深度的深度。注意到，導體43形成一發射電極，其形成至區域44之電接點，因而亦為至電晶體10之發射極之電接點。導體18及連接34形成一基電極，其提供至由區域38及39形成之電晶體10之基極的電接點。如可見，隔片28、36及填充物41之寬度係重要，並構成電晶體10之作用區域之尺寸。隔片36之寬度構成電晶體10之作用基極區之寬度以及發射極之寬度。亦可見，用於形成間隔之步驟係可縮放的，且可用於形成具有更小或大的作用區域之電晶體。另外，用於形成隔片28、36及填充物41之方法形成大體上垂直或正交於表面12之側壁，其有助於準確定位作用元件及準確確定電晶體10之作用元件之間隔及尺寸。目標在於使側壁完全垂直於表面12。然而，如此項技術中所熟知，在過程及溫度上可能存在妨礙側壁完全垂直於表面12之微小變化。此項技術中已熟知，高達約十五(15)度之變化視為偏離恰好垂直於表面12之理想目標之合理變化。
鑒於以上所有描述，顯然揭示了一種新穎裝置及方法。在其他特徵中，包括形成一下伏於一導體之凹座並以導體材料填充該凹座以電接觸電晶體之基極區。使用兩個不同導體有助於形成具有大體上垂直之側壁的校準隔片，以使得該等側壁大體上垂直於基板表面。校準隔片之改良側壁改良了作用區域之間的校準，有助於形成更小的作用區域，並允許將該方法及裝置縮放至更大及更小尺寸。
雖然以特定較佳實施例來描述本發明之主題，但顯然多種替代物及變化將對於熟習半導體技術者為顯而易見的。舉例而言，隔片28係可選的，且在某些實施例中可省略。另外，填充物41可為任何數目之材料(導電的或非導電的)，區域44可被植入或擴散，區域38及39可為一植入層，且連接34可為其他導電材料。此外，在界定發射極開口之後可移除填充物41，或可省略填充物41，且表面12之發射極區可由光微影過程來界定。雖然形成區域44及39之方法經說明為形成電晶體10之個別發射極與基極，但對於其他電晶體結構而言，每一區域之功能及摻雜分佈可視裝置要求而變化。又，電晶體10之各部分可形成於場氧化層之上。更具體言之，本發明之主題係針對於一特定NPN電晶體結構來描述的，儘管該方法可直接應用於PNP雙極電晶體、二極體以及MOS、BiCMOS、金屬半導體FET(MESFET)、HFET及其他電晶體結構。一般技術者將瞭解，所說明之步驟僅為例示性的，且僅構成在半導體基板11上形成電晶體10所需之製造過程步驟的一部分。
10．．．電晶體
11．．．半導體基板
12．．．表面
13．．．場氧化層
16．．．二氧化矽/氧化物
17．．．保護層
18．．．導體
19．．．保護層
20．．．介電質
23．．．遮罩
24．．．開口
26．．．隔片
28．．．保護隔片
29．．．凹座
30．．．底部表面
31．．．第一距離
34．．．導體連接
35．．．氧化物層
36．．．校準隔片
38．．．摻雜區域
39．．．摻雜區域
41．．．填充物
43．．．導體
44．．．摻雜區域
圖1說明根據本發明之雙極電晶體之放大橫截面部分；及圖2至圖7說明根據本發明形成圖1電晶體之方法之各個階段的圖1之電晶體之放大橫截面部分。
鑒於說明之簡單清晰，圖式中元件未必按比例繪製，且不同圖式中之相同參考數字表示相同元件。另外，鑒於描述之簡單，省略為吾人所熟知之步驟及元件之描述及細節。儘管該等裝置在本文中被解釋為某些N－通道或P－通道裝置，但普通熟悉此項技術者將瞭解到，根據本發明互補裝置係亦為可能的。鑒於圖示之清晰，裝置結構之摻雜區域係說明為具有大體直線邊緣及精確角度轉角。然而，熟習此項技術者瞭解到，歸因於摻雜劑之擴散及活化作用，摻雜區域邊緣可能不為直線且轉角可能不為精確角度。
10．．．電晶體
11．．．半導體基板
12．．．表面
13．．．場氧化層
16．．．二氧化矽/氧化物
17．．．保護層
18．．．導體
19．．．保護層
20．．．介電質
28．．．保護隔片
34．．．導體連接
36．．．校準隔片
38．．．摻雜區域
39．．．摻雜區域
41．．．填充物
43．．．導體
44．．．摻雜區域

Claims (16)

  1. 一種用於一電晶體之接點結構，其包含：一半導體基板，其具有一第一表面；一第一摻雜區域，其位於該第一表面上；一第二摻雜區域，其位於該第一表面上且電接觸該第一摻雜區域；一第一導體，其具有一上覆於該第一摻雜區域之第二表面，該第一導體具有一側壁；及一第二導體，其下伏於該第一導體之一部分且自該第二表面延伸以電接觸該第一摻雜區域，其中該第二導體並非位於該第一導體之該側壁上，及一與該第一導體之該側壁實質上共面之校準隔片，其中該第一導體之該側壁係實質上垂直於該第一表面，其中該校準隔片具有一上覆於該第二摻雜區域之開口。
  2. 如請求項1之接點結構，其進一步包括一第三導體，該第三導體上覆於該第二摻雜區域且電接觸該第二摻雜區域，其中該第二導體具有大體上垂直之側壁。
  3. 如請求項2之接點結構，其中該第二摻雜區域係一雙極電晶體之一發射極或一基極其中之一者。
  4. 如請求項1之接點結構，其進一步包括一位於該第一導體之一第三表面上的第一保護層，其中該第三表面係與該第二表面相對。
  5. 如請求項1之接點結構，其進一步包括一位於該第一導體之該側壁上的保護隔片。
  6. 如請求項1之接點結構，其進一步包括一上覆於該第一導體之介電質及一位於該介電質之一側壁及該第一導體之該側壁上之保護隔片，其中該保護隔片係大體上垂直於該第一表面。
  7. 如請求項1之接點結構，其中該校準隔片係位於該第一導體與一第三導體之間。
  8. 一種形成一電晶體之方法，其包含：提供一具有一第一表面之半導體基板；形成一上覆於該半導體基板之該第一表面的至少一部分之氧化物層；形成一第一導體，其具有一同時上覆於該氧化物層之一部分及該第一表面之一第一部分的第二表面且具有一側壁；移除該氧化物層之一部分及形成一第二導體，其自該第二表面延伸以電接觸該第一表面之該第一部分，其中該第二導體係上覆於該氧化層且並非位於該第一導體之該側壁上；形成一第一摻雜區域，其位於該第一表面中且下伏於該第二導體；形成一第二摻雜區域，其位於該第一表面之一第二部分上；形成一第三導體，其上覆於該第二摻雜區域且電接觸該第二摻雜區域。
  9. 如請求項8之方法，其中形成該自該第二表面延伸之第 二導體包括穿過該第一導體形成一曝露該第一導體之該側壁的開口、在該第一導體之該側壁上形成一保護隔片、形成一下伏於該第一導體之凹座及以一導體材料填充該凹座。
  10. 如請求項9之方法，其進一步包括在形成該第二導體之前形成一上覆於該第一導體之介電質、形成該穿過該介電質並曝露該介電質之一側壁及該第一導體之該側壁的開口、及在該介電質之該側壁及該第一導體之該側壁上形成該保護隔片。
  11. 如請求項8之方法，其中形成該第一摻雜區域包括形成該具有一第一導電型之第一摻雜區域及形成該具有一第二導電型之第二摻雜區域。
  12. 一種形成一半導體元件之方法，其包含：提供一具有一第一表面之半導體基板；形成一第一導體，其具有一上覆於該第一表面之一第一部分的第二表面且具有一側壁；在形成該第一導體之後於該第二表面上形成一第二導體，其中該第二導體係電接觸該半導體基板之該第一表面之該第一部分上的一第一摻雜區域，其包括形成該自該第二表面之一部分延伸但並非位於該第一導體之該側壁上的第二導體；形成一第二摻雜區域，其位於該第一表面之一第二部分上且電接觸該第一摻雜區域；及形成一第三導體，其上覆於該第二摻雜區域並電接觸 該第二摻雜區域且不接觸該第一導體或該第二導體。
  13. 如請求項12之方法，其中形成該位於該第二表面上且電接觸該第一摻雜區域之第二導體包括自一具有一第一導電型之摻雜劑的材料形成該第二導體及自該第二導體擴散該摻雜劑之一部分至該第一表面中以形成該第一摻雜區域。
  14. 如請求項12之方法，其中形成該第二摻雜區域包括將具有一第二導電型之雜質植入該第一表面之該第二部分中。
  15. 如請求項12之方法，其中形成該第二摻雜區域包括形成一穿過該第一導體並曝露該第一表面之該第二部分的開口。
  16. 一種形成一半導體元件之方法，其包含：提供一具有一第一表面之半導體基板；形成一第一導體，其具有一上覆於該第一表面之一第一部分的第二表面且具有一側壁；形成一保護隔片，其位於該第一導體之該側壁上；隨後於該第二表面上形成一第二導體，其電接觸該半導體基板之該第一表面之該第一部分上的一第一摻雜區域，其包括形成該自該第二表面之一部分延伸但並非位於該第一導體之該側壁上的第二導體；形成一第二摻雜區域，其位於該第一表面之一第二部分上且電接觸該第一摻雜區域；及形成一第三導體，其上覆於該第二摻雜區域並電接觸該第二摻雜區域且不接觸該第一導體或該第二導體。
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US20070075399A1 (en) 2007-04-05
US7397070B2 (en) 2008-07-08
TW200715551A (en) 2007-04-16
US7300850B2 (en) 2007-11-27
US20080017951A1 (en) 2008-01-24
HK1104667A1 (en) 2008-01-18
KR20070037391A (ko) 2007-04-04
CN1941406B (zh) 2010-09-22
KR101202207B1 (ko) 2012-11-19
CN1941406A (zh) 2007-04-04

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