TWI387826B - Method of manufacturing active device array substrate - Google Patents
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Description
本發明是有關於一種主動元件陣列基板的製造方法，且特別是有關於一種可增加儲存電容之主動元件陣列基板的製造方法。The present invention relates to a method of fabricating an active device array substrate, and more particularly to a method of fabricating an active device array substrate that can increase storage capacitance.
液晶顯示面板主要由主動元件陣列基板、彩色濾光基板和液晶層所構成，其中主動元件陣列基板例如是由多個陣列排列的畫素結構所組成。為了控制個別的畫素結構，通常會經由掃描配線(scan line)與資料配線(date line)以選取特定之畫素結構，並提供適當的操作電壓，以顯示對應此畫素結構之顯示資料。The liquid crystal display panel is mainly composed of an active device array substrate, a color filter substrate and a liquid crystal layer, wherein the active device array substrate is composed of, for example, a plurality of arrayed pixel structures. In order to control the individual pixel structure, a specific pixel structure is usually selected through a scan line and a date line, and an appropriate operating voltage is provided to display the display material corresponding to the pixel structure.
特別是為了保持畫素結構的操作電壓，以增進顯示品質，通常在各畫素結構中會將畫素電極的部分區域覆蓋於掃描線或是電容電極上，以形成儲存電容。In particular, in order to maintain the operating voltage of the pixel structure to improve the display quality, a partial region of the pixel electrode is usually covered on the scan line or the capacitor electrode in each pixel structure to form a storage capacitor.
圖1A為習知的主動元件陣列基板的畫素結構的上視圖。圖1B為沿圖1A的I-I’線的剖面示意圖。請同時參照圖1A與圖1B，在此主動元件陣列基板的畫素結構10中，儲存電容70主要是藉由電容電極30與其上方的畫素電極40耦合而成。在電容電極30與畫素電極40之間配置有閘絕緣層32及保護層60，而形成金屬層/絕緣層/銦錫氧化物層(MII)架構的儲存電容70。1A is a top view of a pixel structure of a conventional active device array substrate. Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A. Referring to FIG. 1A and FIG. 1B simultaneously, in the pixel structure 10 of the active device array substrate, the storage capacitor 70 is mainly formed by coupling the capacitor electrode 30 to the pixel electrode 40 above it. A gate insulating layer 32 and a protective layer 60 are disposed between the capacitor electrode 30 and the pixel electrode 40 to form a storage capacitor 70 of a metal layer/insulating layer/indium tin oxide layer (MII) structure.
儲存電容70主要用以穩定畫素結構10的資料電壓，以提升液晶顯示器的顯示品質。當儲存電容值越大，其穩定畫素結構10的資料電壓的效果越好。有研究者提出一種增加畫素結構10的儲存電容值的方法，亦即增加電容電極30與畫素電極40的重疊面積。然而，此種方法容易導致畫素結構10的開口率(aperture ratio)減少，使得液晶顯示器所顯示的影像容易產生亮度不足的問題。The storage capacitor 70 is mainly used to stabilize the data voltage of the pixel structure 10 to improve the display quality of the liquid crystal display. When the storage capacitor value is larger, the effect of the data voltage of the stable pixel structure 10 is better. Some researchers have proposed a method of increasing the storage capacitor value of the pixel structure 10, that is, increasing the overlapping area of the capacitor electrode 30 and the pixel electrode 40. However, such a method tends to cause a decrease in the aperture ratio of the pixel structure 10, so that the image displayed on the liquid crystal display is liable to cause a problem of insufficient brightness.
有鑑於此，本發明提供一種主動元件陣列基板的製造方法，在不影響畫素之開口率的前提下可提高儲存電容值。In view of the above, the present invention provides a method for fabricating an active device array substrate, which can increase the storage capacitance value without affecting the aperture ratio of the pixel.
本發明提出一種主動元件陣列基板的製造方法。首先，在基板上形成閘極及電容電極。接著，在基板上形成第一絕緣層覆蓋閘極及電容電極。然後，在閘極上方的第一絕緣層上形成通道層。隨之，在通道層上形成源極與汲極，且源極與汲極分別位於閘極之兩側。再者，在基板上全面地形成第二絕緣層。繼之，在基板上形成圖案化光阻層。之後，在一製程時間內，以圖案化光阻層為罩幕移除位於汲極上方及電容電極上方的第二絕緣層以形成接觸窗及開口，其中接觸窗暴露出汲極，而開口暴露出位於電容電極上方的第一絕緣層。接著，於基板上形成畫素電極，且畫素電極透過接觸窗電性連接汲極並填入於開口中。畫素電極、電容電極及位於畫素電極與電容電極之間的第一絕緣層構成儲存電容。The invention provides a method for manufacturing an active device array substrate. First, a gate and a capacitor electrode are formed on a substrate. Next, a first insulating layer is formed on the substrate to cover the gate and the capacitor electrode. Then, a channel layer is formed on the first insulating layer above the gate. Accordingly, a source and a drain are formed on the channel layer, and the source and the drain are respectively located on both sides of the gate. Furthermore, a second insulating layer is formed entirely on the substrate. A patterned photoresist layer is then formed on the substrate. Thereafter, a second insulating layer above the drain and above the capacitor electrode is removed by using the patterned photoresist layer as a mask to form a contact window and an opening, wherein the contact window exposes the drain and the opening is exposed. A first insulating layer is placed over the capacitor electrode. Next, a pixel electrode is formed on the substrate, and the pixel electrode is electrically connected to the drain through the contact window and filled in the opening. The pixel electrode, the capacitor electrode, and the first insulating layer between the pixel electrode and the capacitor electrode constitute a storage capacitor.
在本發明之一實施例中，上述之移除部份第二絕緣層以形成接觸窗及開口的方法包括：進行一乾蝕刻製程。In an embodiment of the invention, the method for removing a portion of the second insulating layer to form the contact window and the opening comprises: performing a dry etching process.
在本發明之一實施例中，藉由控制上述的製程時間使位於電容電極上方且被圖案化光阻層暴露出來的第二絕緣層恰好完全移除。In an embodiment of the invention, the second insulating layer above the capacitor electrode and exposed by the patterned photoresist layer is completely removed by controlling the process time described above.
在本發明之一實施例中，上述之形成圖案化光阻層的方法包括：先於第二絕緣層上形成一光阻材料層。接著，以光罩為罩幕圖案化光阻材料層以形成圖案化光阻層，其中，光罩具有多個光罩圖案，且光罩圖案其中之一設置於汲極上方，而光罩圖案其中之另一設置於電容電極上方。In an embodiment of the invention, the method for forming a patterned photoresist layer comprises: forming a photoresist layer on the second insulating layer. Then, the photoresist layer is patterned with a mask as a mask to form a patterned photoresist layer, wherein the mask has a plurality of mask patterns, and one of the mask patterns is disposed above the drain, and the mask pattern The other one is placed above the capacitor electrode.
在本發明之一實施例中，上述之主動元件陣列基板的製造方法更包括：於源極與通道層之間及汲極與通道層之間形成歐姆接觸層。In an embodiment of the invention, the method for fabricating the active device array substrate further includes forming an ohmic contact layer between the source and the channel layer and between the drain and the channel layer.
本發明另提出一種主動元件陣列基板的製造方法。首先，在基板上形成閘極、電容電極及第一導電接墊。接著，在基板上形成第一絕緣層，且第一絕緣層覆蓋閘極、電容電極及第一導電接墊。然後，在閘極上方的第一絕緣層上形成通道層。接著，在通道層上形成源極與汲極，並同時在第一絕緣層上形成第二導電接墊，其中，源極與汲極分別位於閘極之兩側，而第二導電接墊鄰近第一導電接墊。之後，在基板上全面地形成第二絕緣層。繼之，在第二絕緣層上形成圖案化光阻層。然後，以圖案化光阻層為罩幕進行第一蝕刻製程，移除位於第二導電接墊上方以及第一導電接墊上方的第二絕緣層，以暴露出第二導電接墊及位於第一導電接墊上方的第一絕緣層。隨之，以圖案化光阻層為罩幕進行第二蝕刻製程，移除第一導電接墊上方的第一絕緣層以暴露出第一導電接墊，同時移除汲極上方及電容電極上方的第二絕緣層以形成接觸窗以及開口，其中接觸窗暴露出汲極，而開口暴露出位於電容電極上方的第一絕緣層。之後，於第二絕緣層上形成圖案化電極層，且圖案化電極層包括畫素電極及連接電極。畫素電極透過接觸窗電性連接汲極並填入開口中，而連接電極將第一導電接墊及第二導電接墊電性連接。畫素電極、電容電極及位於畫素電極與電容電極之間的第一絕緣層構成儲存電容。The present invention further provides a method of fabricating an active device array substrate. First, a gate, a capacitor electrode, and a first conductive pad are formed on the substrate. Next, a first insulating layer is formed on the substrate, and the first insulating layer covers the gate, the capacitor electrode and the first conductive pad. Then, a channel layer is formed on the first insulating layer above the gate. Then, a source and a drain are formed on the channel layer, and a second conductive pad is formed on the first insulating layer, wherein the source and the drain are respectively located on two sides of the gate, and the second conductive pad is adjacent to the second conductive pad The first conductive pad. Thereafter, a second insulating layer is entirely formed on the substrate. Next, a patterned photoresist layer is formed on the second insulating layer. Then, performing a first etching process with the patterned photoresist layer as a mask, removing the second insulating layer above the second conductive pad and above the first conductive pad to expose the second conductive pad and located at the second a first insulating layer over a conductive pad. Subsequently, the second photoresist process is performed by using the patterned photoresist layer as a mask, and the first insulating layer above the first conductive pad is removed to expose the first conductive pad while removing the top of the drain and above the capacitor electrode. The second insulating layer forms a contact window and an opening, wherein the contact window exposes the drain, and the opening exposes the first insulating layer above the capacitor electrode. Thereafter, a patterned electrode layer is formed on the second insulating layer, and the patterned electrode layer includes a pixel electrode and a connection electrode. The pixel electrode is electrically connected to the drain through the contact window and filled in the opening, and the connecting electrode electrically connects the first conductive pad and the second conductive pad. The pixel electrode, the capacitor electrode, and the first insulating layer between the pixel electrode and the capacitor electrode constitute a storage capacitor.
在本發明之一實施例中，以第二導電接墊作為第一蝕刻製程的蝕刻終止層。In one embodiment of the invention, the second conductive pad is used as the etch stop layer of the first etch process.
在本發明之一實施例中，以第一導電接墊作為第二蝕刻製程的蝕刻終止層。In one embodiment of the invention, the first conductive pad is used as an etch stop layer for the second etch process.
在本發明之一實施例中，上述之形成圖案化光阻層的方法包括：在第二絕緣層上形成光阻材料層。接著，以半調式光罩為罩幕圖案化光阻材料層以形成圖案化光阻層。此圖案化光阻層可具有多個薄化圖案以及多個穿透口，且薄化圖案分別位於汲極上方及電容電極上方，穿透口分別暴露出第一導電接墊及第二導電接墊上方的第二絕緣層。In one embodiment of the invention, the method of forming a patterned photoresist layer includes forming a photoresist layer on the second insulating layer. Next, the photoresist layer is patterned with a halftone mask as a mask to form a patterned photoresist layer. The patterned photoresist layer may have a plurality of thinned patterns and a plurality of transparent openings, and the thinned patterns are respectively located above the drain electrodes and above the capacitor electrodes, and the through holes respectively expose the first conductive pads and the second conductive pads a second insulating layer above the pad.
舉例而言，上述之形成薄化圖案及穿透口的方法包括：圖案化此光阻材料層以形成多個第一預薄化圖案及多個第二預薄化圖案，其中第一預薄化圖案的膜厚大於第二預薄化圖案的膜厚。接著，進行灰化製程完全移除第二預薄化圖案以形成穿透口並同時使第一預薄化圖案的膜厚減薄以形成薄化圖案。For example, the method for forming a thinned pattern and a through opening includes: patterning the photoresist layer to form a plurality of first pre-thinning patterns and a plurality of second pre-thinning patterns, wherein the first pre-thin The film thickness of the pattern is greater than the film thickness of the second pre-thinned pattern. Next, an ashing process is performed to completely remove the second pre-thinning pattern to form a penetration opening while simultaneously thinning the film thickness of the first pre-thinning pattern to form a thinned pattern.
此外，上述之第一蝕刻製程包括：以圖案化光阻層為罩幕移除穿透口所暴露出來的第二絕緣層，以暴露出第二導電接墊及位於第一導電接墊上方的第一絕緣層。In addition, the first etching process includes: removing a second insulating layer exposed by the transparent opening layer with the patterned photoresist layer as a mask to expose the second conductive pad and the first conductive pad The first insulating layer.
更進一步而言，在進行第一蝕刻製程之後且進行第二蝕刻製程之前，更包括進行一灰化製程以移除薄化圖案以暴露出汲極上方與電容電極上方的第二絕緣層。Further, after performing the first etching process and before performing the second etching process, further including performing an ashing process to remove the thinning pattern to expose the second insulating layer above the drain electrode and above the capacitor electrode.
在本發明之一實施例中，上述之形成該圖案化光阻層的方法包括：在第二絕緣層上形成一光阻材料層。接著，以一灰階光罩為罩幕圖案化此光阻材料層，此圖案化光阻層具有多個第一薄化圖案、多個第二薄化圖案及多個穿透口，其中第一薄化圖案分別位於汲極上方及電容電極上方，而第二薄化圖案的位置位於閘極與電容電極之間、及第一導電接墊與第二導電接墊之間，且第一薄化圖案的膜厚小於第二薄化圖案的膜厚。穿透口分別暴露出第一導電接墊上方及第二導電接墊上方的第二絕緣層。In an embodiment of the invention, the method for forming the patterned photoresist layer comprises: forming a photoresist layer on the second insulating layer. Then, the photoresist layer is patterned by using a gray scale mask as a mask. The patterned photoresist layer has a plurality of first thinned patterns, a plurality of second thinned patterns, and a plurality of through openings. A thinned pattern is respectively located above the drain and above the capacitor electrode, and the second thinned pattern is located between the gate and the capacitor electrode, and between the first conductive pad and the second conductive pad, and the first thin The film thickness of the patterned pattern is smaller than the film thickness of the second thinned pattern. The through openings respectively expose the second insulating layer above the first conductive pads and above the second conductive pads.
在此，形成第一薄化圖案、第二薄化圖案及穿透口的方法包括：圖案化此光阻材料層以形成多個第一預薄化圖案、多個第二預薄化圖案及多個第三預薄化圖案，其中，第一預薄化圖案的膜厚大於第三預薄化圖案的膜厚，而第二預薄化圖案的膜厚大於第一預薄化圖案的膜厚。接著，進行一灰化製程完全移除第三預薄化圖案以形成穿透口，並同時使第一預薄化圖案及第二預薄化圖案的膜厚減薄以分別形成第一薄化圖案及第二薄化圖案。Here, the method of forming the first thinning pattern, the second thinning pattern, and the through opening includes: patterning the photoresist material layer to form a plurality of first pre-thinning patterns, a plurality of second pre-thinning patterns, and a plurality of third pre-thinning patterns, wherein a film thickness of the first pre-thinning pattern is greater than a film thickness of the third pre-thinning pattern, and a film thickness of the second pre-thinning pattern is greater than a film of the first pre-thinning pattern thick. Then, an ashing process is performed to completely remove the third pre-thinning pattern to form a penetration opening, and at the same time, the film thicknesses of the first pre-thinning pattern and the second pre-thinning pattern are thinned to form a first thinning The pattern and the second thinned pattern.
在本發明之一實施例中，上述之第一蝕刻製程包括：以圖案化光阻層為罩幕移除穿透口所暴露出來的第二絕緣層，以暴露出第二導電接墊及位於第一導電接墊上方的第一絕緣層。In an embodiment of the invention, the first etching process includes: removing the second insulating layer exposed by the transparent opening by using the patterned photoresist layer as a mask to expose the second conductive pad and located a first insulating layer above the first conductive pad.
在本發明之一實施例中，在進行第一蝕刻製程之後，且進行第二蝕刻製程之前更包括：進行一灰化製程，將第一薄化圖案完全移除以暴露出汲極上方與電容電極上方的第二絕緣層，並同時使第二薄化圖案的膜厚減薄。In an embodiment of the present invention, after performing the first etching process and before performing the second etching process, the method further includes: performing an ashing process to completely remove the first thinning pattern to expose the top of the drain and the capacitor The second insulating layer above the electrode, while simultaneously reducing the film thickness of the second thinned pattern.
此外，在進行第二蝕刻製程之後且形成圖案化電極層之前，可更包括進行一灰化製程，將第二薄化圖案完全移除以暴露出位於閘極與電容電極之間及第一導電接墊與第二導電接墊之間的第二絕緣層。在一實施例中，形成圖案化電極層的方法包括：於圖案化光阻層及第二絕緣層上全面地形成一電極材料層。並且，在移除圖案化光阻層同時，一併移除覆蓋於圖案化光阻層上的電極材料層，以於第二絕緣層上形成畫素電極及連接電極。In addition, after performing the second etching process and before forming the patterned electrode layer, the method further includes performing an ashing process to completely remove the second thinning pattern to expose the gate and the capacitor electrode and the first conductive a second insulating layer between the pad and the second conductive pad. In one embodiment, the method of forming a patterned electrode layer includes integrally forming an electrode material layer on the patterned photoresist layer and the second insulating layer. Moreover, while removing the patterned photoresist layer, the electrode material layer covering the patterned photoresist layer is removed together to form a pixel electrode and a connection electrode on the second insulating layer.
在本發明之一實施例中，上述之第一蝕刻製程或第二蝕刻製程包括一乾式蝕刻製程。In an embodiment of the invention, the first etching process or the second etching process includes a dry etching process.
在本發明之一實施例中，上述之形成圖案化電極層之前更包括：完全移除圖案化光阻層。In an embodiment of the invention, before the forming the patterned electrode layer, the method further comprises: completely removing the patterned photoresist layer.
在本發明之一實施例中，上述之主動元件陣列基板的製造方法更包括：於源極與通道層之間及汲極與通道層之間形成一歐姆接觸層。In an embodiment of the invention, the method for fabricating the active device array substrate further includes: forming an ohmic contact layer between the source and the channel layer and between the drain and the channel layer.
基於上述，本發明所提出的主動元件陣列基板的製造方法，利用形成接觸窗時一併移除電容電極上方的第二絕緣層。如此一來，僅有第一絕緣層夾於電容電極與畫素電極之間而構成電容值較大的一儲存電容。此外，本發明在蝕刻第二絕緣層以形成接觸窗時更適當地控制製程時間、或是以第一/第二導電接墊作為蝕刻終止層以良好地控制第二絕緣層被移除的深度。因此，本發明的主動元件陣列基板的製造方法具有良好的製程良率，可以避免過度蝕刻或是蝕刻不足的現象發生。Based on the above, the method for fabricating the active device array substrate according to the present invention utilizes the formation of the contact window to remove the second insulating layer above the capacitor electrode. In this way, only the first insulating layer is sandwiched between the capacitor electrode and the pixel electrode to form a storage capacitor having a large capacitance value. In addition, the present invention more appropriately controls the process time when etching the second insulating layer to form a contact window, or uses the first/second conductive pad as an etch stop layer to well control the depth at which the second insulating layer is removed. . Therefore, the method for fabricating the active device array substrate of the present invention has a good process yield and can avoid excessive etching or insufficient etching.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2為本發明較佳實施例的一種主動元件陣列基板的局部剖面示意圖。請參照圖2，此主動元件陣列基板20包括基板200、閘極210、電容電極220、第一絕緣層230、通道層240、源極250、汲極260、第二絕緣層270以及畫素電極280。2 is a partial cross-sectional view of an active device array substrate in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the active device array substrate 20 includes a substrate 200, a gate 210, a capacitor electrode 220, a first insulating layer 230, a channel layer 240, a source 250, a drain 260, a second insulating layer 270, and a pixel electrode. 280.
請繼續參照圖2，閘極210與電容電極220配置於基板200上。第一絕緣層230覆蓋閘極210與電容電極220。通道層240配置於第一絕緣層230上，且通道層240位於閘極210上方。源極250與汲極260皆配置於通道層240上，並且源極250與汲極260的位置分別位於閘極210的兩側。具體而言，源極250與汲極260互不相連，且閘極210、通道層240、源極250與汲極260共同構成一電晶體TFT。Referring to FIG. 2 , the gate 210 and the capacitor electrode 220 are disposed on the substrate 200 . The first insulating layer 230 covers the gate 210 and the capacitor electrode 220. The channel layer 240 is disposed on the first insulating layer 230, and the channel layer 240 is located above the gate 210. The source 250 and the drain 260 are both disposed on the channel layer 240, and the positions of the source 250 and the drain 260 are respectively located on both sides of the gate 210. Specifically, the source 250 and the drain 260 are not connected to each other, and the gate 210, the channel layer 240, the source 250 and the drain 260 together form a transistor TFT.
此外，第二絕緣層270覆蓋於基板200上，且第二絕緣層270具有一接觸窗272以及一開口274。畫素電極280配置於第二絕緣層270上並透過接觸窗272電性連接汲極260。同時，畫素電極280填入於開口274中。值得一提的是，開口274暴露出位於電容電極220上方的第一絕緣層230，以使畫素電極280、電容電極220及位於畫素電極280與電容電極220之間的第一絕緣層230構成儲存電容290。In addition, the second insulating layer 270 covers the substrate 200, and the second insulating layer 270 has a contact window 272 and an opening 274. The pixel electrode 280 is disposed on the second insulating layer 270 and electrically connected to the drain 260 through the contact window 272. At the same time, the pixel electrode 280 is filled in the opening 274. It is worth mentioning that the opening 274 exposes the first insulating layer 230 above the capacitor electrode 220 to make the pixel electrode 280, the capacitor electrode 220 and the first insulating layer 230 between the pixel electrode 280 and the capacitor electrode 220. A storage capacitor 290 is formed.
在本實施例的儲存電容290的結構中僅有一層絕緣層，也就是僅有第一絕緣層230配置於電容電極220與畫素電極280兩導電層之間。根據以下公式(1)，電容(C)導電層面積(A)/絕緣層厚度(T)...(1)In the structure of the storage capacitor 290 of the present embodiment, there is only one insulating layer, that is, only the first insulating layer 230 is disposed between the capacitor electrode 220 and the two conductive layers of the pixel electrode 280. Capacitance (C) according to the following formula (1) Conductive layer area (A) / insulation layer thickness (T)...(1)
可知，在不改變導電層面積的情形下，將絕緣層厚度減薄即可提昇儲存電容。更詳細而言，在導電層(電容電極220、畫素電極280)以相同面積佈局的條件下，本實施例的儲存電容290僅具有第一絕緣層230(絕緣層厚度較薄)，因此相較於習知的儲存電容Cs1(如圖1B所示)而言，本實施例的儲存電容290具有較大的儲存電容值。在不影響主動元件陣列基板20之開口率的前提之下，可有效提高儲存電容290的儲存電容值。It can be seen that the storage capacitor can be increased by reducing the thickness of the insulating layer without changing the area of the conductive layer. In more detail, under the condition that the conductive layer (capacitor electrode 220, pixel electrode 280) is laid out in the same area, the storage capacitor 290 of the embodiment has only the first insulating layer 230 (the thickness of the insulating layer is thin), so the phase Compared with the conventional storage capacitor Cs1 (as shown in FIG. 1B), the storage capacitor 290 of the present embodiment has a large storage capacitance value. The storage capacitor value of the storage capacitor 290 can be effectively increased without affecting the aperture ratio of the active device array substrate 20.
實際上，為了製作具有高儲存電容值的儲存電容290，本發明於下列實施例中提出數種主動元件陣列基板的製造方法。下述製造方法僅為舉例說明之用，並非用以限定本發明。In fact, in order to fabricate the storage capacitor 290 having a high storage capacitance value, the present invention proposes a method of fabricating a plurality of active device array substrates in the following embodiments. The following manufacturing methods are for illustrative purposes only and are not intended to limit the invention.
圖3A至圖3D為本發明第一實施例的主動元件陣列基板的製造方法的示意圖。請先參照圖3A，首先，在基板200上形成閘極210及電容電極220。此閘極210與電容電極220例如是自同一導體層圖案化而成的。接著，在基板200上形成一第一絕緣層230，其覆蓋閘極210及電容電極220。然後，在閘極210上方的第一絕緣層230上形成一通道層240。通道層240例如是一圖案化的半導體層。隨之，在通道層240上形成一源極250與一汲極260，且源極250與汲極260分別位於閘極210之兩側。3A to 3D are schematic views showing a method of manufacturing an active device array substrate according to a first embodiment of the present invention. Referring first to FIG. 3A, first, a gate 210 and a capacitor electrode 220 are formed on a substrate 200. The gate 210 and the capacitor electrode 220 are patterned, for example, from the same conductor layer. Next, a first insulating layer 230 is formed on the substrate 200, which covers the gate 210 and the capacitor electrode 220. Then, a channel layer 240 is formed on the first insulating layer 230 above the gate 210. Channel layer 240 is, for example, a patterned semiconductor layer. A source 250 and a drain 260 are formed on the channel layer 240, and the source 250 and the drain 260 are respectively located on opposite sides of the gate 210.
閘極210、通道層240、源極250與汲極260共同構成一電晶體TFT。此外，在本實施例中，形成通道層240後，例如更於基板200上形成一歐姆接觸層242，以提高電晶體TFT的性能。The gate 210, the channel layer 240, the source 250 and the drain 260 together form a transistor TFT. Further, in the present embodiment, after the channel layer 240 is formed, for example, an ohmic contact layer 242 is formed on the substrate 200 to improve the performance of the transistor TFT.
本實施例於圖3A中所繪示的電晶體TFT結構僅是舉例說明之用，在其他實施例中可以調整電晶體TFT的製作方式而使電晶體TFT呈現其他的結構。舉例而言，通道層240、源極250與汲極260可以在同一個製程步驟中被圖案化，以使源極250與第一絕緣層230之間以及汲極260與第一絕緣層230之間都配置有半導體層。換言之，本發明並不限定電晶體TFT的結構。此外，本實施例不限定電晶體TFT的製作方式，凡所屬技術領域應用於製作電晶體TFT的方法都可以應用在本實施例中。The transistor TFT structure illustrated in FIG. 3A in this embodiment is for illustrative purposes only. In other embodiments, the fabrication mode of the transistor TFT can be adjusted to make the transistor TFT exhibit other structures. For example, the channel layer 240, the source 250, and the drain 260 may be patterned in the same process step to enable the source 250 and the first insulating layer 230 and between the drain 260 and the first insulating layer 230. A semiconductor layer is disposed between them. In other words, the present invention does not limit the structure of the transistor TFT. In addition, this embodiment does not limit the fabrication method of the transistor TFT, and any method applicable to the fabrication of the transistor TFT in the technical field can be applied to the embodiment.
然後，請參照圖3B，在基板200上全面地形成一第二絕緣層270。再來，於基板200上形成一圖案化光阻層300。在此，圖案化光阻層300例如是暴露出汲極260上方的部分第二絕緣層270以及電容電極220上方的部分第二絕緣層270。Then, referring to FIG. 3B, a second insulating layer 270 is entirely formed on the substrate 200. Then, a patterned photoresist layer 300 is formed on the substrate 200. Here, the patterned photoresist layer 300 is, for example, a portion of the second insulating layer 270 exposed above the drain 260 and a portion of the second insulating layer 270 above the capacitor electrode 220.
詳言之，形成圖案化光阻層300的方法例如是先於第二絕緣層270上形成一光阻材料層(未繪示)。接著，以一光罩為罩幕圖案化光阻材料層(未繪示)以形成圖案化光阻層300。具體而言，在此步驟中所使用的光罩(未繪示)例如具有多個光罩圖案(未繪示)。當圖案化此光阻材料層(未繪示)時，光罩圖案其中之一設置於汲極260上方，而光罩圖案其中之另一設置於電容電極220上方。In detail, the method of forming the patterned photoresist layer 300 is, for example, forming a photoresist material layer (not shown) on the second insulating layer 270. Next, a photoresist layer (not shown) is patterned with a mask as a mask to form a patterned photoresist layer 300. Specifically, the reticle (not shown) used in this step has, for example, a plurality of reticle patterns (not shown). When the photoresist layer (not shown) is patterned, one of the reticle patterns is disposed above the drain 260, and the other of the reticle patterns is disposed above the capacitor electrode 220.
如此一來，光阻材料層(未繪示)顯影後而形成的圖案化光阻層300便可暴露出汲極260上方的部分第二絕緣層270以及電容電極220上方的部分第二絕緣層270。值得一提的是，光罩圖案的設計可以隨光阻材料層之材料選用而有所不同。亦即，選用正型光阻材料或是負型光阻材料作為光阻材料層時，需分別搭配不同的光罩圖案以形成圖案化光阻層280。In this way, the patterned photoresist layer 300 formed by developing the photoresist layer (not shown) exposes a portion of the second insulating layer 270 above the drain 260 and a portion of the second insulating layer above the capacitor electrode 220. 270. It is worth mentioning that the design of the mask pattern may vary depending on the material of the photoresist layer. That is, when a positive photoresist material or a negative photoresist material is selected as the photoresist material layer, different mask patterns are separately used to form the patterned photoresist layer 280.
之後，請繼續參照圖3B並同時參照圖3C，在一製程時間內，以圖案化光阻層300為罩幕移除位於汲極260上方及電容電極220上方的第二絕緣層270以形成一接觸窗272及一開口274。接觸窗272暴露出汲極260，而開口274則暴露出位於電容電極220上方的第一絕緣層230。在此，移除部份的第二絕緣層270之方法例如為乾蝕刻製程。Thereafter, referring to FIG. 3B and referring to FIG. 3C, the second insulating layer 270 above the drain 260 and above the capacitor electrode 220 is removed by using the patterned photoresist layer 300 as a mask during a process time to form a Contact window 272 and an opening 274. The contact window 272 exposes the drain 260, and the opening 274 exposes the first insulating layer 230 above the capacitor electrode 220. Here, the method of removing a portion of the second insulating layer 270 is, for example, a dry etching process.
一般而言，電容電極220必需由至少一層絕緣層所覆蓋以提供適當的電容效應。因此，部分的第二絕緣層270被移除的過程必須控制在適當的製程時間內，以免發生過度蝕刻的情形而使第一絕緣層230也被移除。換言之，本實施例移除部份的第二絕緣層270時，可以藉由控制製程時間，以使位於電容電極220上方且被圖案化光阻層300暴露出來的第二絕緣層270恰好完全移除。特別是，搭配乾蝕刻製程可使移除電容電極220上方的第二絕緣層270的精確度更高。在此步驟中，可減薄儲存電容290的絕緣層的整體厚度(僅有第一絕緣層230)。In general, capacitor electrode 220 must be covered by at least one insulating layer to provide a suitable capacitive effect. Therefore, the process of removing part of the second insulating layer 270 must be controlled within a suitable process time to avoid excessive etching and the first insulating layer 230 is also removed. In other words, when the second insulating layer 270 is removed in the embodiment, the second insulating layer 270 located above the capacitor electrode 220 and exposed by the patterned photoresist layer 300 can be completely shifted by controlling the processing time. except. In particular, the precision of the second insulating layer 270 above the capacitor electrode 220 can be made higher by the dry etching process. In this step, the overall thickness of the insulating layer of the storage capacitor 290 can be thinned (only the first insulating layer 230).
接著，請參照圖3D，於基板200上形成一畫素電極280，且畫素電極280透過接觸窗272電性連接汲極260並填入於開口274中。此時，主動元件陣列基板20已大致完成，其中，畫素電極280、電容電極220及位於畫素電極280與電容電極220之間的第一絕緣層230構成一儲存電容290。Next, referring to FIG. 3D , a pixel electrode 280 is formed on the substrate 200 , and the pixel electrode 280 is electrically connected to the drain 260 through the contact window 272 and filled in the opening 274 . At this time, the active device array substrate 20 has been substantially completed, wherein the pixel electrode 280, the capacitor electrode 220, and the first insulating layer 230 between the pixel electrode 280 and the capacitor electrode 220 constitute a storage capacitor 290.
在本實施例中，由於在製作接觸窗272的同時也移除了電容電極220上方的第二絕緣層270，使得畫素電極280與電容電極220之間僅配置有一層第一絕緣層230。因此，除了可有效地增加儲存電容290的電容值還可提昇整體的顯示開口率。In the present embodiment, since the second insulating layer 270 above the capacitor electrode 220 is also removed while the contact window 272 is formed, only one layer of the first insulating layer 230 is disposed between the pixel electrode 280 and the capacitor electrode 220. Therefore, in addition to effectively increasing the capacitance value of the storage capacitor 290, the overall display aperture ratio can be improved.
特別是，本實施例的製造方法在同一道光罩製程中製作接觸窗272與移除第二絕緣層的270，不會增加光罩數量，可降低製作成本。承上述，應用主動元件陣列基板20的液晶顯示器可以具有良好的顯示品質，且在顯示開口率上不會受到負面的影響。In particular, the manufacturing method of the present embodiment can form the contact window 272 and the second insulating layer 270 in the same mask process, without increasing the number of masks, and reducing the manufacturing cost. In view of the above, the liquid crystal display to which the active device array substrate 20 is applied can have good display quality and is not adversely affected in display aperture ratio.
圖4A至圖4F為本發明第二實施例的主動元件陣列基板的製造方法的示意圖。請先參照圖4A，首先提供基板400，其中基板400上配置有如圖3A所繪示的電晶體TFT以及電容電極220。詳細的結構不再予以重述。4A to 4F are schematic views showing a method of manufacturing an active device array substrate according to a second embodiment of the present invention. Referring to FIG. 4A , a substrate 400 is first provided. The substrate 400 is provided with a transistor TFT and a capacitor electrode 220 as illustrated in FIG. 3A . The detailed structure will not be repeated.
值得注意的是，在基板400上更形成有位置相鄰的一第一導電接墊410以及一第二導電接墊420。第一導電接墊410例如是與電晶體TFT的閘極310一併形成，而第二導電接墊420例如是與電晶體TFT的源極250與汲極260一併形成。實際上，第一導電接墊410配置於基板400與第一絕緣層230之間而第二導電接墊420配置於第一絕緣層230與第二絕緣層270之間。It should be noted that a first conductive pad 410 and a second conductive pad 420 adjacent to each other are formed on the substrate 400. The first conductive pad 410 is formed, for example, together with the gate 310 of the transistor TFT, and the second conductive pad 420 is formed, for example, together with the source 250 and the drain 260 of the transistor TFT. In fact, the first conductive pad 410 is disposed between the substrate 400 and the first insulating layer 230 , and the second conductive pad 420 is disposed between the first insulating layer 230 and the second insulating layer 270 .
另外，第二絕緣層270全面地覆蓋於基板400上。第二絕緣層270上形成有一圖案化光阻層430。形成圖案化光阻層430的方法包括在第二絕緣層270上形成一光阻材料層(未繪示)以及以一半調式光罩(未繪示)為罩幕圖案化光阻材料層(未繪示)以形成圖案化光阻層430。In addition, the second insulating layer 270 is entirely covered on the substrate 400. A patterned photoresist layer 430 is formed on the second insulating layer 270. The method of forming the patterned photoresist layer 430 includes forming a photoresist layer (not shown) on the second insulating layer 270 and patterning the photoresist layer with a halftone mask (not shown) as a mask (not shown). Illustrated) to form a patterned photoresist layer 430.
本實施例例如是先如圖4A所示，以半調式光罩為罩幕將光阻材料層(未繪示)圖案化以形成多個第一預薄化圖案432及多個第二預薄化圖案434。在此，第一預薄化圖案432的膜厚例如是大於第二預薄化圖案434的膜厚。另外，第一預薄化圖案432分別位於汲極260上方及電容電極220上方，而第二預薄化圖案434分別位於第一導電接墊410及第二導電接墊420上方In this embodiment, for example, as shown in FIG. 4A, a photoresist material layer (not shown) is patterned by using a halftone mask as a mask to form a plurality of first pre-thinning patterns 432 and a plurality of second pre-thin sheets. Pattern 434. Here, the film thickness of the first pre-thinned pattern 432 is, for example, larger than the film thickness of the second pre-thinned pattern 434. In addition, the first pre-thinning pattern 432 is located above the drain 260 and above the capacitor electrode 220, and the second pre-thinning pattern 434 is located above the first conductive pad 410 and the second conductive pad 420, respectively.
隨之，進行一灰化製程完全移除第二預薄化圖案434以形成如圖4B所示之多個穿透口434A並同時使第一預薄化圖案432的膜厚減薄以形成多個薄化圖案432A。Subsequently, an ashing process is performed to completely remove the second pre-thinned pattern 434 to form a plurality of through-holes 434A as shown in FIG. 4B and simultaneously reduce the film thickness of the first pre-thinned pattern 432 to form a plurality of Thinning patterns 432A.
換言之，圖案化光阻層270具有多個薄化圖案432A以及多個穿透口434A。薄化圖案432A分別位於汲極260上方及電容電極220上方，而穿透口434A分別暴露出第一導電接墊410上方及第二導電接墊420上方的第二絕緣層270。In other words, the patterned photoresist layer 270 has a plurality of thinned patterns 432A and a plurality of through holes 434A. The thinning patterns 432A are respectively located above the drain electrodes 260 and above the capacitor electrodes 220, and the through holes 434A respectively expose the second insulating layer 270 above the first conductive pads 410 and above the second conductive pads 420.
本實施例所提出之形成薄化圖案432A以及穿透口434A的方法僅為舉例說明，本發明不限於此。換言之，在其他實施例中尚可使用不同的製程方式使得圖案化光阻層430具有薄化圖案432A以及穿透口434A。The method of forming the thinned pattern 432A and the through opening 434A proposed in this embodiment is merely illustrative, and the present invention is not limited thereto. In other words, different process modes can be used in other embodiments such that the patterned photoresist layer 430 has a thinned pattern 432A and a through opening 434A.
接著，請參照圖4C，以圖案化光阻層430為罩幕進行一第一蝕刻製程，移除位於第二導電接墊420上方以及第一導電接墊410上方的第二絕緣層270。如此一來，第二導電接墊420及第一導電接墊410上方的第一絕緣層230會被暴露出來。換言之，第一蝕刻製程會將穿透口434A所暴露出來的第二絕緣層270移除。Next, referring to FIG. 4C , a first etching process is performed by patterning the photoresist layer 430 as a mask to remove the second insulating layer 270 above the second conductive pad 420 and above the first conductive pad 410 . As a result, the second conductive pad 420 and the first insulating layer 230 above the first conductive pad 410 are exposed. In other words, the first etching process removes the second insulating layer 270 exposed by the through opening 434A.
特別是，在此以第二導電接墊420作為第一蝕刻製程的蝕刻終止層。更詳細而言，在本實施例中，第二導電接墊420上方僅由第二絕緣層270覆蓋著，而未被圖案化光阻層430所覆蓋。因此，第一蝕刻製程若以第二導電接墊420作為蝕刻終止層，則第一蝕刻製程所蝕刻的深度恰好是第二絕緣層270的膜厚。換言之，第一導電接墊410上的第二絕緣層270在第一蝕刻製程中可以恰好被完全移除，而暴露出第一導電接墊410上方的第一絕緣層230。In particular, the second conductive pad 420 is used herein as an etch stop layer for the first etch process. In more detail, in the present embodiment, the second conductive pad 420 is covered only by the second insulating layer 270, and is not covered by the patterned photoresist layer 430. Therefore, if the first etching process uses the second conductive pad 420 as an etch stop layer, the first etching process etches the depth just by the film thickness of the second insulating layer 270. In other words, the second insulating layer 270 on the first conductive pad 410 may be completely removed in the first etching process to expose the first insulating layer 230 above the first conductive pad 410.
接著，請同時參照圖4C與圖4D，進行一灰化製程，以移除圖案化光阻層430中的薄化圖案432A。薄化圖案432A被移除後，位於汲極260上方以及位於電容電極220上方的第二絕緣層270會被暴露出來。Next, referring to FIG. 4C and FIG. 4D simultaneously, an ashing process is performed to remove the thinned pattern 432A in the patterned photoresist layer 430. After the thinned pattern 432A is removed, the second insulating layer 270 over the drain 260 and over the capacitor electrode 220 is exposed.
然後，請同時參照圖4D與圖4E，繼續以圖案化光阻層430為罩幕進行一第二蝕刻製程，移除第一導電接墊410上方的第一絕緣層230以暴露出第一導電接墊410。同時，在第二蝕刻製程中移除汲極260上方及電容電極220上方的第二絕緣層270以形成一接觸窗272以及一開口274。接觸窗272例如會暴露出汲極260，而開口274暴露出位於電容電極220上方的第一絕緣層230。本實施例的第一蝕刻製程或第二蝕刻製程例如採用乾式蝕刻製程。Then, referring to FIG. 4D and FIG. 4E , the second etching process is continued by using the patterned photoresist layer 430 as a mask to remove the first insulating layer 230 above the first conductive pad 410 to expose the first conductive layer. Pad 410. At the same time, the second insulating layer 270 above the drain 260 and above the capacitor electrode 220 is removed in the second etching process to form a contact window 272 and an opening 274. Contact window 272, for example, exposes drain 260, while opening 274 exposes first insulating layer 230 over capacitor electrode 220. The first etching process or the second etching process of this embodiment uses, for example, a dry etching process.
值得一提的是，第二蝕刻製程是以第一導電接墊410作為蝕刻終止層，也就是說第二蝕刻製程的蝕刻深度恰好可以移除第一絕緣層230的膜厚。此時，被圖案化光阻層430暴露出來的第二絕緣層270也會被移除相同的膜厚而形成接觸窗272與開口274。第二蝕刻製程有第一導電接墊410作為蝕刻終止層，所以第二蝕刻製程在形成開口274時不會將電容電極220上方的第一絕緣層230也移除。因此，蝕刻終止層設計有助於提高本實施例的製程良率。It is worth mentioning that the second etching process uses the first conductive pad 410 as an etch stop layer, that is, the etching depth of the second etching process just removes the film thickness of the first insulating layer 230. At this time, the second insulating layer 270 exposed by the patterned photoresist layer 430 is also removed by the same film thickness to form the contact window 272 and the opening 274. The second etching process has the first conductive pad 410 as an etch stop layer, so the second etching process does not remove the first insulating layer 230 above the capacitor electrode 220 when the opening 274 is formed. Therefore, the etch stop layer design contributes to the improvement of the process yield of the present embodiment.
然後，請參照圖4F，於第二絕緣層270上形成一圖案化電極層440以形成主動元件陣列基板40。圖案化電極層440包括一畫素電極442及一連接電極444。畫素電極442透過接觸窗272電性連接汲極260並填入開口274中，而連接電極444將第一導電接墊410及第二導電接墊420電性連接。在此，畫素電極442、電容電極220及位於畫素電極442與電容電極220之間的第一絕緣層230構成一儲存電容530。值得注意的是，第一導電接墊410例如是位於顯示區(未繪示)中的掃描線或資料線的連接端子，而第二導電接墊420例如是位於周邊區(未繪示)中的用以連接到源極驅動器或閘極驅動器的外部端子，利用如圖4F的設計可以進行跳層式的電性連接，可增加電路設計的自由度。Then, referring to FIG. 4F, a patterned electrode layer 440 is formed on the second insulating layer 270 to form the active device array substrate 40. The patterned electrode layer 440 includes a pixel electrode 442 and a connection electrode 444. The pixel electrode 442 is electrically connected to the drain 260 through the contact window 272 and filled in the opening 274, and the connection electrode 444 electrically connects the first conductive pad 410 and the second conductive pad 420. Here, the pixel electrode 442, the capacitor electrode 220, and the first insulating layer 230 between the pixel electrode 442 and the capacitor electrode 220 constitute a storage capacitor 530. It is to be noted that the first conductive pad 410 is, for example, a connection terminal of a scan line or a data line in a display area (not shown), and the second conductive pad 420 is, for example, located in a peripheral area (not shown). The external terminals for connecting to the source driver or the gate driver can be electrically connected by a jumper layer using the design of FIG. 4F, which increases the degree of freedom in circuit design.
實際上，在形成圖案化電極層440之前更包括完全移除圖4E所示的圖案化光阻層430。圖案化電極層440的形成方式則例如是先形成一電極材料層(未繪示)於基板400上，再圖案化此電極材料層(未繪示)。圖案化此電極材料層(未繪示)的方式可以是進行一微影蝕刻製程。In fact, it is further included to completely remove the patterned photoresist layer 430 shown in FIG. 4E before forming the patterned electrode layer 440. The patterned electrode layer 440 is formed by, for example, forming an electrode material layer (not shown) on the substrate 400, and then patterning the electrode material layer (not shown). The pattern of the electrode material layer (not shown) may be patterned by performing a photolithography process.
由於儲存電容530的結構中僅有第一絕緣層230配置於畫素電極442與電容電極220兩導電層中間，儲存電容530可具有較大的儲存電容值。因此，應用主動元件陣列基板40的液晶顯示器可以具有良好的顯示品質。此外，藉由第二蝕刻製程將電容電極220上方的第二絕緣層270移可以有效提高儲存電容530的電容值而不需增加儲存電容530的面積。所以，應用主動元件陣列基板40的液晶顯示器還可以保有高開口率的特性。Since only the first insulating layer 230 is disposed between the two conductive layers of the pixel electrode 442 and the capacitor electrode 220 in the structure of the storage capacitor 530, the storage capacitor 530 can have a large storage capacitance value. Therefore, the liquid crystal display to which the active device array substrate 40 is applied can have good display quality. In addition, moving the second insulating layer 270 above the capacitor electrode 220 by the second etching process can effectively increase the capacitance of the storage capacitor 530 without increasing the area of the storage capacitor 530. Therefore, the liquid crystal display to which the active device array substrate 40 is applied can also maintain the characteristics of a high aperture ratio.
值得一提的是，電容電極220若被暴露出來會造成產品良率降低。本實施例的第二蝕刻製程以第一導電接墊410作為蝕刻終止層可以避免電容電極220上方的絕緣層被過度蝕刻。因此，本實施例的主動元件陣列基板40的製造方法除上述優點外至少還具有高製程良率的優點。It is worth mentioning that if the capacitor electrode 220 is exposed, the yield of the product will be lowered. The second etching process of the embodiment uses the first conductive pad 410 as an etch stop layer to prevent the insulating layer above the capacitor electrode 220 from being over-etched. Therefore, the manufacturing method of the active device array substrate 40 of the present embodiment has at least the advantage of high process yield in addition to the above advantages.
圖5A至圖5H為本發明第三實施例的主動元件陣列基板的製造方法的示意圖。請先參照圖5A，提供一個如圖4A所繪示的基板400。在本實施例中，除了圖案化光阻層500與圖4A所繪示的圖案化光阻層430不同外，基板400上所配置的其他構件皆與圖4A所繪示之構件相同，在此不再贅述。當然，本實施例中與圖4A相同之構件可以採用相同的方式加以製作，但本發明不限於此。5A to 5H are schematic views showing a method of manufacturing an active device array substrate according to a third embodiment of the present invention. Referring first to FIG. 5A, a substrate 400 as shown in FIG. 4A is provided. In this embodiment, except that the patterned photoresist layer 500 is different from the patterned photoresist layer 430 illustrated in FIG. 4A, other components disposed on the substrate 400 are the same as those illustrated in FIG. 4A. No longer. Of course, the same members of the embodiment as those of FIG. 4A can be fabricated in the same manner, but the invention is not limited thereto.
具體而言，本實施例形成圖案化光阻層500的方法包括在第二絕緣層270上形成一光阻材料層(未繪示)以及以一灰階光罩(未繪示)為罩幕圖案化光阻材料層(未繪示)。如此一來，基板400上例如形成有多個第一預薄化圖案502、多個第二預薄化圖案504及多個第三預薄化圖案506。Specifically, the method for forming the patterned photoresist layer 500 in the embodiment includes forming a photoresist material layer (not shown) on the second insulating layer 270 and masking with a gray scale mask (not shown). A layer of patterned photoresist material (not shown). In this manner, for example, a plurality of first pre-thinning patterns 502, a plurality of second pre-thinning patterns 504, and a plurality of third pre-thinning patterns 506 are formed on the substrate 400.
具體而言，第一預薄化圖案502分別地位於汲極260以及電容電極220上方；第二預薄化圖案504分別地位於閘極210與電容電極220之間及第一導電接墊410與第二導電接墊420之間；且第三預薄化圖案506則分別位於第一導電接墊410上方及第二導電接墊420上方。此外，第一預薄化圖案502的膜厚大於第三預薄化圖案506的膜厚，而第二預薄化圖案504的膜厚大於第一預薄化圖案502的膜厚。Specifically, the first pre-thinning pattern 502 is respectively located above the drain 260 and the capacitor electrode 220; the second pre-thinning pattern 504 is respectively located between the gate 210 and the capacitor electrode 220 and the first conductive pad 410 and The second pre-thinning pattern 506 is located above the first conductive pad 410 and above the second conductive pad 420. In addition, the film thickness of the first pre-thinning pattern 502 is greater than the film thickness of the third pre-thinning pattern 506, and the film thickness of the second pre-thinning pattern 504 is greater than the film thickness of the first pre-thinning pattern 502.
在本實施例中，利用灰階光罩在不同區域可提供不同透光率的特性使得圖案化光阻層500具有階梯狀分布的圖案。如此一來，在後續的蝕刻製程步驟中可以達到差異蝕刻的效果以節省光罩使用數目進而減少製作成本。相似地，在第三實施例中也可使用半調式光罩以達到差異蝕刻的效果。In the present embodiment, the characteristics of different light transmittances can be provided in different regions by using a gray scale mask such that the patterned photoresist layer 500 has a pattern of stepped distribution. In this way, the effect of differential etching can be achieved in the subsequent etching process step to save the number of masks used and thus reduce the manufacturing cost. Similarly, a half-tone mask can also be used in the third embodiment to achieve the effect of differential etching.
接著，請參照圖5B，進行一灰化製程，完全移除第三預薄化圖案506以形成穿透口506A，並同時使第一預薄化圖案502及第二預薄化圖案504的膜厚減薄以分別形成第一薄化圖案502A及第二薄化圖案504A。第一薄化圖案502A分別位於汲極260上方及電容電極220上方，而第二薄化圖案504A的位置位於閘極210與電容電極220之間及第一導電接墊410與第二導電接墊420之間。另外，第一薄化圖案502A的膜厚小於第二薄化圖案504A的膜厚，而穿透口506A則分別地暴露出第一導電接墊410與第二導電接墊420上方的第二絕緣層270。Next, referring to FIG. 5B, an ashing process is performed to completely remove the third pre-thinning pattern 506 to form the transparent opening 506A, and simultaneously make the film of the first pre-thinning pattern 502 and the second pre-thinning pattern 504. The thickness is reduced to form a first thinned pattern 502A and a second thinned pattern 504A, respectively. The first thinned pattern 502A is located above the drain 260 and above the capacitor electrode 220, and the second thinned pattern 504A is located between the gate 210 and the capacitor electrode 220 and the first conductive pad 410 and the second conductive pad. Between 420. In addition, the film thickness of the first thinned pattern 502A is smaller than the film thickness of the second thinned pattern 504A, and the transparent opening 506A exposes the second insulating layer 410 and the second insulating layer 420 respectively. Layer 270.
然後，請參照圖5C，以圖案化光阻層500為罩幕進行第一蝕刻製程以移除穿透口506A所暴露出來的第二絕緣層270。如此，第二導電接墊420及位於第一導電接墊410上方的第一絕緣層230例如被暴露出來。此一製程步驟例如是以第二導電接墊420作為蝕刻終止層，所以第一導電接墊410上的第一絕緣層230不會因為第一蝕刻製程的過度蝕刻而被移除。也就是說，第一蝕刻製程的蝕刻深度可以較正確地被控制。Then, referring to FIG. 5C, a first etching process is performed by patterning the photoresist layer 500 as a mask to remove the second insulating layer 270 exposed by the transparent opening 506A. As such, the second conductive pad 420 and the first insulating layer 230 above the first conductive pad 410 are exposed, for example. This process step is, for example, using the second conductive pad 420 as an etch stop layer, so that the first insulating layer 230 on the first conductive pad 410 is not removed due to excessive etching of the first etching process. That is to say, the etching depth of the first etching process can be controlled more correctly.
接下來，請同時參照圖5C與圖5D，再次進行一灰化製程將第一薄化圖案502A完全移除以暴露出汲極260上方與電容電極220上方的第二絕緣層270，並同時使第二薄化圖案504A的膜厚減薄。Next, referring to FIG. 5C and FIG. 5D simultaneously, an ashing process is performed again to completely remove the first thinned pattern 502A to expose the second insulating layer 270 above the drain 260 and above the capacitor electrode 220, and at the same time The film thickness of the second thinned pattern 504A is reduced.
隨後，請參照圖5E，以圖案化光阻層500為罩幕進行一第二蝕刻製程移除第一導電接墊410上方的第一絕緣層230以暴露出第一導電接墊410。同時，在第二蝕刻製程中移除汲極260上方及電容電極220上方的第二絕緣層270以形成一接觸窗272以及一開口274。Subsequently, referring to FIG. 5E , the first photoresist layer 230 above the first conductive pad 410 is removed by using the patterned photoresist layer 500 as a mask to perform a second etching process to expose the first conductive pad 410 . At the same time, the second insulating layer 270 above the drain 260 and above the capacitor electrode 220 is removed in the second etching process to form a contact window 272 and an opening 274.
為了使電容電極220上方的絕緣層減薄以提高其所提供的電容效應，本實施例在第二蝕刻製程中移除了位於電容電極220上方的第二絕緣層270。另外，第二蝕刻製程在本實施例中是以第一導電接墊410作為蝕刻終止層。所以，第二蝕刻製程的蝕刻深度恰可移除一層絕緣層。也因此，電容電極220上的第一絕緣層230不會因第二蝕刻製程的過度蝕刻而被移除。換言之，第二蝕刻製程的蝕刻深度受到良好的控制而有助於提升本實施例的製程良率。In order to reduce the insulating layer above the capacitor electrode 220 to improve the capacitance effect provided by the capacitor electrode 220, the second insulating layer 270 located above the capacitor electrode 220 is removed in the second etching process. In addition, the second etching process is the first conductive pad 410 as an etch stop layer in this embodiment. Therefore, the etching depth of the second etching process can remove an insulating layer. Therefore, the first insulating layer 230 on the capacitor electrode 220 is not removed by excessive etching of the second etching process. In other words, the etching depth of the second etching process is well controlled to help improve the process yield of the present embodiment.
接著，請參照圖5F，再次進行一灰化製程，將圖5E中所示的第二薄化圖案504A完全移除以暴露出位於閘極210與電容電極220之間及第一導電接墊410與第二導電接墊420之間的第二絕緣層270。此時，基板400上仍有部分第二絕緣層270被圖案化光阻層500所覆蓋。Next, referring to FIG. 5F, an ashing process is performed again, and the second thinned pattern 504A shown in FIG. 5E is completely removed to expose the gate 210 and the capacitor electrode 220 and the first conductive pad 410. A second insulating layer 270 is disposed between the second conductive pads 420. At this time, a part of the second insulating layer 270 is still covered by the patterned photoresist layer 500 on the substrate 400.
然後，請參照圖5G，於圖案化光阻層500及第二絕 緣層270上全面地形成一電極材料層510。Then, please refer to FIG. 5G, in the patterned photoresist layer 500 and the second An electrode material layer 510 is entirely formed on the edge layer 270.
隨之，請同時參照圖5G與圖5H，移除圖案化光阻層500以形成主動元件陣列基板50。在移除圖案化光阻層500同時，覆蓋於圖案化光阻層500上的電極材料層510也會一併移除以形成圖案化電極層520。如此一來，第二絕緣層270上即形成有畫素電極522及連接電極524。換言之，本實施例是以剝除製程(lift-off process)來形成圖案化電極層520。Accordingly, referring to FIG. 5G and FIG. 5H simultaneously, the patterned photoresist layer 500 is removed to form the active device array substrate 50. While the patterned photoresist layer 500 is removed, the electrode material layer 510 overlying the patterned photoresist layer 500 is also removed together to form the patterned electrode layer 520. In this way, the pixel electrode 522 and the connection electrode 524 are formed on the second insulating layer 270. In other words, the present embodiment forms the patterned electrode layer 520 in a lift-off process.
值得一提的是，本實施例在移除圖案化光阻層500的同時就可以將電極材料層(未繪示)圖案化，所以有助於簡化製程步驟。另外，一般的製程中，圖案化電極材料層(未繪示)的方式都必須採用微影蝕刻製程，也就是須再使用一道光罩而使製程成本增加。本實施例不須再使用光罩就可以形成圖案化電極層520，因而更有助於節省製程成本。It is worth mentioning that this embodiment can pattern the electrode material layer (not shown) while removing the patterned photoresist layer 500, so it helps to simplify the process steps. In addition, in a general process, a pattern of patterned electrode material layers (not shown) must be subjected to a photolithography process, that is, a mask is used to increase the process cost. In this embodiment, the patterned electrode layer 520 can be formed without using a photomask, thereby contributing to saving process cost.
此外，在本實施例中，電容電極220、畫素電極522與位於此兩導電層間的第一絕緣層230構成一儲存電容530。兩導電層之間僅有一層絕緣層的設計會使儲存電容530的儲存電容值比習知設計的儲存電容值高。因此，本實施例可以不必增加電容電極220與畫素電極522的重疊面積就可以有效提高儲存電容值而提升主動元件陣列基板50的元件特性。In addition, in the embodiment, the capacitor electrode 220 and the pixel electrode 522 and the first insulating layer 230 between the two conductive layers form a storage capacitor 530. The design of only one insulating layer between the two conductive layers causes the storage capacitor 530 to have a higher storage capacitor value than the conventionally designed storage capacitor. Therefore, in this embodiment, the storage capacitor value can be effectively increased and the component characteristics of the active device array substrate 50 can be improved without increasing the overlapping area of the capacitor electrode 220 and the pixel electrode 522.
綜上所述，本發明利用適當的設計(蝕刻終止層)與製程條件的控制來決定蝕刻製程的蝕刻深度，而使儲存電容中的絕緣層減薄。因此，本發明之主動元件陣列基板中的儲存電容具有較大的電容值而有助於提升主動元件陣列基板的元件特性。另外，主動元件陣列基板的製造方法可具有良好的製程良率與較低的製作成本。再者，本發明之主動元件陣列基板也具有較大的顯示開口率。In summary, the present invention utilizes appropriate design (etch stop layer) and process condition control to determine the etch depth of the etch process, thereby thinning the insulating layer in the storage capacitor. Therefore, the storage capacitor in the active device array substrate of the present invention has a large capacitance value and contributes to improving the element characteristics of the active device array substrate. In addition, the manufacturing method of the active device array substrate can have good process yield and low manufacturing cost. Furthermore, the active device array substrate of the present invention also has a large display aperture ratio.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10、20、40、50．．．主動元件陣列基板10, 20, 40, 50. . . Active device array substrate
30、220．．．電容電極30, 220. . . Capacitor electrode
32．．．閘絕緣層32. . . Brake insulation
40、280、442、522．．．畫素電極40, 280, 442, 522. . . Pixel electrode
60．．．保護層60. . . The protective layer
70、290、530．．．儲存電容70, 290, 530. . . Storage capacitor
200．．．基板200. . . Substrate
210．．．閘極210. . . Gate
230．．．第一絕緣層230. . . First insulating layer
240．．．通道層240. . . Channel layer
242．．．歐姆接觸層242. . . Ohmic contact layer
250．．．源極250. . . Source
260．．．汲極260. . . Bungee
270．．．第二絕緣層270. . . Second insulating layer
272．．．接觸窗272. . . Contact window
274．．．開口274. . . Opening
300、430、500．．．圖案化光阻層300, 430, 500. . . Patterned photoresist layer
432、434、502、504、506．．．預薄化圖案432, 434, 502, 504, 506. . . Pre-thinned pattern
432A、502A、504A．．．薄化圖案432A, 502A, 504A. . . Thinned pattern
434A、506A．．．穿透口434A, 506A. . . Penetration port
TFT．．．電晶體TFT. . . Transistor
圖1A為習知的主動元件陣列基板的畫素結構的上視圖。1A is a top view of a pixel structure of a conventional active device array substrate.
圖1B為沿圖1A的I-I’線的剖面示意圖。Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A.
圖2為本發明較佳實施例的一種主動元件陣列基板的局部剖面示意圖。2 is a partial cross-sectional view of an active device array substrate in accordance with a preferred embodiment of the present invention.
圖3A至圖3D為本發明第一實施例的主動元件陣列基板的製造方法的示意圖。3A to 3D are schematic views showing a method of manufacturing an active device array substrate according to a first embodiment of the present invention.
圖4A至圖4F為本發明第二實施例的主動元件陣列基板的製造方法的示意圖。4A to 4F are schematic views showing a method of manufacturing an active device array substrate according to a second embodiment of the present invention.
圖5A至圖5H為本發明第三實施例的主動元件陣列基板的製造方法的示意圖。5A to 5H are schematic views showing a method of manufacturing an active device array substrate according to a third embodiment of the present invention.
20．．．主動元件陣列基板20. . . Active device array substrate
200．．．基板200. . . Substrate
210．．．閘極210. . . Gate
220．．．電容電極220. . . Capacitor electrode
230．．．第一絕緣層230. . . First insulating layer
240．．．通道層240. . . Channel layer
250．．．源極250. . . Source
260．．．汲極260. . . Bungee
270．．．第二絕緣層270. . . Second insulating layer
272．．．接觸窗272. . . Contact window
274．．．開口274. . . Opening
280．．．畫素電極280. . . Pixel electrode
290．．．儲存電容290. . . Storage capacitor
TFT．．．電晶體TFT. . . Transistor
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98114881A TWI387826B (en) | 2009-05-05 | 2009-05-05 | Method of manufacturing active device array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98114881A TWI387826B (en) | 2009-05-05 | 2009-05-05 | Method of manufacturing active device array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201040639A TW201040639A (en) | 2010-11-16 |
| TWI387826B true TWI387826B (en) | 2013-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98114881A TWI387826B (en) | 2009-05-05 | 2009-05-05 | Method of manufacturing active device array substrate |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI387826B (en) |
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| TW201040639A (en) | 2010-11-16 |
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