TWI387202B - Output buffer circuit with enhanced slew rate - Google Patents

Output buffer circuit with enhanced slew rate Download PDF

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TWI387202B
TWI387202B TW98100070A TW98100070A TWI387202B TW I387202 B TWI387202 B TW I387202B TW 98100070 A TW98100070 A TW 98100070A TW 98100070 A TW98100070 A TW 98100070A TW I387202 B TWI387202 B TW I387202B
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transistor
slew rate
enhancing
control circuit
enhanced
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TW201027915A (en
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Yi Jan Emry Chen
Pang Jung Liu
Jyun Ping Jiang
Tsung Yu Wu
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Himax Tech Ltd
Univ Nat Taiwan
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Description

具增強迴轉率之輸出緩衝電路Output buffer circuit with enhanced slew rate

本發明係有關一種緩衝放大器，特別是關於顯示面板源極驅動器之低功率、高速輸出緩衝電路。This invention relates to a buffer amplifier, and more particularly to a low power, high speed output buffer circuit for a display panel source driver.

由於平面顯示器(例如液晶顯示器)解析度的逐漸增高，使得上千的輸出緩衝放大器或緩衝電路必須製造於驅動積體電路內。為了在驅動積體電路內可以容納這麼多的緩衝放大器，因此必須減少每一緩衝放大器的面積，且必須降低每一緩衝放大器消耗的功率，特別是穩態(static)消耗功率。再者，鑑於大型顯示面板中每一行(column)具有相當大的時間常數(time constant)，為了提供足夠的驅動能力來驅動此大型面板，因此必須具有較小的穩定(settling)時間或者較大的迴轉率(slew rate)。簡單來說，對於高解析度之大型顯示面板而言，低功率、高速之輸出緩衝電路是不可或缺的。Due to the increasing resolution of flat panel displays (such as liquid crystal displays), thousands of output buffer amplifiers or buffer circuits must be fabricated in the driver integrated circuit. In order to accommodate so many buffer amplifiers in the drive integrated circuit, it is necessary to reduce the area of each buffer amplifier and to reduce the power consumed by each buffer amplifier, especially the static power consumption. Furthermore, since each column in a large display panel has a relatively large time constant, in order to provide sufficient driving capability to drive the large panel, it is necessary to have a small settling time or a large Slew rate. In short, for high-resolution large display panels, low-power, high-speed output buffer circuits are indispensable.

鑑於傳統輸出緩衝電路無法有效提供低消耗功率之高驅動能力，因此亟需提出一種新穎具有增強迴轉率的低功率、高速輸出緩衝電路，以適用於高解析度/大型顯示面板。In view of the fact that the conventional output buffer circuit cannot effectively provide high driving power with low power consumption, it is urgent to propose a novel low power, high speed output buffer circuit with enhanced slew rate for high resolution/large display panels.

鑑於上述，本發明的目的之一在於提出一種具增強迴轉率(slew rate)的緩衝放大器，可有效地對平面顯示器的驅動電路提供高驅動能力。In view of the above, it is an object of the present invention to provide a buffer amplifier having an enhanced slew rate which can effectively provide a high driving capability to a driving circuit of a flat panel display.

根據本發明的一個實施例，第一迴轉率增強電晶體受控於第一控制電路，用以增強汲取電晶體的電流汲取能力，而第二迴轉率增強電晶體則受控於第二控制電路，用以增強來源電晶體的電流提供能力。其中，當處於穩態時，第一控制電路、第二控制電路分別關閉第一迴轉率增強電晶體、第二迴轉率增強電晶體。當處於高至低轉態時，第一控制電路開啟第一迴轉率增強電晶體；而當處於低至高轉態時，第二控制電路開啟第二迴轉率增強電晶體。According to an embodiment of the invention, the first slew rate enhancing transistor is controlled by the first control circuit for enhancing the current draw capability of the drawn transistor, and the second slew rate enhancing transistor is controlled by the second control circuit To enhance the current supply capability of the source transistor. Wherein, when in a steady state, the first control circuit and the second control circuit respectively turn off the first rotation rate enhancement transistor and the second rotation rate enhancement transistor. When in the high to low transition state, the first control circuit turns on the first slew rate enhancement transistor; and when in the low to high transition state, the second control circuit turns on the second slew rate enhancement transistor.

根據本發明的另一個實施例，第一迴轉率增強電晶體受控於第一控制電路，用以增強來源電晶體的電流提供能力，而第二迴轉率增強電晶體則受控於第二控制電路，用以增強汲取電晶體的電流汲取能力。其中，當處於穩態時，第一控制電路、第二控制電路分別關閉第一迴轉率增強電晶體、第二迴轉率增強電晶體。當處於低至高轉態時，第一控制電路開啟第一迴轉率增強電晶體；而當處於高至低轉態時，第二控制電路開啟第二迴轉率增強電晶體。According to another embodiment of the present invention, the first slew rate enhancing transistor is controlled by the first control circuit for enhancing the current supply capability of the source transistor, and the second slew rate enhancing transistor is controlled by the second control. A circuit that enhances the current draw capability of the capture transistor. Wherein, when in a steady state, the first control circuit and the second control circuit respectively turn off the first rotation rate enhancement transistor and the second rotation rate enhancement transistor. When in the low to high transition state, the first control circuit turns on the first slew rate enhancing transistor; and when in the high to low transition state, the second control circuit turns on the second slew rate enhancing transistor.

第一圖顯示本發明實施例之具有增強迴轉率(slew rate)的低功率、高速輸出緩衝電路10。在本實施例中，輸出緩衝電路10可適用(但不限定)於驅動顯示面板(例如液晶顯示器，未顯示於圖式中)，特別是高解析度/大型顯示面板。The first figure shows a low power, high speed output buffer circuit 10 having an enhanced slew rate in accordance with an embodiment of the present invention. In the present embodiment, the output buffer circuit 10 is applicable to, but not limited to, a driving display panel (eg, a liquid crystal display, not shown in the drawings), particularly a high resolution/large display panel.

輸出緩衝電路10包含至少一差動對(differential pair)。在本實施例中，輸出緩衝電路10包含第一差動對M1-M2及第二差動對M11-M12，二差動對係互相併聯的。電晶體M1、M2、M11、M12為p型金氧半電晶體(PMOS)。第一差動對M1-M2(或稱為PMOS輸入級)受PMOS M5、Mb及電流源Ib 的偏壓，並以電流鏡(current mirror)M3-M4作為主動負載(active load)，該M3-M4為n型金氧半電晶體(NMOS)。第二差動對M11-M12受PMOS M10、Mb及電流源Ib 的偏壓，並以電流鏡(NMOS)M13-M14作為主動負載。The output buffer circuit 10 includes at least one differential pair. In the present embodiment, the output buffer circuit 10 includes a first differential pair M1-M2 and a second differential pair M11-M12, and the two differential pairs are connected in parallel with each other. The transistors M1, M2, M11, and M12 are p-type gold oxide semi-transistors (PMOS). The first differential pair M1-M2 (or PMOS input stage) is biased by the PMOS M5, Mb and the current source I b , and the current mirror M3-M4 is used as an active load. M3-M4 is an n-type gold oxide semi-transistor (NMOS). The second differential pair M11-M12 is biased by the PMOS M10, Mb and the current source Ib , and the current mirror (NMOS) M13-M14 is used as the active load.

互為串聯的來源(source)電晶體(PMOS)M6及汲取(sink)電晶體(PMOS)M7共同形成輸出緩衝電路10的輸出級。輸出級M6-M7的輸出則用以驅動一負載100，其通常跟著顯示面板的大小增減。在本實施例中，第一迴轉率增強電晶體(PMOS)M8係用以增強汲取(sink)電晶體M7的電流汲取能力。第一迴轉率增強電晶體M8受控於第一控制電路，其由PMOS M15、NMOS M16、M17所組成。在本實施例中，第二迴轉率增強電晶體(PMOS)M9係用以增強來源(source)電晶體M6的電流提供能力。第二迴轉率增強電晶體M9受控於第二控制電路，其由PMOS M18、NMOS M19所組成。A source transistor (PMOS) M6 and a sink transistor (PMOS) M7, which are mutually connected in series, together form an output stage of the output buffer circuit 10. The output of the output stage M6-M7 is used to drive a load 100, which typically follows the size of the display panel. In the present embodiment, the first gyroscopic rate enhancing transistor (PMOS) M8 is used to enhance the current extraction capability of the sink transistor M7. The first slew rate enhancing transistor M8 is controlled by a first control circuit composed of PMOS M15, NMOS M16, M17. In the present embodiment, a second rotation rate enhancement transistor (PMOS) M9 is used to enhance the current supply capability of the source transistor M6. The second slew rate enhancement transistor M9 is controlled by a second control circuit consisting of a PMOS M18, an NMOS M19.

於電路的操作中，第一迴轉率增強電晶體M8於穩態(static state)時係關閉的，因此沒有消耗功率。此處所稱穩態係指輸入節點in+的輸入信號保持於高或低位準(而另一輸入節點in-則連接至輸出節點out)。類似的情形，第二迴轉率增強電晶體M9於穩態時也是關閉的。In operation of the circuit, the first slew rate enhancing transistor M8 is turned off in a static state and therefore consumes no power. The term "steady state" as used herein means that the input signal of the input node in+ remains at a high or low level (while the other input node in- is connected to the output node out). In a similar situation, the second slew rate enhancing transistor M9 is also off at steady state.

在本實施例中，當處於高至低(high-to-low)轉態時，第一控制電路M15-M17會打開電晶體M8，使得電晶體M8的汲極電位拉高。電晶體M8的汲極電性連接並控制汲取(sink)電晶體M7的閘極，使得汲取(sink)電晶體M7的閘至源極(gate-to-source)電壓被拉高，因而自負載100汲取電流(或放電)。藉此，處於高至低(high-to-low)轉態時的開啟電晶體M8大大地增快反應時間(或迴轉率)，並因而增強了電流汲取能力。In the present embodiment, when in a high-to-low transition state, the first control circuit M15-M17 turns on the transistor M8, causing the drain potential of the transistor M8 to be pulled high. The gate of the transistor M8 is electrically connected and controls the gate of the sink transistor M7 so that the gate-to-source voltage of the sink transistor M7 is pulled high, and thus the self-load 100 draw current (or discharge). Thereby, the turn-on transistor M8 in a high-to-low transition greatly increases the reaction time (or slew rate) and thus enhances the current draw capability.

當處於低至高(low-to-high)轉態時，第二控制電路M18-M19會打開電晶體M9。由於電晶體M9的汲極電性連接至輸出級M6-M7的輸出節點out，因此電晶體M9會提供電流(或充電)給負載100。換句話說，電晶體M9提供輔助電流給負載100。藉此，處於低至高(low-to-high)轉態時的開啟電晶體M9大大地增快反應時間(或迴轉率)，並因而增強了電流提供能力。When in a low-to-high transition state, the second control circuit M18-M19 turns on the transistor M9. Since the drain of transistor M9 is electrically coupled to the output node out of output stages M6-M7, transistor M9 provides current (or charging) to load 100. In other words, transistor M9 provides an auxiliary current to load 100. Thereby, the turn-on transistor M9 in the low-to-high transition state greatly increases the reaction time (or slew rate) and thus enhances the current supply capability.

電晶體M15的寬度可適當地設計使得電晶體M15的汲至源極(drain-to-source)電壓VDS 於穩態時可以保持足夠小，因而第一控制電路M15-M17於穩態時，其輸出電壓足夠大而足以關閉第一迴轉率增強電晶體M8。當處於高至低(high-to-low)轉態時，通過第一控制電路M15-M17的電流會增強，因而增大電晶體M15的汲至源極(drain-to-source)電壓VDS 。藉此，第一控制電路M15-M17的輸出變低，用以開啟第一迴轉率增強電晶體M8。The width of the transistor M15 can be appropriately designed such that the drain-to-source voltage V DS of the transistor M15 can be kept sufficiently small at steady state, so that the first control circuit M15-M17 is at a steady state, Its output voltage is large enough to turn off the first slew rate enhancing transistor M8. When in a high-to-low transition state, the current through the first control circuit M15-M17 is enhanced, thereby increasing the drain-to-source voltage V DS of the transistor M15. . Thereby, the output of the first control circuit M15-M17 becomes low to turn on the first slew rate enhancing transistor M8.

類似的情形，電晶體M18的寬度可適當地設計使得電晶體M18的汲至源極(drain-to-source)電壓VDS 於穩態時可以保持足夠小，因而第二控制電路M18-M19於穩態時，其輸出電壓足夠大而足以關閉第二迴轉率增強電晶體M9。當處於低至高(low-to-high)轉態時，通過第二控制電路M18-M19的電流會增強，因而增大電晶體M18的汲至源極(drain-to-source)電壓VDS 。藉此，第二控制電路M18-M19的輸出變低，用以開啟第二迴轉率增強電晶體M9。In a similar situation, the width of the transistor M18 can be appropriately designed so that the drain-to-source voltage V DS of the transistor M18 can be kept small enough in the steady state, and thus the second control circuit M18-M19 At steady state, its output voltage is large enough to turn off the second slew rate enhancing transistor M9. When in a low-to-high transition state, the current through the second control circuit M18-M19 is enhanced, thereby increasing the drain-to-source voltage VDS of the transistor M18. Thereby, the output of the second control circuit M18-M19 becomes low to turn on the second slew rate enhancing transistor M9.

第二圖顯示本發明另一實施例之具有增強迴轉率的低功率、高速輸出緩衝電路20。在本實施例中，輸出緩衝電路20的電路架構類似於前一實施例的輸出緩衝電路10。The second figure shows a low power, high speed output buffer circuit 20 having an enhanced slew rate in accordance with another embodiment of the present invention. In the present embodiment, the circuit architecture of the output buffer circuit 20 is similar to that of the output buffer circuit 10 of the previous embodiment.

輸出緩衝電路20包含第一差動對(NMOS)M1-M2(或稱為NMOS輸入級)，其受NMOS M5、Mb及電流源Ib 的偏壓，並以電流鏡(current mirror)(PMOS)M3-M4作為主動負載(active load)。輸出緩衝電路20還包含第二差動對(NMOS)M11-M12，其與第一差動對M1-M2互相併聯。第二差動對M11-M12受NMOS M10、Mb及電流源Ib 的偏壓，並以電流鏡(PMOS)M13-M14作為主動負載。互為串聯的來源(source)電晶體(PMOS)M6及汲取(sink)電晶體(PMOS)M7共同形成輸出緩衝電路20的輸出級。輸出級M6-M7的輸出則用以驅動一負載200。在本實施例中，第一迴轉率增強電晶體(NMOS)M8係用以增強來源(source)電晶體M6的電流提供能力。第一迴轉率增強電晶體M8受控於第一控制電路，其由PMOS M15、PMOS M16、NMOS 17所組成。在本實施例中，第二迴轉率增強電晶體(NMOS)M9係用以增強汲取(sink)電晶體M7的電流汲取能力。第二迴轉率增強電晶體M9受控於第二控制電路，其由PMOS M18、NMOS M19所組成。The output buffer circuit 20 includes a first differential pair (NMOS) M1-M2 (or NMOS input stage) biased by the NMOS M5, Mb and the current source I b and is a current mirror (PMOS) M3-M4 acts as an active load. The output buffer circuit 20 also includes a second differential pair (NMOS) M11-M12 that is in parallel with the first differential pair M1-M2. The second differential pair M11-M12 is biased by the NMOS M10, Mb and the current source Ib , and the current mirror (PMOS) M13-M14 is used as the active load. A source transistor (PMOS) M6 and a sink transistor (PMOS) M7, which are mutually connected in series, together form an output stage of the output buffer circuit 20. The output of the output stage M6-M7 is used to drive a load 200. In the present embodiment, the first gyroscopic rate enhancing transistor (NMOS) M8 is used to enhance the current supply capability of the source transistor M6. The first slew rate enhancing transistor M8 is controlled by a first control circuit composed of a PMOS M15, a PMOS M16, and an NMOS 17. In the present embodiment, the second rate-of-change enhanced transistor (NMOS) M9 is used to enhance the current extraction capability of the sink transistor M7. The second slew rate enhancement transistor M9 is controlled by a second control circuit consisting of a PMOS M18, an NMOS M19.

於電路的操作中，第一迴轉率增強電晶體M8和第二迴轉率增強電晶體M9於穩態(static state)時係關閉的。在本實施例中，當處於低至高(low-to-high)轉態時，第一控制電路M15-M17會打開電晶體M8，使得電晶體M8的汲極電位拉低。電晶體M8的汲極電性連接並控制來源(source)電晶體M6的閘極，使得來源(source)電晶體M6的源至閘極(source-to-gate)電壓被拉高，因而提供電流(或充電)給負載200。藉此，處於低至高(low-to-high)轉態時的開啟電晶體M8大大地增快反應時間(或迴轉率)，並因而增強了電流提供能力。In operation of the circuit, the first slew rate enhancing transistor M8 and the second slew rate enhancing transistor M9 are turned off in a static state. In the present embodiment, when in a low-to-high transition state, the first control circuit M15-M17 turns on the transistor M8, causing the drain potential of the transistor M8 to be pulled low. The gate of the transistor M8 is electrically connected and controls the gate of the source transistor M6 such that the source-to-gate voltage of the source transistor M6 is pulled high, thereby providing current (or charging) to the load 200. Thereby, the turn-on transistor M8 in the low-to-high transition state greatly increases the reaction time (or slew rate) and thus enhances the current supply capability.

當處於高至低(high-to-low)轉態時，第二控制電路M18-M19會打開電晶體M9。由於電晶體M9的汲極電性連接至輸出級M6-M7的輸出節點out，因此電晶體M9會自負載200汲取電流。換句話說，電晶體M9自負載200輔助汲取電流。藉此，處於高至低(high-to-low)轉態時的開啟電晶體M9大大地增快反應時間(或迴轉率)，並因而增強了電流汲取能力。When in a high-to-low transition state, the second control circuit M18-M19 turns on the transistor M9. Since the drain of the transistor M9 is electrically connected to the output node out of the output stage M6-M7, the transistor M9 draws current from the load 200. In other words, transistor M9 assists in drawing current from load 200. Thereby, the turn-on transistor M9 in a high-to-low transition greatly increases the reaction time (or slew rate) and thus enhances the current draw capability.

電晶體M17的寬度可適當地設計使得電晶體M17的汲至源極(drain-to-source)電壓VDS 於穩態時可以保持足夠小，因而第一控制電路M15-M17於穩態時，其輸出電壓足夠小而足以關閉第一迴轉率增強電晶體M8。當處於低至高(low-to-high)轉態時，通過第一控制電路M15-M17的電流會增強，因而增大電晶體M17的汲至源極(drain-to-source)電壓VDS 。藉此，第一控制電路M15-M17的輸出變高，用以開啟第一迴轉率增強電晶體M8。The width of the transistor M17 can be appropriately designed such that the drain-to-source voltage V DS of the transistor M17 can be kept sufficiently small at a steady state, so that the first control circuit M15-M17 is at a steady state, The output voltage is sufficiently small to turn off the first slew rate enhancing transistor M8. When in a low-to-high transition state, the current through the first control circuit M15-M17 is enhanced, thereby increasing the drain-to-source voltage V DS of the transistor M17. Thereby, the output of the first control circuit M15-M17 becomes high to turn on the first slew rate enhancing transistor M8.

類似的情形，電晶體M19的寬度可適當地設計使得電晶體M19的汲至源極(drain-to-source)電壓VDS 於穩態時可以保持足夠小，因而第二控制電路M18-M19於穩態時，其輸出電壓足夠小而足以關閉第二迴轉率增強電晶體M9。當處於高至低(high-to-low)轉態時，通過第二控制電路M18-M19的電流會增強，因而增大電晶體M19的汲至源極(drain-to-source)電壓VDS 。藉此，第二控制電路M18-M19的輸出變高，用以開啟第二迴轉率增強電晶體M9。In a similar situation, the width of the transistor M19 can be appropriately designed so that the drain-to-source voltage V DS of the transistor M19 can be kept small enough in the steady state, and thus the second control circuit M18-M19 At steady state, its output voltage is small enough to turn off the second slew rate enhancing transistor M9. When in a high-to-low transition state, the current through the second control circuit M18-M19 is increased, thereby increasing the drain-to-source voltage V DS of the transistor M19. . Thereby, the output of the second control circuit M18-M19 becomes high to turn on the second slew rate enhancing transistor M9.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10、20．．．輸出緩衝電路10, 20. . . Output buffer circuit

100、200．．．負載100, 200. . . load

M1-M2．．．第一差動對M1-M2. . . First differential pair

M3-M4．．．電流鏡M3-M4. . . Current mirror

M6-M7．．．輸出級M6-M7. . . Output stage

M5、M10、Mb．．．偏壓電晶體M5, M10, Mb. . . Bias transistor

M8．．．第一迴轉率增強電晶體M8. . . First slew rate enhanced transistor

M9．．．第二迴轉率增強電晶體M9. . . Second slew rate enhanced transistor

M11-M12．．．第二差動對M11-M12. . . Second differential pair

M13-M14．．．電流鏡M13-M14. . . Current mirror

M15-M17．．．第一控制電路M15-M17. . . First control circuit

M18-M19．．．第一控制電路M18-M19. . . First control circuit

Ib ．．．電流源I b . . . Battery

in+．．．輸入節點In+. . . Input node

in-．．．輸入節點In-. . . Input node

out．．．輸出節點Out. . . Output node

第一圖顯示本發明實施例之具有增強迴轉率(slew rate)的低功率、高速輸出緩衝電路。The first figure shows a low power, high speed output buffer circuit with enhanced slew rate in accordance with an embodiment of the present invention.

第二圖顯示本發明另一實施例之具有增強迴轉率的低功率、高速輸出緩衝電路。The second figure shows a low power, high speed output buffer circuit with enhanced slew rate in accordance with another embodiment of the present invention.

10．．．輸出緩衝電路10. . . Output buffer circuit

100．．．負載100. . . load

M1-M2．．．第一差動對M1-M2. . . First differential pair

M3-M4．．．電流鏡M3-M4. . . Current mirror

M6-M7．．．輸出級M6-M7. . . Output stage

M5、M10、Mb．．．偏壓電晶體M5, M10, Mb. . . Bias transistor

M8．．．第一迴轉率增強電晶體M8. . . First slew rate enhanced transistor

M9．．．第二迴轉率增強電晶體M9. . . Second slew rate enhanced transistor

M11-M12．．．第二差動對M11-M12. . . Second differential pair

M13-M14．．．電流鏡M13-M14. . . Current mirror

M15-M17．．．第一控制電路M15-M17. . . First control circuit

M18-M19．．．第一控制電路M18-M19. . . First control circuit

Ib ．．．電流源I b . . . Battery

in+．．．輸入節點In+. . . Input node

in-．．．輸入節點In-. . . Input node

out．．．輸出節點Out. . . Output node

Claims (18)

一種具增強迴轉率(slew rate)之輸出緩衝電路，包含：一輸入級，包含至少一差動對，用以接收一輸入信號；一輸出級，包含一來源(source)電晶體及一汲取(sink)電晶體，用以驅動一負載；一第一迴轉率增強電晶體，用以增強該來源電晶體及汲取電晶體其中一個之迴轉率；一第二迴轉率增強電晶體，用以增強該來源電晶體及汲取電晶體其中另一個之迴轉率；一第一控制電路，用以控制該第一迴轉率增強電晶體；及一第二控制電路，用以控制該第二迴轉率增強電晶體；其中，當處於穩態時，該第一控制電路、第二控制電路分別關閉該第一迴轉率增強電晶體、第二迴轉率增強電晶體；當處於轉態時，則分別開啟該第一迴轉率增強電晶體、第二迴轉率增強電晶體。 An output buffer circuit with an enhanced slew rate, comprising: an input stage comprising at least one differential pair for receiving an input signal; and an output stage comprising a source transistor and a capture ( a sinker for driving a load; a first slew rate enhancement transistor for enhancing a slew rate of one of the source transistor and the capture transistor; and a second slew rate enhancement transistor for enhancing the a rotation rate of the other of the source transistor and the extraction transistor; a first control circuit for controlling the first rate-of-change enhancement transistor; and a second control circuit for controlling the second rate-of-change enhancement transistor Wherein, when in a steady state, the first control circuit and the second control circuit respectively turn off the first rotation rate enhancement transistor and the second rotation rate enhancement transistor; when in the transition state, respectively turn on the first The slew rate enhanced transistor and the second slew rate enhanced transistor. 如申請專利範圍第1項所述具增強迴轉率之輸出緩衝電路，其中上述之負載為顯示面板。 An output buffer circuit with enhanced slew rate as described in claim 1 wherein the load is a display panel. 一種具增強迴轉率(slew rate)之輸出緩衝電路，包含：一輸入級，包含至少一差動對，用以接收一輸入信號；一輸出級，包含一來源(source)電晶體及一汲取(sink)電晶體，用以驅動一負載；一第一迴轉率增強電晶體，用以增強該汲取電晶體的電流汲取能力；一第二迴轉率增強電晶體，用以增強該來源電晶體的電流提供能力；一第一控制電路，用以控制該第一迴轉率增強電晶體；及一第二控制電路，用以控制該第二迴轉率增強電晶體；其中，當處於穩態時，該第一控制電路、第二控制電路分別關閉該第一迴轉率增強電晶體、第二迴轉率增強電晶體；當處於高至低轉態時，該第一控制電路開啟該第一迴轉率增強電晶體；當處於低至高轉態時，該第二控制電路開啟該第二迴轉率增強電晶體。 An output buffer circuit with an enhanced slew rate, comprising: an input stage comprising at least one differential pair for receiving an input signal; and an output stage comprising a source transistor and a capture ( a sink transistor for driving a load; a first slew rate enhancement transistor for enhancing current extraction capability of the capture transistor; and a second rotation rate enhancement transistor for enhancing current of the source transistor Providing a first control circuit for controlling the first slew rate enhancing transistor; and a second control circuit for controlling the second slew rate enhancing transistor; wherein, when in a steady state, the first a control circuit and a second control circuit respectively turn off the first slew rate enhancing transistor and the second slew rate enhancing transistor; and when in a high to low transition state, the first control circuit turns on the first slew rate enhancing transistor The second control circuit turns on the second slew rate enhancing transistor when in a low to high transition state. 如申請專利範圍第3項所述具增強迴轉率之輸出緩衝電路，其中上述之負載為顯示面板。 An output buffer circuit with enhanced slew rate as described in claim 3, wherein the load is a display panel. 如申請專利範圍第3項所述具增強迴轉率之輸出緩衝電路，其中上述之輸入級包含互相併聯之二差動對。 An output buffer circuit with enhanced slew rate as described in claim 3, wherein the input stage comprises two differential pairs connected in parallel with each other. 如申請專利範圍第3項所述具增強迴轉率之輸出緩衝電路，其中上述之輸入級包含一PMOS輸入級。 An output buffer circuit with enhanced slew rate as described in claim 3, wherein the input stage comprises a PMOS input stage. 如申請專利範圍第3項所述具增強迴轉率之輸出緩衝電路，其中上述之第一迴轉率增強電晶體為PMOS電晶體，其汲極連接並控制該汲取電晶體的閘極；當處於高至低轉態時，該開啟的第一迴轉率增強電晶體開啟該汲取電晶體，因而自該負載汲取電流。 An output buffer circuit with enhanced slew rate as described in claim 3, wherein the first slew rate enhancement transistor is a PMOS transistor, the drain of which is connected to and controls the gate of the capture transistor; At the low transition state, the turned-on first slew rate enhancing transistor turns on the capture transistor, thereby drawing current from the load. 如申請專利範圍第7項所述具增強迴轉率之輸出緩衝電路，其中上述之第一控制電路包含一PMOS組成電晶體，其寬度被設計使得該PMOS組成電晶體於穩態時，其汲極電位足夠高而關閉該第一迴轉率增強電晶體；當處於高至低轉態時，該PMOS組成電晶體的汲極電位足夠低而開啟該第一迴轉率增強電晶體。 An output buffer circuit with enhanced slew rate as described in claim 7 wherein the first control circuit comprises a PMOS-constituting transistor whose width is designed such that the PMOS constitutes a transistor in a steady state and has a drain The potential is sufficiently high to turn off the first slew rate enhancing transistor; when in the high to low transition state, the drain potential of the PMOS composing transistor is sufficiently low to turn on the first slew rate enhancing transistor. 如申請專利範圍第3項所述具增強迴轉率之輸出緩衝電路，其中上述之第二迴轉率增強電晶體為PMOS電晶體， 其汲極連接並控制該輸出級的輸出節點；當處於低至高轉態時，該開啟的第二迴轉率增強電晶體提供電流至該負載。 An output buffer circuit with enhanced slew rate as described in claim 3, wherein the second slew rate enhancement transistor is a PMOS transistor. Its drain connects and controls the output node of the output stage; when in the low to high transition state, the turned-on second slew rate enhancing transistor provides current to the load. 如申請專利範圍第9項所述具增強迴轉率之輸出緩衝電路，其中上述之第二控制電路包含一PMOS組成電晶體，其寬度被設計使得該PMOS組成電晶體於穩態時，其汲極電位足夠高而關閉該第二迴轉率增強電晶體；當處於低至高轉態時，該PMOS組成電晶體的汲極電位足夠低而開啟該第二迴轉率增強電晶體。 An output buffer circuit with enhanced slew rate as described in claim 9 wherein the second control circuit comprises a PMOS-constituting transistor whose width is designed such that the PMOS constitutes a transistor in a steady state, and has a drain The potential is sufficiently high to turn off the second slew rate enhancing transistor; when in the low to high transition state, the drain potential of the PMOS composing transistor is sufficiently low to turn on the second slew rate enhancing transistor. 一種具增強迴轉率(slew rate)之輸出緩衝電路，包含：一輸入級，包含至少一差動對，用以接收一輸入信號；一輸出級，包含一來源(source)電晶體及一汲取(sink)電晶體，用以驅動一負載；一第一迴轉率增強電晶體，用以增強該來源電晶體的電流提供能力；一第二迴轉率增強電晶體，用以增強該汲取電晶體的電流汲取能力；一第一控制電路，用以控制該第一迴轉率增強電晶體；及一第二控制電路，用以控制該第二迴轉率增強電晶體； 其中，當處於穩態時，該第一控制電路、第二控制電路分別關閉該第一迴轉率增強電晶體、第二迴轉率增強電晶體；當處於低至高轉態時，該第一控制電路開啟該第一迴轉率增強電晶體；當處於高至低轉態時，該第二控制電路開啟該第二迴轉率增強電晶體。 An output buffer circuit with an enhanced slew rate, comprising: an input stage comprising at least one differential pair for receiving an input signal; and an output stage comprising a source transistor and a capture ( a sink for driving a load; a first slew rate enhancing transistor for enhancing current supply capability of the source transistor; and a second slew rate enhancing transistor for enhancing current of the drawn transistor a first control circuit for controlling the first slew rate enhancing transistor; and a second control circuit for controlling the second slew rate enhancing transistor; The first control circuit and the second control circuit respectively turn off the first rotation rate enhancement transistor and the second rotation rate enhancement transistor when in a steady state; when in a low to high transition state, the first control circuit The first slew rate enhancing transistor is turned on; when in a high to low transition state, the second control circuit turns on the second slew rate enhancing transistor. 如申請專利範圍第11項所述具增強迴轉率之輸出緩衝電路，其中上述之負載為顯示面板。 An output buffer circuit with enhanced slew rate as described in claim 11 wherein the load is a display panel. 如申請專利範圍第11項所述具增強迴轉率之輸出緩衝電路，其中上述之輸入級包含互相併聯之二差動對。 An output buffer circuit with enhanced slew rate as described in claim 11 wherein the input stage comprises two differential pairs connected in parallel with each other. 如申請專利範圍第11項所述具增強迴轉率之輸出緩衝電路，其中上述之輸入級包含一NMOS輸入級。 An output buffer circuit with enhanced slew rate as described in claim 11 wherein the input stage comprises an NMOS input stage. 如申請專利範圍第11項所述具增強迴轉率之輸出緩衝電路，其中上述之第一迴轉率增強電晶體為NMOS電晶體，其汲極連接並控制該來源電晶體的閘極；當處於低至高轉態時，該開啟的第一迴轉率增強電晶體開啟該來源電晶體，因而提供電流至該負載。 An output buffer circuit with enhanced slew rate as described in claim 11 wherein the first slew rate enhancement transistor is an NMOS transistor, the drain of which is connected to and controls the gate of the source transistor; In the highest transition state, the turned-on first slew rate enhancing transistor turns on the source transistor, thereby providing current to the load. 如申請專利範圍第15項所述具增強迴轉率之輸出緩衝電路，其中上述之第一控制電路包含一NMOS組成電晶體，其寬度被設計使得該NMOS組成電晶體於穩態時，其汲極電位足夠低而關閉該第一迴轉率增強電晶體；當處於低至高轉態時，該NMOS組成電晶體的汲極電位足夠高而開啟該第一迴轉率增強電晶體。 An output buffer circuit with enhanced slew rate as described in claim 15 wherein the first control circuit comprises an NMOS transistor, the width of which is designed such that the NMOS transistor is in a steady state and its drain The potential is sufficiently low to turn off the first slew rate enhancing transistor; when in the low to high transition state, the NMOS potential of the NMOS constituent transistor is sufficiently high to turn on the first slew rate enhancing transistor. 如申請專利範圍第11項所述具增強迴轉率之輸出緩衝電路，其中上述之第二迴轉率增強電晶體為NMOS電晶體，其汲極連接並控制該輸出級的輸出節點；當處於高至低轉態時，該開啟的第二迴轉率增強電晶體自該負載汲取電流。 An output buffer circuit with enhanced slew rate as described in claim 11, wherein the second slew rate enhancement transistor is an NMOS transistor, the drain of which is connected to and controls the output node of the output stage; In the low transition state, the turned-on second slew rate enhancing transistor draws current from the load. 如申請專利範圍第17項所述具增強迴轉率之輸出緩衝電路，其中上述之第二控制電路包含一NMOS組成電晶體，其寬度被設計使得該NMOS組成電晶體於穩態時，其汲極電位足夠低而關閉該第二迴轉率增強電晶體；當處於高至低轉態時，該NMOS組成電晶體的汲極電位足夠高而開啟該第二迴轉率增強電晶體。An output buffer circuit with enhanced slew rate as described in claim 17, wherein the second control circuit comprises an NMOS transistor, the width of which is designed such that the NMOS transistor is in a steady state and its drain The potential is sufficiently low to turn off the second slew rate enhancing transistor; when in the high to low transition state, the NMOS potential of the NMOS constituent transistor is sufficiently high to turn on the second slew rate enhancing transistor.
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