TWI386104B - Protection circuit and method - Google Patents

Protection circuit and method Download PDF

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Publication number
TWI386104B
TWI386104B TW096124767A TW96124767A TWI386104B TW I386104 B TWI386104 B TW I386104B TW 096124767 A TW096124767 A TW 096124767A TW 96124767 A TW96124767 A TW 96124767A TW I386104 B TWI386104 B TW I386104B
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Taiwan
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current
light source
shunt path
source
parallel
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TW096124767A
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Chinese (zh)
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TW200824492A (en
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Steele Colins
Ann Hearne Catherine
Paul Singleton David
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Wolfson Microelectronics Plc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/46—Colour picture communication systems
    • H04N1/48—Picture signal generators
    • H04N1/482—Picture signal generators using the same detector device sequentially for different colour components
    • H04N1/484—Picture signal generators using the same detector device sequentially for different colour components with sequential colour illumination of the original
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/20—Controlling the colour of the light
    • H05B45/22—Controlling the colour of the light using optical feedback
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/395—Linear regulators
    • H05B45/397—Current mirror circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/325—Pulse-width modulation [PWM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Led Devices (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Facsimile Scanning Arrangements (AREA)

Description

保護電路及方法Protection circuit and method

本發明係關於一種保護電路及方法，尤其是，但不限於，一種用於保護光源，例如於供照亮目標物體所用的RGB(紅、藍、綠)LED陣列中點亮之LED，之保護電路及方法，其中來自目標物體之光線係由感測器，例如成像裝置，例如光學成像器，即掃描器，中所用之CIS/CCD成像感測器及類似物所偵測。The present invention relates to a protection circuit and method, particularly, but not limited to, a protection for a light source, such as an LED illuminated in an RGB (red, blue, green) LED array for illuminating a target object. Circuits and methods in which light from a target object is detected by a sensor, such as an imaging device, such as an optical imager, i.e., a CIS/CCD imaging sensor used in a scanner, and the like.

第1圖顯示先前技藝用於具有CIS或CCD影像感測器裝置之影像讀取裝置中之LED驅動電路的基本架構圖。LED陣列L1－L3係連接於開關S1－S3及電阻器R1－R3。LED陣列L1－L3、開關電路S1－S3及電阻器R1－R3與類比前端(AFE)電路分開，該類比前端(AFE)電路係用於處理從感測器裝置，例如光電二極管列陣(Photo Diode Array，(PDA))，所接收到的影像資料。Figure 1 shows a basic architectural diagram of a prior art LED driver circuit for use in an image reading device having a CIS or CCD image sensor device. The LED arrays L1-L3 are connected to the switches S1-S3 and the resistors R1-R3. The LED arrays L1-L3, the switching circuits S1-S3, and the resistors R1-R3 are separated from the analog front end (AFE) circuit for processing the slave sensor device, such as a photodiode array (Photo) Diode Array, (PDA)), the received image data.

於彩色影像掃描器中，LED陣列通常包含紅色(L1)、綠色(L2)及藍色(L3)LED。由個別LED所發射出之每一種顏色的光線照射欲掃描的目標物體，並且由物體所反射的光線則射入感測器裝置上。感測器裝置通常包含一列排成直線之線形影像感測器，感測器陣列之每一元件包含光電轉換元件，例如每一像素的光電二極管及電容器，用以將入射光轉換為電流並於電流電容器上累積為電荷。累積在個別電容器上之個別電荷則轉換為個別電壓，接著從感測器列陣(PDA)輸出。In color image scanners, LED arrays typically include red (L1), green (L2), and blue (L3) LEDs. Light of each color emitted by the individual LEDs illuminates the target object to be scanned, and the light reflected by the object is incident on the sensor device. The sensor device typically includes a line of linear image sensors arranged in a line, each element of the sensor array comprising a photoelectric conversion element, such as a photodiode and a capacitor of each pixel, for converting incident light into current and The current capacitor accumulates as a charge. The individual charges accumulated on the individual capacitors are converted to individual voltages and then output from a sensor array (PDA).

從PDA輸出之電壓透過類比數位轉換器(ADC)轉換為數位信號，俾於產生欲掃描的目標物體的影像之過程中供進一步處理。The voltage output from the PDA is converted to a digital signal by an analog digital converter (ADC) for further processing during the generation of an image of the target object to be scanned.

影像掃描通常係使用線掃描操作進行。就彩色影像而言，每條線由紅色、綠色及藍色光源掃描。亦即，開啟紅色LED L1以於掃描方向讀取一線，藉以獲得該線的紅色成分。接著開啟綠色LED L2以獲得該線的綠色成分，接著開啟藍色LED L3以獲得該線的藍色成分。接著，LED陣列及感測器陣列通常在掃描機構(carriage mechanism)上移動，俾對準目標物體上的下一條線。藉由使用從開關控制器邏輯電路SC接收之個別的開關控制信號CS1－CS3，可透過開啟個別的開關S1－S3而開啟每一LED L1－L3。Image scanning is usually done using a line scan operation. For color images, each line is scanned by red, green, and blue light sources. That is, the red LED L1 is turned on to read a line in the scanning direction to obtain the red component of the line. The green LED L2 is then turned on to obtain the green component of the line, and then the blue LED L3 is turned on to obtain the blue component of the line. The LED array and sensor array are then typically moved over a carriage mechanism that aligns with the next line on the target object. Each of the LEDs L1-L3 can be turned on by turning on the individual switches S1-S3 by using the individual switch control signals CS1-CS3 received from the switch controller logic circuit SC.

當掃描一條線時，從感測器列陣(PDA)接受到與前一線掃描有關的影像資料則被連續地讀出，並且由ADC處理。When a line is scanned, image data received from the sensor array (PDA) related to the previous line scan is continuously read and processed by the ADC.

流經每一LED之電流則受到LED的電流－電壓特徵、串聯電阻器的電阻以及電源供應器PSU(開關的導通電阻通常可忽略)所供應的電壓所決定。The current flowing through each LED is determined by the current-voltage characteristics of the LED, the resistance of the series resistor, and the voltage supplied by the power supply PSU (the on-resistance of the switch is typically negligible).

第2a－2d圖顯示在”固定電流”模式中開關控制信號CS1－CS3以及以電源供應器PSU所引出之供應電流IS。接地電流實質上等於供應電流。Figures 2a-2d show the switch control signals CS1-CS3 and the supply current IS drawn by the power supply PSU in the "fixed current" mode. The ground current is substantially equal to the supply current.

除在照亮影像過程中分別通過固定電流之每一LED外，已知可使用脈寬調製(PWM)控制信號來控制每一LED的照度，使得藉由控制PWM控制信號的工作週期及/或頻率可控制LED的照度或強度。由於電源供應電壓的公差及LEDs的(依溫度而定)I－V特徵，讓通過LED之電流可承受廣泛的變化。In addition to passing each LED of a fixed current during illumination of the image, it is known to use pulse width modulation (PWM) control signals to control the illumination of each LED such that by controlling the duty cycle of the PWM control signal and/or The frequency controls the illumination or intensity of the LED. Due to the tolerance of the power supply voltage and the (temperature dependent) I-V characteristics of the LEDs, the current through the LED can withstand wide variations.

第2e－2h圖顯示開關控制信號CS1－CS3以及以PWM模式從電源供應器引出之供應電流IS。Figures 2e-2h show switch control signals CS1-CS3 and supply current IS drawn from the power supply in PWM mode.

應注意，於固定電流和PWM操作模式中，從PDA 3接收的影像資料的品質與個別掃描操作過程點中亮每一LED的強度有關。此外，LED的亮度越亮，則取樣(即積分)更少，因此需要掃描時間也越少，這代表可更快速地操作。因此，希望在最大額定電流處或接近最大額定電流處操作LEDs而不會損壞LEDs。It should be noted that in the fixed current and PWM modes of operation, the quality of the image data received from the PDA 3 is related to the intensity of each LED in the individual scanning operation process points. In addition, the brighter the brightness of the LED, the less sampling (ie, integration), so less scanning time is required, which means faster operation. Therefore, it is desirable to operate the LEDs at or near the maximum rated current without damaging the LEDs.

根據一已知系統，LED L1－L3之亮度係藉由使預設電流通過LED而受控制，其中預設電流係根據LED的已知特性、電源供應或開關電阻而定。然而，由於電源供應電壓的耐受性及LEDs的(依溫度而定)I－V特徵所造成之上述變化，故依此方式設定預設最大電流無法使LED於其絕對最大強度下點亮，因為必須結合某些程度的安全邊際，以容許此等公差。倘若安全邊際做得太小(即為了得到最大可能電流)，則損壞LED的機率增加，亦即由流經LED之過電流所造成。According to a known system, the brightness of the LEDs L1-L3 is controlled by passing a predetermined current through the LED, wherein the predetermined current is based on the known characteristics of the LED, the power supply or the switching resistance. However, due to the tolerance of the power supply voltage and the above-mentioned changes caused by the (depending on temperature) I-V characteristics of the LEDs, setting the preset maximum current in this manner does not cause the LED to illuminate at its absolute maximum intensity. Because some degree of safety margin must be combined to allow for such tolerances. If the margin of safety is made too small (ie, to get the maximum possible current), the chance of damaging the LED increases, that is, caused by the overcurrent flowing through the LED.

亦已知亦可藉由直接監測通過LED之電流量來點亮LED L1－L3，因此LED可以在接近其最大強度之處運作。這包含監測流經LED之真正電流。依此方式於接近最大強度處操作LED亦可能造成LED受到過電流損壞，尤其當從一LED切換至另一者時。換言之，當從一LED切換至另一者時，倘若啟始電流超過LED的最大額定值，則LED將於電流監測器可偵測及調整電流之前受到損壞。It is also known to illuminate LEDs L1-L3 by directly monitoring the amount of current through the LEDs so that the LEDs can operate close to their maximum intensity. This involves monitoring the true current flowing through the LED. Operating the LED near the maximum intensity in this manner may also cause the LED to be damaged by overcurrent, especially when switching from one LED to the other. In other words, when switching from one LED to the other, if the starting current exceeds the maximum rating of the LED, the LED will be damaged before the current monitor can detect and adjust the current.

因此，本發明之目的為提供一種用於保護光源，例如LED，之保護電路及方法，而不會具有上述缺點。Accordingly, it is an object of the present invention to provide a protection circuit and method for protecting a light source, such as an LED, without the above disadvantages.

本發明之第一態樣係提供一種用於保護光源之保護電路。該保護電路包含：一分流路徑，該分流路徑係選擇性地並聯連接於該光源；一偵測電路設置於該分流路徑中，用以於電源供應器點亮光源之前決定即將流經該光源之電流量；以及一比較器，用於當該偵測電路測到該電流量超過預設門檻值時防止或限制電流流經該光源。A first aspect of the invention provides a protection circuit for protecting a light source. The protection circuit includes: a shunt path selectively connected in parallel to the light source; a detecting circuit is disposed in the shunt path for determining that the power source is to flow through the light source before the power supply illuminates the light source And a comparator for preventing or limiting current flow through the light source when the detecting circuit detects that the current amount exceeds a preset threshold.

因此，依據本發明提供一電流偵測器以監測分流路徑中之電流的流動，當達到預設門檻值時，該電流偵測器係用以禁能或限制流經光源之電流。本發明之此態樣具有使流經光源的電流藉由監測分流路徑中，而不是具有光源的路徑中，之電流而受到控制之優點，因此能不損壞光源的情況下使最大電流受到控制。Accordingly, in accordance with the present invention, a current detector is provided to monitor the flow of current in a shunt path that is used to disable or limit current flow through the source when a predetermined threshold is reached. This aspect of the invention has the advantage that the current flowing through the source is controlled by monitoring the current in the shunt path rather than the path having the source, so that the maximum current can be controlled without damaging the source.

本發明之另一態樣係提供一種防止光源遭受過電流之方法。該方法包含步驟為：選擇性地使一分流路徑並聯連接於該光源，使得電流從該光源轉離且通過該分流路徑；偵測在該分流路徑中流動之電流量；以及決定在該分流路徑中流動之電流是否超過預設門檻值，且如果是，則當分流路徑中斷而未與光源並聯連接時防止或限制光源的電流。Another aspect of the present invention provides a method of preventing a light source from being subjected to an overcurrent. The method includes the steps of: selectively connecting a shunt path in parallel to the light source such that current is diverted from the source and passing through the shunt path; detecting an amount of current flowing in the shunt path; and determining the shunt path Whether the current flowing in the current exceeds a preset threshold value, and if so, prevents or limits the current of the light source when the shunt path is interrupted without being connected in parallel with the light source.

以下實施例中係以保護光源為參考說明，本說明書中所述之LED陣列光源包括三種LEDs，即紅色、綠色及藍色。然而，應理解本發明亦可適用於具有二或更多個LEDs之LED陣列，或任何光源，包含一單一光源。再者，任何參照LED之說明意欲涵蓋任一形式的光源，不僅是可見光，亦包含非可見光，例如紫外光(UV)及紅外光(IR)。因此，於較佳實施例中有關LED或LED陣列之說明意欲更普遍地涵蓋一光源或光源陣列。In the following embodiments, reference is made to the protection of the light source. The LED array light source described in this specification includes three kinds of LEDs, namely red, green and blue. However, it should be understood that the present invention is also applicable to LED arrays having two or more LEDs, or any light source, including a single light source. Furthermore, any reference to an LED is intended to cover any form of light source, not only visible light, but also non-visible light, such as ultraviolet (UV) and infrared (IR) light. Thus, the description of an LED or LED array in the preferred embodiment is intended to more generally encompass a light source or array of light sources.

於參照第12b至12d圖詳細說明保護電路之前，將首先說明如第3至11圖所示之用於驅動LED陣列之多種架構，對應本案申請人的共同申請案台灣第096124764號發明申請案中請求的主題。Before the protection circuit is described in detail with reference to FIGS. 12b to 12d, a plurality of structures for driving the LED array as shown in FIGS. 3 to 11 will be first described, which corresponds to the applicant's co-application No. 096124764. The subject of the request.

第3圖顯示一種用於驅動LED陣列之架構的基本方塊概念圖。LED陣列包含紅色、綠色及藍色LED L1、L2、L3。LED開關電路S1、S2、S3係置於與類比前端電路(AFE)，即用於處理從感測器裝置所接收到的影像資料之類比電路，相同的單石結構(即積體電路)上。為了降低與干擾ADC處理之LED切換暫態有關的問題，於電流路徑中提供電流源IS1，較佳者係介於開關S1、S2、S3與地線之間。根據開關S1、S2、S3的狀態，電流源IS1控制流經LEDs L1、L2、L3的電流。Figure 3 shows a basic block concept diagram of an architecture for driving an LED array. The LED array contains red, green and blue LEDs L1, L2, L3. The LED switch circuits S1, S2, and S3 are placed on the same single-rock structure (ie, integrated circuit) as the analog front-end circuit (AFE), which is an analog circuit for processing image data received from the sensor device. . In order to reduce the problems associated with interfering with the LED switching transients of the ADC processing, a current source IS1 is provided in the current path, preferably between switches S1, S2, S3 and ground. The current source IS1 controls the current flowing through the LEDs L1, L2, L3 according to the state of the switches S1, S2, S3.

電流源IS1之提供使得流經LED(L1－L3)之電流受到控制，而非如同第1圖之架構僅能開啟和關閉。因此，流經LED之電流受到電流源IS1界定，與LED I－V特徵或供應電壓公差無關，故LED電流的準確性與電流源的一樣。可藉由直接調整IS1或藉由IS1的PWM調變和開關信號來調整電流。The supply of current source IS1 allows the current flowing through the LEDs (L1-L3) to be controlled, rather than being turned on and off as in the architecture of Figure 1. Therefore, the current flowing through the LED is defined by the current source IS1, independent of the LED I-V characteristics or supply voltage tolerance, so the accuracy of the LED current is the same as that of the current source. The current can be adjusted by directly adjusting IS1 or by PWM modulation and switching signals of IS1.

電流源IS1之引進亦使得通過LED之電流變化率(di/dt)受到控制，例如藉由降電低電流的啟始變化率。第4圖顯示第3圖實施例操作過程中由電路引出的供應電流IS，其中IS1係於每一電路S1、S2、S3關閉之前以S－形形式下降，並且緊接在下一開關開啟之後以S－形形式提高。可發現電流波形IS具有比第2圖的電流波形IS更平滑的S－形轉態區，藉以降低不想要的暫態信號。接地迴路電流波形是類似的。可藉由已知的技術產生此等S－形波形。The introduction of the current source IS1 also controls the rate of change of current (di/dt) through the LED, for example by the initial rate of change of the low current. Figure 4 is a diagram showing the supply current IS drawn by the circuit during operation of the embodiment of Figure 3, wherein IS1 is lowered in the form of an S-shape before each circuit S1, S2, S3 is turned off, and immediately after the next switch is turned on. The S-form is improved. It can be found that the current waveform IS has a smoother S-shaped transition region than the current waveform IS of FIG. 2, thereby reducing unwanted transient signals. The ground loop current waveform is similar. These S-shaped waveforms can be generated by known techniques.

因此，於第3圖之架構中可發現，LED開關(S1－S3)可整合於與AFE處理電路相同的IC上，於其中提供電流源IS1以降低不想要的暫態信號產生。Thus, in the architecture of Figure 3, it can be seen that the LED switches (S1-S3) can be integrated on the same IC as the AFE processing circuitry, in which the current source IS1 is provided to reduce unwanted transient signal generation.

第5圖顯示用於驅動LED陣列之第二架構的基本方塊圖。Figure 5 shows a basic block diagram of a second architecture for driving an LED array.

依照與第3圖相同的方式，LED陣列包含紅色、綠色及藍色LEDs L1、L2、L3。LED開關S1、S2、S3係置於與用以驅動開關電路之類比處理電路(AFE)相同的單石電路上。電流源IS1被設置於介於開關S1、S2、S3與地線之間之電流路徑中，俾控制流經LEDs L1、L2、L3的電流。In the same manner as in FIG. 3, the LED array includes red, green, and blue LEDs L1, L2, and L3. The LED switches S1, S2, and S3 are placed on the same single-pole circuit as the analog processing circuit (AFE) used to drive the switching circuit. The current source IS1 is placed in a current path between the switches S1, S2, S3 and the ground, and controls the current flowing through the LEDs L1, L2, L3.

此第二架構提供一分流路徑50。分流路徑50包含一開關裝置S4。具有開關裝置S4之分流路徑50係與LED陣列及開關電路並聯配置。由於分流路徑50使得接地電流中之有害的暫態現象得以降低，如以下所述，故可減低與干擾ADC處理之LED切換暫態有關的問題。This second architecture provides a shunt path 50. The shunt path 50 includes a switching device S4. The shunt path 50 having the switching device S4 is arranged in parallel with the LED array and the switching circuit. Since the shunt path 50 reduces the unwanted transient phenomena in the ground current, as described below, the problems associated with interfering with the LED switching transients of the ADC processing can be reduced.

以下說明將描述分流路徑50中之開關裝置S4之操作，俾當從一LED切換至另一者時降低暫態信號。The following description will describe the operation of the switching device S4 in the shunt path 50 to reduce the transient signal when switching from one LED to the other.

分流路徑50係當開關裝置S4被開啟時被致能。於LED開關S1－S3操作之後，接著開啟S4，將說明如下。The split path 50 is enabled when the switching device S4 is turned on. After the operation of the LED switches S1-S3, then S4 is turned on, as will be explained below.

請參照第6圖之流程圖，假設S1被開啟(即S1閉路)，步驟61，則電流I1從正電源VDD經由電流源IS1通過LED L1至地線GND。Referring to the flowchart of FIG. 6, it is assumed that S1 is turned on (ie, S1 is closed), and in step 61, current I1 is passed from the positive power source VDD through the current source IS1 through the LED L1 to the ground line GND.

於，例如，掃描器之操作過程中，一旦L1已完成其工作時(例如用以照亮物體而產生一線影像的紅色成分)，則必須藉由關閉S1(即S1開路)來關閉L1，並且必須開啟(閉路)S2，使得L2通過其電流I2(因而使得L2得以照亮物體而產生一線影像的綠色成分)。For example, during the operation of the scanner, once L1 has completed its work (for example, to illuminate an object to produce a red component of a line image), L1 must be turned off by turning off S1 (ie, S1 is open), and S2 must be turned on (closed) so that L2 passes its current I2 (thus enabling L2 to illuminate the object to produce a green component of the line image).

根據此第二架構，於關閉S1之前，開啟開關S4(即閉路)，步驟63，使得電流源IS1高側上的節點A被耦合於供應電壓VDD。According to this second architecture, switch S4 (i.e., closed circuit) is turned on before step S1 is closed, and step 63 is such that node A on the high side of current source IS1 is coupled to supply voltage VDD.

開啟S4具有施加零偏壓或至少相當少的偏壓於LED L1之效果。換言之，S4具有使電流遠離L1/S1電流路徑之效果。通過S4之電流I4受到電流源IS1限制，故總供應或接地電流仍為IS1。Turning on S4 has the effect of applying a zero bias or at least a relatively small bias voltage to LED L1. In other words, S4 has the effect of moving the current away from the L1/S1 current path. The current I4 through S4 is limited by the current source IS1, so the total supply or ground current is still IS1.

即使有效地關閉LED L1，但相關的開關S1仍是閉路的(即開啟)。Even if LED L1 is effectively turned off, the associated switch S1 is still closed (ie, turned on).

此刻在步驟65，S1可為開路的(即關閉)，藉以從電路移走LED L1。總供應或接地電流仍為IS1。At step 65, S1 can be open (ie, turned off) to remove LED L1 from the circuit. The total supply or ground current is still IS1.

接著使開關S2閉路，步驟67，藉以將LED L2連接於電路。於L1與L2之轉換過程中，開關S4保持閉路。Switch S2 is then closed, step 67, to connect LED L2 to the circuit. During the transition between L1 and L2, switch S4 remains closed.

一旦已使開關S2閉路，則可關閉S4，步驟69，即開路，藉以使LED L2變為正偏壓，使得電流I2從正電源VDD透過電流源IS1通過LED L1至地線GND。Once switch S2 has been closed, S4 can be turned off, step 69, which is an open circuit, whereby LED L2 becomes positively biased such that current I2 flows from positive supply VDD through current source IS1 through LED L1 to ground GND.

當從LED L2改變為另一LED，例如L3等等，時，依類似方式進行此順序。This sequence is performed in a similar manner when changing from LED L2 to another LED, such as L3 or the like.

因此，將可理解並非以中斷的非連續方式從電源供應器引出具有大轉換電流成分之電源供應電流IS(即對應於操作過程中由個別LEDs引出之電流I1、I2及IS3)，而是電源供應電流IS保持固定。Therefore, it will be understood that the power supply current IS having a large switching current component (ie, corresponding to the currents I1, I2, and IS3 drawn by the individual LEDs during operation) is not extracted from the power supply in an interrupted discontinuous manner, but is a power supply. The supply current IS remains fixed.

因此，第5圖之電路架構進行差動(differential)電路轉換，使得電流流經LED(例如L1/S1)及電流源IS1，或者流經分流路徑50及電流源IS1。Therefore, the circuit architecture of FIG. 5 performs a differential circuit conversion such that current flows through the LED (eg, L1/S1) and current source IS1, or through the shunt path 50 and the current source IS1.

因此，將可理解第5圖之電路使得實質上固定的電流IS從電源引出，同樣地使實質上固定的電流於接地迴路路徑中流動，其係降低或實質上消除與暫態有關的ADC干擾問題，因此可以將ADC整合於與LED開關陣列(S1－S3)相同的IC上。整合開關於與處理電路相同的IC上具有使涉及應用的成本減至最少之效果。Thus, it will be understood that the circuit of Figure 5 causes a substantially fixed current IS to be drawn from the power supply, again causing a substantially fixed current to flow in the ground return path, which reduces or substantially eliminates transient-related ADC interference. Problem, so the ADC can be integrated on the same IC as the LED switch array (S1-S3). Integrating the switch on the same IC as the processing circuit has the effect of minimizing the cost involved in the application.

第7a－7d圖提供第5圖之開關S1－S4的開關順序之進一步說明。於時間t1 之前，點亮第5圖之LED L1。換言之，開關S1是開啟的(即因為對應的開關控制信號CS1為高準位之故)，然而開關S2、S3及S4是關閉的(即因為對應的開關控制信號CS2、CS3及CS4低準位之故)。接著進行以下操作，俾點亮LED L2來替代LED L1。首先，於時間t1 時，開啟開關S4(即藉由使開關控制信號CS4變高)。此造成第5圖之分流路徑50變成可操作的。接著，於時間t2 時，藉由關閉開關S1(即藉由使開關控制信號CS1變低準位)，將LED L1移走。應可理解，儘管關閉LED L1，但因分流路徑50及電流源IS1之作用，使得從電源引出之電流IS保持固定。於時間t3時，開啟開關S2(即藉由使開關控制信號CS2變高準位)，使得LED L2連接於電路。最後，於時間t4 時，藉由關閉開關S4(即藉由使開關控制信號CS4變低準位)，將分流路徑移走。Figures 7a-7d provide a further illustration of the switching sequence of switches S1-S4 of Figure 5. At time t 1 before the lighting of the LED L1 of FIG. 5. In other words, the switch S1 is turned on (ie, because the corresponding switch control signal CS1 is at a high level), but the switches S2, S3, and S4 are turned off (ie, because the corresponding switch control signals CS2, CS3, and CS4 are low-level) The reason). Then proceed to the following operation, 俾 light LED L2 instead of LED L1. First, at time t 1, turn on the switch S4 (i.e., by the switching control signal CS4 goes high). This causes the split path 50 of Figure 5 to become operational. Next, at time t 2, the switch is turned off by S1 (i.e., by the switching control signal CS1 becomes low level), the LED L1 is removed. It should be understood that although the LED L1 is turned off, the current IS drawn from the power source remains fixed due to the action of the shunt path 50 and the current source IS1. At time t3, switch S2 is turned on (ie, by causing switch control signal CS2 to go high), causing LED L2 to be coupled to the circuit. Finally, at time t 4, by closing the switch S4 (i.e., by the switching control signal CS4 low level), the bypass path is removed.

當從LED L2轉換為LED L3或從LED L3轉換為LED L1時，進行類似的程序。A similar procedure is performed when converting from LED L2 to LED L3 or from LED L3 to LED L1.

第7e圖顯示當進行上述的切換操作時從第5圖的電源供應器引出的電流IS。可發現電流IS實質上保持固定。Fig. 7e shows the current IS drawn from the power supply of Fig. 5 when the above-described switching operation is performed. It can be found that the current IS remains substantially fixed.

相較之下，第7f圖顯示當在第1圖所示的先前技藝架構中進行切換操作時，亦即倘若不具有分流路徑50，如何從電源供應器(或對應的接地迴路電流)引出電源供應電流IS。In contrast, Figure 7f shows how the power is supplied from the power supply (or the corresponding ground loop current) when the switching operation is performed in the prior art architecture shown in Figure 1, that is, if there is no shunt path 50. Supply current IS.

雖然未顯示於第7a至7f中，但應理解第5圖的架構亦可用於PWM操作模式，因此可藉由改變其控制信號的工作週期及/或頻率控制個別開關，例如於當S1至S3中之一者開啟過程中拴牢CS4。Although not shown in Figures 7a through 7f, it should be understood that the architecture of Figure 5 can also be used in a PWM mode of operation, so that individual switches can be controlled by varying the duty cycle and/or frequency of their control signals, for example, when S1 to S3 One of them turned on CS4 during the opening process.

應注意較佳為依照受控方式切換節點A，使得節點A處之電壓改變率(dv/dt)不會太高。It should be noted that it is preferred to switch node A in a controlled manner such that the voltage change rate (dv/dt) at node A is not too high.

第8圖顯示用於驅動LED陣列之第三架構的基本圖示。Figure 8 shows a basic illustration of a third architecture for driving an LED array.

請參照第3及5圖，LED陣列包含紅色、綠色及藍色LEDs L1、L2、L3。LED開關S1、S2、S3可形成與處理從光感測器接收的影像資料之類比處理電路(AFE)相同的單石電路之一部分。為了降低與干擾ADC處理之LED切換暫態有關的問題，於電流路徑中提供電流源IS1，較佳者係介於開關S1、S2、S3與地線之間，俾控制電流流經LEDs L1、L2、L3。具有開關裝置S4之差異性電流路徑50(或分流路徑)係與LEDs陣列及對應的開關S1－S3並聯設置。Referring to Figures 3 and 5, the LED array includes red, green, and blue LEDs L1, L2, and L3. The LED switches S1, S2, S3 can form part of the same single-rock circuit as the analog processing circuit (AFE) that processes the image data received from the light sensor. In order to reduce the problems associated with interfering with the LED switching transients of the ADC processing, a current source IS1 is provided in the current path, preferably between the switches S1, S2, S3 and the ground, and the control current flows through the LEDs L1. L2, L3. The differential current path 50 (or shunt path) with switching device S4 is placed in parallel with the array of LEDs and corresponding switches S1-S3.

此外，根據此架構，第二電流源IS2係設置於分流路徑50中。第二電流源IS2使得可依更受到控制的方式進行分流路徑50之切換。如以下有關第12a至12d圖之更詳細的說明，有一與節點A有關的電容Cp，其為寄生電容或者可能為真實的額外電容器。Further, according to this architecture, the second current source IS2 is disposed in the shunt path 50. The second current source IS2 makes it possible to switch the shunt path 50 in a more controlled manner. As explained in more detail below with respect to Figures 12a through 12d, there is a capacitance Cp associated with node A, which is a parasitic capacitance or may be a true additional capacitor.

如以上所述有關第5、6及7圖所示，藉著於LED開關S1－S3之後切換裝置S4，開啟第二電流源IS2。由第二電流源IS2引出的電流可具有比由LED L1更高的預設量，例如大於5%。舉例來說，藉由包括可分開切換之並聯的95%電流源及10%電流源，可使其於例如105% IS1與95% IS1之間切換。As described above with respect to Figures 5, 6 and 7, the second current source IS2 is turned on by switching the device S4 after the LED switches S1-S3. The current drawn by the second current source IS2 may have a higher predetermined amount than the LED L1, for example greater than 5%. For example, by including a parallelizable 95% current source and a 10% current source, it is possible to switch between, for example, 105% IS1 and 95% IS1.

第9a至9d圖顯示第8圖的開關S1－S4的切換順序。請參照第9a至9d圖，於開關S1恰關閉之前(時間t2 )，透過開關S4開啟第二電流源IS2(時間t1 )，並從電源引出比先前由LED L1從電流源IS1引出的電流IS稍大的電流IS。於IS1與IS2之間的電流差異係用以對節點A上之電容Cp充電，直到節點A提高至第二電流源IS2的電壓順從(voltage compliance)限制以及IS2的輸出電流降至等於IS1為止。換言之，如第9e圖所示，等於IS2之稍大的電流IS係於時間t1後之短暫時間引出。接地迴路電流之調變實質上與供應電流IS相同。應注意當節點A改變電壓時，IS1與IS2間之差異係以位移電流(displacement current)通過Cp。Figures 9a to 9d show the switching sequence of the switches S1-S4 of Fig. 8. Referring to Figures 9a to 9d, before the switch S1 is turned off (time t 2 ), the second current source IS2 is turned on by the switch S4 (time t 1 ), and is taken out from the power source than the current source IS1 from the LED L1. The current IS is slightly larger than the current IS. The current difference between IS1 and IS2 is used to charge capacitor Cp on node A until node A increases to the voltage compliance limit of second current source IS2 and the output current of IS2 drops to equal IS1. In other words, as shown in Fig. 9e, a slightly larger current IS equal to IS2 is drawn for a short time after time t1. The ground loop current is modulated substantially the same as the supply current IS. It should be noted that when node A changes voltage, the difference between IS1 and IS2 is through Cp with a displacement current.

當從使用一LED(例如L1)轉換為使用另一LED(例如L2)時，如前所述，S1可於時間t2 時開路(關閉)以隔絕LED L1，並且S2可於時間t3 時閉路以連接LED L2。於此切換操作過程中，開關S4保持閉路。When (e.g., L1) is converted to another using the LED (eg L2) when the use of a LED, as described above, S1 can be t 2 when open (OFF) at time to isolate LED L1, and S2 may be at time t 3 when Closed circuit to connect LED L2. During this switching operation, switch S4 remains closed.

一旦開關S2閉路，則降低電流源IS2至小於IS1，並且節點A將以藉由Cp和IS1與IS2間之差決定之速率降低電壓。節點A將降低電壓，直到LED L2開始取得差異電流為止。接著可於時間t4 時關閉開關S4(即開路)，藉以停止電流流經IS2並完全地正偏壓LED L2，使得LED L2變為被點亮，並且從供應器引出受到電流源IS1驅動之電流。Once switch S2 is closed, current source IS2 is reduced to less than IS1, and node A will reduce the voltage at a rate determined by the difference between Cp and IS1 and IS2. Node A will lower the voltage until LED L2 begins to draw a differential current. May then be closed at the time t 4 when switch S4 (i.e. open), thereby stopping the current flowing through the positive bias and completely IS2 LED L2, it becomes such that the LED L2 is lit, and being drawn from the supply of the drive current source IS1 Current.

當從LED L2轉換為另一LED時，重複此程序。Repeat this procedure when switching from LED L2 to another LED.

因此，並非如第9f圖所示具有從其中引出大轉換電流IS之電源供應器(即對應於個別LED電流I1、I2及IS3的中斷或非連續方式)，電源供應器具有從其中引出之遠較平滑或連續的電流IS(如第9e圖所示)。接地電流將等於固定電流源IS1加上任一充電Cp的短暫暫態電流，故在此情況下之接地電流將為IS1加或減例如5%。供應電流調變將是相同的。相較之下，第9f圖顯示在第1圖所示的先前技藝架構中如何引出電流ISPROR ART ，亦如果不具有IS2及S4。如第9f圖所示，當從一LED切換至另一者時，從供應器引出的電流ISPROR ART 將於ISPROR ART 與零之間切換。Therefore, instead of having a power supply from which a large switching current IS is drawn (i.e., an interrupt or discontinuous manner corresponding to individual LED currents I1, I2, and IS3) as shown in Fig. 9f, the power supply has a distance from it. A smoother or continuous current IS (as shown in Figure 9e). The ground current will be equal to the short-lived current of fixed current source IS1 plus any charge Cp, so the ground current in this case will be plus or minus 5% for IS1. The supply current modulation will be the same. In contrast, Figure 9f shows how the current IS PROR ART is derived in the prior art architecture shown in Figure 1, if not IS2 and S4. As shown in Figure 9f, when switching from one LED to the other, the current IS PROR ART from the supply will switch between IS PROR ART and zero.

本發明之較小的切換電流使切換暫態的效果減至最少，使得ADC可整合於與LED陣列相同的IC上，並且可將IC置於掃描頭上。此一整合架構具有減少與此應用有關的成本之效果。The smaller switching current of the present invention minimizes the effects of switching transients so that the ADC can be integrated on the same IC as the LED array and the IC can be placed on the scan head. This integrated architecture has the effect of reducing the costs associated with this application.

根據又一架構，可使用脈寬調變(PWM)控制信號來控制第8圖實施例中的開關。藉由拴牢CS1等等可達成此目的，但為了降低電源和接地電流漣波，必須反相拴牢CS4。然而，較佳者為在分流路徑中實施PWM。換言之，當開關S2閉路時，則使用PWM控制信號來控制S4，藉以間接地控制通過LED L2之電流，因而控制LED L2的平均強度。第10a至10i圖顯示PWM操作，其中L1係以100%工作週期運作，L2係以小的工作週期運作，並且L3係以中等工作週期運作。According to yet another architecture, a pulse width modulation (PWM) control signal can be used to control the switches in the embodiment of Figure 8. This can be achieved by clinching CS1, etc., but in order to reduce the power and ground current ripple, it is necessary to reverse the CS4. However, it is preferred to implement the PWM in the shunt path. In other words, when switch S2 is closed, the PWM control signal is used to control S4, thereby indirectly controlling the current through LED L2, thus controlling the average intensity of LED L2. Figures 10a through 10i show PWM operation, where L1 operates at 100% duty cycle, L2 operates with a small duty cycle, and L3 operates at a medium duty cycle.

根據又一實施例，為了使LED電流變化而不需PWM切換，電流源IS1(及IS2)之改變量對所有LEDs而言可為相同的數量或對每一LED而言有所差異。換言之，可固定電流源IS1及IS2(即設定為依照預設的操作模式進行操作)，或可經程式化使得電流源是可變的。本發明之此態樣的進一步討論將於討論電流源IS1及電流源IS2之後更詳細地提供。According to yet another embodiment, in order to vary the LED current without PWM switching, the amount of change in current source IS1 (and IS2) may be the same amount for all LEDs or different for each LED. In other words, the current sources IS1 and IS2 can be fixed (ie, set to operate in accordance with a preset mode of operation), or can be programmed such that the current source is variable. Further discussion of this aspect of the invention will be provided in more detail after discussion of current source IS1 and current source IS2.

第11a圖顯示可用於第3、5及8圖架構中之電流源IS1的更詳細實施例。Figure 11a shows a more detailed embodiment of the current source IS1 that can be used in the architecture of Figures 3, 5 and 8.

請參照第11a圖，參考電流產生器(CRG)主要係設定全部電路用之參考電流Iref1。Referring to Figure 11a, the reference current generator (CRG) is mainly used to set the reference current Iref1 for all circuits.

提供給CRG中之放大器的輸入的參考電壓Vref較佳者為能隙(bandgap)參考電壓，因而是準確且安定的。The reference voltage Vref supplied to the input of the amplifier in the CRG is preferably a bandgap reference voltage and is therefore accurate and stable.

於此特定的CRG實施例中，Vref係施加於放大器A1的輸入端。反饋放大器A1及電晶體MN0迫使節點Pin上之電壓等於Vref，因而可透過電阻Rext設定電流。此電流通過MN0，俾提供輸出電流Iref1，等於Vref/Rext。In this particular CRG embodiment, Vref is applied to the input of amplifier A1. The feedback amplifier A1 and the transistor MN0 force the voltage on the node Pin to be equal to Vref, so that the current can be set through the resistor Rext. This current is supplied through MN0, which provides an output current Iref1 equal to Vref/Rext.

“Pin”可代表IC上的輸出接腳。藉由改變外部電值(Rext)的數值，使得使用者可設定參考電流Iref1至所需數值。使用者設定Iref1的能力是較佳的，因為其係有關所有具有不同特性之LEDs(L1－L3)的類型。另外，Rext可結合A1，其可以是可修剪的或可數位程式化的以提供調整。“Pin” represents the output pin on the IC. By changing the value of the external electrical value (Rext), the user can set the reference current Iref1 to the desired value. The ability of the user to set Iref1 is preferred because it is related to all types of LEDs (L1-L3) having different characteristics. In addition, Rext can incorporate A1, which can be prunable or digitally stylized to provide adjustment.

電流源IS1包含一系列用於界定電流Iref2及Iref3之受控的電流源MP2/MP3，而Iref2及Iref3係Iref1的鏡射版本。Current source IS1 contains a series of controlled current sources MP2/MP3 for defining currents Iref2 and Iref3, while Iref2 and Iref3 are mirrored versions of Iref1.

電流源IS1包含一可變電流源，例如電流數位類比轉換器(CDAC)，其係由一組2N－1 個NMOS電晶體及開關架構所組成：其中N可為大於1之整數。應注意Iref2及Iref3建立CDAC的電流吸入能力，如下所述。Current source IS1 includes a variable current source, such as a current digital analog converter (CDAC), which is comprised of a set of 2 N-1 NMOS transistors and a switch architecture: where N can be an integer greater than one. It should be noted that Iref2 and Iref3 establish the current sinking capability of the CDAC as described below.

於CDAC內，每一個別開關受到控制，以使相關的NMOS電晶體連接於節點A、開關S1－S4的較低側。應注意CDAC NMOS電晶體MLSB、...、MMSB具有二進位加權的W/L比值，使得每一後繼的電晶體於開啟時可吸入上一個電晶體的電流的二倍。於接近每一電晶體MLSB、...、MMSB處係以編號1、2、...、2N－1 表示。此一架構使電流被CDAC吸入，俾於廣泛的電流數值範圍內受到準確地控制。Within the CDAC, each individual switch is controlled to connect the associated NMOS transistor to the lower side of node A, switches S1-S4. It should be noted that the CDAC NMOS transistors MLSB, ..., MMSB have binary-weighted W/L ratios such that each subsequent transistor can draw twice the current of the previous transistor when turned on. It is represented by numbers 1, 2, ..., 2 N-1 near each of the transistors MLSB, ..., MMSB. This architecture allows current to be drawn in by the CDAC and is accurately controlled over a wide range of current values.

如以上所述，於操作過程中，紅色、綠色及藍色LEDs L1－L3可能須有不同的電流值通過其中。這一部分係因為LEDs的不同特性所致，以及一部分係因為掃描操作過程中每一LED所需的亮度所致。應注意LED的亮度越亮，則取樣(即積分)更少，因此需要掃描時間，此代表可更快速地操作。因此，希望在最大額定電流處或接近最大額定電流情況下操作LEDs而不會損壞LEDs。As mentioned above, red, green and blue LEDs L1-L3 may have different current values through them during operation. This part is due to the different characteristics of the LEDs, and part of it is due to the required brightness of each LED during the scanning operation. It should be noted that the brighter the brightness of the LED, the less sampling (ie, integration), so the scan time is required, which means that it can operate more quickly. Therefore, it is desirable to operate the LEDs at or near the maximum rated current without damaging the LEDs.

於第11a圖的電路中，通過MN1之電流Iref1係為MN2及MLSB、...、MMSB之鏡射(mirror)。為了維持準確性，除節點A之電壓變化外，必須引入放大器A2。於A2的反相輸入端上的電壓係為節點A的電壓，並於操作過程中改變。經由MN1導入的電壓反相及增益來自A2的非反相輸入的負回饋造成MN1的閘極電壓下降至用以吸入來自MP2輸出之電流Iref2所需的電壓。MN2及MP3不是必要的，但在關閉所有CDAC NMOS電晶體(MLSB－MMSB)之情形中(即零輸出電流)被導入以維持回饋。In the circuit of Fig. 11a, the current Iref1 through MN1 is a mirror of MN2 and MLSB, ..., MMSB. In order to maintain accuracy, in addition to the voltage change of node A, amplifier A2 must be introduced. The voltage at the inverting input of A2 is the voltage at node A and changes during operation. The voltage inversion introduced via MN1 and the negative feedback from the non-inverting input of A2 cause the gate voltage of MN1 to drop to the voltage required to sink the current Iref2 from the MP2 output. MN2 and MP3 are not necessary, but in the case where all CDAC NMOS transistors (MLSB-MMSB) are turned off (ie, zero output current) are introduced to maintain feedback.

現代的電子系統及尤其掃描器目前係以低供應電壓操作，以降低電源消耗、電源發散以及主動和被動元件成本。就低電壓應用而言，例如VDD=5伏特之情形，電流源IS1被選擇及設計成使得最大可能的電壓降存在於跨越LEDs L1-L3之處，而最小可能的電壓降則存在於跨越電流源IS1之處。Modern electronic systems and, in particular, scanners are currently operating at low supply voltages to reduce power consumption, power divergence, and active and passive component costs. For low voltage applications, such as VDD = 5 volts, current source IS1 is selected and designed such that the largest possible voltage drop exists across LEDs L1-L3, while the smallest possible voltage drop is present across the current. Source IS1.

假設CDAC具有8位元(N=8)，則於255階中，從零至Imax3有256個分離的位準(因為28 =256)，故每一階(ILSB )為Imax3/255，其中Imax3為CDAC的最大輸出電流。Assuming that CDAC has 8 bits (N=8), there are 256 separate levels from zero to Imax3 in 255 steps (because 2 8 = 256), so each order (I LSB ) is Imax3/255. Where Imax3 is the maximum output current of CDAC.

假設通過LEDs之任一者的最大所需電流為Imax1(於LEDs中容許公差)，則容許某些邊際(margin)，Imax3<Imax1。Assuming that the maximum required current through any of the LEDs is Imax1 (tolerance in the LEDs), some margin is allowed, Imax3 < Imax1.

為了正確操作，IS2係配置為可提供比Imax3稍大的電流Imax2，使得Imax2>Imax3，其理由從以下說明當可明白。For proper operation, the IS2 is configured to provide a current Imax2 that is slightly larger than Imax3 such that Imax2 > Imax3, for reasons that will be apparent from the following description.

較佳者，設定MN1的電晶體通道寬長比W/L與CDAC的LSB NMOS電晶體相同(於閘極端下方以數字”1”表示)。因此，MN1吸入等於Imax3/255之Iref2，也就是等於ILSB 。應注意的是Iref2可以大於或小於Iref1，而此目的可藉由計算電晶體MP2的電晶體W/L比例相對於電晶體MP1之電晶體通道寬長比W/L的尺寸來達成。同樣地，藉由估算MN1相對於CDAC NMOS電晶體MLSB、...、MMSB之大小，可透過Imax3調整Iref2的大小。Preferably, the transistor channel width to length ratio W/L of MN1 is set to be the same as the LSB NMOS transistor of CDAC (indicated by the number "1" below the gate terminal). Therefore, MN1 inhales Iref2 equal to Imax3/255, which is equal to I LSB . It should be noted that Iref2 may be larger or smaller than Iref1, and this object can be achieved by calculating the transistor W/L ratio of the transistor MP2 with respect to the transistor channel width-to-length ratio W/L of the transistor MP1. Similarly, by estimating the size of MN1 relative to the CDAC NMOS transistors MLSB, ..., MMSB, the size of Iref2 can be adjusted by Imax3.

所示的電晶體NM2具有寄生閘極-汲極電容CGD 。此一電容存在於CDAC的所有NMOS電晶體中，雖然並未顯示於圖中：此一寄生電容被稱為米勒(Miller)電容。The illustrated transistor NM2 has a parasitic gate-drain capacitance C GD . This capacitor is present in all NMOS transistors of the CDAC, although not shown in the figure: this parasitic capacitance is called a Miller capacitor.

應注意的是，其為所有這些電容的組合閘極-汲極電容CGDTOT ，(關於MN2以及在CDAC中切換的NMOS電晶體以及可能是A2的輸入電晶體)，提供一種加重先前所述的電源和接地電流暫態之機構，因而產生如以上有關第5圖所述之促使節點的轉換率(slew rate)變小之需求。It should be noted that it is the combined gate-drain capacitance C GDTOT of all of these capacitors (with respect to MN2 and the NMOS transistor switched in CDAC and possibly the input transistor of A2), providing an emphasis on the previously described The mechanism of power and ground current transients thus creates a need to cause the node's slew rate to become smaller as described above with respect to Figure 5.

請參照第5圖，於第5圖架構中之CGDTOT 的作用在於，當該分流路徑被致能(即關閉S4)且連接供應電壓VDD至MN2和致能的CDAC NMOS電晶體的高側處時，在節點A上有大的dv/dt。這代表透過CGDTOT 連接此等在其電流上造成突波之電晶體的閘極的交流電，而此等電流係以電源軌上之暫態顯現，視CGDTOT 的數值而定，其將對於ADC造成較大或較小的效應。Referring to FIG. 5, the function of the C GDTOT in the architecture of FIG. 5 is that when the shunt path is enabled (ie, S4 is turned off) and the supply voltages VDD to MN2 and the high side of the enabled CDAC NMOS transistor are connected At the time, there is a large dv/dt on node A. This represents the AC current connected to the gate of the transistor that causes a surge in its current through C GDTOT , and these currents appear as transients on the power rail, depending on the value of C GDTOT , which will be for the ADC. Causes a larger or smaller effect.

第二效應是，例如在使用第11a圖所示之電流源IS1時，在MN2及其他並聯的NMOS電晶體MLSB、...、MMSB之閘極上的暫態衝擊干擾了放大器A2之偏壓點設定。A2將僅具有有限的頻寬，故可能花一些時間安定或重建穩定狀態偏壓點。於此時間中，來自CDAC之電流輸出將偏離名義數值。因此，有必要控制節點A處之換轉率。The second effect is that, for example, when using the current source IS1 shown in FIG. 11a, the transient impact on the gates of the MN2 and other parallel NMOS transistors MLSB, . . . , MMSB interferes with the bias point of the amplifier A2. set up. A2 will only have a limited bandwidth, so it may take some time to stabilize or reconstruct the steady state bias point. During this time, the current output from the CDAC will deviate from the nominal value. Therefore, it is necessary to control the switching rate at node A.

應注意的是，在本發明之非常基本的型態中，可藉由可變電阻、電阻受控開關等實施第5圖中所示之S4，故其可依受控方式開啟以避免節點A上之高電壓變化率dv/dt。就第8圖實施例中之IS2而言亦同。It should be noted that in the very basic form of the present invention, S4 shown in FIG. 5 can be implemented by a variable resistor, a resistance controlled switch, etc., so that it can be turned on in a controlled manner to avoid node A. The high voltage change rate dv/dt. The same applies to IS2 in the embodiment of Fig. 8.

由於具有跨越LEDs的最大可能的電壓降及跨越電流源IS1之最小電壓降之需求，第11a圖之電路因第5圖節點A處之高電壓而易遭受損壞。這是因為節點A的高電壓造成MN2的閘極上的電壓因米勒(Miller)電容效應而上升，因而造成MN2開啟。The circuit of Figure 11a is susceptible to damage due to the high voltage at node A of Figure 5 due to the need for the maximum possible voltage drop across the LEDs and the minimum voltage drop across the current source IS1. This is because the high voltage of node A causes the voltage on the gate of MN2 to rise due to the Miller capacitance effect, thus causing MN2 to turn on.

鑑於此可能性，第11b圖顯示較佳的改良方式，其中串疊(cascode)電晶體係連接於MN2的汲極，藉以遮蔽MN2免受第5圖節點A處之電壓作用。串疊電晶體受到，例如由所示的電流源架構供應所的參考電壓Vbias的偏壓。In view of this possibility, Figure 11b shows a preferred modification in which a cascode cell system is connected to the drain of MN2 to shield MN2 from the voltage at node A of Figure 5. The tandem transistor is biased, for example, by a reference voltage Vbias supplied by the current source architecture as shown.

於第11b圖中所示且與MN2有關的串疊電晶體較較好是用來做為與每一CDAC NMOS電晶體(未顯示)有關的個別開關之基礎。於CDAC中之每一”串疊”開關係獨立地受到對個別串疊開關偏壓之控制信號的控制。於CDAC中利用串疊開關的優點在於有助於使CDAC及接地電源軌與暫態分離。The tandem transistor shown in Figure 11b and associated with MN2 is preferably used as the basis for the individual switches associated with each CDAC NMOS transistor (not shown). Each "cascade" open relationship in the CDAC is independently controlled by a control signal to the individual string switching bias. The advantage of using a cascade switch in CDAC is that it helps to separate the CDAC and ground supply rails from transients.

如以上所述，於低壓應用中，較佳的方式是具有跨越每一LEDs之最大可能電壓降，俾使通過LEDs之電流達到最大，此意味著跨越每一開關S1－S3及電流源IS1之最小可能電壓降。應注意的是，開關的導通電阻實質上是可忽略的，因此相較於有關電流源IS1之電壓降是低的。As mentioned above, in low voltage applications, the preferred way is to have the largest possible voltage drop across each LED s, maximizing the current through the LEDs, which means crossing each switch S1-S3 and current source IS1 The smallest possible voltage drop. It should be noted that the on-resistance of the switch is substantially negligible and therefore the voltage drop is low compared to the associated current source IS1.

為了使通過電流源IS1之電壓降減至最少，跨越MN1及MN2的汲極－源極以及CDAC電晶體和開關元件的電壓降必須是低的。然而，為了將MN2保持在飽和區中以便提供極佳的電流源，必須保持此等電晶體的VDSsat 是低的。In order to minimize the voltage drop across current source IS1, the voltage drop across the drain-source of MN1 and MN2 and the CDAC transistor and switching elements must be low. However, in order to remain in the saturation region MN2 to provide excellent current source, V DSsat must maintain these transistors is low.

NMOS電晶體的轉移電導(gm)大致上是：gm＝2.IDS/VDSsat The transfer conductance (gm) of an NMOS transistor is roughly: gm=2.IDS/V DSsat

因此，gm係與VDSsat 成反比，故低VDSsat 產生高gm。Therefore, the gm system is inversely proportional to V DSsat , so low V DSsat produces a high gm.

電晶體MN1與MN2任何的不匹配將於MN2的閘極端產生有效的補償電壓。由於MN2的高增益(gm)，此一補償造成誤差。從以上公式可發現，有效的閘極電壓補償△V將在輸出電流Iref3中提供相較於Iref2而言較少的誤差△I，其中△I/IDS＝gm.△V/IDS＝2.△V/VDSsat Any mismatch between transistor MN1 and MN2 will produce an effective compensation voltage at the gate terminal of MN2. This compensation causes an error due to the high gain (gm) of the MN2. From the above formula, it can be found that the effective gate voltage compensation ΔV will provide less error ΔI in the output current Iref3 compared to Iref2, where ΔI/IDS=gm.ΔV/IDS=2. V/V DSsat

當CDAC內之電晶體被切換時，這特別是真實的，因為其亦具有如MN2之高轉移電導且為二進位加權並受到相似大小的有效補償電壓所驅動。This is especially true when the transistor within the CDAC is switched because it also has a high transfer conductance like MN2 and is weighted by the binary and is driven by an effective compensation voltage of similar magnitude.

為了獲致8位元準確度，100毫伏特(mV)VDSsat 之MN1需要低於毫伏特的補償值。藉由提高其閘極面積可降低NMOS電晶體的隨機製造補償電壓。然而，由於補償電壓僅與其閘極面積的平方根成反比：故導致不切實際的大MN1裝置及CDAC裝置。為了克服此問題，可以提供第二、更準確的電流源，藉此以第一電流源的輸出校正此第二電流源。於本實施例中，IS2包含第二電流源。IS2具有遠更多的高空(headroom)，幾乎是VDD全部，故就所需的準確度而言，可包含具有較大的VDSsat 及較小的面積之裝置。In order to achieve 8-bit accuracy, MN1 of 100 millivolts (mV) V DSsat requires a compensation value below millivolts. The random fabrication compensation voltage of the NMOS transistor can be reduced by increasing its gate area. However, since the compensation voltage is only inversely proportional to the square root of its gate area: this results in an impractical large MN1 device and CDAC device. To overcome this problem, a second, more accurate current source can be provided whereby the second current source is corrected with the output of the first current source. In this embodiment, IS2 includes a second current source. IS2 has far more headroom, almost all VDD, so it can include devices with larger V DSsat and smaller area in terms of required accuracy.

為了提供電流源IS2之更詳細說明，請參照第12a至12d圖，其中：第12a圖顯示第8圖中所用的電流源IS2之簡化實施例。In order to provide a more detailed description of the current source IS2, please refer to Figures 12a to 12d, wherein: Figure 12a shows a simplified embodiment of the current source IS2 used in Figure 8.

第12b圖顯示根據本發明用於偵測最大電流(Imax)之保護電路之實施例，第12c圖顯示如何關閉第12b圖之保護電路，以及第12d圖顯示第8及12a圖中所示的電流源IS2之更詳細實施例。Figure 12b shows an embodiment of a protection circuit for detecting the maximum current (Imax) according to the present invention, Figure 12c shows how to turn off the protection circuit of Figure 12b, and Figure 12d shows the picture shown in Figures 8 and 12a. A more detailed embodiment of current source IS2.

請參照第12b及12d圖，此刻將更進一步說明分流路徑50具有保護電路120以防止過電流通過LED L1-L3。於12d圖中：電晶體MP5、MN4及MN5組成第12b圖中之電流源IS3；電晶體MP4、MN3及MN6組成第12b圖中之電流源IS5；電晶體MP10、MN11及MN7組成第12b圖中之電流源IS4。Referring to Figures 12b and 12d, it will be further explained at this point that the shunt path 50 has a protection circuit 120 to prevent overcurrent from passing through the LEDs L1-L3. In Fig. 12d: transistors MP5, MN4 and MN5 form current source IS3 in Figure 12b; transistors MP4, MN3 and MN6 form current source IS5 in Figure 12b; transistors MP10, MN11 and MN7 form Figure 12b Current source IS4.

請參照第12d圖，電晶體MP4係由適合的電壓，例如第11a圖之節點X，驅動，俾傳送電流Iref4，Iref1之複製電流。其係受到電晶體MN3及MN6鏡射，接著再度受到MP9及MP8鏡射。大部分MP8的輸出電流接著透過MP6輸出，以提供輸出電流Iref4，進而當LEDs受到電流源IS2分流時可傳送電流Imax2。Referring to Fig. 12d, the transistor MP4 is driven by a suitable voltage, such as node X of Fig. 11a, to transmit currents Iref4, Iref1. It is mirrored by the transistors MN3 and MN6, and then mirrored again by MP9 and MP8. Most of the MP8's output current is then output through the MP6 to provide an output current Iref4, which in turn can deliver current Imax2 when the LEDs are shunted by current source IS2.

保護電路120之MP7鏡射電流Imax2流經電晶體MP6。應注意，MP7的電晶體通道寬長比W/L可為，例如MP6之1/1000。這代表最大電流偵測器電路僅轉移少部份的MP8輸出電流，並且當進行電流偵測功能時僅消耗最小功率。The MP7 mirror current Imax2 of the protection circuit 120 flows through the transistor MP6. It should be noted that the transistor channel width to length ratio W/L of the MP7 can be, for example, 1/1000 of the MP6. This means that the maximum current detector circuit only transfers a small portion of the MP8 output current and consumes only minimal power when performing current sensing.

MP5受到與MP4相同的閘極電壓驅動，以提供另一複製電流Iref5，其接著係透過MN4及MN5鏡射。MN5係連接於MP7：倘若MP7攜帶比MN5更多電流，則在其共同汲極節點處之電壓變高，並且倘若MP7攜帶比MN5更少電流，則在其共同汲極節點處之電壓變低。由於I(MP7)為I(MP8)的已知分率(例如1/1000)，故其標記是否I(MP8)小於或大於某些預設的門檻值，此預設的門檻值主要係由鏡射的電晶體大小比例MP6：MP7、MN5：MN4及MP4、MP5對例如第11a圖之MP1的比例決定。The MP5 is driven by the same gate voltage as MP4 to provide another replica current Iref5, which is then mirrored through MN4 and MN5. MN5 is connected to MP7: if MP7 carries more current than MN5, the voltage at its common bungee node becomes higher, and if MP7 carries less current than MN5, the voltage at its common bungee node becomes lower . Since I(MP7) is a known fraction of I(MP8) (for example, 1/1000), its flag is whether I(MP8) is less than or greater than some preset threshold. This preset threshold is mainly caused by The ratio of mirrored transistor size MP6: MP7, MN5: MN4 and MP4, MP5 is determined, for example, by the ratio of MP1 in Figure 11a.

比較器Ca比較電晶體MP7和MN5的共同汲極節點的電壓與參考電壓Vref。因此，倘若流經MP8之最大電流超過預設門檻值，則設定比較器輸出信號ILEDmax 以顯示此情況。The comparator Ca compares the voltage of the common drain node of the transistors MP7 and MN5 with the reference voltage Vref. Therefore, if the maximum current flowing through the MP8 exceeds the preset threshold, the comparator output signal I LEDmax is set to indicate this.

於操作中，MP6的輸出端係連接於IS1的輸出端，如所示，並且傳導電流I4。倘若IS1小於I4(即IMP6)，則節點A將提高，直到MP6的源極電壓(即MP6的汲極電壓)以提高至足以讓MP8從飽和態進入三極操作為止，亦即通過被視為電流源之MP8的輸出電壓順從。MP7仍將輸出相同分率的I4(即IMP6)，故比較器標記I(IS1)是否小於或大於I4(IMP6)的預設門檻值。In operation, the output of MP6 is connected to the output of IS1, as shown, and conducts current I4. If IS1 is less than I4 (ie, IMP6), node A will increase until the source voltage of MP6 (ie, the drain voltage of MP6) is raised enough to allow MP8 to enter the three-pole operation from saturation, that is, by being considered The output voltage of the MP8 of the current source is compliant. MP7 will still output the same fraction of I4 (ie IMP6), so the comparator flag I (IS1) is less than or greater than the preset threshold of I4 (IMP6).

然而，當傳送以MP8界定之I4時，倘若IS1大於I4(IMP6)，則節點A將降低，直到節點A達到IS1的電壓順從為止。通過MP7之電流將變高，故比較器將標記此結果。此”標記”信號ILEDmax 接著可用以抑制開關S1－S3開啟，俾防止IS1電流引進LEDs，至少直到對於IS1 CDAC之數位控制已被調整至減至所需的安全準位為止，藉以保護LED。However, when transmitting I4 defined by MP8, if IS1 is greater than I4 (IMP6), node A will decrease until node A reaches the voltage compliance of IS1. The current through MP7 will go high, so the comparator will flag this result. This "mark" signal I LEDmax can then be used to inhibit the switches S1-S3 from turning on, preventing the IS1 current from being introduced into the LEDs, at least until the digital control for the IS1 CDAC has been adjusted to the desired safe level to protect the LEDs.

因此，根據本發明，保護電路120使LEDs於其最大強度下點亮，同時防止過電流流經LEDs L1－L3中之任一者。Thus, in accordance with the present invention, protection circuit 120 causes LEDs to illuminate at their maximum intensity while preventing overcurrent from flowing through any of LEDs L1-L3.

於IS2之運行中，藉由使用開關S4＊ 控制MP8的閘極，可開啟及關閉輸出電流I4。(註：S4＊ 開路相當於以上圖示中之S4閉路，反之亦然)。In the operation of IS2, the output current I4 can be turned on and off by controlling the gate of the MP8 using the switch S4 * . (Note: S4 * Open circuit is equivalent to S4 closed circuit in the above illustration, and vice versa).

如以上所述，較佳者為限制節點A上的電壓轉換率(slew rate)。此可使用電容器C之輔助以及來自MN6至MP11之受控的充電電流而實施。請看第12b圖，應注意由電流源IS4(MP11)供應的電流IIS4係為由電流源IS5(MP6)供應的電流IIS5的二倍，使得：當S4＊ 開路時，電流源IS5吸入拉引電晶體MP8及MP9的閘極以及電容器C的低側朝地線之電流。電晶體MP8及MP9係以受到電容器C影響之速率開啟，且MP8鏡射流經電晶體MP9的放大電流。當S4＊ 閉路時，電流源IS4有效地拉引電晶體MP8及MP9的閘極以及電容器C的低側朝向電源VDD，而電晶體MP8及MP9係以受到電容器C影響之速率關閉，藉以逐漸地停止電流(I4)流至電流源IS1。As described above, it is preferable to limit the voltage slew rate on the node A. This can be implemented using the assistance of capacitor C and the controlled charging current from MN6 to MP11. Looking at Figure 12b, it should be noted that the current IIS4 supplied by the current source IS4 (MP11) is twice the current IIS5 supplied by the current source IS5 (MP6), so that when the S4 * is open, the current source IS5 is pulled in and pulled. The gates of the transistors MP8 and MP9 and the low side of the capacitor C are directed to the ground. The transistors MP8 and MP9 are turned on at a rate affected by the capacitor C, and the MP8 mirrors the amplified current flowing through the transistor MP9. When S4 * is closed, current source IS4 effectively pulls the gates of transistors MP8 and MP9 and the low side of capacitor C toward power supply VDD, while transistors MP8 and MP9 are turned off at a rate affected by capacitor C, thereby gradually The stop current (I4) flows to the current source IS1.

電容器C，相當大的電容器，連接於電晶體MP8及MP9的共閘極端，係發揮延緩電晶體MP8及MP9的閘極電壓上升之功能，因此並非二個電晶體於相當短期間內開啟，而是此等電晶體的啟動時間相當緩慢。這具有降低節點A上的電壓變化率dv/dt的效果。應理解可改變所用的電晶體大小及電容器的數值以極LED電流數值，進而產生所需的效果，亦即節點A處之降低的dv/dt。Capacitor C, a relatively large capacitor connected to the common gate terminal of transistors MP8 and MP9, functions to delay the rise of the gate voltage of transistors MP8 and MP9, so that not two transistors are turned on in a relatively short period of time. It is the start-up time of these transistors that is quite slow. This has the effect of reducing the voltage change rate dv/dt on the node A. It will be appreciated that the transistor size used and the value of the capacitor can be varied to the extreme LED current value to produce the desired effect, i.e., the reduced dv/dt at node A.

請參照第12c圖，較佳者為將開關機構，如所示之開關S5及S6，***保護電路120(Imax Det)中。藉由***此等開關，最初流經LED之電流係為流經LED達到其為導通電流之持續時間之電流的指標，故可禁能LED電路監測。S5及S6受到反相信號驅動，使得當S5閉路時，S6為開路，反之亦然。Referring to Figure 12c, it is preferred to insert the switching mechanism, such as switches S5 and S6 as shown, into protection circuit 120 (Imax Det). By inserting these switches, the current flowing through the LED is an indicator of the current flowing through the LED to the duration of its on-current, so that LED circuit monitoring can be disabled. S5 and S6 are driven by the inverted signal so that when S5 is closed, S6 is open and vice versa.

從以上所述，可發現第12b、12c及12d所示之較佳電流源之架構使得每一LED的電流設定可被測量：倘若其超過最大值，則不連接LED，故LED受到保護。無論是否致能分流電路，這都是有效的，不論是在LEDs之間切換時或者是PWM模式中之脈衝間的”關閉”時間。這優點在於使電流得以在分流路徑中，而不是在真正含有LED之路徑中。From the above, the architecture of the preferred current source shown in Figures 12b, 12c and 12d can be found such that the current setting of each LED can be measured: if it exceeds the maximum value, the LED is not connected and the LED is protected. This is effective whether or not the shunt circuit is enabled, whether it is switching between LEDs or the "off" time between pulses in PWM mode. This has the advantage of allowing current to flow in the shunt path rather than in the path that actually contains the LED.

應注意，必要時可縮放MP8的電晶體通道寬長比W/L。舉例來說，MP8的電晶體通道寬長比W/L可經縮放為MP9的2N *1.2倍(即就8位元而言=256*1.2倍)，俾提供對於IS1放大1.2倍之名義IS2。類似地，可縮放例如MN5的電晶體通道寬長比W/L以調整限制門檻值。It should be noted that the transistor channel width to length ratio W/L of the MP8 can be scaled as necessary. For example, the MP8's transistor channel width-to-length ratio W/L can be scaled to 2 N * 1.2 times MP9 (ie, 256 * 1.2 times for 8-bit), and provides a nominal 1.2 times for IS1 amplification. IS2. Similarly, the transistor channel width to length ratio W/L, such as MN5, can be scaled to adjust the threshold threshold.

於另一實施例中，除MP8為固定大小外，其可分割為例如256個片段，並且經數位地控制以充當電流DAC。由於其具有更多可利用的高空，故其在實體上可以是小的。當使用MP8 CDAC設定所需的電流時，可重複IS1，直到其在I(MP8)(嚴格地說，為I(IMP6))的LSB內為止。依此方式，準確性需求及因此IS1中之CDAC的物體尺寸可保持在合理界限內。In another embodiment, in addition to MP8 being a fixed size, it can be partitioned into, for example, 256 segments and digitally controlled to act as a current DAC. It can be physically small because it has more available altitude. When the required current is set using the MP8 CDAC, IS1 can be repeated until it is within the LSB of I (MP8) (strictly speaking, I (IMP6)). In this way, the accuracy requirements and therefore the size of the object of the CDAC in IS1 can be kept within reasonable limits.

應理解，以上具體例提供LED電流控制的PWM或絕對控制之選擇。為了控制照射亮度及成像週期，因此可以利用兩種技術，即調整絕對電流或改變PWM控制的導通時間。It should be understood that the above specific examples provide for the selection of PWM or absolute control of LED current control. In order to control the illumination brightness and imaging period, two techniques can be utilized, namely adjusting the absolute current or changing the on-time of the PWM control.

藉由使LED亮度達到最大，用於偵測最大LED電路之保護電路120使掃描時間減至最少。藉著以接近最大額定電流操作 LED可達成此目的。為了避免對於LED之損壞，必須於連接LED於電源供應器之前檢查LED電流係在LED最大額定電流範圍內。By maximizing the brightness of the LED, the protection circuit 120 for detecting the largest LED circuit minimizes scan time. By operating at near maximum rated current LEDs can achieve this. In order to avoid damage to the LED, it is necessary to check that the LED current is within the maximum rated current range of the LED before connecting the LED to the power supply.

應注意，於上述架構之說明中，係假設例如第9e圖中之LED L2及LED L3引出與LED L1相同的電流，即I1=I2=I3。然而，應理解每一LED的最佳可操作電流可為不同的。再者，操作電流可能必須是可調整的、可能必須調整物體的照度至符合特殊感測器的敏感度或物體的反射係數。It should be noted that in the above description of the architecture, it is assumed that, for example, LED L2 and LED L3 in Fig. 9e draw the same current as LED L1, i.e., I1 = I2 = I3. However, it should be understood that the optimum operational current for each LED can be different. Furthermore, the operating current may have to be adjustable and the illumination of the object may have to be adjusted to match the sensitivity of the particular sensor or the reflection coefficient of the object.

亦應理解，在每一架構中之電流源IS1可經配置以提供預設的電流，及/或經配置以使電流是可變的(例如視開關LEDs L1-L3中之何者而定)。換言之，電流源IS1可被固定(即設定為在預設的操作模式下操作)，或經程式化以使電流源的操作是可變的。It should also be understood that the current source IS1 in each architecture can be configured to provide a predetermined current, and/or configured to make the current variable (eg, depending on which of the switch LEDs L1-L3). In other words, current source IS1 can be fixed (ie, set to operate in a preset mode of operation) or programmed to make the operation of the current source variable.

亦應理解，雖然本發明之較佳具體例係關於提供一種當切換於LED陣列中的LEDs之間時之保護電路，但本發明亦適用於提供單一LED或光源的保護電路，使得單一LED或光源未被過電流損壞。It should also be understood that while a preferred embodiment of the present invention is directed to providing a protection circuit when switching between LEDs in an LED array, the present invention is also applicable to a protection circuit that provides a single LED or light source such that a single LED or The light source is not damaged by overcurrent.

應注意上述的具體例係用以說明本發明，而非限制本發明，並且熟習本技藝之人士可設計許多替代的具體例，而不脫離如附申請專利範圍或圖式的範圍。”包含”一詞並非排除申請專利範圍中所列者以外之元件或步驟之存在，”a”或”an”並非排除複數，並且單一元件或其他單元可達成申請專利範圍中所述之若干單元的功能。申請專利範圍中之任一代號不應視為用於限制其範圍。It is to be noted that the specific embodiments described above are intended to be illustrative of the invention, and are not intended to The word "comprising" does not exclude the existence of the elements or the steps in the application of the patent application. "a" or "an" does not exclude the plural. The function. Any code in the scope of patent application shall not be deemed to limit its scope.

50．．．分流路徑50. . . Split path

120．．．保護電路120. . . protect the circuit

A1、A2．．．放大器A1, A2. . . Amplifier

ADC．．．類比數位轉換器ADC. . . Analog digital converter

AFE．．．類比前端電路AFE. . . Analog front end circuit

C、CGD 、Cp．．．電容器C, C GD , Cp. . . Capacitor

Ca．．．比較器Ca. . . Comparators

Cascode．．．串疊電晶體Cascode. . . Tandem transistor

CDAC．．．電流數位類比轉換器CDAC. . . Current digital analog converter

CS1、CS2、CS3、CS4．．．開關控制信號CS1, CS2, CS3, CS4. . . Switch control signal

GND．．．地線GND. . . Ground wire

I1、I2、I3、I4、ISPRIOR ART ．．．電流I1, I2, I3, I4, I SPRIOR ART . . . Current

IC．．．積體電路IC. . . Integrated circuit

ILEDmax ．．．比較器輸出信號I LEDmax . . . Comparator output signal

Iref1、Iref2、Iref3．．．參考電流Iref1, Iref2, Iref3. . . Reference current

IS．．．供應電流IS. . . Supply current

IS1、IS2、IS3、IS4、IS5．．．電流源IS1, IS2, IS3, IS4, IS5. . . Battery

L1、L2、L3．．．LED陣列L1, L2, L3. . . LED array

MN0－7．．．電晶體MN0-7. . . Transistor

MLSB、MMSB．．．電晶體MLSB, MMSB. . . Transistor

MP1－11．．．電晶體MP1-11. . . Transistor

Node A．．．節點ANode A. . . Node A

Node X．．．節點XNode X. . . Node X

PDA．．．光電二極管列陣PDA. . . Photodiode array

Pin．．．輸出接腳Pin. . . Output pin

PSU．．．電源供應器PSU. . . Power Supplier

PWM．．．脈寬調變PWM. . . Pulse width modulation

R1、R2、R3．．．電阻器R1, R2, R3. . . Resistor

Rext．．．電阻Rext. . . resistance

S1、S2、S3、S4、S5、S6、S4＊ ．．．開關S1, S2, S3, S4, S5, S6, S4 * . . . switch

SC．．．開關控制器邏輯電路SC. . . Switch controller logic

Vbias．．．參考電壓Vbias. . . Reference voltage

VDD．．．供應電壓VDD. . . Supply voltage

Vref．．．參考電壓Vref. . . Reference voltage

第1圖顯示先前技藝系統的基本方塊圖；第2a－2h圖顯示於固定電流與PWM模式中，當於LEDs之間切換時之第1圖中的開關控制信號以及引出的電流；第3圖顯示如本案申請人的共同申請案台灣第096124764號發明申請案中所述用於驅動LED陣列之驅動裝置的基本方塊概念圖；第4圖顯示當於LEDs之間切換時之第2圖電路引出的電流；第5圖顯示用於驅動LED陣列之第二架構的基本方塊概念圖；第6圖顯示有關第5圖的開關S1－S4的切換順序之流程圖；第7a至7f圖為顯示第5圖的開關S1－S4的切換順序之信號圖；第8圖顯示用於驅動LED陣列之第三架構的基本方塊概念圖；第9a至9f圖為顯示第8圖的開關S1－S4的切換順序之信號圖(當以固定電流模式於LEDs之間切換時)；第10a至10i圖為顯示第8圖的開關S1－S4的切換順序之信號圖(當以PWM模式於LEDs之間切換時)；第11a圖提供第8圖之更詳細的說明，尤其第一電流源IS1；第11b圖顯示第11a圖之另一選擇改良方式；第12a圖顯示第8圖中所用的電流源IS2之簡化實施例；第12b圖顯示根據本發明之保護電路之實施例；第12c圖顯示如何關閉第12b圖之保護電路，以及第12d圖顯示第8及12a圖中所示的電流源IS2之更詳細實施例。Figure 1 shows the basic block diagram of the prior art system; Figure 2a-2h shows the switch control signal and the extracted current in Figure 1 when switching between LEDs in fixed current and PWM modes; A basic block conceptual diagram of a driving device for driving an LED array as described in the co-pending application No. 096,124,764, the entire disclosure of which is incorporated by reference. The current is shown in Figure 5; the basic block diagram of the second architecture for driving the LED array is shown; the sixth diagram shows the flow chart of the switching sequence of the switches S1-S4 in Figure 5; the 7a to 7f are the first 5 is a signal diagram of the switching sequence of the switches S1-S4; FIG. 8 shows a basic block conceptual diagram of the third architecture for driving the LED array; and FIGS. 9a to 9f are diagrams showing the switching of the switches S1-S4 of FIG. Sequence signal diagram (when switching between LEDs in fixed current mode); Figures 10a to 10i are signal diagrams showing the switching sequence of switches S1-S4 in Figure 8 (when switching between LEDs in PWM mode) ); Figure 11a provides a more detailed description of Figure 8, In particular, the first current source IS1; FIG. 11b shows another alternative modification of FIG. 11a; FIG. 12a shows a simplified embodiment of the current source IS2 used in FIG. 8; and FIG. 12b shows the protection circuit according to the present invention. Embodiments; Figure 12c shows how to turn off the protection circuit of Figure 12b, and Figure 12d shows a more detailed embodiment of the current source IS2 shown in Figures 8 and 12a.

120．．．保護電路120. . . protect the circuit

Cascode．．．串疊電晶體Cascode. . . Tandem transistor

CGD ．．．電容器C GD . . . Capacitor

Iref3．．．參考電流Iref3. . . Reference current

MN2．．．電晶體MN2. . . Transistor

Vbias．．．參考電壓Vbias. . . Reference voltage

Claims (20)

一種用於保護光源之保護電路，該保護電路包含：一分流路徑，該分流路徑係選擇性地並聯耦合於該光源；一偵測電路設置於該分流路徑中，用以在該光源被一電源供應器點亮之前決定將流經該光源之電流量；以及一比較器，用以在當該偵測電路測到該電流量超過預設門檻值時防止或限制流經該光源之電流；其中該分流路徑包含具有第一電晶體裝置之電流源，用以當該分流路徑並聯耦合於該光源時控制流經該分流路徑之電流，其中流經該分流路徑之電流量係為當該分流路徑中斷與該光源並聯時將流經該光源之電流量的指標。 A protection circuit for protecting a light source, the protection circuit comprising: a shunt path selectively coupled in parallel to the light source; a detection circuit disposed in the shunt path for being powered by the light source Determining a current amount flowing through the light source before the light is turned on; and a comparator for preventing or limiting a current flowing through the light source when the detecting circuit detects that the current amount exceeds a preset threshold value; The shunt path includes a current source having a first transistor device for controlling a current flowing through the shunt path when the shunt path is coupled in parallel to the source, wherein a current amount flowing through the shunt path is when the shunt path An indicator that interrupts the amount of current flowing through the source when it is connected in parallel with the source. 如申請專利範圍第1項所述之保護電路，其中該偵測電路包含第二電晶體裝置，該第二電晶體裝置係連接為一電流鏡，適用於監測流經該第一電晶體裝置之部分電流。 The protection circuit of claim 1, wherein the detection circuit comprises a second transistor device connected to a current mirror for monitoring flow through the first transistor device. Part of the current. 如申請專利範圍第2項所述之保護電路，其中該比較器包含：一第一輸入端，係連接於該第二電晶體裝置；一第二輸入端，係連接於一參考電壓；以及一輸出端，用於提供一輸出信號，俾當該第一輸入端上的電壓超過該第二輸入端上的電壓時防止或限制電流流動。 The protection circuit of claim 2, wherein the comparator comprises: a first input terminal connected to the second transistor device; a second input terminal connected to a reference voltage; and a The output terminal is configured to provide an output signal to prevent or limit current flow when the voltage on the first input exceeds the voltage on the second input terminal. 如申請專利範圍第2或3項所述之保護電路，其中該第二電晶體裝置的通道寬長比W/L為該第一電晶體裝置的通道寬長比W/L之預設分數。 The protection circuit of claim 2, wherein the channel width to length ratio W/L of the second transistor device is a preset fraction of a channel width to length ratio W/L of the first transistor device. 如申請專利範圍第4項所述之保護電路，其中該第二電晶體裝置的通道寬長比W/L為該第一電晶體裝置的通道寬長比W/L之1/1000。 The protection circuit of claim 4, wherein the channel width to length ratio W/L of the second transistor device is 1/1000 of the channel width to length ratio W/L of the first transistor device. 如申請專利範圍第1項所述之保護電路，其中該保護電路於該分流路徑並聯連接於該光源時為可操作的。 The protection circuit of claim 1, wherein the protection circuit is operable when the shunt path is connected in parallel to the light source. 如申請專利範圍第1項所述之保護電路，更包含開關陣列用以當該分流路徑並聯連接於該光源時以有選擇性地操作該保護電路。 The protection circuit of claim 1, further comprising a switch array for selectively operating the protection circuit when the shunt path is connected in parallel to the light source. 如申請專利範圍第7項所述之保護電路，其中該分流路徑於該開關陣列從一光源轉換為另一光源之前並聯連接於該光源陣列，且其中該分流路徑係在該開關陣列完成從該第一光源轉換為該第二光源之後被切斷連接。 The protection circuit of claim 7, wherein the shunt path is connected in parallel to the light source array before the switch array is converted from a light source to another light source, and wherein the shunt path is completed from the switch array The first light source is switched to the second light source and then disconnected. 如申請專利範圍第1項所述之保護電路，其中該分流路徑與該光源之並聯連接使得電流暫時地停止流經該光源，但通過該分流路徑，藉此令該電流可於該分流路徑中被監測。 The protection circuit of claim 1, wherein the shunt path is connected in parallel with the light source such that a current temporarily stops flowing through the light source but passes through the shunt path, thereby allowing the current to be in the shunt path. Being monitored. 如申請專利範圍第9項所述之保護電路，其中該光源形成用於控制含有至少第一和第二光源之光源陣列之驅動裝置的一部分，且其中當從一光源切換為另一光源時，該分流路徑與該光源陣列並聯聯接。 The protection circuit of claim 9, wherein the light source forms a portion of a driving device for controlling an array of light sources including at least first and second light sources, and wherein when switching from one light source to another light source, The shunt path is coupled in parallel with the array of light sources. 如申請專利範圍第8至10項中任一項所述之保護電路，其中該分流路徑係選擇性地並聯連接於該光源陣列，俾提供控制一光源之強度的PWM操作模式，而該電流係於該分流路徑並聯連接時受到監測。 The protection circuit according to any one of claims 8 to 10, wherein the shunt path is selectively connected in parallel to the light source array, and provides a PWM operation mode for controlling the intensity of a light source, and the current system It is monitored when the shunt paths are connected in parallel. 一種用於保護光源免於過電流的方法，該方法包含步驟：選擇性地使一分流路徑並聯連接於該光源，使得電流從該光源轉離，並且通過該分流路徑；偵測在該分流路徑中流動的電流量；以及決定在該分流路徑中流動之電流是否超過一預設門檻值，如果是，則當該分流路徑中斷並聯連接於該光源時防止或限制流經該光源之電流；其中偵測在該分流路徑中流動的電流量之該步驟包含：提供一電流源於該分流路徑中，該電流源具有第一電晶體裝置用以當該分流路徑並聯連接該光源時控制流經該分流路徑之電流，其中流經該分流路徑之電流量係為當該分流路徑中斷與該光源並聯連接時將流經該光源之電流量的指標。 A method for protecting a light source from overcurrent, the method comprising the steps of: selectively connecting a shunt path to the light source in parallel, causing current to be diverted from the light source, and passing through the shunt path; detecting the shunt path The amount of current flowing in the medium; and determining whether the current flowing in the shunt path exceeds a predetermined threshold value, and if so, preventing or limiting the current flowing through the light source when the shunt path is interrupted in parallel to the light source; The step of detecting the amount of current flowing in the shunt path includes: providing a current source in the shunt path, the current source having a first transistor device for controlling flow through the shunt path when the source is connected in parallel The current of the shunt path, wherein the amount of current flowing through the shunt path is an indicator of the amount of current that will flow through the source when the shunt path is interrupted in parallel with the source. 如申請專利範圍第12項所述之方法，其中該偵測步驟包含，提供一第二電晶體裝置，該第二電晶體裝置係連接為電流鏡，適用於監測流經該第一電晶體裝置之部分電流。 The method of claim 12, wherein the detecting step comprises: providing a second transistor device connected to the current mirror for monitoring the flow through the first transistor device Part of the current. 如申請專利範圍第13項所述之方法，其中該決定步驟包含：比較流經該第二電晶體裝置之部分電流與一參考電壓，並且提供一輸出信號以防止或限制電流流經該光源。 The method of claim 13, wherein the determining step comprises: comparing a portion of the current flowing through the second transistor device with a reference voltage, and providing an output signal to prevent or limit current flow through the source. 如申請專利範圍第13或14項所述之方法，其中該第二電晶體裝置的通道寬長比W/L為該第一電晶體裝置的通道寬長比W/L的預設分數。 The method of claim 13 or 14, wherein the channel width to length ratio W/L of the second transistor device is a preset fraction of the channel width to length ratio W/L of the first transistor device. 如申請專利範圍第15項所述之方法，其中該第二電晶體裝置的通道寬長比W/L為該第一電晶體裝置的通道寬長比W/L之1/1000。 The method of claim 15, wherein the channel width to length ratio W/L of the second transistor device is 1/1000 of the channel width to length ratio W/L of the first transistor device. 如申請專利範圍第12項所述之方法，其中該分流路徑與該光源之並聯連接使得電流暫時地停止流經該光源，但通過該分流路徑，藉此令該電流可於該分流路徑中被監測。 The method of claim 12, wherein the shunt path is connected in parallel with the light source such that current temporarily stops flowing through the light source but passes through the shunt path, thereby allowing the current to be in the shunt path monitor. 如申請專利範圍第17項所述之方法，其中該光源形成用於控制含有至少第一和第二光源之光源陣列之驅動裝置的一部分，並且更包含當從一光源切換為另一光源時使該分流路徑並聯連接於該光源陣列之步驟。 The method of claim 17, wherein the light source forms part of a driving device for controlling an array of light sources containing at least first and second light sources, and further comprises when switching from one light source to another The shunt path is connected in parallel to the step of the light source array. 如申請專利範圍第18項所述之方法，更包含步驟：在從一光源轉換為另一光源之前使該分流路徑並聯連接於該光源陣列，並且在完成從該第一光源轉換為該第二光源之後中斷該分流路徑。 The method of claim 18, further comprising the step of: connecting the shunt path to the array of light sources in parallel before converting from a light source to another source, and converting from the first source to the second The shunt path is interrupted after the light source. 如申請專利範圍第12項所述之方法，其中該分流路徑係選擇性地並聯連接於該光源陣列，俾提供控制光源的強度之PWM操作模式，其中電流係於當該分流路徑並聯連接時受到監測。The method of claim 12, wherein the shunt path is selectively connected in parallel to the array of light sources, and provides a PWM mode of operation for controlling the intensity of the light source, wherein the current is received when the shunt path is connected in parallel monitor.
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