TWI382539B - 薄膜電晶體基板及其製程 - Google Patents
薄膜電晶體基板及其製程 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 23
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- 229910052751 metal Inorganic materials 0.000 claims description 12
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- 239000003990 capacitor Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 8
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- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
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- 229910052732 germanium Inorganic materials 0.000 description 3
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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Description
本發明係關於一種薄膜電晶體基板及其製程。
液晶顯示面板通常包括一薄膜電晶體基板、一彩色濾光片基板及夾於該二基板之間之液晶層,其係藉由分別施加電壓至該二基板,控制其間液晶分子扭轉而實現光之通過或不通過,從而達到顯示之目的。傳統液晶顯示面板之液晶驅動方式為扭轉向列模式,然而其視角範圍比較窄,即,從不同角度觀測畫面時,將觀測到不同之顯示效果。
邊緣電場開關(FringeFieldSwitching,FFS)技術是基於傳統液晶顯示面板之視角狹小等問題而提出之解決方案,其與平面內開關(In-PlaneSwitching,IPS)廣視角技術不同之處在於,邊緣開關技術將藉由透明導電層形成之公共電極整體置於畫素電極上方或下方,從而獲得了高效之邊緣電場,提高了開口率,並減少了光洩漏。因此,邊緣電場開關技術具有更好之視角及對比度。
請參閱圖1,係一種先前技術薄膜電晶體基板之局部平面示意圖。該薄膜電晶體基板100包括複數平行間隔設置之掃描線117、複數平行間隔設置之資料線146、複數薄膜電晶體101、複數畫素電極135及一公共電極156。該複數資料線146與該複數掃描線117垂直絕緣相交。該薄膜電晶體101位於該掃描線117與該資料線146之相交處。該薄膜電晶體101之閘極116連接至該掃描線117,源極
144連接至該資料線146,汲極145連接至該畫素電極135。
請一併參閱圖2,其係該薄膜電晶體基板100沿II1-II1方向及II2-II2方向之剖面示意圖。該薄膜電晶體基板100包括一玻璃基底111。該掃描線117及該閘極116設置於該玻璃基底111之上表面。該掃描線117、該閘極116及該玻璃基底111之上表面設置有一閘極絕緣層121。該半導體通道層126對應該閘極116設置於該閘極絕緣層121之上表面,該畫素電極135鄰近該半導體通道層126設置於該閘極絕緣層121之上表面。該源極144及該汲極145對應該閘極116設置於該半導體層通道層126之上表面,且該汲極145覆蓋介於該半導體通道層126與該畫素電極135之間之閘極絕緣層121及該畫素電極135之一部份,該資料線146對應該掃描線117設置於該閘極絕緣層121之上表面。該鈍化層151覆蓋該資料線146、該閘極絕緣層121、該源極144、該汲極145及該畫素電極135。該公共電極156對應該資料線146及該畫素電極135設置於該鈍化層151之上表面。
請一併參閱圖3,其係該薄膜電晶體基板1OO之製造流程圖。該薄膜電晶體基板1OO之製程主要包括五道光罩,其主要步驟如下:
步驟S11:形成閘極及掃描線;
步驟S12:形成閘極絕緣層及半導體通道層;
步驟S13:形成畫素電極;
步驟S14:形成源極、汲極、資料線及溝槽;
步驟S15:形成鈍化層及公共電極;
惟,由上述製程得到之該薄膜電晶體基板100,其資料線146與公共電極156之間及畫素電極135與公共電極156之間均僅具有一鈍化層151,從而該資料線146與該公共電極156構成之電容及該畫素電極135與該公共電極156構成之電容之二極板間之厚度較薄,使該二電容之容值較大,故對該二電容充電需耗費較多電量且需較長之充電時間。
有鑑於此,提供一種耗電少且充電時間短之薄膜電晶體基板實為必要。
另,提供上述薄膜電晶體基板之製程亦為必要。
一種薄膜電晶體基板,其包括複數掃描線,複數與該掃描線設置於同一層之第一資料線,複數跨過該掃描線而連接該第一資料線之第二資料線,複數薄膜電晶體。該薄膜電晶體之閘極連接至該掃描線,源極連接至該第二資料線。
一種薄膜電晶體基板之製程,其包括如下步驟:提供一基底,於該基底上形成閘極、掃描線及第一資料線;於該基底上形成畫素電極;於該閘極、該掃描線、該第一資料線及該畫素電極上形成一閘極絕緣層;於該閘極絕緣層上依序形成一半導體導通層;於該半導體通道層上形成該源極、該汲極及該第二資料線;於該源極、該汲極及該第二資料線上形成一鈍化層;於該鈍化層上依序形成一公共
電極。
相較於先前技術,本發明薄膜電晶體基板及其製程於第一資料線與公共電極之間及畫素電極與公共電極之間均增加一閘極絕緣層,從而該第一資料線與該公共電極構成之電容之二極板間之厚度增加,使該電容之容值減小,故可縮短該電容之充電時間且可達到省電之效果。
請參閱圖4,係本發明薄膜電晶體基板第一實施方式之局部平面示意圖。該薄膜電晶體基板200包括複數掃描線217、複數第一資料線218、複數第二資料線256、複數薄膜電晶體201、複數畫素電極225、一公共電極266、複數第一通孔243及複數第二通孔245。
該複數掃描線217相互平行且間隔設置。該第一資料線218與該掃描線217相互垂直且設置於同一層,該第一資料線218於靠近該掃描線217處斷開使得其與該該掃描線217相互絕緣。該第二資料線256位於該掃描線217之正上方,且藉由二第一通孔243跨接位於該掃描線217二側之第一資料線218。該薄膜電晶體201之閘極216連接至該掃描線217,源極254連接至該第二資料線256,汲極255藉由該第二通孔245連接至該畫素電極225。該公共電極266覆蓋該掃描線217、該第一資料線218、該第二資料線256及該畫素電極225。
請一併參閱圖5,其係該薄膜電晶體基板200沿V1-V1方向及V2-V2方向之剖面示意圖。該薄膜電晶體基板200
包括一玻璃基底211。該二第一資料線218、該掃描線217、該閘極216及該畫素電極225設置於該玻璃基底211之上表面。該二第一資料線218位於該掃描線217兩側,該畫素電極225位於該閘極216之一側。該二第一資料線218、該掃描線217、該閘極216、該畫素電極225及該玻璃基底211之上表面設置有一閘極絕緣層231。該閘極絕緣層231對應該第一資料線218鄰近該掃描線217之二端部各形成一第一通孔243,對應該畫素電極225鄰近該汲極255之位置形成一第二通孔245。該半導體通道層236對應該閘極216設置於該閘極絕緣層231之上表面。該源極254及該汲極255對應該閘極216設置於該半導體層通道層236之上表面,且該汲極255覆蓋該第二通孔245及介於該半導體通道層236與該第二通孔之間之閘極絕緣層231,該第二資料線256覆蓋該二第一通孔243及介於該二第一通孔243之間之閘極絕緣層231。該鈍化層261覆蓋該閘極絕緣層231、該第二資料線256、該源極254及該汲極255。該公共電極266對應該第一資料線218、該第二資料線256及該畫素電極225設置於該鈍化層261之上表面。
請一併參閱圖6至圖18,圖6係該薄膜電晶體基板200之製造流程圖,圖7至圖18係該薄膜電晶體基板200之製程各步驟之側面結構示意圖。該薄膜電晶體基板200之製程主要包括六道光罩,具體步驟如下:
步驟S21:形成閘極、掃描線及第一資料線;
請一併參閱圖7及圖8,提供一玻璃基底211,於其上
依序形成一閘極金屬層213及一第一光阻層215。其中,該閘極金屬層213可以為一單層結構,亦可以為一多層結構,其材質可為鋁係金屬、鉬、鉻或銅。
提供一第一光罩(圖未示)對準該第一光阻層215進行曝光,再對曝光後之第一光阻層215進行顯影,從而形成一預定之光阻圖案。對該閘極金屬層213進行蝕刻,以去除未被該光阻圖案覆蓋之部份閘極金屬層213,移除該第一光阻層215,進而形成該閘極216、該掃描線217及該第一資料線218。其中,該閘極216連接至該掃描線217。該第一資料線218與該掃描線217相互垂直。
步驟S22:形成畫素電極;請參閱圖9及圖10,於該閘極216、該掃描線217及該第一資料線218上依序形成一第一透明導電層221及一第二光阻層223。提供一第二光罩(圖未示)對準該第二光阻層223進行曝光,再對曝光後之第二光阻層223進行顯影,從而形成一預定光阻圖案。對該第一透明導電層221進行蝕刻,以去除未被該光阻圖案覆蓋之部份透明導電層221,移除該第二光阻層223,進而形成該畫素電極225。
步驟S23:形成閘極絕緣層及半導體通道層;請參閱圖11及圖12,於該閘極216、該掃描線217、該第一資料線218及該畫素電極225上依序形成一閘極絕緣層231、一半導體層233及一第三光阻層235。其中,該閘極絕緣層231為一氮化矽(SiNx)薄膜,該半導體層233包括一位於該閘極絕緣層231上之非晶矽層2332及一位於
該非晶矽層上之重摻雜非晶矽層2331。
提供一第三光罩(圖未示)對準該第三光阻層235進行曝光,再對曝光後之第三光阻層235進行顯影,從而形成一預定之光阻圖案。對該半導體層233進行蝕刻,以去除未被該光阻圖案覆蓋之部份半導體層233,移除該第三光阻層235,進而形成該半導體通道層236。
步驟S24:形成第一通孔及第二通孔;請參閱圖13及圖14,於該閘極絕緣層231及該半導體通道層236上形成一第四光阻層241。提供一第四光罩(圖未示)對準該第四光阻層241進行曝光,再對曝光後之第四光阻層241進行顯影,從而形成一預定之光阻圖案。對該閘極絕緣層231進行蝕刻,以去除未被該光阻圖案覆蓋之部份閘極絕緣層231,進而形成該第一通孔243及該第二通孔245,移除該第四光阻層241,使得該第一資料線218及該畫素電極部份暴露於外。
步驟S25:形成源極、汲極、第二資料線及溝槽;請參閱圖15及圖16,於該閘極絕緣層231、該第一通孔243、該第二通孔245及該半導體通道層236上依序形成一源/汲極金屬層251及一第五光阻層253。提供一第五光罩(圖未示)對準該第五光阻層253進行曝光,再對曝光後之第五光阻層253進行顯影,從而形成一預定之光阻圖案。對該源/汲極金屬層251進行蝕刻,進而形成該源極254、該汲極255及該第二資料線256。進一步採用HCl(氯化氫)與SF6(六氟化硫)之混合氣體作為蝕刻氣體對該半導
體通道層236進行蝕刻,形成該溝槽257,移除該第五光阻層253。其中,該源極254連接至該第二資料線256,該第二資料線256藉由二第一通孔243跨接該第一資料線218,使得該第一資料線形成一条貫通該薄膜電極體極板200之資料線,該汲極255藉由該第二通孔245連接至該畫素電極225。
步驟S26:形成鈍化層及公共電極。
請參閱圖17及圖18,於該閘極絕緣層231、該源極254、該汲極255、該第二資料線256及該溝槽257上依序形成一鈍化層261、一第二透明導電層263及一第六光阻層265。提供一第六光罩(圖未示)對準該第六光阻層265進行曝光,再對曝光後之第六光阻層265進行顯影,從而形成一預定之光阻圖案。對該第二透明導電層263進行蝕刻,移除該第六光阻層265,進而形成該公共電極266。
相較於先前技術,本發明薄膜電晶體基板200及其製程中,於該第一資料線218與該公共電極266之間,及該畫素電極225與該公共電極266之間均增加一閘極絕緣層231,從而該第一資料線218與該公共電極266構成之電容之二極板間之厚度增加,亦使得該畫素電極225與該公共電極266構成之電容之二極板間之厚度增加,減小該二電容之容值,故可縮短該二電容之充電時間且可達到省電之效果。
請參閱圖19,係本發明薄膜電晶體基板第二實施方式之製程流程圖。該薄膜電晶體基板與第一實施方式電晶體
基板200大致相同,主要包括六道光罩,具體步驟如下:步驟S31:形成閘極、掃描線及第一資料線;步驟S32:形成畫素電極;步驟S33:形成閘極絕緣層、第一通孔及第二通孔;步驟S34:形成半導體通道層;步驟S35:形成源極、汲極、第二資料線及溝槽;步驟S36:形成鈍化層及公共電極。
其主要區別在於:於第三道光罩形成閘極絕緣層、第一通孔及第二通孔,於第四道光罩形成半導體通道層。
綜上所述,本發明確已符合發明專利之要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,本發明之範圍並不以上述實施方式為限,舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
薄膜電晶體基板‧‧‧200
薄膜電晶體‧‧‧201
閘極‧‧‧216
源極‧‧‧254
汲極‧‧‧255
掃描線‧‧‧217
第一資料線‧‧‧218
第二資料線‧‧‧256
畫素電極‧‧‧225
公共電極‧‧‧266
第一通孔‧‧‧243
第二通孔‧‧‧245
玻璃基底‧‧‧211
閘極金屬層‧‧‧213
第一光阻層‧‧‧215
第一透明導電層‧‧‧221
第二光阻層‧‧‧223
閘極絕緣層‧‧‧231
半導體層‧‧‧233
非晶矽層‧‧‧2331
重摻雜非晶矽層‧‧‧2332
第三光阻層‧‧‧235
半導體通道層‧‧‧236
第四光阻層‧‧‧241
源/汲極金屬層‧‧‧251
第五光阻層‧‧‧253
溝槽‧‧‧257
鈍化層‧‧‧261
第二透明導電層‧‧‧263
第六光阻層‧‧‧265
圖1係一種先前技術薄膜電晶體基板之局部平面示意圖。
圖2係圖1所示薄膜電晶體基板沿II1-II1方向及II2-II2方向之剖面示意圖。
圖3係圖1所示薄膜電晶體基板之製造流程圖。
圖4係本發明薄膜電晶體基板第一實施方式之局部平面示意圖。
圖5係圖4所示薄膜電晶體基板沿V1-V1方向及V2-V2方向之剖面示意圖。
圖6係圖4所示薄膜電晶體基板之製造流程圖。
圖7至圖18係圖4所示薄膜電晶體基板之製程各步驟之側面結構示意圖。
圖19係本發明薄膜電晶體基板第二實施方式之製造流程圖。
薄膜電晶體基板‧‧‧200
薄膜電晶體‧‧‧201
閘極‧‧‧216
源極‧‧‧254
汲極‧‧‧255
掃描線‧‧‧217
第一資料線‧‧‧218
第二資料線‧‧‧256
畫素電極‧‧‧225
公共電極‧‧‧266
第一通孔‧‧‧243
第二通孔‧‧‧245
Claims (17)
- 一種薄膜電晶體基板,其包括:複數掃描線;複數第一資料線,其與該掃描線設置於同一層;複數第二資料線,其跨過該掃描線而連接該第一資料線;及複數薄膜電晶體,其閘極連接至該掃描線,源極連接至該第二資料線。
- 如申請專利範圍第1項所述之薄膜電晶體基板,其進一步包括複數第一通孔,該第一資料線與該掃描線相互垂直且於靠近該掃描線處斷開,該第二資料線藉由二第一通孔跨接位於該掃描線二側之第一資料線。
- 如申請專利範圍第2項所述之薄膜電晶體基板,其進一步包括複數畫素電極,該畫素電極與該掃描線設置於同一層。
- 如申請專利範圍第3項所述之薄膜電晶體基板,其進一步包括複數第二通孔,該薄膜電晶體之汲極藉由該第二通孔連接至該畫素電極。
- 如申請專利範圍第4項所述之薄膜電晶體基板,其進一步包括一公共電極,其覆蓋該掃描線、該第一資料線、該第二資料線及該畫素電極。
- 如申請專利範圍第4項所述之薄膜電晶體基板,其中,該第一通孔及該第二通孔係同一光罩製程步驟中形成。
- 如申請專利範圍第5項所述之薄膜電晶體基板,其中,該畫素電極及該公共電極之材質均為透明導電層。
- 如申請專利範圍第1項所述之薄膜電晶體基板,其中,該第一資料線與該掃描線為相同材質。
- 一種薄膜電晶體基板之製程,其包括如下步驟:a.提供一基底,於該基底上形成一閘極、一掃描線及一第一資料線;b.於該基底上形成一畫素電極;c.於該閘極、該掃描線、該第一資料線及該畫素電極上形成一閘極絕緣層;於該閘極絕緣層上依序形成一半導體導通層;d.於該半導體通道層上形成一源極、一汲極及一第二資料線;e.於該源極、該汲極及該第二資料線上形成一鈍化層;於該鈍化層上形成一公共電極層。
- 如申請專利範圍第9項所述之薄膜電晶體基板之製程,其中,該步驟c中進一步包括形成貫穿該閘極絕緣層之複數第一通孔及複數第二通孔,該第一通孔對應該第二資料線,該第二通孔對應該薄膜晶體管之汲極。
- 如申請專利範圍第10項所述之薄膜電晶體基板之製程,其中,該第一通孔及該第二通孔係同一光罩製程步驟中形成。
- 如申請專利範圍第11項所述之薄膜電晶體基板之製 程,其中,該步驟c具體如下:於該閘極、該掃描線、該第一資料線及該畫素電極上依序形成一閘極絕緣層、一半導體層及一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該半導體層進行蝕刻,移除該光阻層,進而形成該半導體通道層;於該閘極絕緣層及該半導體通道層上形成另一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該閘極絕緣層進行蝕刻,移除該光阻層,進而形成該第一通孔及該第二通孔。
- 如申請專利範圍第11項所述之薄膜電晶體基板之製程,其中,該步驟c具體如下:於該閘極、該掃描線、該第一資料線及該畫素電極上依序形成一閘極絕緣層及一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該閘極絕緣層進行蝕刻,移除該光阻層,進而形成該第一通孔及該第二通孔;於該閘極絕緣層、該第一通孔及該第二通孔上依序形成一半導體層及另一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該半導體層進行蝕刻,移除該光阻層,進而形成該半導體通道層。
- 如申請專利範圍第9項所述之薄膜電晶體基板之製程,其中,該步驟a中,該閘極、該掃描線及該第一資 料線係同一光罩製程步驟中形成。
- 如申請專利範圍第14項所述之薄膜電晶體基板之製程,其中,該步驟a具體如下:於該基底上依序形成一閘極金屬層及一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該閘極金屬層進行蝕刻,移除該光阻層,進而形成該閘極、該掃描線及該第一資料線。
- 如申請專利範圍第9項所述之薄膜電晶體基板之製程,其中,該步驟d中,該源極、該汲極及該第二資料線係同一光罩製程步驟中形成。
- 如申請專利範圍第16項所述之薄膜電晶體基板之製程,其中,該步驟d具體如下:於該閘極絕緣層、該第一通孔、該第二通孔及該半導體通道層上依序形成一源/汲極金屬層及一光阻層,提供一光罩對準該光阻層進行曝光,再對該光阻層進行顯影,從而形成一預定之光阻圖案,對該源/汲極金屬層進行蝕刻,移除該光阻層,進而形成該源極、該汲極及該第二資料線。
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JP3133676B2 (ja) | 1996-06-25 | 2001-02-13 | 松下電器産業株式会社 | 液晶表示装置 |
KR100311214B1 (ko) | 1999-06-29 | 2001-11-02 | 박종섭 | 고개구율 및 고투과율 액정 표시 장치 |
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2008
- 2008-07-18 TW TW097127346A patent/TWI382539B/zh not_active IP Right Cessation
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2009
- 2009-07-20 US US12/460,489 patent/US8421078B2/en active Active
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US6512565B1 (en) * | 1998-05-29 | 2003-01-28 | Hyundai Display Technology Inc. | Homeotropic alignment liquid crystal display having multi-domain |
US6525798B1 (en) * | 1999-10-21 | 2003-02-25 | Matsushita Electric Industrial Co., Ltd. | Liquid crystal display unit |
US20010024246A1 (en) * | 2000-03-13 | 2001-09-27 | Song Jang-Kun | Liquid crystal display and a TFT panel applied thereto |
US20020018166A1 (en) * | 2000-07-05 | 2002-02-14 | Kimikazu Matsumoto | Liquid crystal display device and method of fabricating the same |
US6646707B2 (en) * | 2000-10-10 | 2003-11-11 | Boe-Hydis Technology Co., Ltd. | Fringe field switching mode LCD |
US20070153204A1 (en) * | 2005-12-29 | 2007-07-05 | Lg Philips Lcd Co., Ltd. | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
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TW201005945A (en) | 2010-02-01 |
US8421078B2 (en) | 2013-04-16 |
US20100012938A1 (en) | 2010-01-21 |
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