TWI381265B - A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit - Google Patents
A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit Download PDFInfo
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本發明係屬於類比晶片設計領域，其可提供一種具有啟動電路並可同時提供與溫度無關的參考電流及參考電壓之帶差參考電路，尤其是涉及啟動電路、參考電流電路及參考電壓電路等電路所構成，可以同時提供與溫度無關的參考電流與參考電壓，提高電路的應用廣度與競爭力；再者，利用啟動電路，該帶差參考電路可以在低電壓條件下操作，達到節省功率的效果者。The invention belongs to the field of analog wafer design, and can provide a difference reference circuit having a starting circuit and simultaneously providing a temperature-independent reference current and a reference voltage, in particular, a circuit such as a starting circuit, a reference current circuit and a reference voltage circuit. The composition can simultaneously provide reference current and reference voltage independent of temperature, improve the application breadth and competitiveness of the circuit; further, with the start circuit, the difference reference circuit can be operated under low voltage conditions to achieve power saving effect. By.
在類比電路範疇已廣泛使用電壓與電流參考電路，一個理想的參考電路應該和電源供應、溫度及製程參數無關。惟因溫度變化會大大影響半導體的物理特性，容易造成電路的工作點偏移，所以必須利用正負溫係數相互抵消的方式，來抑制溫度對電路的影響，這也是一個好的參考電路所必備的條件。Voltage and current reference circuits are widely used in the analog circuit category. An ideal reference circuit should be independent of power supply, temperature, and process parameters. However, temperature changes will greatly affect the physical properties of the semiconductor, and it is easy to cause the operating point of the circuit to shift. Therefore, it is necessary to use the method of canceling the positive and negative temperature coefficients to suppress the influence of temperature on the circuit. This is also a necessary reference circuit. condition.
第一圖所示為習知帶差參考電路的基本架構圖，其係由兩個電壓訊號所組合應用而成。第一個電壓訊號為雙載子接面電晶體的射基極電壓VEB ，其係為一種負溫度係數電壓；第二個電壓訊號為正溫度係數電壓VP ，其被放大K倍後與第一個電壓訊號相加，藉以達到溫度補償功能。The first figure shows the basic architecture of a conventional differential reference circuit, which is a combination of two voltage signals. The first voltage signal is the base voltage V EB of the bipolar junction transistor, which is a negative temperature coefficient voltage; the second voltage signal is the positive temperature coefficient voltage V P , which is amplified by K times and then The first voltage signal is added to achieve temperature compensation.
依第一圖之習知架構，曾經有人提出以PMOS輸入的運算放大器來開發低電壓帶差參考電路。第二圖所示為一種習知的低電壓帶差參考電路200，其包括金氧半埸效電晶體M201、M202、M203、雙極接面電晶體Q201、Q202、電阻R201、R202、R203、R204、R205、R206以及運算放大器A201。該電路可以產生穩定的參考電流I，流經電阻R206產生穩定的輸出參考電壓Vref_2 。惟因溫度的變化依然會影響到電阻R206的阻值變化，易造成輸出參考電壓的變動，因此仍需要進一步進行補償。再者，在單電源供應的條件下，使用具PMOS輸入的運算放大器會有直流偏壓偏低與溫度漂移的問題，會造成接地端偏壓電晶體無法操作在飽和區，而出現不正常運作的情形；解決之道可以改用具NMOS輸入的運算放大器，惟仍需要進一步進行偏壓的補償工作，以使運算放大器可以正常工作。至於應用方面，大部分的參考電路只能單獨提供參考電壓或參考電流，若能同時提供與溫度無關的參考電壓及參考電流，將可擴大該帶差參考電路的產業應用範圍。According to the conventional architecture of the first figure, it has been proposed to develop a low voltage band difference reference circuit with a PMOS input operational amplifier. The second figure shows a conventional low voltage band difference reference circuit 200, which includes a gold-oxygen semiconductor transistor M201, M202, M203, a bipolar junction transistor Q201, Q202, a resistor R201, a R202, a R203, R204, R205, R206 and operational amplifier A201. The circuit can generate a stable reference current I, flowing through the resistor R206 to produce a stable output reference voltage V ref_2 . However, the temperature change will still affect the resistance change of the resistor R206, which is easy to cause the fluctuation of the output reference voltage, so further compensation is needed. Furthermore, in the case of single-supply operation, the use of an op amp with a PMOS input has a problem of low DC bias and temperature drift, which causes the ground-biased transistor to be inoperable in the saturation region and malfunctions. The solution can be changed to an NMOS input op amp, but further bias compensation is still needed to make the op amp work properly. As for the application, most of the reference circuits can only provide the reference voltage or the reference current separately. If the temperature-independent reference voltage and reference current can be provided at the same time, the industrial application range of the difference reference circuit can be expanded.
本發明的目的係在於：提供一種與溫度無關的參考電路，特別係關於啟動電路、參考電流電路及參考電壓電路所構成，可以同時輸出與溫度無關的參考電流與參考電壓，提高其產業利用性；並可透過啟動電路在低電壓條件下操作，達到節省功率的效果者。The object of the present invention is to provide a temperature-independent reference circuit, in particular to a start-up circuit, a reference current circuit and a reference voltage circuit, which can simultaneously output a reference current and a reference voltage independent of temperature, thereby improving industrial utilization. And can be operated under low voltage conditions through the startup circuit to achieve power saving effect.
本發明的目的又在於：使用含有三個電晶體元件的啟動(start-up)電路，當所有的電晶體流過的電流為零時，該三個電晶體處於關閉狀態；待加入電源電壓時，該啟動電路能於低電壓(小於1.5伏特)條件下啟動帶差參考電路，並於完成啟動工作後進入截止狀態，不會影響到帶差參考電路的正常操作。A further object of the invention is to use a start-up circuit comprising three transistor elements, the three transistors being in a closed state when the current flowing through all of the transistors is zero; when the supply voltage is to be added The starting circuit can start the band difference reference circuit under the condition of low voltage (less than 1.5 volts), and enters the off state after completing the starting work, and does not affect the normal operation of the band difference reference circuit.
本發明的目的還在於：利用同時可以提供與溫度無關的參考電壓及參考電流的輸出，可以增加帶差參考電路的功能擴充性，達到擴大其產業利用性的效果者。Another object of the present invention is to increase the functional expandability of the difference reference circuit by utilizing the output of the reference voltage and the reference current which are independent of temperature, and to achieve an effect of expanding the industrial applicability.
為實現上述本發明的目的，並且根據如所實施和概括描述的相關優點，本發明提供了一種具有啟動電路並可同時提供與溫度無關的參考電流與參考電壓之帶差參考電路，其技術特徵在於：係為啟動電路、參考電流電路及參考電壓電路所構成；其中，所述的啟動電路，具有一第一P型金氧半場效電晶體(Mp)、一第二P型金氧半場效電晶體(Ms)與一第三N型金氧半場效電晶體(Mn)等之電性連接所組成；所述的參考電流電路，具有一第四P型金氧半場效電晶體(M1)、一第五P型金氧半場效電晶體(M2)、一第七P型金氧半場效電晶體(M4)、一N型差動輸入的運算放大器(N-type OPA)、一第一升壓電阻(Ra1)、一第二升壓電阻(Ra2)、一第四補償電阻(Rb1)、一第五補償電阻(Rb2)、一第七偏壓電阻(R2)、一第一雙極接面電晶體(Q1)及一第二雙極接面電晶體(Q2)等之電性連接所組成；所述的參考電壓電路，具有一第六P型金氧半場效電晶體(M3)、一N型差動輸入的運算放大器(N-type OPA)、一第一升壓電阻(Ra1)、一第二升壓電阻(Ra2)、一第三升壓電阻(Ra3)、一第四補償電阻(Rb1)、一第五補償電阻(Rb2)、一第六補償電阻(Rb3)、一第七電阻(R2)、一第一雙極接面電晶體(Q1)、一第二雙極接面電晶體(Q2)及一第三雙極接面電晶體(Q3)等之電性連接所組成。To achieve the above objects of the present invention, and in accordance with the related advantages as embodied and generally described, the present invention provides a band difference reference circuit having a start-up circuit and simultaneously providing a temperature-independent reference current and a reference voltage, the technical characteristics of which are The invention is composed of a starting circuit, a reference current circuit and a reference voltage circuit; wherein the starting circuit has a first P-type MOS field effect transistor (Mp) and a second P-type MOS half-field effect The transistor (Ms) is electrically connected with a third N-type gold-oxygen half field effect transistor (Mn) or the like; the reference current circuit has a fourth P-type gold-oxygen half field effect transistor (M1) , a fifth P-type gold-oxygen half-field effect transistor (M2), a seventh P-type gold-oxygen half-field effect transistor (M4), an N-type differential input operational amplifier (N-type OPA), a first Boosting resistor (Ra1), a second boosting resistor (Ra2), a fourth compensating resistor (Rb1), a fifth compensating resistor (Rb2), a seventh biasing resistor (R2), and a first bipolar The electrical connection between the junction transistor (Q1) and a second bipolar junction transistor (Q2); the reference electricity The circuit has a sixth P-type MOS field-effect transistor (M3), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), and a second boost resistor (Ra2), a third boosting resistor (Ra3), a fourth compensating resistor (Rb1), a fifth compensating resistor (Rb2), a sixth compensating resistor (Rb3), a seventh resistor (R2), and a The first bipolar junction transistor (Q1), a second bipolar junction transistor (Q2) and a third bipolar junction transistor (Q3) are electrically connected.
另，本發明所述之一種具有啟動電路並可同時提供與溫度無關的參考電流與參考電壓之帶差參考電路，其中該帶差參考電壓電路中所設置之第一升壓電阻(Ra1)與第二升壓電阻(Ra2)係用以提升該N型差動輸入的運算放大器之正負極的偏壓電位。In addition, the present invention has a start-up circuit and can simultaneously provide a temperature-independent reference current and a reference voltage difference reference circuit, wherein the first boost resistor (Ra1) and the set voltage difference circuit are provided. The second boosting resistor (Ra2) is used to boost the bias potential of the positive and negative terminals of the operational amplifier of the N-type differential input.
又，所述之參考電流電路之第二雙極接面電晶體(Q2)的射基極電壓(VBE2 )具有負電壓溫度係數特性，而使第五補償電阻(Rb2)具有負電流溫度係數；第一雙極接面電晶體(Q1)與第二雙極接面電晶體(Q2)的射基極電壓差(ΔVBE )具有正電壓溫度係數，使得流經第七偏壓電阻(R2)的電流具有正電流溫度係數，其可與第五補償電阻(Rb2)之負電流溫度係數互相抵消，形成與溫度無關的參考電流，經由第四P型金氧半場效電晶體(M1)、第五P型金氧半場效電晶體(M2)與第七P型金氧半場效電晶體(M4)所組成的電流鏡輸出參考電流，如此即可得到與溫度無關的參考電流(Iref )。Moreover, the base voltage (V BE2 ) of the second bipolar junction transistor (Q2) of the reference current circuit has a negative voltage temperature coefficient characteristic, and the fifth compensation resistor (Rb2) has a negative current temperature coefficient. The base voltage difference (ΔV BE ) of the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2) has a positive voltage temperature coefficient such that it flows through the seventh bias resistor (R2) The current has a positive current temperature coefficient, which can cancel out the negative current temperature coefficient of the fifth compensation resistor (Rb2) to form a temperature-independent reference current, via the fourth P-type gold-oxygen half-field effect transistor (M1), A current mirror outputting a reference current composed of a fifth P-type gold-oxygen half-field effect transistor (M2) and a seventh P-type gold-oxygen half-field effect transistor (M4), thereby obtaining a temperature-independent reference current (I ref ) .
再，所述之參考電壓電路的第六P型金氧半場效電晶體(M3)可以藉由電流鏡效應而能提供與溫度無關的參考電流；由於第三雙極接面電晶體(Q3)的射基極電壓(VBE )具有負電壓溫度係數特性，加入第三升壓電阻(Ra3)所具有的正電壓溫度係數，如此可以補償第三雙極接面電晶體(Q3)的射基極電壓(VBE )之負電壓溫度係數，得到與溫度無關的參考電壓(Vref )。Furthermore, the sixth P-type metal oxide half field effect transistor (M3) of the reference voltage circuit can provide a temperature-independent reference current by a current mirror effect; due to the third bipolar junction transistor (Q3) The base voltage (V BE ) has a negative voltage temperature coefficient characteristic, and a positive voltage temperature coefficient of the third boosting resistor (Ra3) is added, so that the base of the third bipolar junction transistor (Q3) can be compensated. The negative voltage temperature coefficient of the pole voltage (V BE ) gives a temperature-independent reference voltage (V ref ).
另外，所述之第一升壓電阻(Ra1)、第二升壓電阻(Ra2)、第三升壓電阻(Ra3)、第四補償電阻(Rb1)、第五補償電阻(Rb2)與第六補償電阻(Rb3)係由N型井(N-well)所製成，具有較高的溫度係數；而第七偏壓電阻(R2)則由N型擴散區域(n+ -diffusion)所製成，具有較低的溫度係數。In addition, the first boosting resistor (Ra1), the second boosting resistor (Ra2), the third boosting resistor (Ra3), the fourth compensating resistor (Rb1), the fifth compensating resistor (Rb2), and the sixth The compensation resistor (Rb3) is made of N-well and has a high temperature coefficient; and the seventh bias resistor (R2) is made of N-type diffusion region (n + -diffusion). , has a lower temperature coefficient.
以下茲將本發明為達成其發明目的之整體構造、設計，配合附圖及實施例，作進一步詳細說明如下：首先請參閱第三圖所示，係本發明之具有啟動電路並可同時提供與溫度無關的參考電流與參考電壓之帶差參考電路300，其特徵在於：係為啟動(start-up)電路1、參考電流電路2及參考電壓電路3所構成，可在低電壓(小於1.5伏特)條件下工作，達到節省功率的效果；其中，所述的啟動電路(請參考第三圖)，含有三個電晶體元件，分別為第一P型金氧半場效電晶體(Mp)、第二P型金氧半場效電晶體(Ms)與第三N型金氧半場效電晶體(Mn)；其中，該第一P型金氧半場效電晶體(Mp)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極電性耦接至該N型差動輸入的運算放大器之輸出端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則電性耦接至第二P型金氧半場效電晶體(Ms)之第一閘極端；該第二P型金氧半場效電晶體(Ms)包括一第一閘極、一第二源極、一第三汲極與一第四基底，該第一閘極電性耦接至該第一P型金氧半場效電晶體(Mp)之第三汲極端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則電性耦接至N型差動輸入的運算放大器(N-type OPA)之負極輸入端(Vin-)；該第三N型金氧半場效電晶體(Mn)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極、第二源極與第四基底(Body)同時電性耦接至電源的接地端(VSS )，而該第三汲極則電性耦接至第一P型金氧半場效電晶體(Mp)之第三汲極端。The overall structure and design of the present invention for achieving the object of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. First, referring to the third figure, the present invention has a start-up circuit and can simultaneously provide The temperature-independent reference current and reference voltage difference reference circuit 300 is characterized in that it is composed of a start-up circuit 1, a reference current circuit 2 and a reference voltage circuit 3, and can be at a low voltage (less than 1.5 volts). Working under conditions to achieve power saving effect; wherein the starting circuit (please refer to the third figure), comprising three transistor components, respectively being the first P-type gold-oxygen half field effect transistor (Mp), a second P-type gold oxide half field effect transistor (Ms) and a third N-type gold oxide half field effect transistor (Mn); wherein the first P-type gold-oxygen half field effect transistor (Mp) comprises a first gate, a second source, a third drain, and a fourth body. The first gate is electrically coupled to an output of the N-type differential input operational amplifier, the second source and the second four substrate electrically coupled to the positive terminal of the power supply (V DD), and the third drain is electrically Connected to a first gate terminal of a second P-type MOS field-effect transistor (Ms); the second P-type MOS field-effect transistor (Ms) includes a first gate, a second source, and a first a third gate and a fourth substrate, the first gate is electrically coupled to the third drain terminal of the first P-type MOS field-effect transistor (Mp), and the second source and the fourth substrate are electrically connected Coupling to the positive terminal (V DD ) of the power supply, and the third drain is electrically coupled to the negative input terminal (Vin-) of the N-type differential input operational amplifier (N-type OPA); The N-type MOS field-effect transistor (Mn) includes a first gate, a second source, a third drain and a fourth substrate. The first gate, the second source and the first The fourth body is electrically coupled to the ground terminal (V SS ) of the power source, and the third drain is electrically coupled to the third terminal of the first P-type metal oxide half field effect transistor (Mp). .
請同時參考第三圖、第四圖與第五圖，當該帶差參考電路處於無電源狀態時，所有的電晶體進入關閉狀態，使得電晶體所流過的電流為零；而當電源電壓VDD 逐漸升高時(請參考第四圖)，因為該第一P型金氧半場效電晶體(Mp)與第三N型金氧半場效電晶體(Mn)操作於三汲區(Triode region)，使得該第二P型金氧半場效電晶體(Ms)之閘極端的電位約為電源電壓(VDD )的一半；而當該第二P型金氧半場效電晶體(Ms)的閘極電壓(VMS,G )迅速提高時，該第二P型金氧半場效電晶體(Ms)立即進入導通狀態，源極電流IMS 快速提高(請參考第五圖)，流經該N型差動輸入的運算放大器(N-type OPA)下方的第一升壓電阻(Ra1)與第四補償電阻(Rb1)，使得該N型差動輸入的運算放大器(N-type OPA)之輸入電壓開始啟動，同時在該N型差動輸入的運算放大器(N-type OPA)的輸出端(VOPA,out )產生電壓輸出，進而啟動第四P型金氧半場效電晶體(M1)、第五P型金氧半場效電晶體(M2)、第六P型金氧半場效電晶體(M3)與第七P型金氧半場效電晶體(M4)。在啟動工作完成後，該第二P型金氧半場效電晶體(Ms)的閘極電壓(VMS,G )持續上升，導致第二P型金氧半場效電晶體(Ms)進入截止狀態，源極電流IMS 下降至零；此時，第一P型金氧半場效電晶體(Mp)操作於三汲區，其功能近似電阻，因而使得第二P型金氧半場效電晶體(Ms)的閘極電壓(VMS,G )會隨著電源電壓VDD 的上升而同步上升，促使第一P型金氧半場效電晶體(Mp)瞬間進入截止狀態，啟動電路與主電路分離而不會影響到帶差參考電路的正常操作。Please refer to the third diagram, the fourth diagram and the fifth diagram at the same time. When the strap difference reference circuit is in the no-power state, all the transistors enter the off state, so that the current flowing through the transistor is zero; and when the power supply voltage When V DD is gradually increased (please refer to the fourth figure), because the first P-type gold oxide half field effect transistor (Mp) and the third N-type gold oxide half field effect transistor (Mn) are operated in the triode region (Triode) The potential of the gate terminal of the second P-type metal oxide half field effect transistor (Ms) is about half of the power supply voltage (V DD ); and when the second P-type gold oxide half field effect transistor (Ms) When the gate voltage (V MS, G ) is rapidly increased, the second P-type MOS field-effect transistor (Ms) immediately enters a conducting state, and the source current I MS is rapidly increased (refer to FIG. 5), flowing through The first boosting resistor (Ra1) and the fourth compensating resistor (Rb1) under the N-type differential input operational amplifier (N-type OPA) make the N-type differential input operational amplifier (N-type OPA) the input voltage is started, while producing an output voltage at an output terminal of the N-type differential input operational amplifier (N-type OPA) of (V OPA, out), and further a first start P-type gold-oxygen half field effect transistor (M1), fifth P-type gold-oxygen half-field effect transistor (M2), sixth P-type gold-oxygen half-field effect transistor (M3) and seventh P-type gold-oxygen half-field effect transistor (M4). After the startup work is completed, the gate voltage (V MS, G ) of the second P-type MOS field-effect transistor (Ms) continues to rise, causing the second P-type MOS field-effect transistor (Ms) to enter an off state. The source current I MS drops to zero; at this time, the first P-type gold-oxygen half-field effect transistor (Mp) operates in the three-turn region, and its function approximates resistance, thus making the second P-type gold-oxygen half-field effect transistor ( The gate voltage (V MS, G ) of Ms) rises synchronously with the rise of the power supply voltage V DD , prompting the first P-type gold-oxygen half-field effect transistor (Mp) to enter the off state instantaneously, and the startup circuit is separated from the main circuit. It does not affect the normal operation of the differential reference circuit.
所述的參考電流電路(請再參考第三圖)，具有一第四P型金氧半場效電晶體(M1)、一第五P型金氧半場效電晶體(M2)、一第七P型金氧半場效電晶體(M4)、一N型差動輸入的運算放大器(N-type OPA)、一第一升壓電阻(Ra1)、一第二升壓電阻(Ra2)、一第四補償電阻(Rb1)、一第五補償電阻(Rb2)、一第七偏壓電阻(R2)、一第一雙極接面電晶體(Q1)及一第二雙極接面電晶體(Q2)等之電性連接而成，可以形成與溫度無關的參考電流(Iref )其中，該第四P型金氧半場效電晶體(M1)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極電性耦接至該N型差動輸入的運算放大器之輸出端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則同時電性耦接至第二P型金氧半場效電晶體(Ms)之第三汲極端及該N型差動輸入的運算放大器之負極輸入端(Vin-)；該第五P型金氧半場效電晶體(M2)包括一第一閘極、一第二源極、一第三汲極與一第四基底，該第一閘極電性耦接至該N型差動輸入的運算放大器(N-type OPA)之輸出端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則電性耦接至該N型差動輸入的運算放大器(N-type OPA)之正極輸入端(Vin+)；該第七P型金氧半場效電晶體(M4)包括一第一閘極、一第二源極、一第三汲極與一第四基底，該第一閘極電性耦接至該N型差動輸入的運算放大器之輸出端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則電性耦接至該參考電流電路的輸出端(Iref )；該N型差動輸入的運算放大器(N-type OPA)包括負極輸入端(Vin-)、正極輸入端(Vin+)與輸出端(VOPA,out )等端點，該負極輸入端(Vin-)同時電性耦接到第二P型金氧半場效電晶體(Ms)之第三汲極端、該第四P型金氧半場效電晶體(M1)之第三汲極端與第一升壓電阻(Ra1)之第一端，該正極輸入端(Vin+)同時電性耦接到第五P型金氧半場效電晶體(M2)之第三汲極端與第二升壓電阻(Ra2)之第一端，而該輸出端(VOPA,out )則同時電性耦接至第一(Mp)、第四(M1)、第五(M2)與第七(M4)P型金氧半場效電晶體之第一閘極端；該第一升壓電阻(Ra1)包括第一端與第二端，該第一端係電性耦接到該N型差動輸入的運算放大器之負極輸入端(Vin-)，而該第二端則同時電性耦接到第四補償電阻(Rb1)的第一端與第一雙極接面電晶體(Q1)之第二射極端；該第二升壓電阻(Ra2)包括第一端與第二端，該第一端係電性耦接到該N型差動輸入的運算放大器之正極輸入端(Vin+)，而該第二端則同時電性耦接到第五補償電阻(Rb2)的第一端與第七偏壓電阻(R2)之第一端；該第四補償電阻(Rb1)包括第一端與第二端，該第一端係同時電性耦接到該第一升壓電阻(Ra1)的第二端與該第一雙極接面電晶體(Q1)之第二射極端，而該第二端則接地；該第五補償電阻(Rb2)包括第一端與第二端，該第一端係同時電性耦接到該第二升壓電阻(Ra2)的第二端與該第七偏壓電阻(R2)的第一端，而該第二端則接地；該第七偏壓電阻(R2)包括第一端與第二端，該第一端係同時電性耦接到該第二升壓電阻(Ra2)的第二端與該第五補償電阻(Rb2)之第一端，而該第二端則電性耦接到第二雙極接面電晶體(Q2)之第二射極端；該第一雙極接面電晶體(Q1)包括一第一基極(Base)、一第二射極(Emitter)與一第三集極(Collector)，該第一基極同時電性耦接到第二雙極接面電晶體(Q2)的第一基極及接地端，該第二射極同時電性耦接到第一升壓電阻(Ra1)的第二端與該第四補償電阻(Rb1)之第一端，而該第三集極則接地；該第二雙極接面電晶體(Q2)包括一第一基極(Base)、一第二射極(Emitter)與一第三集極(Collector)，該第一基極同時電性耦接到第一雙極接面電晶體(Q1)的第一基極及接地端，該第二射極電性耦接到第七偏壓電阻(R2)的第二端，而該第三集極則接地。The reference current circuit (please refer to the third figure) has a fourth P-type MOS field effect transistor (M1), a fifth P-type MOS field-effect transistor (M2), and a seventh P Type MOS half-field effect transistor (M4), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), a second boost resistor (Ra2), and a fourth Compensation resistor (Rb1), a fifth compensation resistor (Rb2), a seventh bias resistor (R2), a first bipolar junction transistor (Q1), and a second bipolar junction transistor (Q2) And electrically connected to form a temperature-independent reference current (I ref ), wherein the fourth P-type MOS field-effect transistor (M1) includes a first gate, a second source, and a a third drain is electrically coupled to the output of the operational amplifier of the N-type differential input, and the second source is electrically coupled to the fourth substrate The positive terminal (V DD ) of the power supply, and the third drain is electrically coupled to the third terminal of the second P-type MOS field-effect transistor (Ms) and the operational amplifier of the N-type differential input The negative input terminal (Vin-); the fifth P type The oxygen half field effect transistor (M2) includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the N-type differential input operation An output of the amplifier (N-type OPA), the second source and the fourth substrate are electrically coupled to the positive terminal (V DD ) of the power source, and the third drain is electrically coupled to the N-type difference a positive input terminal (Vin+) of an operationally input operational amplifier (N-type OPA); the seventh P-type MOS half-effect transistor (M4) includes a first gate, a second source, and a third 汲The first gate is electrically coupled to the output of the operational amplifier of the N-type differential input, and the second source and the fourth substrate are electrically coupled to the positive terminal of the power supply (V) DD ), the third drain is electrically coupled to the output of the reference current circuit (I ref ); the N-type differential input operational amplifier (N-type OPA) includes a negative input (Vin-) The positive input terminal (Vin+) and the output terminal (V OPA, out ) and the like, the negative input terminal (Vin-) is simultaneously electrically coupled to the third P-type metal oxide half field effect transistor (Ms)汲 extreme, the fourth P-type gold oxygen half-field effect The third terminal of the transistor (M1) is connected to the first end of the first boosting resistor (Ra1), and the positive input terminal (Vin+) is simultaneously electrically coupled to the fifth P-type gold-oxygen half field effect transistor (M2). The third terminal is connected to the first end of the second boosting resistor (Ra2), and the output terminal (V OPA, out ) is electrically coupled to the first (Mp), the fourth (M1), and the fifth a first gate terminal of the (M2) and the seventh (M4) P-type metal oxide half field effect transistor; the first boosting resistor (Ra1) includes a first end and a second end, the first end is electrically coupled a negative input terminal (Vin-) of the N-type differential input operational amplifier, and the second end is electrically coupled to the first end of the fourth compensation resistor (Rb1) and the first bipolar junction a second emitter terminal of the crystal (Q1); the second boost resistor (Ra2) includes a first end and a second end, the first end is electrically coupled to the positive input of the operational amplifier of the N-type differential input a terminal (Vin+), wherein the second end is electrically coupled to the first end of the fifth compensating resistor (Rb2) and the first end of the seventh bias resistor (R2); the fourth compensating resistor (Rb1) The first end and the second end are included, and the first end is electrically coupled at the same time a second end of the first boosting resistor (Ra1) and a second emitter of the first bipolar junction transistor (Q1), and the second end is grounded; the fifth compensation resistor (Rb2) includes the first And the second end, the first end is electrically coupled to the second end of the second boosting resistor (Ra2) and the first end of the seventh bias resistor (R2), and the second end The seventh bias resistor (R2) includes a first end and a second end, the first end is electrically coupled to the second end of the second boost resistor (Ra2) and the fifth compensation a first end of the resistor (Rb2), and the second end is electrically coupled to the second emitter end of the second bipolar junction transistor (Q2); the first bipolar junction transistor (Q1) includes a first base (Base), a second emitter (Emitter) and a third collector (Collector), the first base is electrically coupled to the second bipolar junction transistor (Q2) at the same time a first base and a ground end, the second emitter is electrically coupled to the second end of the first boosting resistor (Ra1) and the first end of the fourth compensation resistor (Rb1), and the third set Extremely grounded; the second bipolar junction transistor (Q2) includes a first base (Bas e), a second emitter (Emitter) and a third collector (collector), the first base is simultaneously electrically coupled to the first base of the first bipolar junction transistor (Q1) and grounded The second emitter is electrically coupled to the second end of the seventh bias resistor (R2), and the third collector is grounded.
所述的參考電壓電路，具有一第四P型金氧半場效電晶體(M1)、一第五P型金氧半場效電晶體(M2)、一第六P型金氧半場效電晶體(M3)、一N型差動輸入的運算放大器(N-type OPA)、一第一升壓電阻(Ra1)、一第二升壓電阻(Ra2)、一第三升壓電阻(Ra3)、一第四補償電阻(Rb1)、一第五補償電阻(Rb2)、一第六補償電阻(Rb3)、一第七偏壓電阻(R2)、一第一雙極接面電晶體(Q1)、一第二雙極接面電晶體(Q2)及一第三雙極接面電晶體(Q3)等之電性連接所組成；其中，該第四P型金氧半場效電晶體(M1)、第五P型金氧半場效電晶體(M2)、N型差動輸入的運算放大器(N-type OPA)、第一升壓電阻(Ra1)、第二升壓電阻(Ra2)、第四補償電阻(Rb1)、第五補償電阻(Rb2)、第七偏壓電阻(R2)、第一雙極接面電晶體(Q1)與第二雙極接面電晶體(Q2)等元件之電性連接方式如同參考電流電路之連接方式，不再贅述。而該第六P型金氧半場效電晶體(M3)包括一第一閘極、一第二源極、一第三汲極與一第四基底，該第一閘極電性耦接至該N型差動輸入的運算放大器之輸出端，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則電性耦接至該參考電壓電路的輸出端(Vref )；該第三升壓電阻(Ra3)包括第一端與第二端，該第一端係電性耦接到該參考電壓電路的輸出端(Vref )，而該第二端則同時電性耦接到第六補償電阻(Rb3)的第一端與第三雙極接面電晶體(Q3)之第二射極端；該第六補償電阻(Rb3)包括第一端與第二端，該第一端係同時電性耦接到該第三升壓電阻(Ra3)的第二端與該第三雙極接面電晶體(Q3)之第二射極端，而該第二端則接地；該第三雙極接面電晶體(Q3)包括一第一基極(Base)、一第二射極(Emitter)與一第三集極(Collector)，該第一基極接地，該第二射極同時電性耦接到第三升壓電阻(Ra3)的第二端與第六補償電阻(Rb3)之第一端，而該第三集極則接地。The reference voltage circuit has a fourth P-type gold-oxygen half field effect transistor (M1), a fifth P-type gold-oxygen half-field effect transistor (M2), and a sixth P-type gold-oxygen half-field effect transistor ( M3), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), a second boost resistor (Ra2), a third boost resistor (Ra3), and a a fourth compensation resistor (Rb1), a fifth compensation resistor (Rb2), a sixth compensation resistor (Rb3), a seventh bias resistor (R2), a first bipolar junction transistor (Q1), a The second bipolar junction transistor (Q2) and a third bipolar junction transistor (Q3) are electrically connected; wherein the fourth P-type gold oxide half field effect transistor (M1), Five P-type gold-oxygen half-field effect transistor (M2), N-type differential input operational amplifier (N-type OPA), first boost resistor (Ra1), second boost resistor (Ra2), fourth compensation resistor Electrical connection between (Rb1), fifth compensation resistor (Rb2), seventh bias resistor (R2), first bipolar junction transistor (Q1) and second bipolar junction transistor (Q2) The method is the same as the connection method of the reference current circuit, and will not be described again. The sixth P-type MOS field-effect transistor (M3) includes a first gate, a second source, a third drain, and a fourth substrate. The first gate is electrically coupled to the first gate. An output terminal of the N-type differential input operational amplifier, the second source and the fourth substrate are electrically coupled to the positive terminal (V DD ) of the power supply, and the third drain is electrically coupled to the reference voltage An output terminal (V ref ) of the circuit; the third boosting resistor (Ra3) includes a first end and a second end, the first end being electrically coupled to the output end (V ref ) of the reference voltage circuit, and The second end is electrically coupled to the first end of the sixth compensating resistor (Rb3) and the second end of the third bipolar junction transistor (Q3); the sixth compensating resistor (Rb3) includes One end and a second end, the first end is electrically coupled to the second end of the third boosting resistor (Ra3) and the second emitter of the third bipolar junction transistor (Q3), The second end is grounded; the third bipolar junction transistor (Q3) includes a first base (Base), a second emitter (Emitter) and a third collector (Collector). a base is grounded, and the second emitter is simultaneously electrically To a third boost resistor (Ra3,) the second end of the sixth compensating resistors (Rb3) of a first end, and the third set of electrodes is grounded.
所設置之第一升壓電阻(Ra1)與第二升壓電阻(Ra2)係用以提升該N型差動輸入的運算放大器(N-type OPA)之偏壓電位，而第三升壓電阻(Ra3)係用以補償第三雙極接面電晶體(Q3)的射基極電壓。也就是說，該第一雙極接面電晶體(Q1)、第二雙極接面電晶體(Q2)及第三雙極接面電晶體(Q3)的射基極電壓均具有負電壓溫度係數特性，因而造成流經第四補償電阻(Rb1)、第五補償電阻(Rb2)與第六補償電阻(Rb3)的電流均具有負電流溫度係數，配合流經第七偏壓電阻之正電流溫度係數(係由第一雙極接面電晶體(Q1)與第二雙極接面電晶體(Q2)之射基極電位差所產生的正電壓溫度係數)，即可得到與溫度變化無關的參考電流。再者，由於流經第三升壓電阻(Ra3)的電流為與溫度變化無關的參考電流，使得第三升壓電阻(Ra3)的跨壓呈現正電壓溫度係數，可以用來補償第三雙極接面電晶體(Q3)之射基極電壓的負電壓溫度係數，進而得到與溫度變化無關的參考電壓(Vref )。請參考第六圖，在未加入補償電阻(Rb系列)時，其輸出參考電壓對溫度變化的變異性相當大(補償前的輸出參考電壓)；而在加入補償電阻後，明顯使得輸出參考電壓對溫度變化量所產生的變化下降(補償後的輸出參考電壓)，達到補償效果。並請參考第七圖，其係本電路製作成晶片後所實測得到的輸出參考電壓對溫度變化所產生的輸出結果；在溫度範圍介於0℃~100℃間，其帶差參考電壓的平均輸出值約為0.8886伏特(V)，而其輸出參考電壓因溫度變化所產生的最大變異值為4.35微伏特(mV)；若溫度範圍介於30℃~100℃間，則其帶差參考電壓的平均輸出值約為0.88876伏特(V)，而其輸出電壓因溫度變化所產生的最大變異值為0.8微伏特(mV)，足見其輸出參考電壓已達穩定補償效果。第八圖所示為本電路晶片所實測得到的輸出參考電壓對電源供應電壓所產生的輸出結果，由該輸出結果可以得知，本帶差參考電路可於電源供應電壓為1.35伏特時啟動，即該帶差參考電路可以在低電壓條件下操作，達到節省功率的效果。第九圖所示為本電路晶片所實測得到的輸出參考電流(nA)對溫度變化(℃)所產生的電流輸出結果，由該輸出結果可以得知，本帶差參考電路的電流輸出相當穩定，己達到補償效果。The first boosting resistor (Ra1) and the second boosting resistor (Ra2) are used to boost the bias potential of the N-type differential input operational amplifier (N-type OPA), and the third boosting The resistor (Ra3) is used to compensate the base voltage of the third bipolar junction transistor (Q3). That is, the base voltages of the first bipolar junction transistor (Q1), the second bipolar junction transistor (Q2), and the third bipolar junction transistor (Q3) all have a negative voltage temperature. The coefficient characteristic causes the current flowing through the fourth compensation resistor (Rb1), the fifth compensation resistor (Rb2) and the sixth compensation resistor (Rb3) to have a negative current temperature coefficient, and a positive current flowing through the seventh bias resistor The temperature coefficient (the temperature coefficient of the positive voltage generated by the base potential difference between the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2)) can be obtained independently of the temperature change. Reference current. Furthermore, since the current flowing through the third boosting resistor (Ra3) is a reference current independent of the temperature change, the voltage across the third boosting resistor (Ra3) exhibits a positive voltage temperature coefficient, which can be used to compensate for the third double The negative voltage temperature coefficient of the base voltage of the pole junction transistor (Q3), thereby obtaining a reference voltage (V ref ) independent of the temperature change. Please refer to the sixth figure. When the compensation resistor (Rb series) is not added, the variability of the output reference voltage to the temperature change is quite large (the output reference voltage before compensation); and after the compensation resistor is added, the output reference voltage is obviously made. The change in the amount of temperature change is reduced (the compensated output reference voltage) to achieve the compensation effect. Please refer to the seventh figure, which is the output result of the measured reference voltage to temperature change after the circuit is fabricated into a wafer; the average of the difference reference voltage is between 0 °C and 100 °C in the temperature range. The output value is approximately 0.8886 volts (V), and the maximum variation of the output reference voltage due to temperature changes is 4.35 microvolts (mV); if the temperature range is between 30 ° C and 100 ° C, the differential reference voltage The average output value is about 0.88876 volts (V), and the maximum variation of the output voltage due to temperature changes is 0.8 microvolts (mV), which shows that the output reference voltage has reached a stable compensation effect. The eighth figure shows the output result of the output reference voltage measured by the circuit chip to the power supply voltage. It can be known from the output result that the difference reference circuit can be started when the power supply voltage is 1.35 volts. That is, the band difference reference circuit can be operated under low voltage conditions to achieve power saving effect. The ninth figure shows the current output result of the output reference current (nA) measured by the circuit chip and the temperature change (°C). It can be known from the output result that the current output of the band difference reference circuit is quite stable. , has achieved the compensation effect.
接著，請參考第十圖，係本發明所採用之具N型差動輸入的運算放大器(600)電路實現圖，係由鏡射(telescope)放大電路、輸出放大電路與補償電路所組成。該鏡射放大電路係由一第八P型金氧半場效電晶體(M601)、一第九P型金氧半場效電晶體(M602)、一第十N型金氧半場效電晶體(M603)、一第十一N型金氧半場效電晶體(M604)與一第十二N型金氧半場效電晶體(M605)等電晶體之電性連接所組成；其中，該第八P型金氧半場效電晶體(M601)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極同時電性耦接到該第九P型金氧半場效電晶體(M602)之第一閘極、該第八P型金氧半場效電晶體(M601)之第三汲極及該第十N型金氧半場效電晶體(M603)之第三汲極，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則同時電性耦接至該第八P型金氧半場效電晶體(M601)之第一閘極、該第九P型金氧半場效電晶體(M602)之第一閘極及該第十N型金氧半場效電晶體(M603)之第三汲極；該第九P型金氧半場效電晶體(M602)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極同時電性耦接到該第八P型金氧半場效電晶體(M601)之第一閘極與第三汲極及該第十N型金氧半場效電晶體(M603)之第三汲極，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則同時電性耦接至該第十一N型金氧半場效電晶體(M604)之第三汲極、該第十三P型金氧半場效電晶體(M606)之第一閘極及該第十五P型金氧半場效電晶體(M_Rc)之第二源極；該第十N型金氧半場效電晶體(M603)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極電性耦接到該第一升壓電阻(Ra1)的第一端(Vin-)，該第二源極與第四基底同時電性耦接到第十一N型金氧半場效電晶體(M604)之第二源極及該第十二N型金氧半場效電晶體(M605)之第三汲極，該第三汲極則電性耦接至第八P型金氧半場效電晶體(M601)的第一閘極與第三汲極；該第十一N型金氧半場效電晶體(M604)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極電性耦接到該第二升壓電阻(Ra2)的第一端(Vin+)，該第二源極與第四基底同時電性耦接到第十N型金氧半場效電晶體(M603)之第二源極及該第十二N型金氧半場效電晶體(M605)之第三汲極，該第三汲極則同時電性耦接至第九P型金氧半場效電晶體(M602)的第三汲極、第十五P型金氧半場效電晶體(M_Rc)的第二源極與第十三P型金氧半場效電晶體(M606)的第一閘極；該第十二N型金氧半場效電晶體(M605)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極同時電性耦接到該偏壓電壓(Vbias)與該第十四N型金氧半場效電晶體(M607)之第一閘極，該第二源極與第四基底同時電性耦接到接地端，該第三汲極則同時電性耦接至第十N型金氧半場效電晶體(M603)的第二源極與第十一N型金氧半場效電晶體(M604)的第二源極。Next, please refer to the tenth figure, which is a circuit implementation diagram of an operational amplifier (600) with an N-type differential input used in the present invention, which is composed of a telescope amplification circuit, an output amplification circuit and a compensation circuit. The mirror amplification circuit is composed of an eighth P-type gold-oxygen half field effect transistor (M601), a ninth P-type gold-oxygen half-field effect transistor (M602), and a tenth N-type gold-oxygen half-field effect transistor (M603). And an eleventh N-type gold oxide half field effect transistor (M604) and a twelfth N-type gold oxygen half field effect transistor (M605) and other isoelectric crystals; wherein the eighth P type The metal oxide half field effect transistor (M601) includes a first gate, a second source, a third drain and a fourth body. The first gate is electrically coupled to the ninth a first gate of a P-type gold oxide half field effect transistor (M602), a third gate of the eighth P-type gold-oxygen half field effect transistor (M601), and the tenth N-type gold oxide half field effect transistor (M603) a third drain, the second source and the fourth substrate are electrically coupled to the positive terminal (V DD ) of the power source, and the third drain is electrically coupled to the eighth P-type gold oxide The first gate of the half field effect transistor (M601), the first gate of the ninth P-type gold oxide half field effect transistor (M602), and the third of the tenth N-type gold oxide half field effect transistor (M603) Bungee pole; the ninth P-type gold oxide half field effect transistor (M602) includes a first gate, a second source, a third drain, and a fourth body, the first gate being electrically coupled to the eighth P-type MOS field-effect transistor (M601) The first gate and the third drain and the third drain of the tenth N-type MOS field-effect transistor (M603), the second source and the fourth substrate are electrically coupled to the positive terminal of the power source ( V DD ), and the third drain is electrically coupled to the third drain of the eleventh N-type metal oxide half field effect transistor (M604), the thirteenth P-type gold oxide half field effect transistor a first gate of (M606) and a second source of the fifteenth P-type MOS field-effect transistor (M_Rc); the tenth N-type MOS field-effect transistor (M603) includes a first gate a second source, a third drain, and a fourth body. The first gate is electrically coupled to the first end (Vin-) of the first boost resistor (Ra1). The second source and the fourth substrate are simultaneously electrically coupled to the second source of the eleventh N-type metal oxide half field effect transistor (M604) and the twelfth N-type gold oxide half field effect transistor (M605) a third drain, the third drain is electrically coupled to the eighth P-type metal oxide half field effect transistor a first gate and a third drain of (M601); the eleventh N-type metal oxide half field effect transistor (M604) includes a first gate, a second source, a third drain and a first a fourth body electrically coupled to the first end (Vin+) of the second boosting resistor (Ra2), the second source and the fourth substrate being electrically coupled to the tenth a second source of the N-type gold-oxygen half field effect transistor (M603) and a third drain of the twelfth N-type gold-oxygen half field effect transistor (M605), the third drain is electrically coupled to The third source of the ninth P-type gold oxide half field effect transistor (M602), the second source of the fifteenth P-type gold oxide half field effect transistor (M_Rc), and the thirteenth P-type gold oxide half field effect transistor a first gate of (M606); the twelfth N-type gold oxide half field effect transistor (M605) includes a first gate, a second source, a third drain, and a fourth substrate The first gate is electrically coupled to the bias voltage (Vbias) and the first gate of the fourteenth N-type MOS field-effect transistor (M607), the second source and the fourth substrate At the same time, it is electrically coupled to the grounding end, and the third drain is electrically coupled to the first The second source of the N-type metal-oxide-semiconductor field effect transistor (M603) and a second electrode of the source electrode of the eleventh N-type metal-oxide-semiconductor field effect transistor (M604) is.
該輸出放大電路係由一第十三P型金氧半場效電晶體(M606)與一第十四N型金氧半場效電晶體(M607)等電晶體之電性連接所組成；其中，該第十三P型金氧半場效電晶體(M606)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極同時電性耦接到該第九P型金氧半場效電晶體(M602)之第三汲極、該第十一N型金氧半場效電晶體(M604)之第三汲極及該第十五P型金氧半場效電晶體(M_Rc)之第二源極，該第二源極與第四基底電性耦接至電源的正端(VDD )，而該第三汲極則同時電性耦接至該第一補償電容(Cc)的第一端、該第四P型金氧半場效電晶體(M1)之第一閘極、該第五P型金氧半場效電晶體(M2)之第一閘極與該第十四N型金氧半場效電晶體(M607)之第三汲極。該第十四N型金氧半場效電晶體(M607)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極同時電性耦接到該第十二N型金氧半場效電晶體(M605)之第一閘極，該第二源極與第四基底電性耦接至電源的接地端(VSS )，而該第三汲極則同時電性耦接至該第一補償電容(Cc)的第一端、該第四P型金氧半場效電晶體(M1)之第一閘極、該第五P型金氧半場效電晶體(M2)之第一閘極與該第十三P型金氧半場效電晶體(M606)之第三汲極。The output amplifying circuit is composed of a thirteenth P-type gold-oxygen half field effect transistor (M606) and a fourteenth N-type gold-oxygen half field effect transistor (M607) and other transistors; The thirteenth P-type MOS field effect transistor (M606) includes a first gate, a second source, a third drain and a fourth substrate. The first gate is electrically coupled at the same time. Receiving a third drain of the ninth P-type metal oxide half field effect transistor (M602), a third drain of the eleventh N-type gold-oxygen half field effect transistor (M604), and the fifteenth P-type gold a second source of the oxygen half field effect transistor (M_Rc), the second source and the fourth substrate are electrically coupled to the positive terminal (V DD ) of the power source, and the third drain is electrically coupled to the a first end of the first compensation capacitor (Cc), a first gate of the fourth P-type MOS field-effect transistor (M1), and a first of the fifth P-type MOS field-effect transistor (M2) The gate is the third drain of the fourteenth N-type gold-oxygen half field effect transistor (M607). The fourteenth N-type metal oxide half field effect transistor (M607) includes a first gate, a second source, a third drain and a fourth substrate. The first gate is simultaneously electrically And coupled to the first gate of the twelfth N-type MOS field-effect transistor (M605), the second source and the fourth substrate are electrically coupled to the ground end (V SS ) of the power source, and the The third gate is electrically coupled to the first end of the first compensation capacitor (Cc), the first gate of the fourth P-type MOS field-effect transistor (M1), and the fifth P-type gold oxide The first gate of the half field effect transistor (M2) and the third gate of the thirteenth P type gold oxide half field effect transistor (M606).
該補償電路係由一第十五P型金氧半場效電晶體(M_Rc)與一第一補償電容(Cc)等元件之電性連接所組成；其中，該第十五P型金氧半場效電晶體(M_Rc)包括一第一閘極、一第二源極、一第三汲極與一第四基底(Body)，該第一閘極電性耦接到接地端，該第二源極同時電性耦接到該第九P型金氧半場效電晶體(M602)之第三汲極、該第十一N型金氧半場效電晶體(M604)之第三汲極及該第十三P型金氧半場效電晶體(M606)之第一閘極，該第三汲極電性耦接到第一補償電容(Cc)的第二端，該第四基底則電性耦接至電源的正端(VDD )；該第一補償電容(Cc)包括一第一端與第二端，該第一端同時電性耦接到第十三P型金氧半場效電晶體(M606)之第三汲極、該第四P型金氧半場效電晶體(M1)之第一閘極、該第五P型金氧半場效電晶體(M2)之第一閘極與該第十四N型金氧半場效電晶體(M607)之第三汲極，該第二端電性耦接到第十五P型金氧半場效電晶體(M_Rc)之第三汲極。The compensation circuit is composed of a fifteenth P-type MOS field-effect transistor (M_Rc) and a first compensation capacitor (Cc) and the like; wherein the fifteenth P-type MOS half-field effect The transistor (M_Rc) includes a first gate, a second source, a third drain, and a fourth body. The first gate is electrically coupled to the ground, the second source. Simultaneously electrically coupled to the third drain of the ninth P-type MOS field-effect transistor (M602), the third drain of the eleventh N-type MOS field-effect transistor (M604), and the tenth a first gate of the three P-type MOS field-effect transistor (M606), the third gate is electrically coupled to the second end of the first compensation capacitor (Cc), and the fourth substrate is electrically coupled to a positive terminal (V DD ) of the power supply; the first compensation capacitor (Cc) includes a first end and a second end, the first end being electrically coupled to the thirteenth P-type MOS field-effect transistor (M606) a third gate, a first gate of the fourth P-type MOS field-effect transistor (M1), a first gate of the fifth P-type MOS field-effect transistor (M2), and the tenth The third pole of the four N-type gold oxygen half field effect transistor (M607), Is electrically coupled to the second end of the fifteenth P-type metal oxide semiconductor field effect transistor (M_Rc) of the third drain.
接著，說明本發明之帶差參考電流的公式推導。首先，假定第三圖中的電晶體皆為理想、電晶體M1、M2與M3皆相同、電阻Ra1與Ra2相同、電阻Rb1與Rb2相同且放大器的正負輸入端為虛短路(Vin+=Vin-)，則Next, the formula derivation of the difference reference current of the present invention will be described. First, assume that the transistors in the third figure are all ideal, the transistors M1, M2 and M3 are the same, the resistors Ra1 and Ra2 are the same, the resistors Rb1 and Rb2 are the same, and the positive and negative inputs of the amplifier are virtual short circuits (Vin+=Vin-). ,then
VEB1 =VEB2 +VR2 ................................................(公式1)V EB1 =V EB2 +V R2 .......................................... ......(Formula 1)
IRb1 =IRb2 ...........................................................(公式2)I Rb1 =I Rb2 ............................................. ..............(Formula 2)
IRa1 =IRa2 ..............................................................(公式3)I Ra1 =I Ra2 ............................................. .................(Formula 3)
IRa2 =IRb2 +IR2 .....................................................(公式4)I Ra2 =I Rb2 +I R2 .......................................... ...........(Formula 4)
以(公式4)為例，其對溫度(T)的變化為Taking (Formula 4) as an example, the change in temperature (T) is
因為IRb2 =VEB1 /Rb2 且IR2 =(VEB1 -VEB2 )/R2 ，可以得知IRb2 是負電流溫度係數，且存在著調整因子Rb2 ；同理，IR2 是正電流溫度係數，且存在著調整因子R2 。藉由調整因子的調整可以使IRb2 與IR2 的溫度變化值對消，得到與溫度變化無關的電流IRa2 ，經由第五P型金氧半場效電晶體(M2)與第七P型金氧半場效電晶體(M4)所組成的電流鏡，將電流IRa2 鏡射至輸出電流，即可得到與溫度變化無關的參考電流(Iref )。Since I Rb2 =V EB1 /R b2 and I R2 =(V EB1 -V EB2 )/R 2 , it can be known that I Rb2 is a negative current temperature coefficient and there is an adjustment factor R b2 ; similarly, I R2 is a positive current Temperature coefficient, and there is an adjustment factor R 2 . By adjusting the adjustment factor, the temperature change values of I Rb2 and I R2 can be canceled, and the current I Ra2 independent of the temperature change is obtained, via the fifth P-type gold-oxygen half-field effect transistor (M2) and the seventh P-type gold. A current mirror composed of an oxygen half-field effect transistor (M4) mirrors the current I Ra2 to the output current to obtain a reference current (I ref ) independent of the temperature change.
請再參考第三圖，本發明之參考電壓(Vref )在加入第三升壓電阻(Ra3)之後，可以得到Referring to the third figure, the reference voltage (V ref ) of the present invention can be obtained after adding the third boosting resistor (Ra3).
Vref =IRa3 ×Ra3 +VBE3 ......................................................(公式6)V ref =I Ra3 ×R a3 +V BE3 ....................................... ...............(Formula 6)
其對溫度(T)的變化為Its change to temperature (T) is
其中，IRa3 為與溫度變化無關的參考電流()，電阻Ra3 為正溫度係數的電阻，而第三雙極接面電晶體(Q3)之射基極電壓為負電壓溫度係數()；藉由適當地選擇Ra3 與IRa3 的值，可以得到與溫度變化無關的輸出參考電壓Vref 。值得注意的是，所有的升壓電阻(Ra 系列)與補償電阻(Rb 系列)均需採用具有較高溫度係數之N型井電阻(N-well)，而第七偏壓電阻則需採用具有較低溫度係數之N型擴散區域(n+ -diffusion)。Where I Ra3 is a reference current independent of temperature changes ( ), the resistor R a3 is a positive temperature coefficient resistor, and the base voltage of the third bipolar junction transistor (Q3) is a negative voltage temperature coefficient ( By appropriately selecting the values of R a3 and I Ra3 , an output reference voltage V ref independent of the temperature change can be obtained. It is worth noting that all boost resistors (R a series) and compensation resistors (R b series) require N-well resistors with a higher temperature coefficient, while the seventh bias resistors require An N-type diffusion region (n + -diffusion) having a lower temperature coefficient is employed.
以上所述，係本發明較佳可行實施例之具體說明，惟非因此即拘限本發明專利範圍，對於本領域的技術人員，很明顯地，在不脫離本發明的精神或範圍的情況下，能對本發明進行多種改進和變化。因此，如果這些改進和變化，直接或間接落在所附權利要求及其等同物的範圍內，則本發明涵蓋這些改進和變化，合予陳明。The foregoing is a detailed description of the preferred embodiments of the present invention, and the scope of the present invention is not to be construed as being limited to the scope of the present invention. Many modifications and variations of the present invention are possible. Therefore, the present invention covers such modifications and variations as may be apparent from the scope of the appended claims and the equivalents thereof.
再，為使本發明更加顯現其進步性與實用性，茲將其使用實施上之優點另列舉如下：Further, in order to make the present invention more expressive and practical, the advantages of its implementation are listed as follows:
1.本發明設有三個元件所組成的啟動(Start Up)電路，當該帶差參考電路正常運作時，該啟動電路即進入關閉狀態，不會影響其他電路的正常操作；該啟動電路元件數少，具有架構簡單、省電與快速啟動等優點。1. The present invention is provided with a start up circuit composed of three components. When the differential reference circuit is in normal operation, the startup circuit enters a closed state, which does not affect the normal operation of other circuits; Less, with the advantages of simple architecture, power saving and quick start.
2.本發明同時具有輸出與溫度變化無關的參考電壓及參考電流，可以使本發明之應用範圍擴大，提高本發明的附加價值並具有小型化等優點。2. The present invention has both a reference voltage and a reference current whose output is independent of temperature variation, which can expand the application range of the present invention, improve the added value of the present invention, and have the advantages of miniaturization and the like.
3.本發明具有較佳的溫度補償功能，可以使得參考電壓的輸出值相對穩定，並且能在低電壓下工作，減少功率消耗，具有省能效果，符合工商界或產業界的實際所需，具產業利用價值。3. The invention has better temperature compensation function, can make the output value of the reference voltage relatively stable, and can work under low voltage, reduce power consumption, has energy-saving effect, and meets the actual needs of the industrial and commercial circles or industries. With industrial use value.
綜上所述，本發明在突破先前之技術結構下，確實已達到所欲增進之功效，且也非熟悉該項技藝者所易於思及；再者，本發明具有進步性、實用性，顯已符合發明專利之申請要件，爰依法提出發明申請。In summary, the present invention has achieved the desired effect under the prior art structure, and is also unfamiliar to those skilled in the art; further, the present invention is progressive, practical, and obvious. Has met the application requirements of the invention patent, and filed an invention application according to law.
200．．．低電壓帶差參考電路200. . . Low voltage band difference reference circuit
A201．．．運算放大器A201. . . Operational Amplifier
M201、M202、M203．．．金氧半埸效電晶體M201, M202, M203. . . Gold oxide semi-effect transistor
Q201、Q202．．．雙極接面電晶體Q201, Q202. . . Bipolar junction transistor
R201、R202、R203、R204、R205、R206．．．電阻R201, R202, R203, R204, R205, R206. . . resistance
300．．．帶差參考電路300. . . Differential reference circuit
1．．．啟動電路1. . . Startup circuit
2．．．參考電流電路2. . . Reference current circuit
3．．．參考電壓電路3. . . Reference voltage circuit
Mp．．．第一P型金氧半場效電晶體Mp. . . First P-type gold oxide half field effect transistor
Ms．．．第二P型金氧半場效電晶體Ms. . . Second P-type gold oxide half field effect transistor
Mn．．．第三N型金氧半場效電晶體Mn. . . Third N-type gold oxygen half field effect transistor
M1．．．第四P型金氧半場效電晶體M1. . . Fourth P-type gold oxide half field effect transistor
M2．．．第五P型金氧半場效電晶體M2. . . Fifth P-type gold oxide half field effect transistor
M3．．．第六P型金氧半場效電晶體M3. . . Sixth P-type gold oxide half field effect transistor
M4．．．第七P型金氧半場效電晶體M4. . . The seventh P-type gold oxygen half field effect transistor
OPA．．．N型輸入的運算放大器OPA. . . N-type input operational amplifier
Ra1．．．第一升壓電阻Ra1. . . First boost resistor
Ra2．．．第二升壓電阻Ra2. . . Second boost resistor
Ra3．．．第三升壓電阻Ra3. . . Third boost resistor
Rb1．．．第四補償電阻Rb1. . . Fourth compensation resistor
Rb2．．．第五補償電阻Rb2. . . Fifth compensation resistor
Rb3．．．第六補償電阻Rb3. . . Sixth compensation resistor
R2．．．第七偏壓電阻R2. . . Seventh bias resistor
Q1．．．第一雙極接面電晶體Q1. . . First bipolar junction transistor
Q2．．．第二雙極接面電晶體Q2. . . Second bipolar junction transistor
Q3．．．第三雙極接面電晶體Q3. . . Third bipolar junction transistor
VDD ．．．電源的正端V DD . . . Positive end of the power supply
VSS ．．．電源的接地端V SS . . . Ground terminal of the power supply
Iref ．．．參考電流I ref . . . Reference current
Vref ．．．參考電壓V ref . . . Reference voltage
Cc．．．第一補償電容Cc. . . First compensation capacitor
Vbias ．．．偏壓電壓V bias . . . Bias voltage
600．．．具N型差動輸入的運算放大器600. . . Operational amplifier with N-type differential input
M601．．．第八P型金氧半場效電晶體M601. . . The eighth P-type gold oxygen half field effect transistor
M602．．．第九P型金氧半場效電晶體M602. . . Ninth P-type gold oxide half field effect transistor
M603．．．第十N型金氧半場效電晶體M603. . . Tenth N-type gold oxygen half field effect transistor
M604．．．第十一N型金氧半場效電晶體M604. . . The eleventh N-type gold oxygen half field effect transistor
M605．．．第十二N型金氧半場效電晶體M605. . . Twelfth N-type gold oxygen half field effect transistor
M606．．．第十三P型金氧半場效電晶體M606. . . The thirteenth P-type gold oxygen half field effect transistor
M607．．．第十四N型金氧半場效電晶體M607. . . The fourteenth N-type gold oxygen half field effect transistor
M_Rc．．．第十五P型金氧半場效電晶體M_Rc. . . Fifteenth P-type gold oxide half field effect transistor
第一圖係習知帶差參考電路的基本架構圖。The first figure is a basic architecture diagram of a conventional reference circuit with a difference.
第二圖係習知的低電壓帶差參考電路的電路圖。The second figure is a circuit diagram of a conventional low voltage band difference reference circuit.
第三圖係本發明之電路實現圖(代表圖)。The third figure is a circuit implementation diagram (representative diagram) of the present invention.
第四圖係本發明之啟動電路的電壓輸出波形圖。The fourth figure is a voltage output waveform diagram of the startup circuit of the present invention.
第五圖係本發明之啟動電路的電流輸出波形圖。The fifth figure is a current output waveform diagram of the startup circuit of the present invention.
第六圖係本發明之補償前、後的參考電壓輸出對溫度變化之輸出波形圖。The sixth graph is an output waveform diagram of the reference voltage output versus temperature change before and after compensation according to the present invention.
第七圖係本發明之參考電壓對溫度變化所實測的電壓輸出結果圖。The seventh figure is a graph showing the voltage output of the reference voltage versus temperature change of the present invention.
第八圖係本發明之參考電壓對電源供應電壓所實測的電壓輸出結果圖。The eighth figure is a graph showing the voltage output measured by the reference voltage of the present invention with respect to the power supply voltage.
第九圖係本發明之參考電流對溫度變化所實測的電流輸出結果圖。The ninth graph is a graph showing the current output of the reference current versus temperature change of the present invention.
第十圖係本發明所採用之N型差動輸入的運算放大器之電路實現圖。The tenth figure is a circuit implementation diagram of an operational amplifier of an N-type differential input used in the present invention.
1．．．啟動電路1. . . Startup circuit
2．．．參考電流電路2. . . Reference current circuit
3．．．參考電壓電路3. . . Reference voltage circuit
Mp．．．第一P型金氧半場效電晶體Mp. . . First P-type gold oxide half field effect transistor
Ms．．．第二P型金氧半場效電晶體Ms. . . Second P-type gold oxide half field effect transistor
Mn．．．第三N型金氧半場效電晶體Mn. . . Third N-type gold oxygen half field effect transistor
M1．．．第四P型金氧半場效電晶體M1. . . Fourth P-type gold oxide half field effect transistor
M2．．．第五P型金氧半場效電晶體M2. . . Fifth P-type gold oxide half field effect transistor
M3．．．第六P型金氧半場效電晶體M3. . . Sixth P-type gold oxide half field effect transistor
M4．．．第七P型金氧半場效電晶體M4. . . The seventh P-type gold oxygen half field effect transistor
OPA．．．N型差動輸入運算放大器OPA. . . N-type differential input operational amplifier
Ra1．．．第一升壓電阻Ra1. . . First boost resistor
Ra2．．．第二升壓電阻Ra2. . . Second boost resistor
Ra3．．．第三升壓電阻Ra3. . . Third boost resistor
Rb1．．．第四補償電阻Rb1. . . Fourth compensation resistor
Rb2．．．第五補償電阻Rb2. . . Fifth compensation resistor
Rb3．．．第六補償電阻Rb3. . . Sixth compensation resistor
R2．．．第七偏壓電阻R2. . . Seventh bias resistor
Q1．．．第一雙極接面電晶體Q1. . . First bipolar junction transistor
Q2．．．第二雙極接面電晶體Q2. . . Second bipolar junction transistor
Q3．．．第三雙極接面電晶體Q3. . . Third bipolar junction transistor
VDD ．．．電壓正端V DD . . . Positive voltage
VSS ．．．電壓接地端V SS . . . Voltage ground
Iref ．．．參考電流I ref . . . Reference current
Vref ．．．參考電壓V ref . . . Reference voltage
300．．．帶差參考電路300. . . Differential reference circuit
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW98124623A TWI381265B (en) | 2009-07-21 | 2009-07-21 | A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit |
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| TW98124623A TWI381265B (en) | 2009-07-21 | 2009-07-21 | A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit |
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| TW201104381A TW201104381A (en) | 2011-02-01 |
| TWI381265B true TWI381265B (en) | 2013-01-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98124623A TWI381265B (en) | 2009-07-21 | 2009-07-21 | A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI457743B (en) * | 2012-09-20 | 2014-10-21 | Novatek Microelectronics Corp | Bandgap reference circuit and self-referenced regulator |
| CN103645769B (en) * | 2013-12-10 | 2015-07-01 | 电子科技大学 | low-voltage band-gap reference source circuit |
| JP2021110994A (en) | 2020-01-07 | 2021-08-02 | ウィンボンド エレクトロニクス コーポレーション | Constant current circuit |
| CN111930169B (en) * | 2020-07-27 | 2022-02-11 | 重庆邮电大学 | Negative feedback subsection curvature compensation band gap reference circuit |
| TWI832227B (en) * | 2021-04-28 | 2024-02-11 | 極創電子股份有限公司 | Reference voltage circuit with temperature compensation |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710641B1 (en) * | 2001-08-28 | 2004-03-23 | Lattice Semiconductor Corp. | Bandgap reference circuit for improved start-up |
| TW583526B (en) * | 2001-10-10 | 2004-04-11 | Taiwan Semiconductor Mfg | Bandgap reference voltage generator with a low-cost, low-power, fast start-up circuit |
| US7113025B2 (en) * | 2004-04-16 | 2006-09-26 | Raum Technology Corp. | Low-voltage bandgap voltage reference circuit |
| US20070052404A1 (en) * | 2005-09-07 | 2007-03-08 | Texas Instruments Incorporated | Current-mode bandgap reference voltage variation compensation |
| TW200717213A (en) * | 2005-10-27 | 2007-05-01 | Realtek Semiconductor Corp | Startup circuit, bandgap voltage genertor utilizing the startup circuit, and startup method thereof |
| TW200827978A (en) * | 2006-12-29 | 2008-07-01 | Mediatek Inc | Bandgap reference circuits and start-up methods thereof |
| TW200837526A (en) * | 2006-12-22 | 2008-09-16 | Intel Corp | Start-up circuit for supply independent biasing |
-
2009
- 2009-07-21 TW TW98124623A patent/TWI381265B/en not_active IP Right Cessation
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710641B1 (en) * | 2001-08-28 | 2004-03-23 | Lattice Semiconductor Corp. | Bandgap reference circuit for improved start-up |
| TW583526B (en) * | 2001-10-10 | 2004-04-11 | Taiwan Semiconductor Mfg | Bandgap reference voltage generator with a low-cost, low-power, fast start-up circuit |
| US7113025B2 (en) * | 2004-04-16 | 2006-09-26 | Raum Technology Corp. | Low-voltage bandgap voltage reference circuit |
| US20070052404A1 (en) * | 2005-09-07 | 2007-03-08 | Texas Instruments Incorporated | Current-mode bandgap reference voltage variation compensation |
| TW200717213A (en) * | 2005-10-27 | 2007-05-01 | Realtek Semiconductor Corp | Startup circuit, bandgap voltage genertor utilizing the startup circuit, and startup method thereof |
| TW200837526A (en) * | 2006-12-22 | 2008-09-16 | Intel Corp | Start-up circuit for supply independent biasing |
| TW200827978A (en) * | 2006-12-29 | 2008-07-01 | Mediatek Inc | Bandgap reference circuits and start-up methods thereof |
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| Publication number | Publication date |
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| TW201104381A (en) | 2011-02-01 |
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