TWI380475B - Light source, light-emitting device and display device - Google Patents

Light source, light-emitting device and display device Download PDF

Info

Publication number
TWI380475B
TWI380475B TW98101231A TW98101231A TWI380475B TW I380475 B TWI380475 B TW I380475B TW 98101231 A TW98101231 A TW 98101231A TW 98101231 A TW98101231 A TW 98101231A TW I380475 B TWI380475 B TW I380475B
Authority
TW
Taiwan
Prior art keywords
light
layer
emitting elements
substrate
emitting
Prior art date
Application number
TW98101231A
Other languages
Chinese (zh)
Other versions
TW200933939A (en
Inventor
Kenzo Hanawa
Yoshinori Abe
Original Assignee
Showa Denko Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko Kk filed Critical Showa Denko Kk
Publication of TW200933939A publication Critical patent/TW200933939A/en
Application granted granted Critical
Publication of TWI380475B publication Critical patent/TWI380475B/en

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
  • Liquid Crystal (AREA)

Description

1380475 六、發明說明： 【發明所屬之技術領域】 本發明係關於光源、發光裝置及顯示裝置者β 【先前技術】 近年以來’使用發光—極體（LED: Light Emitting Diode )等之發光元件的發光裝置被多樣地實用化。如此 之發光裝置乃廣泛利用做爲照明裝置、或液晶面板之背光 等。又’例如於液晶電視等，伴隨畫面尺寸之大型化等， 需要背光等之光源光量之增大。對於如是之要求，就達成 使用上述發光元件之背光等之光源光量之增大的形態而言 ’可有使用大型尺寸之發光元件，或增加發光元件之數量 等之方法。 發光元件之發光量會隨元件之尺寸的增大而增加，但 是一般而言大型尺寸之發光元件的發光效率則較低。即， 大型尺寸之發光元件之時，於發光元件流入均勻之電流之 故，設於發光元件之電極墊片之面積不得不變大。此時， 於電極墊片本身會有吸收從發光元件發出之光線的特性之 故，電極墊片之面積愈大，被電極墊片吸收之光量亦會增 加。 另一方面，增加發光元件之數量時，例如爲了得與到 大型尺寸之發光元件同等之發光量，相較於大型尺寸之發 光元件，需設更多之發光元件數量。此時，例如安裝基板 之發光元件之安裝費會變高，而導致製品之成本的上昇。 -4 - 1380475 對此，做爲減少安裝基板之發光元件之安裝數的對策 ，有將複數之發光元件集中成一個而封裝化的方法。此時 ，在一個封裝內，可爲電性並列複數之發光元件，或可爲 直列連接之方式。在此，使用直列連接之方式時，相較於 並列連接之方式而言，一個封裝之驅動電壓需被提高之故 ，更具備多數此封裝之發光裝置的驅動電壓則更會被提升 ··, 〇 另一方面，對於並列連接複數之發光元件之公報記載 之以往技術而言，揭示有將電性並列連接之複數之發光元 件的光源，例如使用於上述之背光裝置等之技術（例如參 照專利文獻1 )。 更且，揭示有於電性並列連接複數之發光元件時，爲 使此等之複數之發光元件之順向電壓的參差在0.IV以內 ，事先選擇區別發光元件加以使用之技術（例如參照專利 文獻2 )。 [專利文獻1]日本特開2007-134 72 2號公報 [專利文獻2]日本特開2006-222412號公報 【發明內容】 [發明欲解決之課題] 然而，將關於阻抗値等之電性特性有參差之複數之發 光元件加以電性並列之時，此等之發光元件之阻抗値最低 之發光元件中，較其他之發光元件而言會流入更多之電流 。發光元件之光量一般而言與電流成比例之故，由於流入 -5- 1380475 共列連接之複數之發光元件間之電流量之不均，在於複數 之發光元件間，會有產生光量不均之疑慮。更且，在阻抗 値最小之發光元件中，會集中負荷之故，此發光元件之壽 命有可能會明顯變短，使得做爲光源之可靠性爲之下降。 本發明乃爲解決以上之技術課題而成者，其目的乃在 並列連接複數之發光元件之光源時，提供可抑制產生於複 數之發光元件間之光量之不均的光源等。 [爲解決課題之手段] 在此目的之下，適用於本發明之光源乃具備：複數之 發光元件、電性並列連接前述複數之發光元件之並列連接 手段；構成前述複數之發光元件之各發光元件乃包含：元 件基板、和直接層積於III族氮化物化合物半導體所成前 述元件基板之上的第1之層、和直接層積於前述第1之層 上，（ 0002 )面之搖擺曲線半値寬爲lOOarcsec以下，（ 10-10 )面之搖擺曲線半値寬爲25〇arCSec以下之III族氮 化物化合物半導體所成第2之層。 在_此，第…2之層爲（0002 )面乏搖擺函線半1寬爲_ 60arcsec以下，（10-10 )面之搖擺曲線半値寬爲 250arcSec以下之III族氮化物化合物半導體爲特徵時，由 於可更抑制電性並列連接之複數之發光元件之例如阻抗値 等之不均之故，是爲較佳者< 於此光源中，並列連接手段乃安裝前述複數之發光元 件的同時，形成供電於該複數之發光元件之供電路徑的安 -6- 1380475 裝體爲特徵者。 又，於如此光源中，前述第1之層乃具有21nm以上 40nm以下之層厚爲特徵者。此時，第1之層乃經由濺鍍 法而成膜爲特徵。更且元件基板爲藍寶石基板，第1之層 乃A1N，前述第2之層乃GaN爲特徵者。 更且，於如此光源中，更具備：與前述複數之發光元 件不同之其他之複數之發光元件，電性並列連接前述其他 之複數之發光元件之其他之並列連接手段；電性連接前述 並列連接手段與前述其他之並列連接手段的連接手段爲特 徵者。 然後，令本發明做爲發光裝置之時。備有：具備複數 之發光元件、和電性並列連接該複數之發光元件的第1之 供電路徑的發光體，和設置安裝複數個前述發光體，與設 於各該當發光體之前述第1之供電路徑電性連接的第2之 供電路徑的安裝基板；構成前述複數之發光元件之各發光 元件乃包含：元件基板、和直接層積於ΠΙ族氮化物化合 物半導體所成前述元件基板之上的第1之層、和直接層積 於前述第1之層上，（〇〇〇2 )面之搖擺曲線半値寬爲 lOOarcsec以下，（1 0 -1 0 )面之搖擺曲線半値寬爲 250 arcsec以下之III族氮化物化合物半導體所成第2之層 者。 此時，複數之發光體乃在安裝基板，以等間隔加以配 置爲特徵時，可抑制做爲發光裝置整體之光量的不均，因 此爲佳。 -7- 1380475 然後，令本發明做爲顯示裝置之時，包含顯示畫像之 顯示面板、和設於該顯示面板之背面，向該顯示面板照射 光線之背光的顯示裝置中，前述背光乃具備：備有複數之 發光元件、和電性並列連接該複數之發光元件的第1之供 電路徑的發光體，和設置安裝複數個前述發光體，與設於 各該當發光體之前述第1之供電路徑電性連接的第2之供 電路徑的安裝基板；構成前述複數之發光元件之各發光元 件乃包含：元件基板、和直接層積於III族氮化物化合物 半導體所成前述元件基板之上的第1之層、和直接層積於 前述第1之層上，（0002 )面之搖擺曲線半値寬爲 lOOarcsec以下，（10-10 )面之搖擺曲線半値寬爲 25 Oarcsec以下之III族氮化物化合物半導體所成第2之層 者。 於如此顯示裝置中，更包含·.各別電性連接構成前述 複數之發光體之2個以上之發光體，形成複數之發光體群 的複數之連接導體、和對於構成前述複數之連接導體之各 個連接導體而言，進行供電之複數電源爲特徵者。 [發明之效果] 根據本發明時，可提供抑制電性並列連接複數之發光 元件時之產生於複數之發光元件間之光量之不均的光源等 【實施方式】 1380475 以下，參照圖面，對於爲實施本發明之最佳形態（以 • 下稱實施形態）加以說明。 [實施形態1] 圖1乃顯示適用於本實施形態之液晶顯示裝置之整體 構成圖。然而，圖1中，令液晶顯示裝置之縱方向V及 橫方向Η以箭頭加以表示。 φ 液晶顯示裝置乃具備液晶顯示模組5 0、和設於此液 , 晶顯示模組50之背面側（圖1爲下部側）之背光裝置（ 背光）40。 做爲發光裝置工作之背光裝置40乃具備收容光源之 背光框體（框體）41、和複數排列發光二極體（以下說明 稱LED)之發光單元42。又，背光裝置40乃具備將做爲 光學薄膜之層積體，對於可視具有光透過性之樹脂爲材料 ，爲使面整體均勻明亮，而使光線散亂·擴散之擴散板 φ 43(板或薄膜）、和具有向前方之聚光效果之繞射光柵薄 膜之棱鏡薄片44、45。又，依需要，具備爲提升亮度之 擴散•反射型之亮度提升薄膜46。 另一方面’液晶顯示模組5 0乃具備經由2枚之玻璃 基板挾持液晶而構成之液晶面板51、層積於此液晶面板 51之各個玻璃基板，將光波振動限制於某方向之偏光板 52、53。更且，於液晶顯示裝置中，裝設有未圖示之驅動 用LSI等之周邊構件。 做爲顯示面板之一之液晶面板51乃包含未圖示之各 1380475 種構成要素所構成。例如，於2枚玻璃基板，具備未圖示 之顯示電極、薄膜電晶體（TFT: Thin Film Transistor) 等之主動元件、液晶、間隔件、密封劑、配向膜、共通電 極、保護膜、彩色濾光片等。 然而，背光裝置40之構成單位可任意選擇。例如僅 具有發光單元42之背光框體41之單位中，稱之爲「背光 裝置（背光）」，可有不包含擴散板43、稜鏡薄片44、 45、亮度提升薄膜46之流通形態。 圖2乃爲說明做爲發光裝置之背光裝置40之背光框 體41及發光單元42之構成圖，乃將背光裝置40由圖1 所示之液晶顯示模組5 0側（上面側）所視得之圖。 背光框體41乃例如形成以鋁或鎂、鐵或含此等之金 屬合金等所生成之框體構造。然後，於該框體構造之內側 ，例如貼有具有白色高反射性能之聚酯薄膜等，亦可做爲 反射器加以工作。做爲此框體構造，具對應於液晶顯示模 組50之大小而設之背面部、和包圍此背面部之四角藩之 側面部。又，於此背面部或側面部，依需要，形成由爲予 排熱之冷卻葉片等所成之散熱片構造。又，於背光框體 41之背面部，設置在於構成發光單元42之複數之LED封 包20(後述），爲進行供電之連接器（未圖示）。 發光單元42乃具備8枚之發光模組30。然後，此等 8枚之發光模組30乃在背光框體41之背面部，在縱向方 向V配置2列，在橫方向Η配置4列。 圖3 ( a )’（ b )乃爲對於發光模組3 0加以說明之 -10- 1380475 圖。圖3(a)乃發光模組30之上面圖，圖3(b)乃從圖 • 3 (a)所示箭頭A所視得之發光模組30之側面圖。又， • 於圖3(b)中，配合關於LED封裝20之部分剖面圖加以 表示。 發光模組30乃具備複數（此例中爲120個）之LED 封裝20、和做爲安裝基板之模組用基板31。 做爲光源及發光體工作之LED封裝20乃具備複數之 φ LED晶片10(後述），爲發出白色光者。然後，複數之 LED封裝20乃如圖3(a)所示於模組基板31上，在縱 向方向V配置12列，在橫方向Η配置10列。又，於適 用本實施形態之發光模組3 0中，配置於模組用基板31之 複數之LED封裝20乃使鄰接於縱方向V之LED封裝20 彼此之間隔設定呈幾近相等（在此例中約1英吋），且使 鄰接於橫方向Η之LED封裝20彼此之間隔設定呈幾近相 等（在此例中約1英吋）。因此，於模組用基板31上， φ 120個之LED封裝20乃排列成幾近格子狀。然而，複數 之LED封裝20乃在模組用基板3 1，配置成略等間隔即可 ，例如使鄰接之3個之LED封裝20形成呈略正三角形而 加以配置亦可。 更且，於一枚發光模組30中，位於最外圍之LED封 裝20至模組用基板31之端部的距離，則設計成較1/2英 吋爲短。經由如此之設定，如圖2所示，.將8枚之發光模 組30安裝於背光框體41之時，亦可使鄰接之LED封裝 20彼此之縱方向V及橫方向Η之間隔配置成相等（此例 -11 - 1380475 中約爲1英吋）》 實際上，適用本實施形態之發光單元42中，960個 (120x8)之LED封裝20乃使鄰接之LED封裝20彼此之 縱方向V及橫方向Η之間隔配置成幾近相等，於背光框 體4 1排列成幾近格子狀。 模組用基板31乃安裝如上述之複數之LED封裝20 者。此模組用基板31之母材乃例如可使用在玻璃纖維含 浸環氧樹脂之所謂玻璃環氧樹脂等。又，如圖3 (b)所 示，於模組用基板31，在安裝LED封裝20之面（以下稱 安裝面），形成有爲供電至LED封裝20之電性配線圖案 32。然後，於模組用基板31之安裝面，電性配線圖案32 與LED封裝20則經由焊錫電性連接^ 又，於此模組用基板31之安裝面，使從LED封裝20 照射之光線能被反射，形成有白色光阻劑。 又，如圖3 ( a )及圖3 ( b )所示，於模組用基板3 1 ，設有爲將發光模組3 0安裝於背光框體4 1之螺絲孔3 6b 。然後，使用螺絲36a，於此螺絲孔36b之部分，將模組 用基板31面定在背光框體41。 ........ 然後，於一枚之發光模組30中，於圖3(a)以虛線 所示，形成成爲發光控制單元之發光區塊300。做爲發光 體群之發光區塊3 00乃具有在縱方向V6列、在橫方向H2 列之合計12個之LED封裝20。然後，發光模組30中， 此發光區塊3 00則爲設有在縱向方向V配置2列，在橫 方向Η配置5列之合計1 〇區塊。 -12- 1380475 然而，於本實施形態中，設於模組用基板31之電性 配線圖案32則做爲第2之供電路徑及連接導體而工作。 圖4 ( a) ( b)乃對於LED封裝20加以說明之圖。 圖4乃LED封裝20之上面圖（發光面側），圖4(b)乃 顯示圖4 ( a )之IV -1V剖面圖。 LED封裝20乃發出具有紅色（R)、綠（G)、藍色 (B)之三原色之白色光。然後，LED封裝20乃如圖4 ( a)所示，具備3個LED晶片10、和正極用引線框291及 負極用引線框2 92、和做爲安裝體工作之殼體293。 各LED晶片10乃發出藍色之光線之藍色LED。又， 於本實施形態中，LED晶片10之尺寸乃350/zm平方， 該厚度爲80//m者。然後，於LED封裝20中，此等之3 個LED晶片丨0乃電性並列加以連接。然而，有關此LED 晶片1 〇之構造等，則於後加以詳細說明。 正極用引線框291及負極用引線框292乃如圖4 ( a )所示，將金屬板打掉呈E字狀而製作者。然後，如圖4 (b )所示，經由將白色樹脂等做爲材料之殼體293，固 定此等正極用引線框291及負極用引線框292之各個位置 關係。 然後，3個LED晶片10乃在各別正極用引線框291 之上，經由焊錫，機械性地加以安裝。更且，3個LED晶 片1 〇之正極（後述）乃經由打線等電性連接於在各別正 極用引線框291，3個LED晶片10之負極（後述）乃經 由打線等電性連接於在各別負極用引線框292。如此， -13- 1380475 LED封裝20之3個LED晶片10乃電性並歹! 然而，於本實施形態中，正極用引線框 引線框292則做爲並列連接手段或做爲第1 以工作。 又，正極用引線框291及負極用引線框 LED晶片1 0電性逢接之側中，各別設有引; 、2 92a (參照圖4 ( b))。然後，此引線中 2 92 a在上述模組用基板31之電性配線圖案 加以連接，LED封裝與模組用基板3 1之電 械性地加以連接。 又，如圖4(a)及（b)所示，在3個 之周圍，設置反射壁27。此反射壁27乃反！ 10照射之光線者，有效率地將從LED晶片 ，朝向擴散板43等（參照圖1 )加以照射 反射壁27之內側，使3個LED晶片10被 封閉樹脂28。然後，於本實施形態中，於妾 添加接受藍色之光而發出紅色之光的螢光體 之光而發出綠色之光的螢光體。 圖5(a)〜（c)乃對於LED封裝20 狀，爲說明其他之例之圖者。圖5(a)〜（ 封裝20乃與圖4(a)者基本上構成爲相同 線框29 1及負極用引線框292之形狀爲不同 於與使用圖4(a)說明之LED封裝20相同 上同一符號，省略詳細之說明。 J加以連接。 2 9 1及負極用 之供電路徑加 292中，未與 辕框端子291a ΐ端子291a、 32，使用焊錫 性連接可更機 LED晶片10 付從LED晶片 10發出之光線 。更且，於此 埋入，設置有 ί閉樹脂28， ，及接受藍色 之引線框之形 c )所示LED ，但正極用引 者。然而，對 的部分，則附 -14- 1380475 圖5 (a)所示LED封裝20之例乃具備具有凸形狀之 正極用引線框291、和具有凹形狀之負極用引線框292 β 然後，1個LED晶片10安裝於正極用引線框291之突出 部，其他之2個LED晶片1 0則各別安裝於正極用引線框 291之突出部以外之部分。然後，與上述例相同，進行 LED晶片10與引線框之電性連接，3個LED晶片10則並 列連接。 接著，圖5 ( b )所示LED封裝20之例中，正極用引 線框291及負極用引線框292則各別具有矩形狀。又，各 引線框保持特定距離，幾***行地加以配置。然後，3個 LED晶片10則安裝於正極用引線框291，與上述例同樣 地，3個LED晶片1 0則並列連接。 更且，圖5 ( c)所示LED封裝20之例乃具備具有L 字形狀之正極用引線框291、和具有收容於L字形狀之內 側之正方形狀的負極用引線框292。然後，3個LED晶片 1.0乃沿具有L字形狀之正極用引線框291之L字，保持 特定間隔加以安裝。然後，與上述例相同，於此例子之時 ，設於LED封裝20之3個LED晶片10則並列連接。 圖6乃爲對於發光模組3 0之電性連接加以說明之圖 〇 在此，將一枚之發光模組30做爲代表例做了說明， 但對於設在背光裝置40之其他之發光模組30亦是相同》 又，於圖6以虛線所示之框乃顯示發光區塊300，以一點 鏈鎖線所示之框乃相當於1個之LED封裝20之單位》 -15- 1380475 首先，於圖6以一點鏈鎖線所示之LED封裝20中’ 3個LED晶片10乃並列加以連接。如上所述，此等之3 個LED晶片10之並列連接乃經由引線框291、292加以 實現。 然後，圖6中以虛線所示1處之發光區塊3 00中，12 個LED封裝20乃直列連接。此12個LED封裝20之直列 連接乃經由設於模組用基板31之電性配線圖案32加以實 現》更且，如圖6所示，於每一發光區塊300(直列連接 之12個LED封裝20 )，各別設置各別之電源Ρ。然後， 12個LED封裝20乃藉由電性配線圖案32等，連接於電 源P。 接著，對於背光裝置40 (參照圖1 )之發光動作加以 說明。 設於背光裝置40之各發光模組3 0中，經由各電源P ，在直接連接於每一發光區塊300之12個之LED封裝20 ，施加上電壓。然後，於各發光區塊300之12個之LED 封裝20，各別流入電流。此時，各LED封裝20中，於相 互並列連接之3個LED晶片1 0，流入電流。 然後，於3個LED晶片10，各別流入電流之結果， LED晶片10乃發光呈藍光。此時，從LED晶片10發出 之藍色光之一部分乃經由添加於封閉樹脂28之螢光體， 變換成紅色或綠色。結果，從1個LED封裝20乃發出含 紅色（R)、綠（G)、藍色（B)之光線的白色光。 然後，其他之發光區塊3 00，更且於其他之發光模組 -16- 1380475 30中，同樣從LED封裝20發出含紅色（R)、 、藍色（B)之光線的白色光。然後，此光線乃 體41內混色，照射至擴散板43，更且經由擴散 ，促進混色之後，朝向液晶顯示模組50加以照穿 又，如上所述，適用本實施之形態之背光裝 ，於每一發光區塊300，設置電源P之故，經由 源P，可於每一發光區塊300，獨立進行點燈、 制。由此，做爲液晶顯示裝置顯示畫像之時，可 位於顯示畫像中成爲黑色之處所之背面側之發光 等之所謂區域控制。 又，於LED封裝20中，經由分散設置3個； 片10，例如與在LED封裝20設置一個大型尺 5 5 0 /z m平方）之晶片時比較，可控制溫度之上昇 然而，例如如適用本實施形態之液晶顯示裝 ，在發光面積爲大之裝置之光源中，爲我特定之 度等），需設多數之LED晶片10。此時，適用 態之LED封裝20纏繞3個LED晶片10而備有 將對於安裝對象之基板等之安裝作業例如可減少 又，備於LED封裝20中之3個LED晶片1 連接。因此，於LED封裝20中，相較於直列連 L E D晶片1 〇之時，可抑制驅動電壓。然後，伴 做爲背光裝置40’更甚之做爲液晶顯示裝置之 亦可被抑制。 接著’於上述LED封裝20中，對於電性並 綠（G) 在背光框 板43等 \ » 置 40中 控制各電 滅燈之控 進行滅燈 區塊 3 0 0 之LED晶 寸（例如 〇 置之背光 光量（亮 本實施形 之故，可 至 1/3。 〇乃並列 接3個之 隨於此， 驅動電壓 列連接之 -17- 1380475 LED晶片1 〇之構成加以說明》 圖7乃模式性顯示LED晶片1 0之剖面圖。 LED晶片10乃如圖7所示，具備缺爲元件基板之基 板11、做爲第1層之種子層12、做爲III族元素之含Ga 之ΠΙ族氮化物化合物半導體所成半導體層100。然後， 於種子層12上，η型半導體層14、發光層15及p型半導 體層16之各層乃依此順序層積。由此構成半導體層1〇〇 <基板> 適用本實施之形態之LED晶片10之基板1 1乃將藍 寶石做爲材料。做爲可使用於此基板11之材料，只要是 可將ΠΙ族氮化物化合物半導體結晶，磊晶成長於表面之 基板材料，則無需特別加以限定。 <種子層> 種子層12乃形成基板11 (藍寶石基板）之c面上。 於本實施之形態中，種子層1 2乃爲A1N材料。做爲可使 用於種子層12之材料，只要是III族氮化物化合物半導 體帕可，做爲III族元素，含Ga、In亦無妨，但其中以 含A1之組成爲佳。又，做爲種子層12之材料，使用 GaAIN亦可，此時，A1組成爲50%以上者爲佳。 又，種子層12乃至少被覆基板11之表面60%以上 ，較佳爲需被覆80%以上，被覆90%以上加形成者爲更 -18- 1380475 佳。又，種子層12乃被覆基板11之表面100%’即將基 板11之表面上無間隙地加以被覆形成者爲最佳。 種子層12被覆基板11之表面範圍變小時’基板11 會成爲大爲曝露之狀態。此時，成膜於種子層12上之基 底層14a與直接成膜於基板11上之基底層14a之晶格常 數會變得不同，不能成爲均勻之結晶，會產生龜裂或凹坑 之虞。 又，種子層12乃除了基板11之表面，亦被覆側面而 形成亦可，更且被覆基板11之背面而形成亦可。 然而，於本實施形態中，LED晶片1 〇之種子層1 2之 膜厚乃設定收斂於21 nm以上40nm以下之範圍。 <半導體層> <n型半導體層> η型半導體層14乃由層積於種子層12之基底層i4a 、和層積於基底層14a上之η型連接層14b、和層積於n 型連接層Mb之η型包覆層He所構成。 <基底層> 做爲第2之層之基底層14a乃令GaN爲材料。基底 層14a之材料，與種子層12相同或不同皆無妨，但以含 Ga之III族氮化物化合物半導體，即GaN系化合物半導 體爲佳’由AlxGai.xN層（OSxSi’較佳爲〇$xs〇 5, 更佳爲OSxSO.l)構成者爲更佳。又，本發明人實驗的 -19- 1380475 結果，做爲使用於基底層14a之材料，含Ga之III族氮 化物化合物半導體，即GaN系化合物半導體者爲佳。 基底層14a中，依需要，η型不純物雖可在lxlO17〜 lx 1019個/cm3之範圍內加以摻雜亦可，亦可爲未摻雜（ <1χ1017個/cm3)，而未摻雜者可維持良好之結晶之故因 而較佳。 例如，基板11具有導電性之時，經由在於基底層 14a摻雜摻雜劑而呈導電性，可於LED晶片10之上下， 形成電極。另一方面，做爲基板11使用絕緣性之材料時 ，在LED晶片10之同一面，採設置正極及負極之各電極 之晶片構造之故，基板11正上之層爲不摻雜之結晶者， 可得良好之結晶性之故因而較佳。 做爲η型不純物雖未特別加以限定，例如可列舉Si 、Ge及Sn等，較佳可列舉Si及Ge。 又，做爲基底層14a之膜厚，則設定成6/zm。然而 ，對於基底層14a之厚度雖未特別加以限定，一般而言爲 0.5；am〜20/zm之範圍爲佳。不足0.5//m時，會有換位 之迥圈化不充分之情形，較20 # m爲大之時，機能上無 大變化，只是會延長處理時間而已。因此較佳爲l/zm〜 1 5从m之範圍。 < η型連接層> η型連接層14b乃具有lxl〇19/cm3之電子濃度之厚2 y m之Si摻雜GaN。 -20- 1380475 然而，對於η型連接層14b而言，雖未特別加以限定 ，η型型連接層14b乃與基底層14a相同，由AlxGai_xN 層（OSxSl，較佳爲OSxSO.5，更佳爲OSxSO.l)構 成者爲佳。 更且，於η型連接層14b中，摻雜η型不純物爲佳， 當11型不純物以1><1〇17〜1><1〇19個/£；„13，更佳爲1><10丨8〜 1 xlO19個/cm3之濃度而含有之時，在於與負極之良好電性 φ 接觸之維持、龜裂產生之抑制、良好結晶性之維持上爲較 . 佳者。做爲η型不純物雖未特別加以限定，例如可列舉 Si、Ge及Sn等，較佳可爲Si及Ge» 然而，構成基底層14a及η型連接層14b之III族氮 化物化合物半導體乃同一組成者爲佳，令此等合計之膜厚 設定於〇.5~20/im，較佳設定於1〜15μιη，更佳爲設定於 1〜10；zm之範圍者。膜厚在此範圍時，半導體之結晶可被 良好維持。 < η型包覆層> 於η型連接層14b與發光層15間，設置η型包覆層 14c者爲佳。經由設置η型包覆層14c，可具有活性層之 電子供給，晶格常數差之緩和等之效果。 本實施形態中，η型包覆層Ik乃具有〗xl〇u/cm3之 電子濃度之厚20nm之Ino.iGao.9N。 然而，η型包覆層14a非限定於此，可經由AIGaN、 GaN ' GalnN等加以成膜。又，可爲此等之構造之異質接 -21 - 1380475 合或複數次層積之超晶格構造。令η型包覆層14c成爲 GalnN時，較井層之GalnN之In濃度爲低者爲佳。 又，η型包覆層14c之η型掺雜濃度爲 ΙχΙΟ17〜 lxl02G個/cm3之範圍爲佳，更佳者爲ΙχΙΟ18〜lxlO19個 /cm3之範圍。掺雜濃度爲此範圍時，在此良好之結晶性之 維持及發光元件之動作電壓之減低之方面上爲較佳者。 然而，η型連接層雖可兼爲基底層，及/或η型包覆 層，但基底層亦可兼做爲η型連接層，及/或η型包覆層 <發光層> 發光層15乃層積於η型半導體層14上的同時，ρ型 半導體層16層積於其上之層者》發光層15乃可採用多重 量子井構造，單一井構造，體構造等。於本實施形態中， 發光層15乃如圖7所示，交互重覆層積III族氮化物化 合物半導體所成障壁層15a、和含銦之III族氮化物化合 物半導體所成井層15b，且，於η型半導體層14側及ρ 型—半—導體層Τ(5 _俱Γ，ΙΒ置障壁_層—1 5 a。圖_ —7— _之—例φ :發光— 層15乃交互重覆6層之障壁層15a、和5層之井層15b， 於發光層15之最上層及最下層配置障壁層15a，成爲於 各障壁層15a間配置井層15b之多重量子井構成。 於本實施形態中，障壁層15a乃厚16nm之GaN。做 爲此障壁層15a，例如可使用AlcGai_eN(0Sc<0.3)等 之III族氮化物化合物半導體。 -22- 1380475 又’井層1 5b乃層厚3nm之InQ.2Ga〇.8N。又，此井 層15b中’做爲含銦之III族氮化物化合物半導體，例如 可使用Gai.sInsNCiXsCO.O等之氮化鎵銦。 <P型半導體層> P型半導體層16乃由p型包覆層16a及p型連接層 16b所構成。又，p型連接層乃可兼做爲p型包覆層而構 • 成。 < P型包覆層> P型包覆層16a乃摻雜Mg之AlmGao.gsN爲材料， 該膜厚乃5nm。做爲此p型包覆層16a，可列舉 AUGauNCiXdSOJ、較佳爲 O.lSd 鑫 0.3)者。p 型包 覆層1 6a乃由如此AlGaN所成之時，在於發光層15之載 子之封閉的層面上是爲較佳者。 φ P型包覆層16a之p型掺雜濃度爲ΙχΙΟ18〜lM〇2i個 /cm3爲佳，更佳者爲1χ1〇19〜lxl02Q個/cm3。p型摻雜劑 濃度爲上述範圍時，結晶性不會下降，可得良好之p型結 晶。做爲p型不純物雖未特別加以限定，例如較佳可列舉 Mg。 < P型連接層> P型連接層16b乃摻雜Mg之Alo.Q2Gao.98N，該膜厚 乃膜厚0.2/zm。做爲p型連接層16b，爲至少含有由 -23- 13804751380475. The invention relates to a light source, a light-emitting device, and a display device. [Prior Art] In recent years, a light-emitting element such as a light-emitting diode (LED) has been used. The light-emitting device has been variously put into practical use. Such a light-emitting device is widely used as a lighting device or a backlight of a liquid crystal panel. Further, for example, in a liquid crystal television or the like, an increase in the amount of light of a light source such as a backlight is required as the size of the screen increases. In order to achieve an increase in the amount of light of the light source such as the backlight of the light-emitting element, there is a method of using a large-sized light-emitting element or increasing the number of light-emitting elements. The amount of light emitted from the light-emitting element increases as the size of the element increases, but in general, the light-emitting element of a large-sized light-emitting element has a low luminous efficiency. That is, in the case of a large-sized light-emitting element, a uniform current flows into the light-emitting element, and the area of the electrode pad provided in the light-emitting element has to be increased. At this time, the electrode pad itself has a characteristic of absorbing light emitted from the light-emitting element, and the larger the area of the electrode pad, the larger the amount of light absorbed by the electrode pad. On the other hand, when the number of light-emitting elements is increased, for example, in order to obtain the same amount of light emission as that of a large-sized light-emitting element, it is necessary to provide a larger number of light-emitting elements than a large-sized light-emitting element. At this time, the installation cost of the light-emitting element such as the mounting substrate may become high, resulting in an increase in the cost of the product. In the meantime, as a measure for reducing the number of mounting of the light-emitting elements of the mounting substrate, there is a method in which a plurality of light-emitting elements are collectively packaged. In this case, in one package, the light-emitting elements may be electrically parallel or plural, or may be in-line connection. Here, when the in-line connection method is used, the driving voltage of one package needs to be improved as compared with the method of parallel connection, and the driving voltage of the light-emitting device having most of the packages is further improved. On the other hand, in the prior art described in the publication of a plurality of light-emitting elements connected in parallel, a light source of a plurality of light-emitting elements electrically connected in parallel is disclosed, for example, a technique used in the above-described backlight device (for example, a reference patent) Literature 1). Furthermore, it is disclosed that in order to electrically connect a plurality of light-emitting elements in parallel, in order to make the variation of the forward voltage of the plurality of light-emitting elements within 0. IV, a technique for distinguishing the light-emitting elements is used in advance (for example, refer to a patent) Literature 2). [Patent Document 1] JP-A-2007-13472 (Patent Document 2) Japanese Laid-Open Patent Publication No. JP-A No. 2006-222412 [Draft of the Invention] [Problems to be Solved by the Invention] However, electrical characteristics such as impedance 値 are used. When a plurality of staggered light-emitting elements are electrically juxtaposed, among the light-emitting elements having the lowest impedance of the light-emitting elements, more current flows into the other light-emitting elements. The amount of light of the light-emitting element is generally proportional to the current, and the unevenness of the amount of current flowing between the plurality of light-emitting elements connected to the -5 to 1380475 is a variation in the amount of light between the plurality of light-emitting elements. doubt. Further, in the light-emitting element having the smallest impedance ,, the load is concentrated, and the life of the light-emitting element may be significantly shortened, so that the reliability as a light source is lowered. The present invention has been made to solve the above problems, and an object of the invention is to provide a light source or the like which can suppress unevenness in the amount of light generated between a plurality of light-emitting elements when a plurality of light-emitting elements are connected in parallel. [Means for Solving the Problem] For the purpose of the present invention, a light source suitable for use in the present invention includes: a plurality of light-emitting elements; a parallel connection means electrically connecting the plurality of light-emitting elements in parallel; and each of the light-emitting elements constituting the plurality of light-emitting elements The element includes: an element substrate; and a first layer directly laminated on the element substrate formed by the group III nitride compound semiconductor; and a rocking curve of the (0002) plane directly laminated on the first layer The half-turn width is less than lOOarcsec, and the rocking curve of the (10-10) plane has a half-width of 25 arCSec. In this case, the layer of the second layer is characterized by a (0002) plane lacking wobble line half 1 width of _60 arcsec or less, and a (10-10) plane rocking curve having a half-turn width of 250 arccec or less of a group III nitride compound semiconductor. It is preferable that the light-emitting elements of the plurality of light-emitting elements connected in parallel are electrically suppressed, for example, the impedance 値, etc., in which the parallel connection means is mounted with the plurality of light-emitting elements. An An-6-1380475 package that forms a power supply path for the plurality of light-emitting elements is characterized. Further, in such a light source, the first layer is characterized by having a layer thickness of 21 nm or more and 40 nm or less. At this time, the first layer is characterized by a sputtering method. Further, the element substrate is a sapphire substrate, the first layer is A1N, and the second layer is GaN. Furthermore, the light source further includes: a plurality of other light-emitting elements different from the plurality of light-emitting elements; and another parallel connection means electrically connecting the other plurality of light-emitting elements in parallel; and electrically connecting the parallel connection The means for connecting the means to the other parallel connection means are characterized. Then, the present invention is made to be a light-emitting device. A light-emitting body having a plurality of light-emitting elements and a first power supply path electrically connected to the plurality of light-emitting elements in parallel, and a plurality of the light-emitting bodies mounted and mounted on the first one of the respective light-emitting bodies a mounting substrate of the second power supply path electrically connected to the power supply path; and each of the light-emitting elements constituting the plurality of light-emitting elements includes an element substrate and a layer directly laminated on the element substrate of the bismuth nitride compound semiconductor The first layer and the layer directly layered on the first layer, the rocking curve of the (〇〇〇2) plane has a half-width of less than 100 secsec, and the rocking curve of the (1 0 -1 0) plane has a half-width of 250 arcsec or less. The group III nitride compound semiconductor is formed into the second layer. In this case, when a plurality of illuminants are arranged on the mounting substrate at equal intervals, it is preferable to suppress unevenness in the amount of light as a whole of the light-emitting device. -7- 1380475. When the present invention is used as a display device, the display panel including the display image and the display device provided on the back surface of the display panel and illuminating the display panel with light are provided with the backlight: a plurality of light-emitting elements, and an illuminant electrically connected to the first power supply path of the plurality of light-emitting elements, and a plurality of the illuminants provided, and the first power supply path provided in each of the illuminants a mounting substrate of the second power supply path electrically connected; each of the light-emitting elements constituting the plurality of light-emitting elements includes an element substrate and a first layer directly laminated on the element substrate of the group III nitride compound semiconductor The layer and the layered directly on the first layer, the (0002) plane has a half-turn width of less than 100 arcsec, and the (10-10) plane has a rocking curve of a group III nitride compound semiconductor having a half-width of 25 Oarcsec or less. The second layer. In the display device of the present invention, the plurality of illuminants constituting the plurality of illuminants are electrically connected to each other, and a plurality of connecting conductors forming a plurality of illuminant groups and a plurality of connecting conductors constituting the plurality of illuminants are formed. For each of the connecting conductors, a plurality of power sources that supply power are characterized. [Effect of the Invention] According to the present invention, it is possible to provide a light source or the like which generates unevenness in the amount of light generated between a plurality of light-emitting elements when a plurality of light-emitting elements are electrically connected in parallel. [Embodiment] 1380475 Hereinafter, with reference to the drawings, The best mode for carrying out the invention (hereinafter referred to as the embodiment) will be described. [Embodiment 1] Fig. 1 is a view showing the overall configuration of a liquid crystal display device to which the present embodiment is applied. However, in Fig. 1, the vertical direction V and the lateral direction 液晶 of the liquid crystal display device are indicated by arrows. The φ liquid crystal display device includes a liquid crystal display module 50 and a backlight device (backlight) 40 provided on the back side of the liquid crystal display module 50 (the lower side in Fig. 1). The backlight unit 40 that operates as a light-emitting device includes a backlight housing (frame) 41 that houses a light source, and a light-emitting unit 42 that arranges a plurality of light-emitting diodes (hereinafter referred to as LEDs). In addition, the backlight device 40 is provided with a laminate which is a laminate of an optical film, and which is a material which is light-transmissive, and which is a material which makes the entire surface uniform and bright, and diffuses and diffuses the light. The film) and the prism sheets 44, 45 of the diffraction grating film having the condensing effect toward the front. Further, if necessary, a diffusion/reflection type brightness enhancement film 46 for improving the brightness is provided. On the other hand, the liquid crystal display module 50 is provided with a liquid crystal panel 51 which is formed by holding liquid crystal via two glass substrates, and a glass substrate which is laminated on each of the liquid crystal panels 51, and which restricts light wave vibration to a certain direction. 53, 53. Further, in the liquid crystal display device, peripheral members such as a driving LSI (not shown) are mounted. The liquid crystal panel 51 which is one of the display panels is composed of 1,380,475 constituent elements (not shown). For example, two glass substrates include a display electrode (not shown), an active element such as a thin film transistor (TFT: Thin Film Transistor), a liquid crystal, a spacer, a sealant, an alignment film, a common electrode, a protective film, and a color filter. Light sheet and so on. However, the constituent unit of the backlight device 40 can be arbitrarily selected. For example, the unit of the backlight housing 41 having only the light-emitting unit 42 is referred to as a "backlight device (backlight)", and may have a flow pattern that does not include the diffusion plate 43, the ruthenium sheets 44, 45, and the brightness enhancement film 46. FIG. 2 is a view showing the configuration of the backlight frame 41 and the light-emitting unit 42 of the backlight device 40 as a light-emitting device, and the backlight device 40 is viewed from the 50 side (upper side) of the liquid crystal display module shown in FIG. Get the picture. The backlight housing 41 is formed, for example, in a frame structure formed of aluminum or magnesium, iron, or a metal alloy containing the same. Then, on the inner side of the frame structure, for example, a polyester film having a white high reflection property or the like is attached, and it can also be operated as a reflector. This frame structure has a back surface portion corresponding to the size of the liquid crystal display module 50, and a side surface portion surrounding the four corners of the back surface portion. Further, in the back surface portion or the side surface portion, a fin structure formed by cooling fins for preheating or the like is formed as needed. Further, a plurality of LED packages 20 (described later) constituting the light-emitting unit 42 are provided on the back surface portion of the backlight housing 41, and are connectors (not shown) for supplying power. The light-emitting unit 42 is provided with eight light-emitting modules 30. Then, the eight light-emitting modules 30 are disposed on the back surface portion of the backlight housing 41 in two rows in the longitudinal direction V and four rows in the lateral direction. Figure 3 (a)'(b) is a diagram of -10-1380475 illustrating the illumination module 30. Figure 3 (a) is a top view of the light-emitting module 30, and Figure 3 (b) is a side view of the light-emitting module 30 as seen from the arrow A shown in Figure 3 (a). Further, in Fig. 3(b), a partial cross-sectional view of the LED package 20 is shown. The light-emitting module 30 is provided with a plurality of (120 in this example) LED packages 20 and a module substrate 31 as a mounting substrate. The LED package 20 which operates as a light source and an illuminator has a plurality of φ LED chips 10 (described later) for emitting white light. Then, the plurality of LED packages 20 are arranged on the module substrate 31 as shown in Fig. 3(a), and are arranged in 12 columns in the longitudinal direction V and 10 columns in the lateral direction. Further, in the light-emitting module 30 of the present embodiment, the plurality of LED packages 20 disposed on the module substrate 31 have the interval between the LED packages 20 adjacent to the vertical direction V set to be nearly equal (here) In the example, about 1 inch), and the interval between the LED packages 20 adjacent to the lateral direction is set to be nearly equal (about 1 inch in this example). Therefore, on the module substrate 31, φ 120 LED packages 20 are arranged in a nearly lattice shape. However, the plurality of LED packages 20 may be arranged at equal intervals on the module substrate 31. For example, the adjacent three LED packages 20 may be arranged in a substantially equilateral triangle. Further, in one of the light-emitting modules 30, the distance from the outermost LED package 20 to the end portion of the module substrate 31 is designed to be shorter than 1/2 inch. With such a setting, as shown in FIG. 2, when eight light-emitting modules 30 are mounted on the backlight housing 41, the distance between the adjacent LED packages 20 in the longitudinal direction V and the horizontal direction may be arranged. Equal (about 1 inch in this example -11 - 1380475) In fact, in the light-emitting unit 42 of the present embodiment, 960 (120x8) LED packages 20 are used to make the adjacent LED packages 20 longitudinally V The intervals in the lateral direction are arranged to be nearly equal, and the backlight housings 4 1 are arranged in a nearly lattice shape. The module substrate 31 is mounted with a plurality of LED packages 20 as described above. The base material of the substrate 31 for a module can be, for example, a so-called glass epoxy resin in which a glass fiber is impregnated with an epoxy resin. Further, as shown in Fig. 3 (b), an electrical wiring pattern 32 for supplying power to the LED package 20 is formed on the surface of the module substrate 31 on which the LED package 20 is mounted (hereinafter referred to as a mounting surface). Then, on the mounting surface of the module substrate 31, the electrical wiring pattern 32 and the LED package 20 are electrically connected via solder, and the light from the LED package 20 is mounted on the mounting surface of the module substrate 31. It is reflected and formed with a white photoresist. Further, as shown in FIG. 3(a) and FIG. 3(b), the module substrate 3 1 is provided with a screw hole 3 6b for attaching the light-emitting module 30 to the backlight housing 4 1 . Then, the module substrate 31 is placed on the backlight housing 41 by using a screw 36a and a portion of the screw hole 36b. . . . Then, in one of the light-emitting modules 30, as shown by a broken line in Fig. 3(a), a light-emitting block 300 serving as a light-emitting control unit is formed. The light-emitting block 300 as an illuminant group is an LED package 20 having a total of 12 columns in the vertical direction V6 column and the horizontal direction H2 column. Then, in the light-emitting module 30, the light-emitting block 300 is provided with two rows arranged in the longitudinal direction V and five columns in the horizontal direction. -12- 1380475 However, in the present embodiment, the electrical wiring pattern 32 provided on the module substrate 31 operates as the second power supply path and the connection conductor. 4(a) and (b) are diagrams for explaining the LED package 20. 4 is a top view (light emitting surface side) of the LED package 20, and FIG. 4(b) is a sectional view taken along line IV-1V of FIG. 4(a). The LED package 20 emits white light having three primary colors of red (R), green (G), and blue (B). Then, as shown in Fig. 4(a), the LED package 20 includes three LED chips 10, a positive lead frame 291, a negative lead frame 292, and a case 293 which is a mounting body. Each of the LED chips 10 is a blue LED that emits blue light. Further, in the present embodiment, the size of the LED wafer 10 is 350/zm square, and the thickness is 80//m. Then, in the LED package 20, the three LED chips 丨0 are electrically connected in parallel. However, the structure and the like of the LED chip 1 will be described in detail later. The positive lead frame 291 and the negative lead frame 292 are produced by knocking off the metal plate in an E shape as shown in Fig. 4 (a). Then, as shown in Fig. 4 (b), the positional relationship between the positive electrode lead frame 291 and the negative electrode lead frame 292 is fixed via a casing 293 made of a white resin or the like. Then, the three LED chips 10 are mechanically mounted on the respective lead frames 291 for positive electrodes via solder. Further, the positive electrodes (described later) of the three LED chips are electrically connected to the lead frames 291 for the respective positive electrodes via wire bonding, and the negative electrodes (described later) of the three LED chips 10 are electrically connected to each other via wire bonding or the like. A lead frame 292 for each negative electrode. Thus, the three LED chips 10 of the -13-1380475 LED package 20 are electrically connected. However, in the present embodiment, the lead frame lead frame 292 for the positive electrode is used as a parallel connection means or as the first operation. Further, in the side of the positive electrode lead frame 291 and the negative electrode lead frame LED wafer 10, each of them is provided with a lead; 2 92a (see Fig. 4 (b)). Then, the lead wires are connected to the electrical wiring patterns of the module substrate 31, and the LED packages are mechanically connected to the module substrate 31. Further, as shown in Figs. 4(a) and 4(b), reflective walls 27 are provided around the three. This reflective wall 27 is reverse! The light irradiated by 10 is efficiently irradiated from the LED chip toward the diffusion plate 43 (see Fig. 1) inside the reflection wall 27, and the three LED wafers 10 are sealed with the resin 28. Then, in the present embodiment, a phosphor that emits green light is emitted by adding light of a phosphor that emits blue light and emits red light. 5(a) to 5(c) show the shape of the LED package 20, and other figures are described. 5(a) to (the package 20 is substantially the same as the shape of the lead frame 29 1 and the negative lead frame 292 of FIG. 4(a), which is different from the same shape as the LED package 20 described with reference to FIG. 4(a). The same reference numerals will be omitted, and the detailed description will be omitted. J is connected. 2 9 1 and the power supply path for the negative electrode are added 292, and the terminals 291a and 291 are not connected to the terminals 291a and 32, and the soldering connection can be used to make the LED chip 10 payable. The light emitted from the LED chip 10 is further embedded in the resin, and the LED shown in the form c) of the blue lead frame is received, but the positive electrode is used. However, the pair of parts is attached to -14-380,475. The example of the LED package 20 shown in Fig. 5 (a) is provided with a lead frame 291 for a positive electrode having a convex shape, and a lead frame 292 for a negative electrode having a concave shape. Then, 1 The LED chips 10 are attached to the protruding portions of the positive electrode lead frame 291, and the other two LED chips 10 are attached to portions other than the protruding portions of the positive electrode lead frame 291. Then, in the same manner as in the above example, the LED chip 10 is electrically connected to the lead frame, and the three LED chips 10 are connected in parallel. Next, in the example of the LED package 20 shown in Fig. 5 (b), the positive electrode lead frame 291 and the negative electrode lead frame 292 have rectangular shapes. Further, each lead frame is held at a specific distance and arranged almost in parallel. Then, the three LED chips 10 are mounted on the positive lead frame 291, and the three LED chips 10 are connected in parallel as in the above example. Further, the LED package 20 shown in Fig. 5(c) has a lead frame 291 for a positive electrode having an L shape and a lead frame 292 for a negative electrode having a square shape accommodated on the inner side of the L shape. Then, the three LED chips 1.0 are mounted along the L-shape of the lead frame 291 for the positive electrode having an L shape and held at a predetermined interval. Then, similarly to the above example, in this example, the three LED chips 10 provided in the LED package 20 are connected in parallel. FIG. 6 is a diagram for explaining the electrical connection of the light-emitting module 30. Here, a single light-emitting module 30 is taken as a representative example, but for other light-emitting modes provided in the backlight device 40. The group 30 is also the same. Further, the frame shown by the broken line in Fig. 6 shows the light-emitting block 300, and the frame shown by the one-point chain lock line is equivalent to the unit of one LED package 20" -15 - 1380475 First, In the LED package 20 shown by the one-point chain lock line in Fig. 6, the three LED chips 10 are connected in parallel. As described above, the parallel connection of the three LED chips 10 is realized by the lead frames 291, 292. Then, in the light-emitting block 3 00 shown by a broken line in Fig. 6, the 12 LED packages 20 are connected in series. The in-line connection of the 12 LED packages 20 is realized by the electrical wiring pattern 32 provided on the module substrate 31. Further, as shown in FIG. 6, in each of the light-emitting blocks 300 (the 12 LEDs connected in series) Package 20), each set of separate power supply Ρ. Then, the twelve LED packages 20 are connected to the power source P by an electrical wiring pattern 32 or the like. Next, the light-emitting operation of the backlight device 40 (see Fig. 1) will be described. In each of the light-emitting modules 30 of the backlight device 40, an upper voltage is applied to the 12 LED packages 20 directly connected to each of the light-emitting blocks 300 via the respective power sources P. Then, in each of the 12 LED packages 20 of each of the light-emitting blocks 300, current flows in each. At this time, in each of the LED packages 20, current flows in the three LED chips 10 connected in parallel with each other. Then, as a result of the respective currents flowing into the three LED chips 10, the LED chip 10 emits blue light. At this time, a part of the blue light emitted from the LED wafer 10 is converted into red or green via the phosphor added to the sealing resin 28. As a result, white light containing red (R), green (G), and blue (B) light is emitted from one LED package 20. Then, in other light-emitting blocks 300, and in other light-emitting modules -16-1380475 30, white light containing red (R), blue (B) light is also emitted from the LED package 20. Then, the light is mixed in the body 41, and is irradiated onto the diffusion plate 43. Further, after the color mixture is promoted by diffusion, the liquid crystal display module 50 is irradiated, and as described above, the backlight package of the embodiment is applied. Each of the light-emitting blocks 300 is provided with a power source P. Through the source P, lighting can be independently performed for each of the light-emitting blocks 300. Therefore, when the image is displayed on the liquid crystal display device, the so-called area control such as light emission on the back side where the black image is displayed in the image can be displayed. Further, in the LED package 20, three wafers are disposed by dispersion; for example, the wafer 10 can be controlled to have a temperature rise as compared with a wafer having a large size of 5500/zm square in the LED package 20. However, for example, In the liquid crystal display device of the embodiment, a large number of LED chips 10 are required for a specific light source of a device having a large light-emitting area. In this case, the LED package 20 of the applicable state is wound around the three LED chips 10, and the mounting work for the substrate or the like to be mounted is reduced, for example, and the three LED chips 1 provided in the LED package 20 are connected. Therefore, in the LED package 20, the driving voltage can be suppressed as compared with the case of the in-line L E D wafer 1 . Then, it can be suppressed as a backlight device 40' or even as a liquid crystal display device. Then, in the above LED package 20, for the electrical green (G) in the backlight frame 43 or the like, the control of each electric light is controlled to extinguish the LED crystal of the block 300 (for example, 〇 The amount of backlighting (the brightness of this embodiment can be up to 1/3. 〇 is connected in parallel with the three, along with the drive voltage column connected -17- 1380475 LED chip 1 〇 composition to illustrate) Figure 7 is A schematic view of the LED chip 10 is shown in Fig. 7. As shown in Fig. 7, the LED wafer 10 includes a substrate 11 which is a substrate substrate, a seed layer 12 which is a first layer, and a Ga-containing layer which is a group III element. The group nitride semiconductor compound is formed into the semiconductor layer 100. Then, on the seed layer 12, the respective layers of the n-type semiconductor layer 14, the light-emitting layer 15, and the p-type semiconductor layer 16 are laminated in this order. Thus, the semiconductor layer 1 is formed. <Substrate> The substrate 1 to which the LED wafer 10 of the present embodiment is applied is made of sapphire as a material which can be used as the material of the substrate 11, as long as the bismuth nitride compound semiconductor can be crystallized, and epitaxial The substrate material that grows on the surface does not need to be specially <Seed Layer> The seed layer 12 is formed on the c-plane of the substrate 11 (sapphire substrate). In the embodiment of the present embodiment, the seed layer 12 is an A1N material, and is used as a material which can be used for the seed layer 12. As long as it is a group III nitride compound semiconductor Paco, as a group III element, it may be contained in Ga or In, but it is preferable to have a composition containing A1. Also, as a material of the seed layer 12, GaAIN may be used. In this case, it is preferable that the composition of A1 is 50% or more. Further, the seed layer 12 is at least 60% or more of the surface of the substrate 11 to be coated, preferably 80% or more, and more than 90% of the coating is formed to be more -18- Further, it is preferable that the seed layer 12 is formed by coating the surface of the substrate 11 by 100% 'that is, the surface of the substrate 11 is not covered with a gap. The surface of the seed layer 12 covering the substrate 11 becomes small. In a state of being largely exposed, at this time, the lattice constant of the underlying layer 14a formed on the seed layer 12 and the underlying layer 14a directly formed on the substrate 11 may be different, and it may not become a uniform crystal, and a turtle may be produced. Crack or pit. Also, the seed layer 12 is a base. The surface of the 11 may be formed by coating the side surface, and may be formed on the back surface of the substrate 11. However, in the present embodiment, the film thickness of the seed layer 12 of the LED wafer 1 is set to converge to 21 nm. The above range of 40 nm or less. <Semiconductor layer><n-type semiconductor layer> The n-type semiconductor layer 14 is composed of a base layer i4a laminated on the seed layer 12, and an n-type connection laminated on the base layer 14a. The layer 14b is formed of an n-type cladding layer He laminated on the n-type connection layer Mb. <Base layer> The base layer 14a as the second layer is made of GaN. The material of the underlayer 14a may be the same as or different from the seed layer 12, but it is preferable to include a Group III nitride compound semiconductor containing Ga, that is, a GaN-based compound semiconductor. The layer is made of AlxGai.xN (OSxSi' is preferably 〇$xs 〇5, better for OSxSO.l) is better. Further, as a result of the experiment of the present inventors, -19 to 1380475, as a material for the underlayer 14a, a Group III nitride compound semiconductor containing Ga, that is, a GaN-based compound semiconductor is preferable. In the underlayer 14a, if necessary, the n-type impurity may be doped in the range of lxlO17 to lx 1019/cm3, or may be undoped (<1χ1017/cm3), and undoped. It is preferred to maintain good crystallization. For example, when the substrate 11 is electrically conductive, it is electrically conductive by doping a dopant with the underlying layer 14a, and an electrode can be formed above and below the LED wafer 10. On the other hand, when an insulating material is used as the substrate 11, the wafer structure of each of the positive electrode and the negative electrode is formed on the same surface of the LED wafer 10. The layer immediately above the substrate 11 is an undoped crystal. It is preferable to obtain good crystallinity. The n-type impurity is not particularly limited, and examples thereof include Si, Ge, and Sn, and examples thereof include Si and Ge. Moreover, as the film thickness of the base layer 14a, it is set to 6/zm. However, the thickness of the underlayer 14a is not particularly limited, but is generally 0.5; the range of am~20/zm is preferably. When it is less than 0.5/m, there is a case where the circle of the transposition is insufficient. When the 20 # m is large, there is no significant change in the function, but the processing time is prolonged. Therefore, it is preferably in the range of l/zm to 15 from m. < n-type connection layer> The n-type connection layer 14b is Si-doped GaN having a thickness of 2 y m of an electron concentration of 1 x 1 〇 19 / cm 3 . -20- 1380475 However, the n-type connection layer 14b is not particularly limited, and the n-type connection layer 14b is the same as the under layer 14a, and is composed of an AlxGai_xN layer (OSxS1, preferably OSxSO.5, more preferably OSxSO.l) is better. Further, in the n-type connection layer 14b, it is preferable to dope the n-type impurity, and when the type 11 impurity is 1><1〇17~1><1〇19/£; „13, more preferably 1> When the concentration of <10丨8~1 xlO19/cm3 is contained, it is preferable to maintain the contact with the good electrical property φ of the negative electrode, suppress the occurrence of cracks, and maintain the good crystallinity. The n-type impurity is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge». However, the group III nitride compound semiconductor constituting the underlayer 14a and the n-type connection layer 14b has the same composition. Preferably, the total film thickness is set to 〇5 to 20/im, preferably set to 1 to 15 μm, more preferably set to 1 to 10; zm. When the film thickness is within this range, The crystal of the semiconductor can be favorably maintained. <N-type cladding layer> Preferably, the n-type cladding layer 14c is provided between the n-type connection layer 14b and the light-emitting layer 15. By providing the n-type cladding layer 14c, The effect of the electron supply of the active layer, the relaxation of the difference in lattice constant, etc. In the present embodiment, the n-type cladding layer Ik has a value of xl〇u/cm3. Ino.iGao.9N having a thickness of 20 nm is used. However, the n-type cladding layer 14a is not limited thereto, and may be formed by AIGaN, GaN 'GalnN, etc. Further, a heterostructure which can be constructed for this purpose-21 - 1380475 Super-lattice structure in which a plurality of layers are laminated. When the n-type cladding layer 14c is GalnN, it is preferable that the In concentration of GalnN of the well layer is lower. Further, the n-type of the n-type cladding layer 14c The doping concentration is preferably in the range of ΙχΙΟ17 to lxlO2G/cm3, and more preferably in the range of ΙχΙΟ18 to lxlO19/cm3. When the doping concentration is in this range, the good crystallinity is maintained and the operating voltage of the light-emitting element is maintained. However, although the n-type connection layer can also serve as a base layer and/or an n-type cladding layer, the base layer can also serve as an n-type connection layer, and/or an n-type layer. Coating layer <Light-emitting layer> The light-emitting layer 15 is laminated on the n-type semiconductor layer 14, and the layer on which the p-type semiconductor layer 16 is laminated is a multi-quantum well structure. A single well structure, a bulk structure, etc. In the present embodiment, the light-emitting layer 15 is as shown in FIG. The barrier layer 15a formed by the group II nitride compound semiconductor and the well layer 15b formed of the group III nitride compound semiconductor containing indium are formed on the side of the n-type semiconductor layer 14 and the p-type-semiconductor layer (5 _ Γ , ΙΒ 障 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层The barrier layer 15a is disposed in the uppermost layer and the lowermost layer, and is configured as a multiple quantum well in which the well layer 15b is disposed between the barrier layers 15a. In the present embodiment, the barrier layer 15a is GaN having a thickness of 16 nm. For this barrier layer 15a, for example, a group III nitride compound semiconductor such as AlcGai_eN (0Sc < 0.3) can be used. -22- 1380475 And 'well layer 15b is a layer of Innm.2Ga〇.8N with a thickness of 3nm. Further, in the well layer 15b, 'as a group III nitride compound semiconductor containing indium, for example, gallium indium nitride such as Gai.sInsNCiXsCO.O can be used. <P-type semiconductor layer> The P-type semiconductor layer 16 is composed of a p-type cladding layer 16a and a p-type connection layer 16b. Further, the p-type connection layer can also be constructed as a p-type cladding layer. <P-type cladding layer> The P-type cladding layer 16a is made of Mg-doped AlmGao.gsN, and the film thickness is 5 nm. As the p-type cladding layer 16a, AUGauNCiXdSOJ, preferably O.lSd Xin 0.3) can be cited. When the p-type cladding layer 16a is formed of such AlGaN, it is preferable that the carrier of the light-emitting layer 15 is closed. The p-type doping concentration of the φ P-type cladding layer 16a is preferably ΙχΙΟ18~lM〇2i/cm3, more preferably 1χ1〇19~lx102Q/cm3. When the p-type dopant concentration is in the above range, crystallinity does not decrease, and good p-type crystals can be obtained. The p-type impurity is not particularly limited, and for example, Mg is preferably used. <P-type connection layer> The P-type connection layer 16b is doped with Mg of Alo.Q2Gao.98N, and the film thickness is 0.2/zm. As the p-type connection layer 16b, it is at least contained by -23- 1380475

AleGa丨.eN(0Se<0.5，較佳爲 OSeSO.2，更佳爲 OSe SO.1)所成III族氮化物化合物半導體。A1組成在上述 範圍之時，在於良好結晶性之維持及透光性電極17)( 後述）良好之電性接觸之層面上爲較佳。 又’P型連接層16b，使P型掺雜劑以lxio18〜 1 χΙΟ21個/cm3之範圍濃度而含有時，在於良好之電性連接 之維持’龜裂產生之防止，良好之結晶之維持的觀點上爲 較佳，更佳者爲5M019〜5xl〇2Q個/cm3之範圍。做爲p 型不純物雖未特別加以限定，例如較佳可列舉Mg。 然而，構成本發明之LED晶片10之半導體層1〇〇乃 非限定於上述實施形態者。 做爲半導體10 0之材料，除了上述者之外，例如有以 —般式 AlxGayInzNi-AMA ( 0SXS 1、os YS 1、OS 1 且X+Y+Z=l。記號Μ爲表示除了氮（N)之外之第V 族元素，0SA<1。）所示之III族氮化物化合物半導體 爲眾所周知’於本發明中，此等周知之III族氮化物化合 物半導體可無限制地加以使用。 _又，做爲n iH秦’含Ga之ΊΐΙ族—處一化初花合物半 導體乃除了 Al、Ga及In以外，可含有其他之in族元素 ，依需要可含有 Ge、Si、Mg、Ca、Zn、Be、P、As 及 B 等之元素。更且，不限於有意圖添加之元素，有包含關連 於成膜條件等，必然含有之不純物，以及原料，或含於反 應管材質之微量不純物之情形。 -24- 1380475 <透光性正極> 透光性正極17乃具有形成於p型半導體層16上之透 光性的電極。 做爲透光性正極1 7之材質，未特別加以限制，可使 用 ITO ( ln2〇3-Sn02 ) 、AZO ( Zn0-Al203 ) 、IZO (A group III nitride compound semiconductor formed by AleGa丨.eN (0Se<0.5, preferably OSeSO.2, more preferably OSe SO.1). When the composition of A1 is in the above range, it is preferable that the crystallinity is maintained and the light-transmitting electrode 17) (described later) is in good electrical contact. Further, when the P-type dopant layer 16b is contained in a concentration range of lxio18 to 1 χΙΟ21/cm3, the P-type dopant is maintained in a good electrical connection, and the occurrence of cracking is prevented, and the maintenance of good crystals is maintained. Preferably, it is preferably 5M019~5xl〇2Q/cm3. The p-type impurity is not particularly limited, and for example, Mg is preferable. However, the semiconductor layer 1 constituting the LED wafer 10 of the present invention is not limited to the above embodiment. As the material of the semiconductor 100, in addition to the above, for example, AlxGayInzNi-AMA (0SXS 1, os YS 1, OS 1 and X+Y+Z=l. The symbol Μ indicates nitrogen except N (N) The group III nitride compound semiconductor represented by the group V element other than 0SA <1.) is well known in the present invention, and such well-known group III nitride compound semiconductors can be used without limitation. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Elements such as Ca, Zn, Be, P, As, and B. Further, it is not limited to the elements which are intended to be added, and includes impurities which are inevitably contained in the film forming conditions, and the like, and the raw materials or the trace impurities contained in the reaction tube material. -24-1380475 <Translucent positive electrode> The translucent positive electrode 17 is a translucent electrode formed on the p-type semiconductor layer 16. The material of the transparent positive electrode 17 is not particularly limited, and ITO (ln2〇3-Sn02), AZO (Zn0-Al203), and IZO (

In203-ZnO ) 、GZO ( ZnO-Ga202)等之材料。又，做爲透 光性正極17，則包含以往公知之構造，可不受任何限制 之使用任何之構造。 又，透光性正極17乃被覆p型半導體層16上之全面 加以形成亦可，開出間隙形成呈格子狀或樹形狀亦可。 <正極靜墊> 正極銲墊18乃形成於上述透光性正極17上之略圓形 之電極。 做爲正極靜墊18之材料，眾所周知有使用Au、A1、 φ Ni及Cu等之各種構造，可無任何限制使用此周知材料、 構造者。惟’需與GaN或ITO、IZO等造成結合，在Cr 、Ti等之氧化物以安定之金屬製作結合時，需有載置Au 等，成爲可打線之構造。 正極銲墊18之膜厚乃以100〜l〇〇〇nm之範圍內爲佳 。又，銲墊之特性上，爲厚者接合性爲高之故，正極銲墊 18之厚度成爲300nm以上者爲佳。更且，從製造成本之 觀點視之，50Gnm以下者爲佳。 -25- 1380475 <負極> 負極19乃接觸於構成半導體層100之η型半導體層 14之η型連接層14b。爲此，負極19乃如圖7所示，除 去P型半導體層16、發光層15及η型半導體層14之一 部分，於露出η型連接層14b之露出範圍14d上，形成呈 略圓形狀。 做爲負極19之材料，各種組成及構造之負極皆爲公 知者，可任意無限制使用此等之公知負極》 接著，對於LED晶片1 0之製造方法加以說明。 製造圖7所示LED晶片10時，首先，於基板11上 ，製作形成半導體層1 〇〇之層積半導體晶圓。製作層積半 導體晶圓時，首先準備基板11。基板11乃施以前處理之 後加以使用者爲佳。例如，使用藍寶石所成基板1 1時， 可使用進行周知之RCA洗淨方法等之濕式方法，將表面 進行氫終端之方法。由此，成膜製程則會安定。 又，於濺鍍裝置之處理室內配置基板11，於形成種 子層12前，經由濺鍍等之方法，進行前處理亦可。具體 而言，於處理室內，由蔣基被1 1曝露―於Ar或n m 漿中，可進行洗淨表面之前處理。將Ar氣體或N2氣體之 電漿，經由作用於基板11之表面，可除去附著於基板11 表面之有機物或氧化物。此時，於標靶不施加功率，在基 板11與處理室間，施加電壓時，電漿粒子可有效率地作 用於基板11。 於基板11進行前處理之後，經由濺鍍法，於基板11 -26- 1380475 上成膜種子層12。 形成於種子層12上之η型半導體層14之配 ' 子層12之狀態很大之影響。之前爲得結晶性高 12時，MOCVD法爲期望者。但是，MOCVD法 板11上，將分解之金屬堆疊之方法，最初會形 著於核之周圍成長結晶，進而成膜之故，在形成 12之薄膜時，會有均勻性不充分之情形。 φ 對此，濺鍍法乃可進行高密度之成膜之故， 之時，可生成均勻之膜之故，因而爲佳。因此， 12經由濺鍍法形成之時，可使基板11之表面上 覆而形成種子層12，更且可面內均勻形成種子層 後於面內均勻之種子層12上，成長結晶配向高;; 導體層14。 然而，本實施形態中，在濺鍍法中，採用難 靶表面充電上昇，成膜速度安定之RF (高頻）溺 φ 濺鍍法所成種子層12之成膜時之基板溫度 300〜800 °C。又，做爲濺鍍法之標靶，使用 Α1 於爐內之壓力與氮分壓而言，令爐內之壓力爲0. 。較此爲低之壓力時，氮之存量量變少，濺鍍之 成爲氮化物而加以附著。然而，有關壓力之上限 電漿可安定存在之程度，則不特別加以限定。 又，氮與氬之流量而言之氮流量比乃使設: 20%以上90%以下。在此以下之流量比時，濺 直接以金屬附著，另一方面，在此以上之流量比 向乃受種 之種子層 乃是在基 成核，接 如種子層 形成薄膜 令種子層 無間隙被 "2，然 艺η型半 以產生標 ;鍍法。 乃設定於 。又，對 3Pa以上 金屬不會 ，只要是 定氮成爲 鍍金屬會 時，氬以 -27- 1380475 量變少’會使得濺鍍速度下降。然而，做爲特別期望之條 件，做爲氮流量之比，可列舉令氮爲3 0 %以上90 %以下 者。 做爲氮原料，一般所周知之化合物則可無疑問地加以 使用’尤其令氮爲原料使用之時，裝置雖可簡化，但難以 得高的反應速度。但是，本實施之形態中，則使用N2。 即使爲N2亦可得可利用程度之成膜速度，考量裝置成本 之兼顧時，最好爲氮源者。 於本實施之形態中，將C面藍寶石基板導入至濺鍍裝 置，於處理室內，將基板加熱至500°C，將氮氣以4〇Sccm 之流量導入。之後，將處理室內之壓力保持在2.OPa，於 基板側施加100 W之高頻偏壓，經由在氮電漿曝露15秒 ，洗淨基板表面。 接著，將標靶與基板之距離調整爲60mm，導入氬與 氮氣體，將基板溫度加熱至5 00 °C，之後，施加特定輸出 之高頻功率於標靶側，將爐內壓力保持於l.OPa，以氬氣 lOsccm，氮氣30sccm之流通條件（對氣體整體而言，氮 之比爲75% )，於藍寶石基板c面上，開始A1N層之成 膜。然後，成膜A1N於特定時間後，停止電漿之發動， 使基板溫度下降。 將成膜有由濺鍍裝置取出之種子層12之基板11，導 入至MOCVD爐，經由以下之方法，進行η型半導體層14 (GaN層）之成膜。 首先，在配置於M0CVD爐內之加熱用之碳製承受器 -28- 1380475 上’放置基板，於MOCVD爐內流通氮氣之後，啓動加熱 器，將基板溫度昇溫至1150 °C。氨量乃調整至V族元素 /III族元素比爲6000。接著，將含三甲基鎵（TMG)之蒸 氣之氫，供給至MOCVD爐內，開始對於基板上之GaN層 之成膜。在約1小時下，以非摻雜進行6/zm膜厚之GaN 之成長後，終止原料之MOCVD爐的供給，而停止成長。 之後，停止對加熱器之通電，將基板溫度降溫至室溫。然 而，取出之基板乃成爲無色透明之鏡狀。 於之後種子層12之成膜基板11上，如圖7所示，將 基底層14a與η型連接層14b與η型包覆層14c所成η型 半導體層14、由障壁層15a、井層15b所成發光層15、ρ 型半導體層16p型包覆層16a及p型連接層16b，以可結 晶性良好形成之MOCVD法（有機金屬化學氣相成長法） 加以成膜。 然而，MOCVD法中，做爲載體氣體使用氫（H2)或 氮（N2 )、做爲III族原料之Ga源，使用三甲基鎵（ TMG )或三乙基鎵（TEG )，做爲A1源，使用三甲基鋁 (TMA )或三乙基鋁（TEA )、做爲In源使用三甲基銦 (TMI)或三乙基銦（TEI)、做爲V族原料之N源使用 氨）、聯胺等。 又，摻雜劑之η型不純物中，做爲Si原料可利用單 矽烷（SiH4)或二矽烷（Si2H6)，做爲Ge原料，可利用 鍺氣（GeH4)，或四甲基鍺（（CH3)4Ge)或四乙基鍺（ (C2H5)4Ge)等之有機鍺化合物。 -29- 1380475 摻雜元素之P型不純物中，做爲Mg原料， 雙環戊二烯鎂（ChMg)或雙乙基環戊二烯鎂（ )β 於如此所得圖7所示之半導體層100之ρ 16b上，使用光微影法，順序形成透光性正極1 銲墊18。 接著，將透光性正極17及正極銲墊18之形 體層100，經由乾蝕刻，形成η型連接層14b上 圍 1 4 d 〇 之後，於露出範圔14d上，經由使用光微影 負極1 9，可得圖7所示LED晶片1 0。 然而，本發明之LED晶片10之製造方法乃 述之例者，例如半導體層1 〇〇之成膜乃可以i MOCVD (有機金屬化氣相層積法）、HVPE (鹵 層積法）、MBE (分子線磊晶法）等之可使半導 之任何方法加以組合進行。 接著，對於種子層12之膜厚與基底層14a 加以說明》 圖8乃對於複數之LED晶片之樣本，顯示I 之膜厚與基底層14a之搖擺曲線半値寬度之關係 ，搖擺曲線半値寬乃評估基底層14a等之配向程 之一。 在此，半導體層1〇〇乃順序於基底層14a層 接層14b、於η型連接層14b上層積η型包覆層 例如使用 'EtCp2Mg 型連接層 7及正極 成之半導 之露出範 法，形成 不限於上 賤鍍法、 化物氣相 體之成長 之結晶性 重子層12 圖。然而 度之指標 積η型連 14c、於 -30- 1380475 η型包覆層14c上層積發光層15、p型半導體層16。因此 • ，基底層14a之結晶之配向性爲良好之時，半導體層100 ' 之結晶性會變好，基底層14a之結晶之配向性爲不佳之時 ，半導體層1〇〇之結晶性會變差。 又，基底層14a (A1N)之結晶構造乃呈最密塡充構 造，（10-10)面乃相當於垂直於基底層14a之結晶之基 板面的面。基底層14a之結晶乃於基板面，六角柱垂直成 φ 長之構造。例如，基底層14a之結晶之六角柱在平面內， . 以相同朝向整齊配置時，不會有間隙，但是只要些微不同 ，在六角柱與六角柱間會產生間隙。此間隙乃顯示結晶之 配向程度者，相當於貫通換位者。因此，於基底層14a中 ，不單是平行於基板面之（〇〇〇2)面，垂直於基板面之（ 1 0-1 0 )面之結晶配向性亦需滿足特定之條件。 更且，此基底層14a層積於種子層12上之故’基底 層14a之結晶配向性乃大大受到種子層12之結晶狀態之 φ 影響。 在此，本發明人等乃進行各別改變形成於基板11上 之種子層12之厚度，更且準備在於其上形成基底層14a 之6種樣本，將各樣本之基底層14a之結晶面，經由搖擺 曲線法加以測定的實驗。 具體而言，做爲滿足適用本實施之形態之種子層12 之膜厚條件（21nm〜40nm者）’製作了樣本A1、樣本 A2、樣本A3及樣本A4。又，相較之下，亦製作不滿足 適用本實施之形態之種子層1 2之膜厚條件之樣本B 1及樣 -31 - 1380475 本B2。對於此等之樣本之種子層12之成膜條件及膜厚， 示於如下。然而，此等之樣本乃除了使種子層12之成膜 條件（或膜厚）呈不同之外，所有根據上述之製造方法加 以製作。 [表1] 種子層12 樣本 測鍍輸出(W) 成膜時間(Sec.) 膜厚(nm) A1 1000 60 21 A2 700 180 27 A3 1500 60 31 A4 1000 120 40 B1 700 60 11 B2 1000 180 60 對於上述6種樣本，對於基底層14a之（0002)面及 (10-10)面，測定X線搖擺曲線半値寬度。 此X線搖擺曲線法之測定中，做爲X線源，使用 CuKa線，使用發散角Ο.ΟΓ之入射光，採用SPECTRIS公 司製.PANa.l.y.ti..cal X’.pe.rt _P.r.o. MR_D_ 裝置加以測定-。 然而，考量到基板之裝置之安裝方式或對於基板之配 向方向，由於測定試料而有所不同之誤差，（0002 )面之 搖擺曲線測定乃發現相當於（0002 )面之尖峰之後，使 20與ω最佳化，之後調整Psi，經由進行測定尖峰強度成 爲最大之方向之搖擺曲線，而進行補正。 又，（10-10)面之搖擺曲線測定乃在X線全反射之 條件下，使用透過面內之X線加以進行。具體而言，將 -32- 1380475 對於放置呈水平之被測定試料而言，向垂直方向發散之X 線，從水平方向入射之時，一部分會全反射之故，因而利 用此X線。又，令檢出器固定於相當（10-10)面之20 位置，進行Φ掃瞄。然後，測定六次對稱之尖峰，於顯示 最大強度之尖峰位置，固定光學系統之後，使20與ω最 佳化，進行搖擺曲線測定。 如圖8所示，基底層14a之（0002)面之X線搖擺曲 線半値寬度乃在種子層12之膜厚爲20nm以下之樣本B1 中，約大到180 arc sec»相較之下，種子層12之膜厚爲含 於2 1nm以上40nm以下之範圍的樣本A1、樣本A2、樣 本A3及樣本A4乃約爲小到50arcsec之値。又，種子層 12之膜厚爲41nm以上之樣本B2中，則約成爲50arcsec 以下。 另一方面，如圖8所示，基底層14a之（10-10)面 之X線搖擺曲線半値寬度乃在種子層12之膜厚爲20nm 以下之樣本B1中，約大到270arcsec。相較之下，種子層 12之膜厚爲含於21nm以上40nm以下之範圍的樣本A1、 樣本A2、樣本A3及樣本A4乃安定在200〜225arCSec之 範圍。然後，種子層12之膜厚爲41 nm以上之樣本B2中 ，則成爲260arcsec，膜厚超過41nm之範圍下，會有變大 之傾向。 考量以上結果，種子層12之膜厚較21 nm爲薄之範 圍中，種子層12之結晶性不佳，形成於其上之基底層 14a之（0002)面及（10-10)面之配向不充分之故，X線 -33- 1380475 搖擺曲線半値寬因而變大。另一方面，種子層12之膜厚 較21nm爲厚時，種子層12被結晶化，結晶面被整飭之 故，基底層14a之（ 00 02)面及（10-10)面之配向性則 提升，X線搖擺曲線半値寬因而變小。但是，（10-10) 面之結晶性乃從基板11得到資訊之故，種子層12之膜厚 超過40nm時，形成於其上之基底層14a乃難以從基板11 得到資訊，配向程度會變差，使得X線搖擺曲線半値寬 因而變大。 圖9 ( a )( b )乃爲對於適用本實施之形態之LED晶 片1 〇、和比較用之L E D晶片9 0之順方向電流一順方向電 壓特性（以下稱IF-VF特性）加以說明之圖β 在此，準備從根據與上述樣本A3同樣之種子層12 之膜厚條件所製作之層積半導體晶圓切出3個LED晶片 10 ( 10-1、10-2 ' 10-3 )、和從根據與上述樣本B1同樣 之種子層12之膜厚條件所製作之層積半導體晶圓切出3 個 L E D 晶片 9 0 ( 9 0 · 1 ' 9 0 - 2、9 0 - 3 )，測定各別之 I f - V F 特性》 首先，對於比較用之LED晶片90，如圖9 ( b )所示 ’在比較用LED晶片90-1、90-2及90-3間，則於If-Vf 特性上產生不均。即，可得知比較用之複數LED晶片9〇 間之阻抗値之不均爲大。此乃，意味在於比較用之複數 LED晶片90各別施加相同電壓時，流於各LED晶片90 之電流之不均爲大。 又，LED晶片之發光晶乃比例於電流之故，如此將 -34- 1380475Materials such as In203-ZnO) and GZO (ZnO-Ga202). Further, the light-transmitting positive electrode 17 includes a conventionally known structure, and any structure can be used without any limitation. Further, the translucent positive electrode 17 may be formed entirely on the p-type semiconductor layer 16 to be coated, and the opening gap may be formed in a lattice shape or a tree shape. <Positive Electrode Mat> The positive electrode pad 18 is a slightly circular electrode formed on the above-mentioned translucent positive electrode 17. As the material of the positive electrode static pad 18, various structures such as Au, A1, φ Ni, and Cu are known, and the known materials and structures can be used without any limitation. However, it is necessary to combine with GaN, ITO, IZO, etc., and when an oxide such as Cr or Ti is bonded to a stable metal, it is necessary to mount Au or the like to form a wire bondable structure. The film thickness of the positive electrode pad 18 is preferably in the range of 100 to 1 〇〇〇 nm. Further, in the characteristics of the pad, the bondability of the thick portion is high, and the thickness of the positive electrode pad 18 is preferably 300 nm or more. Furthermore, from the viewpoint of manufacturing cost, those below 50 Gnm are preferred. -25-1380475 <Negative Electrode> The negative electrode 19 is in contact with the n-type connection layer 14b of the n-type semiconductor layer 14 constituting the semiconductor layer 100. For this reason, as shown in Fig. 7, the negative electrode 19 is formed into a substantially circular shape on the exposed portion 14d of the exposed n-type connecting layer 14b except for a part of the P-type semiconductor layer 16, the light-emitting layer 15, and the n-type semiconductor layer 14. As the material of the negative electrode 19, the negative electrode of various compositions and structures is known, and such a known negative electrode can be used arbitrarily and without limitation. Next, a method of manufacturing the LED wafer 10 will be described. When the LED wafer 10 shown in Fig. 7 is manufactured, first, a laminated semiconductor wafer on which a semiconductor layer 1 is formed is formed on the substrate 11. When fabricating a semiconductor wafer, first, the substrate 11 is prepared. It is preferred that the substrate 11 is applied to the user after the previous treatment. For example, when a substrate 1 made of sapphire is used, a method in which a surface is subjected to hydrogen termination using a wet method such as a well-known RCA cleaning method can be used. As a result, the film forming process will be stable. Further, the substrate 11 is placed in the processing chamber of the sputtering apparatus, and pretreatment may be performed by a method such as sputtering before the seed layer 12 is formed. Specifically, in the processing chamber, Jiang Ji is exposed to the Ar or n m slurry by 1 1 to perform the treatment before washing the surface. The organic gas or oxide adhering to the surface of the substrate 11 can be removed by applying a slurry of Ar gas or N2 gas to the surface of the substrate 11. At this time, no power is applied to the target, and plasma particles can be efficiently applied to the substrate 11 when a voltage is applied between the substrate 11 and the processing chamber. After the substrate 11 is subjected to pretreatment, the seed layer 12 is formed on the substrate 11 -26 - 1380475 by sputtering. The state of the 'sublayer 12' of the n-type semiconductor layer 14 formed on the seed layer 12 is greatly affected. In the past, when the crystallinity was high, the MOCVD method was expected. However, in the MOCVD method 11, the method of stacking the decomposed metal initially forms crystals around the core, and further forms a film. When the film of 12 is formed, uniformity may be insufficient. φ In this regard, the sputtering method is capable of high-density film formation, and it is preferable to form a uniform film. Therefore, when 12 is formed by a sputtering method, the surface of the substrate 11 can be overlaid to form the seed layer 12, and the seed layer can be uniformly formed in the surface, and then the seed layer 12 is uniformly formed on the surface, and the crystal growth ratio is high; ; conductor layer 14. However, in the present embodiment, in the sputtering method, the substrate temperature of 300 to 800 when the seed layer 12 is formed by the RF (high frequency) 溺 φ sputtering method in which the hard surface of the hard target is raised and the film formation speed is stabilized is stabilized. °C. Further, as the target of the sputtering method, the pressure in the furnace and the partial pressure of nitrogen are used to make the pressure in the furnace 0. When the pressure is lower than this, the amount of nitrogen stored is small, and the sputtering becomes a nitride and adheres. However, the upper limit of the pressure is not limited to the extent that the plasma can be settled. Further, the nitrogen flow ratio of the flow rates of nitrogen and argon is set to be 20% or more and 90% or less. In the following flow ratio, the splash is directly adhered to the metal. On the other hand, the flow rate ratio is higher than that of the seed layer which is seeded, and the seed layer is formed into a film so that the seed layer has no gap. ; 2, Ranyi η type half to produce the standard; plating method. It is set at . Further, for metals of 3 Pa or more, as long as the nitrogen is set to be a metal plating, the amount of argon is reduced by -27 to 1380 475, which causes the sputtering rate to decrease. However, as a particularly desirable condition, the nitrogen flow rate ratio may be, for example, a nitrogen content of 30% or more and 90% or less. As a nitrogen raw material, a generally known compound can be used without any problem. In particular, when nitrogen is used as a raw material, the apparatus can be simplified, but it is difficult to obtain a high reaction rate. However, in the embodiment of the present embodiment, N2 is used. Even if it is N2, the film formation speed of the usable degree can be obtained, and when considering the cost of the device, it is preferable to use it as a nitrogen source. In the embodiment, the C-plane sapphire substrate was introduced into a sputtering apparatus, and in the processing chamber, the substrate was heated to 500 ° C, and nitrogen gas was introduced at a flow rate of 4 〇 Sccm. Thereafter, the pressure in the treatment chamber was maintained at 2.OPa, a high-frequency bias of 100 W was applied to the substrate side, and the surface of the substrate was washed by exposure to nitrogen plasma for 15 seconds. Next, the distance between the target and the substrate is adjusted to 60 mm, argon and nitrogen gas are introduced, and the substrate temperature is heated to 500 ° C. Thereafter, a specific output of high frequency power is applied to the target side, and the pressure in the furnace is maintained at l. .OPa, in the flow condition of argon gas 10sccm, nitrogen gas 30sccm (the ratio of nitrogen to the whole gas is 75%), on the surface of the sapphire substrate c, the film formation of the A1N layer is started. Then, after the film formation A1N is applied for a certain period of time, the start of the plasma is stopped to lower the substrate temperature. The substrate 11 on which the seed layer 12 taken out by the sputtering apparatus is formed is introduced into an MOCVD furnace, and a film formation of the n-type semiconductor layer 14 (GaN layer) is performed by the following method. First, the substrate was placed on a carbon susceptor -28-1380475 for heating in a M0CVD furnace, and after flowing nitrogen gas in the MOCVD furnace, the heater was started to raise the temperature of the substrate to 1,150 °C. The amount of ammonia is adjusted to a ratio of Group V elements to Group III of 6000. Next, hydrogen of a vapor containing trimethylgallium (TMG) was supplied into the MOCVD furnace to start film formation on the GaN layer on the substrate. After about 1 hour, the growth of GaN having a film thickness of 6/zm was carried out without being doped, and the supply of the MOCVD furnace of the raw material was terminated, and the growth was stopped. Thereafter, the energization of the heater is stopped, and the substrate temperature is lowered to room temperature. However, the removed substrate is a colorless and transparent mirror. On the film formation substrate 11 of the seed layer 12, as shown in FIG. 7, the base layer 14a and the n-type connection layer 14b and the n-type cladding layer 14c are formed into an n-type semiconductor layer 14, by the barrier layer 15a, and the well layer. The light-emitting layer 15 and the p-type semiconductor layer 16p-type cladding layer 16a and the p-type connection layer 16b formed by 15b are formed by an MOCVD method (organic metal chemical vapor phase growth method) in which crystallinity is formed. However, in the MOCVD method, hydrogen (H2) or nitrogen (N2) is used as a carrier gas, and a Ga source is used as a group III raw material, and trimethylgallium (TMG) or triethylgallium (TEG) is used as A1. Source, using trimethylaluminum (TMA) or triethylaluminum (TEA), using trimethylindium (TMI) or triethylindium (TEI) as the source of In, and using N as the source of the V group ), hydrazine, and the like. Further, in the n-type impurity of the dopant, as the Si raw material, monodecane (SiH4) or dioxane (Si2H6) can be used as the Ge raw material, and helium gas (GeH4) or tetramethylguanidine ((CH3) can be used. An organic germanium compound such as 4Ge) or tetraethylphosphonium ((C2H5)4Ge). -29- 1380475 P-type impurity of doping element, as Mg raw material, dicyclopentadienyl magnesium (ChMg) or bisethylcyclopentadienyl magnesium ( ) β is thus obtained as the semiconductor layer 100 shown in FIG. On the ρ 16b, the light-transmitting positive electrode 1 pad 18 was sequentially formed by photolithography. Next, the body layer 100 of the light-transmitting positive electrode 17 and the positive electrode pad 18 is dry-etched to form an n-type connection layer 14b for a period of 14 d 〇, and then exposed to the image electrode 14d via the photolithographic negative electrode 1 9, the LED chip 10 shown in Figure 7 can be obtained. However, the method for manufacturing the LED chip 10 of the present invention is, for example, a film formation of the semiconductor layer 1 can be performed by MOCVD (organic metallization vapor deposition method), HVPE (halogen deposition method), MBE. (Molecular line epitaxy method) or the like can be combined by any method which can make a semiconductor. Next, the film thickness of the seed layer 12 and the underlying layer 14a will be described. FIG. 8 shows the relationship between the film thickness of I and the half-turn width of the rocking curve of the base layer 14a for a sample of a plurality of LED wafers. One of the alignment processes of the base layer 14a and the like. Here, the semiconductor layer 1 is sequentially laminated on the underlayer 14a of the underlayer 14a, and the n-type cladding layer is laminated on the n-type connection layer 14b, for example, an exposure method using the 'EtCp2Mg type connection layer 7 and the positive electrode. The formation of a crystalline barbed layer 12 which is not limited to the growth of the upper ruthenium plating method and the gas phase of the chemical vapor is formed. However, the index n-type junction 14c, the -30- 1380475 η-type cladding layer 14c is laminated on the luminescent layer 15 and the p-type semiconductor layer 16. Therefore, when the alignment of the crystal of the underlayer 14a is good, the crystallinity of the semiconductor layer 100' is improved, and the crystallinity of the underlayer 14a is not good, the crystallinity of the semiconductor layer 1 becomes difference. Further, the crystal structure of the underlayer 14a (A1N) is the most densely packed structure, and the (10-10) plane corresponds to the surface of the substrate plane perpendicular to the crystal of the underlayer 14a. The crystal of the underlayer 14a is on the surface of the substrate, and the hexagonal column is perpendicular to the structure of φ. For example, the hexagonal column of the crystal of the base layer 14a is in a plane, and when there is a neat arrangement in the same orientation, there is no gap, but as long as it is slightly different, a gap is formed between the hexagonal column and the hexagonal column. This gap is the degree of alignment of the crystal, which corresponds to the through-transfer. Therefore, in the underlying layer 14a, not only the (〇〇〇2) plane parallel to the substrate surface but also the crystal alignment perpendicular to the (1 0-1 0) plane of the substrate surface is required to satisfy specific conditions. Further, since the underlayer 14a is laminated on the seed layer 12, the crystal orientation of the underlying layer 14a is greatly affected by the φ of the crystal state of the seed layer 12. Here, the present inventors have separately changed the thickness of the seed layer 12 formed on the substrate 11, and further prepared six kinds of samples on which the underlying layer 14a is formed, and the crystal faces of the underlying layer 14a of each sample, An experiment determined by a rocking curve method. Specifically, Sample A1, Sample A2, Sample A3, and Sample A4 were prepared as film thickness conditions (21 nm to 40 nm) of the seed layer 12 to which the present embodiment was applied. Further, in comparison with the sample B 1 and the sample -31 - 1380475 B2 which do not satisfy the film thickness condition of the seed layer 1 2 of the embodiment to which the present embodiment is applied. The film formation conditions and film thickness of the seed layer 12 of these samples are shown below. However, these samples were produced in accordance with the above-described manufacturing method except that the film formation conditions (or film thicknesses) of the seed layer 12 were made different. [Table 1] Seed layer 12 Sample plating output (W) Film formation time (Sec.) Film thickness (nm) A1 1000 60 21 A2 700 180 27 A3 1500 60 31 A4 1000 120 40 B1 700 60 11 B2 1000 180 60 For the above six samples, the X-ray rocking curve half-turn width was measured for the (0002) plane and the (10-10) plane of the base layer 14a. In the measurement of the X-ray rocking curve method, as the X-ray source, the CuKa line is used, and the incident light of the divergence angle Ο.ΟΓ is used, and PANa.lyti..cal X'.pe.rt _P. Ro MR_D_ device is measured -. However, considering the mounting method of the device to the substrate or the alignment direction of the substrate, the error of the measurement of the sample is different, and the measurement of the rocking curve of the (0002) plane is found to be equivalent to the peak of the (0002) plane, so that 20 and ω is optimized, and then Psi is adjusted, and correction is performed by performing a rocking curve in which the peak intensity is maximized. Further, the measurement of the rocking curve of the (10-10) plane was carried out using X-rays in the transmission plane under the condition of total reflection of X-rays. Specifically, -32- 1380475 is used for the sample to be placed horizontally, and the X-ray which is diverged in the vertical direction is totally reflected when it is incident from the horizontal direction, and thus the X-ray is utilized. Further, the detector is fixed at 20 positions on the equivalent (10-10) plane to perform Φ scanning. Then, the peak of the sixth symmetry was measured, and after the optical system was fixed at the peak position showing the maximum intensity, 20 and ω were optimized, and the rocking curve was measured. As shown in FIG. 8, the X-axis rocking curve half width of the (0002) plane of the base layer 14a is in the sample B1 in which the seed layer 12 has a film thickness of 20 nm or less, as large as 180 arc sec», in comparison with the seed. The film thickness of the layer 12 is such that the sample A1, the sample A2, the sample A3, and the sample A4 contained in the range of 21 nm or more and 40 nm or less are as small as about 50 arcsec. Further, in the sample B2 in which the seed layer 12 has a film thickness of 41 nm or more, it is about 50 arcsec or less. On the other hand, as shown in Fig. 8, the X-ray rocking curve half width of the (10-10) plane of the base layer 14a is about 270 arcsec in the sample B1 in which the seed layer 12 has a film thickness of 20 nm or less. In contrast, the sample thickness of the seed layer 12 is such that the sample A1, the sample A2, the sample A3, and the sample A4 contained in the range of 21 nm or more and 40 nm or less are in the range of 200 to 225 arCSec. Then, in the sample B2 in which the thickness of the seed layer 12 is 41 nm or more, it becomes 260 arcsec, and the film thickness tends to become larger in the range of more than 41 nm. Considering the above results, in the range where the film thickness of the seed layer 12 is thinner than 21 nm, the crystallinity of the seed layer 12 is poor, and the alignment of the (0002) plane and the (10-10) plane of the base layer 14a formed thereon is obtained. Insufficient, the X-ray -33-1380475 rocking curve is half-width wide and thus becomes larger. On the other hand, when the film thickness of the seed layer 12 is thicker than 21 nm, the seed layer 12 is crystallized, and the crystal face is tidy, and the alignment of the (00 02) plane and the (10-10) plane of the base layer 14a is Ascension, the X-ray rocking curve is half-width wide and thus small. However, the crystallinity of the (10-10) surface is obtained from the substrate 11. When the film thickness of the seed layer 12 exceeds 40 nm, it is difficult for the underlying layer 14a formed thereon to obtain information from the substrate 11, and the degree of alignment becomes variable. Poor, making the X-ray rocking curve half-width wide and thus large. Fig. 9 (a) and (b) illustrate the forward-current-current-current voltage characteristics (hereinafter referred to as IF-VF characteristics) of the LED chip 1A to which the present embodiment is applied and the LED chip 90 for comparison. Here, it is prepared to cut out three LED wafers 10 (10-1, 10-2' 10-3) from the laminated semiconductor wafer fabricated under the film thickness conditions of the seed layer 12 similar to the sample A3 described above. And three LED chips 90 (9 0 · 1 '9 0 - 2, 9 0 - 3 ) were cut out from the laminated semiconductor wafer prepared according to the film thickness condition of the seed layer 12 similar to the sample B1 described above. The respective I f - VF characteristics" First, for the LED wafer 90 for comparison, as shown in Fig. 9 (b) 'between the LED chips 90-1, 90-2 and 90-3 for comparison, then at If- Unevenness in the Vf characteristics. That is, it can be seen that the impedance 値 between the plurality of LED chips 9 for comparison is not large. This means that when the same voltage is applied to each of the plurality of LED chips 90 for comparison, the current flowing through each of the LED chips 90 is not large. Moreover, the illuminating crystal of the LED chip is proportional to the current, so that -34- 1380475

If-Vf特性有大的不均之比較用之複數LED晶片90並列 • 連接之時，此等每一LED晶片90中，發光量則會大爲不 ' 均。 對此，如圖9 ( a )所示，在LED晶片10-1、10-2及 10-3之IF-VF特性乃各別呈幾近相同者。因此，如上所述 ，每一此等之LED晶片1 0之阻抗値之不均亦小，於施加 相同電壓時，流入電流之不均亦會變小。因此，並列連接 φ 複數之LED晶片10之時，仍可抑制各LED晶片10之光 _ 量的不均。 更且，複數之LED晶片10之阻抗値爲均勻之故，亦 可抑制負荷集中於任一之1個之LED晶片1 0，可提高做 爲具備複數之LED晶片10之LED封裝20之可靠性（耐 久性）。 如上所述，經由使形成於基板11之種子層12之成膜 條件呈最佳化，使得層積於其上之半導體層100之結晶性 φ 變得良好。因此，可從結晶性良好之層積半導體晶圓，得 均質之LED晶片10，更且可使所得之複數之LED晶片10 彼此之例如阻沆値等之電性特性的不均變小。 又，如前段之說明，將複數個之LED晶片1 0安裝於 LED封裝20之時，設於1個之LED封裝20之各LED晶 片10之光量之不均當然會變小，於與其他之LED封裝20 之關係下，亦可使光量之不均變小。更且，將如此光量不 均變小之複數之LED封裝20，備於背光裝置40時，可抑 制背光裝置40之光量之不均的產生。 -35- 1380475 以上所說明之LED封裝20雖爲使用引線框者，但不 一定限定於使用引線框之形態。 圖10(a) (b)乃對於LED封裝290加以說明之圖 。圖10 ( a)乃LED封裝290之上面圖（發光面側），圖 10(b)乃顯示圖10(a)之X-X剖面圖。然而，對於與 上述LED封裝20相同的部分，則附上同一符號，省略詳 細之說明。 如圖10 ( a)所示，LED封裝290乃具備3個LED晶 片10、和安裝此等3個LED晶片10之封裝用基板22。 封裝用基板22乃例如可將玻璃環氧樹脂基板等做爲材料 加以使用。然後，封裝用基板22乃如圖10(b)所示， 具有安裝LED晶片10之面（以下稱安裝面），和安裝上 述LED封裝20時，對向於模組用基板3 1之面（以下稱 非安裝面）。 如圖10(b)所示，於做爲安裝體工作之封裝用基板 22之安裝面，則對應於各LED晶片10，各設置供電泵25 與散熱用泵26。另一方面，於封裝用基板22之非安裝面 中，形成成爲供電於LED晶片1 0時之路徑之電性配線圖 案23、及伴隨LED晶片10之發光而產生熱之散出路徑之 散熱圖案24。然後，經由電性配線圖案23，3個LED晶 片1 〇乃電性並列連接。 然後，設於封裝用基板22之安裝面側之供電栗25與 設於非安裝面側之電性配線圖案23乃經由貫通封裝用基 板22而設之穿孔，加以電性連接。又，同樣地，設於封 -36- 1380475 裝用基板22之安裝面側之散熱用泵26與設於非安裝面側 之散熱圖案24乃經由貫通封裝用基板22而設之穿孔等’ 加以導熱性連接。 將各LED晶片10安裝於封裝用基板22之時，散熱 用泵26與LED晶片10乃經由焊錫熱傳導地連接，更且 ，設於LED晶片10之電極與上述供電泵25乃經由打線 等電性連接。 然後，具有以上構成之LED封裝290乃與上述LED 封裝20相同，於模組用基板3 1電性加以連接（參照圖3 (a) (b))。然而，此時，於模組用基板31形成散熱 用之配線圖案時，可將LED封裝29 0所產生之熱更有效 地加以散出。如此，LED封裝290乃在3個LED晶片10 ，各別形成散熱路徑之部分者爲佳。 如以上所述，於LED封裝20或LED封裝290中，對 於複數LED晶片1 0電性並列連接之例做了說明。可是， 不一定在LED封裝20等之封單位上，需要使複數LED晶 片10電性並列加以連接。例如，將複數之LED晶片10 直接安裝於模組用基板31而構成，經由設於模組用基板 31之電性配線圖案32，可使此等複數之LED晶片10中 例如3個3個地加以電性並列連接而構成。此時，模組用 基板3 1乃做爲並列連接手段及連接手段加以工作。 又，經由改變LED晶片10之井層15b之In組成， 使可發光呈紫外光者。於此時，例如經由添加在封閉樹脂 28接受紫外光而發出紅色之光之螢光體、發出綠光之螢 -37- 1380475 光體、發出藍光之螢光體，可得發出白色光之LED封裝 20 〇 又，於以上之說明中，雖說明了設於LED封裝20之 LED晶片10之數量爲3個之例子，但非限定於此。設於 LED封裝20之LED晶片10之數量只要是複數者，任何 數量皆無妨。 【圖式簡單說明】 [圖1 ]顯示適用於本實施形態之液晶顯示裝置之整體 構成圖。 [圖2]爲說明背光框體及發光單元構成之圖。 [圖3 ]( a )( b )乃爲對於發光模組加以說明之圖。 [圖4] ( a) ( b )乃爲對於LED封裝加以說明之圖。 [圖5](a)〜（c)乃對於引線框之形狀而言，爲說 明其他之例子之圖。 [圖6]爲對於發光模組之電性連接加以說明之圖。 [圖7]模式性顯示LED晶片之剖面圖。 [圖_ 8]_對於複數__之_ 晶片之樣本，_呆種¥層之膜 厚與基底層之搖擺曲線半値寬度之關係圖。If the If-Vf characteristic has a large unevenness, the plurality of LED chips 90 are juxtaposed. • When connected, the amount of luminescence in each of the LED chips 90 is greatly reduced. On the other hand, as shown in Fig. 9 (a), the IF-VF characteristics of the LED chips 10-1, 10-2, and 10-3 are almost the same. Therefore, as described above, the unevenness of the impedance of each of the LED chips 10 is also small, and when the same voltage is applied, the unevenness of the inflow current is also small. Therefore, when the φ plurality of LED chips 10 are connected in parallel, the unevenness of the amount of light of each of the LED chips 10 can be suppressed. Further, since the impedance of the plurality of LED chips 10 is uniform, it is also possible to suppress the load from being concentrated on any one of the LED chips 10, and the reliability of the LED package 20 having the plurality of LED chips 10 can be improved. (Durability). As described above, the film formation conditions of the seed layer 12 formed on the substrate 11 are optimized, so that the crystallinity φ of the semiconductor layer 100 laminated thereon becomes good. Therefore, the semiconductor wafer can be laminated from a semiconductor wafer having good crystallinity, and the unevenness of electrical characteristics such as resistance of the plurality of LED wafers 10 can be made small. Further, as described in the foregoing paragraph, when a plurality of LED chips 10 are mounted on the LED package 20, the unevenness of the amount of light of each of the LED chips 10 provided in one of the LED packages 20 is naturally small, and other In the relationship of the LED package 20, the unevenness of the amount of light can also be made small. Further, when the plurality of LED packages 20 having such a small amount of light are reduced in the backlight device 40, unevenness in the amount of light of the backlight device 40 can be suppressed. -35- 1380475 The LED package 20 described above is a lead frame, but is not necessarily limited to the form in which a lead frame is used. 10(a) and (b) are diagrams for explaining the LED package 290. Fig. 10 (a) is a top view (light emitting surface side) of the LED package 290, and Fig. 10 (b) is a cross-sectional view taken along line X-X of Fig. 10 (a). However, the same portions as those of the LED package 20 described above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in Fig. 10 (a), the LED package 290 is provided with three LED wafers 10 and a package substrate 22 on which the three LED chips 10 are mounted. The package substrate 22 can be used, for example, as a material such as a glass epoxy substrate. Then, as shown in FIG. 10(b), the package substrate 22 has a surface on which the LED chip 10 is mounted (hereinafter referred to as a mounting surface), and when the LED package 20 is mounted, it faces the surface of the module substrate 31 ( Hereinafter referred to as the non-installation surface). As shown in Fig. 10 (b), in the mounting surface of the package substrate 22 which is a mounting body, the power supply pump 25 and the heat radiation pump 26 are provided for each of the LED chips 10. On the other hand, in the non-mounting surface of the package substrate 22, an electrical wiring pattern 23 that serves as a path for supplying the LED wafer 10 and a heat dissipation pattern that generates a heat dissipation path accompanying the light emission of the LED wafer 10 are formed. twenty four. Then, via the electrical wiring pattern 23, the three LED wafers 1 are electrically connected in parallel. Then, the power supply chip 25 provided on the mounting surface side of the package substrate 22 and the electrical wiring pattern 23 provided on the non-mounting surface side are electrically connected via through holes penetrating through the package substrate 22. In the same manner, the heat dissipation pump 26 provided on the mounting surface side of the mounting substrate 22 of the package -36-1380475 and the heat dissipation pattern 24 provided on the non-mounting surface side are pierced or the like provided through the package substrate 22. Thermally conductive connection. When the LED chips 10 are mounted on the package substrate 22, the heat dissipation pump 26 and the LED wafer 10 are thermally connected by soldering, and the electrodes provided on the LED chip 10 and the power supply pump 25 are electrically connected via the wire. connection. Then, the LED package 290 having the above configuration is electrically connected to the module substrate 31 in the same manner as the LED package 20 (see FIGS. 3(a) and (b)). However, at this time, when the wiring pattern for heat dissipation is formed on the module substrate 31, the heat generated by the LED package 290 can be more effectively dissipated. As such, the LED package 290 is preferably formed on the three LED chips 10, each of which forms a heat dissipation path. As described above, in the LED package 20 or the LED package 290, an example in which the plurality of LED chips are electrically connected in parallel is explained. However, it is not necessarily required to connect the plurality of LED wafers 10 in parallel in the sealed unit of the LED package 20 or the like. For example, a plurality of LED chips 10 are directly mounted on the module substrate 31, and three or three of the plurality of LED chips 10 can be formed via the electrical wiring patterns 32 provided on the module substrate 31. It is constructed by electrically connecting in parallel. At this time, the module substrate 31 is operated as a parallel connection means and a connection means. Further, by changing the In composition of the well layer 15b of the LED wafer 10, it is possible to emit ultraviolet light. At this time, for example, an LED emitting white light can be obtained by a phosphor which emits red light by receiving ultraviolet light in the sealing resin 28, a phosphor emitting green light-37-38080475, and a phosphor emitting blue light. In the above description, although the number of the LED chips 10 provided in the LED package 20 is three, the present invention is not limited thereto. The number of LED chips 10 provided in the LED package 20 may be any number as long as it is plural. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] A view showing the overall configuration of a liquid crystal display device to which the present embodiment is applied. FIG. 2 is a view for explaining a configuration of a backlight housing and a light-emitting unit. FIG. [Fig. 3] (a) (b) is a diagram for explaining a light-emitting module. [Fig. 4] (a) (b) is a diagram for explaining an LED package. [Fig. 5] (a) to (c) are diagrams showing other examples of the shape of the lead frame. Fig. 6 is a view for explaining an electrical connection of a light-emitting module. FIG. 7 is a cross-sectional view schematically showing an LED chip. [Fig. 8] _ For the sample of the complex ___ wafer, the relationship between the film thickness of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

[圖9] (a) (b)乃爲對於適用本實施之形態之LED 晶片、和比較用之LED晶片之順方向電流一順方向電壓 特性加以說明之圖。 [圖l〇](a) (b)乃爲對於LED封裝之其他例子加 以說明之圖。 -38- 1380475 【主要元件符號說明】 10 : LED晶片 1 1 :基板 1 2 :種子層[Fig. 9] (a) (b) is a diagram illustrating the forward-current-current voltage characteristics of the LED chip to which the present embodiment is applied and the LED chip for comparison. [Fig. 1〇] (a) (b) is a diagram illustrating other examples of LED packages. -38- 1380475 [Explanation of main component symbols] 10 : LED chip 1 1 : Substrate 1 2 : Seed layer

1 4a :基底層 14b : η型連接層 1 4c : η型包覆層 1 4d :露出範圍 1 5 a :障壁層 1 5b :井層 16 : p型半導體層 1 6a : p型包覆層 16b : p型連接層 100 :半導體層 20 ： LED封裝 3 0 :發光模組 3 1 :模組用基板 3 00 :發光區塊 40 :背光裝置 42 :發光單元 5 〇 :液晶顯示模組 -39-1 4a : base layer 14b : n type connection layer 1 4c : n type cladding layer 1 4d : exposure range 1 5 a : barrier layer 1 5b : well layer 16 : p type semiconductor layer 1 6a : p type cladding layer 16b : p-type connection layer 100 : semiconductor layer 20 : LED package 30 : light-emitting module 3 1 : module substrate 3 00 : light-emitting block 40 : backlight device 42 : light-emitting unit 5 〇 : liquid crystal display module - 39-

Claims (1)

1380475 _ 、 π年1月Μ曰修正替換頁 第098101231號專利申請案中文申請專利範圍修正本 民國101年9月21曰修正 七、申請專利範圍： 1. 一種光源，其特徵乃具備：複數之發光元件、 電性並列連接前述複數之發光元件之並列連接手段； 構成前述複數之發光元件之各發光元件乃包含： 元件基板、 和直接層積於ΠΙ族氮化物化合物半導體所成前述元 件基板之上的種子層、 和直接層積於前述種子層上，（0 002 )面之搖擺曲線 半値寬爲lOOarcsec以下，（10-10 )面之搖擺曲線半値寬 爲2 50arcsec以下之III族氮化物化合物半導體所成基底 層者。 2. 如申請專利範圍第1項之光源，其中，前述基底 層乃 (0002 )面之搖擺曲線半値寬爲 6〇arcsec以下，（ 10-10)面之搖擺曲線半値寬爲25 0arCSec以下之III族氮 化物化合物半導體。 3. 如申請專利範圍第1項之光源，其中，前述並列 連接手段乃安裝前述複數之發光元件的同時，形成供電於 該複數之發光元件之供電路徑的安裝體。 4. 如申請專利範圍第1項之光源，其中，前述種子 層乃具有21nm以上40nm以下之層厚。 5. 如申請專利範圍第4項之光源，其中，前述種子 1380475 ，月ή日修“ 一^j 層乃經由濺鍍法而成膜者。 6. 如申請專利範圍第1項之光源，其中，前述元件 基板爲藍寶石基板，前述種子層乃 Α1Ν，前述基底層乃 GaN 者。 7. 如申請專利範圍第1項之光源，其中，更具備： 與前述複數之發光元件不同之其他之複數之發光元件， 電性並列連接前述其他之複數之發光元件之其他之並 列連接手段； 電性連接前述並列連接手段與前述其他之並列連接手 段的連接手段。 8. —種發光裝置，其特徵乃備有：具備複數之發光 元件、和電性並列連接該複數之發光元件的第1之供電路 徑的發光體， 和設置安裝複數個前述發光體，與設於各該發光體之 前述第1之供電路徑電性連接的第2之供電路徑的安裝基 板； 構成前述複數之發光元件之各發光元件乃包含： -元件基板、 * … 一…… 和直接層積於III族氮化物化合物半導體所成前述元 件基板之上的種子層、 和直接層積於前述種子層上，（ 00 02)面之搖擺曲線 半値寬爲100 arc sec以下，（10-10)面之搖擺曲線半値寬 爲250arcSeC以下之III族氮化物化合物半導體所成基底 13804751380475 _ , π 1 Μ曰 替换 替换 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 098 、 、 、 、 、 、 、 、 a light-emitting element, a parallel connection means for electrically connecting the plurality of light-emitting elements in parallel; each of the light-emitting elements constituting the plurality of light-emitting elements includes: an element substrate; and a layer directly deposited on the element substrate of the bismuth nitride compound semiconductor The upper seed layer, and the layer layer directly deposited on the seed layer, the rocking curve of the (0 002) plane has a half-width of less than lOOarcsec, and the rocking curve of the (10-10) plane has a half-width of the group III nitride compound of less than 2 50 arcsec. The base layer of the semiconductor. 2. The light source of claim 1, wherein the base layer has a rocking curve of a (0002) plane having a half-turn width of 6 〇 arcsec or less, and a (10-10) plane rocking curve has a half-width of 25 arCSec or less. Group nitride compound semiconductor. 3. The light source according to claim 1, wherein the parallel connection means is a mounting body for supplying a power supply path for supplying the plurality of light-emitting elements while mounting the plurality of light-emitting elements. 4. The light source of claim 1, wherein the seed layer has a layer thickness of 21 nm or more and 40 nm or less. 5. For the light source of claim 4, wherein the seed 1380475 is repaired on the following day, the film is formed by sputtering. 6. If the light source of claim 1 is used, The element substrate is a sapphire substrate, the seed layer is Ν1, and the underlayer is GaN. 7. The light source of claim 1 further comprising: a plurality of other than the plurality of light-emitting elements The light-emitting element is electrically connected in parallel to the other parallel connection means of the other plurality of light-emitting elements; and the connection means of the parallel connection means and the other parallel connection means are electrically connected. 8. A light-emitting device characterized by a light-emitting element having a plurality of light-emitting elements and a first power supply path electrically connected to the plurality of light-emitting elements, and a plurality of the light-emitting elements mounted thereon, and the first power supply provided in each of the light-emitting bodies a mounting substrate of the second power supply path electrically connected to the path; each of the light-emitting elements constituting the plurality of light-emitting elements includes: - an element substrate , * ... a ... and a seed layer directly deposited on the element substrate of the group III nitride compound semiconductor, and directly laminated on the seed layer, the rocking curve of the (00 02) plane has a half width of 100 Below arc sec, the (10-10) plane of the rocking curve has a half-turn width of 250 arrSe below the group III nitride compound semiconductor substrate 1380475 ϋ’年1月$修正替換頁 9.如申請專利範圍第8項之發光裝置，其中，前述 複數之發光體乃在前述安裝基板，以等間隔加以配置者。 10· 一種顯示裝置，包含顯示畫像之顯示面板、和設 於該顯示面板之背面’向該顯示面板照射光線之背光的顯 示裝置，其特徵乃 前述背光乃具備： 備有複數之發光元件、和電性並列連接該複數之發光 元件的第1之供電路徑的發光體， 和設置安裝複數個前述發光體，與設於各該發光體之 前述第1之供電路徑電性連接的第2之供電路徑的安裝基 板； 構成前述複數之發光元件之各發光元件乃包含： 元件基板、 和直接層積於III族氮化物化合物半導體所成前 述元件基板之上的種子層、 和直接層積於前述種子層上，（ 0002 )面之搖擺 曲線半値寬爲lOOarcsec以下，（10-10 )面之搖擺曲線半 値寬爲25〇arcseC以下之III族氮化物化合物半導體所成 基底層者。 11.如申請專利範圍第10項之顯示裝置，其中，更 包含：各別電性連接構成前述複數之發光體之2個以上之 發光體，形成複數之發光體群的複數之連接導體、 和對於構成前述複數之連接導體之各個連接導體而言 ，進行供電之複數電源。 -3-The illuminating device of the eighth aspect of the invention, wherein the plurality of illuminants are disposed at equal intervals on the mounting substrate. 10. A display device comprising: a display panel for displaying an image; and a display device provided on a back surface of the display panel with a backlight for illuminating the display panel, wherein the backlight comprises: a plurality of light-emitting elements; An illuminant electrically connected to the first power supply path of the plurality of light-emitting elements, and a second power supply that is provided with a plurality of the illuminators and electrically connected to the first power supply path of each of the illuminants a mounting substrate of the path; each of the light-emitting elements constituting the plurality of light-emitting elements includes: an element substrate; and a seed layer directly laminated on the element substrate formed by the group III nitride compound semiconductor, and directly layered on the seed On the layer, the rocking curve of the (0002) plane has a half-width of less than lOOarcsec, and the rocking curve of the (10-10) plane has a half-turn width of a group III nitride compound semiconductor of 25 〇arcseC or less. 11. The display device of claim 10, further comprising: electrically connecting two or more illuminants constituting the plurality of illuminants, forming a plurality of connecting conductors of the plurality of illuminant groups, and For each of the connection conductors constituting the plurality of connection conductors, a plurality of power sources for supplying power are supplied. -3-
TW98101231A 2008-01-16 2009-01-14 Light source, light-emitting device and display device TWI380475B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008007413A JP5526478B2 (en) 2008-01-16 2008-01-16 Light source, light emitting device and display device

Publications (2)

Publication Number Publication Date
TW200933939A TW200933939A (en) 2009-08-01
TWI380475B true TWI380475B (en) 2012-12-21

Family

ID=40885360

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98101231A TWI380475B (en) 2008-01-16 2009-01-14 Light source, light-emitting device and display device

Country Status (3)

Country Link
JP (1) JP5526478B2 (en)
TW (1) TWI380475B (en)
WO (1) WO2009090972A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101039937B1 (en) 2010-04-28 2011-06-09 엘지이노텍 주식회사 Light emitting device, method for fabricating the same, light emitting device package and lighting system
FR2964176B1 (en) * 2010-09-01 2015-10-16 Saint Gobain DECORATIVE AND LIGHTING PANEL WITH ELECTROLUMINESCENT DIODES
JP2013012684A (en) * 2011-06-30 2013-01-17 Sharp Corp Nitride semiconductor light-emitting element
JP6176141B2 (en) * 2014-02-19 2017-08-09 豊田合成株式会社 Group III nitride semiconductor light emitting device manufacturing method
JP2020092155A (en) * 2018-12-05 2020-06-11 株式会社ダイセル Optical semiconductor device
CN117239043B (en) * 2023-11-16 2024-02-27 江西鸿利光电有限公司 Light-emitting device and preparation method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4034241B2 (en) * 2003-06-27 2008-01-16 日本ライツ株式会社 LIGHT SOURCE DEVICE AND LIGHT SOURCE DEVICE MANUFACTURING METHOD
JP4833616B2 (en) * 2004-09-13 2011-12-07 昭和電工株式会社 Method for producing group III nitride semiconductor
JP4856463B2 (en) * 2005-10-17 2012-01-18 株式会社 日立ディスプレイズ Liquid crystal display
JP2007242856A (en) * 2006-03-08 2007-09-20 Rohm Co Ltd Chip-type semiconductor light emitting device
JP2007287751A (en) * 2006-04-12 2007-11-01 Toyoda Gosei Co Ltd Light emitting device
EP2019437B1 (en) * 2006-05-10 2018-07-11 Toyoda Gosei Co., Ltd. Iii nitride compound semiconductor laminated structure

Also Published As

Publication number Publication date
TW200933939A (en) 2009-08-01
JP2009170672A (en) 2009-07-30
WO2009090972A1 (en) 2009-07-23
JP5526478B2 (en) 2014-06-18

Similar Documents

Publication Publication Date Title
US8669560B2 (en) Light-emitting device, light-emitting device package and lighting system
US9455371B2 (en) Light emitting device
US8748863B2 (en) Light emitting device
US8723158B2 (en) Light emitting diode, light emitting device package including the same and lighting system
US8405102B2 (en) Light emitting device, and lighting apparatus
TWI380475B (en) Light source, light-emitting device and display device
KR101860320B1 (en) Light emitting device
KR101855063B1 (en) Light emitting device
TW200807752A (en) III group nitride semiconductor light emitting element, process for producing III group nitride semiconductor light emitting element, and lamp
JP2011205132A (en) Nitride-based semiconductor light-emitting element, lighting system, liquid crystal display device, method for manufacturing nitride-based semiconductor light-emitting element, and method for manufacturing lighting system
US9029911B2 (en) Light emitting device
US8405093B2 (en) Light emitting device
EP2453487B1 (en) Light emitting device
KR101778159B1 (en) Light Emitting device and Light Emitting device Package
KR101877384B1 (en) Light emitting device
KR20140092958A (en) Light emitting device
KR101709991B1 (en) Light emitting device and fabrication method thereof
KR101895925B1 (en) Light emitting device
KR20160029942A (en) Semiconductor light emitting device
KR20130040009A (en) Light emitting device package
KR102019745B1 (en) Light emitting device
KR101986720B1 (en) Light emitting device
KR20130066990A (en) Light emitting device
KR101983349B1 (en) Light emitting device and manufacturing method thereof
KR20130056368A (en) Light emitting device