1380111 AU0812043 30769twf.doc/a 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晝素陣列及顯示面板，且特別是 關於一種兼具省電效果及高開口率的畫素陣列及顯示面 板。 【先前技術】 在現今顯示面板的晝素陣列（pixel array)結構當中， 有類被稱為半源極驅動（half source driving，以下簡稱 為HSD)架構。HSD架構藉著減半資料線的數目，以^到 源極驅動器（source driver)的驅動通道（driving channels) 數也可以減半之目的，因此可以節省驅動畫素陣列所需的 能源。 一般而言，當將HSD架構應用於高解析度的產品中 時，一般會將紅色、綠色、藍色彩色濾光圖案以直線型的 方式排列。但是在高解析度產品，因為各晝素結構中的薄 膜電晶體佔用面積過大，導致晝素陣列中畫素結構的開口 區域無法對齊，也就是相鄰兩晝素結構的開口區域會有錯 位的情況。如此一來，當此顯示面板於顯示晝面時，容易 產生斜紋(mura)瑕疵，而造成顯示品質不足。 【發明内容】 本發明提出一種晝素陣列，可維持高開口率並避免斜 紋瑕疲的產生。 1380111 AU0812043 30769twf.doc/n 具育上述畫素陣列，可 本發明又提出一種顯示面板 兼具省電效果並維持高亮度。 、，發明提出一種晝素陣列，其由多個晝素單元所構 成，每:晝素單元包括第一掃描線、第二掃描線、第一資 料線、第二資料線、第一開關元件、第二開關元件、第一 晝素電極以及第二畫素電極。第-掃減、第二掃描缘、 口料'，及第二資料線設置於基板上，以於U定 〜一=旦素區’且第—晝素區具有第一、第二子晝素區。 弟:關70件與第二掃描線以及第一資料線電性連接，並 =於第晝素區的第一子晝素區内。第二開關元件盘第一 = 開_件電性連接，並位於第—畫素區的 子旦素區内。第—晝素電極位於第—畫素區的第一子 ::區内’並且與第-、第二開關元件電性連接。第-查 ^極位於第—晝素區的第二 關元件電性連接。 且/、弟一開 在本發明之一實施例中，上述晝素陣列更包 =金::開關元件、第四開關元件、第三晝素電極:及 I:;:二置於基板上，以於基板上定 =二晝素區的第二子畫素區内 二 =^開關，連接，並且位於第二晝Ϊ 不蚩各旦素區内。第二晝素電極位於第二書辛區的篦 一子晝素區内，並且與第四開關元件電性連接= 1380111 AU0812043 30769twf.doc/n 第 電極位於第二晝素區的第二子晝素區内，並且與第二 四開關元件電性連接。 η 二 在本發明之-實施财，上述第—_元件 關兀件設置於第二掃描線的正上方。 -掃赠，增：關元件敦置於第 三掃實侧中，上述第三卩·元件殘置於第 四開第-:第:、第三、第 苐三=體， 觸窗、第二接上述晝素陣列更包括第-接 畫素電極、第晝素區内’其電性連接第-振極。第二接觸窗位於;一:=第:電晶體的 每觸窗位於第=去广，弟二薄膜電晶體的汲極。第三 三晝素電極以及;四;子晝素區内，其電性連接第 第二晝素區的第二去電日日體的汲極。第四接觸窗位於 極、第三薄膜電曰麫二;區内’其電性連接第四晝素電 在本發明>日日盘、極以及第四薄膜電晶體的源極。 償線=第=償ΓΓ，上述畫素陣列更包括第一補 仏線弟—補償線位於第一晝素區的第二 1380111 AU0812043 30769twf.doc/n 掃描線延伸。第二補償線位於第二 -素&的第-子晝素區内，並往第三掃描線延伸。 極引實ΐ例中’上述畫素陣列更包括多條閉 刀閘極y線位於兩相鄰的資料線之間。 母 在本發明之一實施例中，上述第—、 四開關元件分別為第一、第二、第三、第二上弟 且第-薄膜電晶體的祕以及第二薄 r S曰體， :;:=赚，第三薄=== 、電日日體的源極分別與第四晝素電極電性 觸窗在^發明之—實闕中’上述更包括第-接 第一接觸窗、第三接觸窗、第四接觸窗、第五 第六賴窗。帛—細窗位於第_絲 息素區内，其電性連接第一書 ^ ” 、苐—子 第二接觸二=體 」技生連接第二晝素電極以及第及 位於第-畫素區的第-子畫素區内 晶體的汲極，= ，及第四薄膜電晶體:及:内第畫素電 二子晝素區内，其電性連接第四畫素電極素 晝素區内，盆電生、車1:::弟二晝素區的第二子 汲極。/、電11連接弟四晝素電極與第三薄膜電晶體的 7 1380111 AU0812043 30769twf.doc/n 在本發明之一實施例中，上述畫素陣列更包括第一擬 接觸窗、以及第二擬接觸窗。第一擬接觸窗位於第一畫素 區的第二子晝素區内，其與第二晝素電極電性連接。第二 擬接觸固位於第二畫素區的第一子晝素區内，其與第三書 素電極電性連接。 、… ~~~ 本發明又提出一種顯示面板，包括上述之晝素陣列、 彩色濾光陣列以及顯示介質。彩色濾光陣列位於畫素陣列 的對向。顯不介質位於晝素陣列與彩色濾光陣列之間。 ，在本發明之-實施例中，上述彩色遽光陣列包括多個 第一、第二、第三彩色濾光圖案，且多個第一、第二、第 二衫色遽光圖案各自為直列式排列。 基於上述，由於本發明所提出的晝素陣列排列整齊、 且開口區不容易產生錯位，因此可轉高開口率並避免斜 紋的產生。此外，本發明所提出的顯示面板，由於具有上 述晝素陣列，因此可兼具省電效果並維持高亮度。八 —為讓本發明之上述特徵和優點更明顯易十董，下文特 舉貝％例，並配^合所附圖式作詳細說明如下。 【實施方式】. 第一實施例 圖1A為本發明第一實施例之晝素陣列200的等效電 路圖。圖1B為晝素陣列·的上視示意圖。圖1(：為對廊 於圖⑴的晝素陣列細中，a_a，、b_b，、Μ及^，的剖面 不意圖。請參照圖1A、圖1B及圖1C，在本發明的第一 AU0812043 30769twf.doc/n 實施例中，晝素陣列200是由位於基板202上的多個晝素1380111 AU0812043 30769twf.doc/a VI. Description of the Invention: [Technical Field] The present invention relates to a halogen array and a display panel, and more particularly to a pixel array having both power saving effect and high aperture ratio And display panel. [Prior Art] Among the pixel array structures of today's display panels, there is a class called a half source driving (HSD) architecture. By reducing the number of data lines, the HSD architecture can also halve the number of driving channels from the source driver, thus saving the energy required to drive the pixel array. In general, when the HSD architecture is applied to a high-resolution product, the red, green, and blue color filter patterns are generally arranged in a straight line. However, in high-resolution products, because the area occupied by the thin film transistor in each halogen structure is too large, the open areas of the pixel structure in the pixel array cannot be aligned, that is, the open areas of the adjacent two-dimensional structures may be misaligned. Happening. In this way, when the display panel is displayed on the kneading surface, it is easy to produce a mura 瑕疵, resulting in insufficient display quality. SUMMARY OF THE INVENTION The present invention provides a halogen array that maintains a high aperture ratio and avoids the occurrence of skew fatigue. 1380111 AU0812043 30769twf.doc/n Having the above pixel array, the present invention further provides a display panel which has both power saving effects and high brightness. The invention provides a pixel array, which is composed of a plurality of pixel units, each of which includes a first scan line, a second scan line, a first data line, a second data line, a first switching element, a second switching element, a first halogen electrode, and a second pixel electrode. The first sweeping, the second scanning edge, the mouth material ', and the second data line are disposed on the substrate to form a first and second sub-small element Area. Brother: The 70 pieces are electrically connected to the second scanning line and the first data line, and are in the first sub-dimension area of the Dioxin area. The second switching element disk is first electrically connected to the first pixel element and located in the sub-denier region of the first pixel region. The first halogen element is located in the first sub-area region of the first pixel region and is electrically connected to the first and second switching elements. The second-level element of the first-character region is electrically connected. And in one embodiment of the present invention, the above-mentioned halogen array further includes a gold:: switching element, a fourth switching element, a third halogen electrode: and I:; In the second sub-pixel region of the substrate, the second sub-pixel region is switched, connected, and located in the second region. The second halogen electrode is located in the sub-single element region of the second Shuxin region, and is electrically connected to the fourth switching element = 1380111 AU0812043 30769twf.doc/n the second electrode of the second pixel region In the prime zone, and electrically connected to the second four switching elements. η 2 In the present invention, the above-mentioned first-component switch is disposed directly above the second scanning line. - Sweep, increase: the component is placed in the third sweeping side, and the third 卩 component is placed in the fourth opening -: the third, the third, the third = body, the touch window, the second The above-mentioned pixel array further includes a first-pixel pixel, and the second region is electrically connected to the first electrode. The second contact window is located; one: = the first: each window of the transistor is located at the bottom of the second, the second of the thin film transistor. The third trioxad electrode and the fourth; the sub-dirugene region are electrically connected to the second de-electrode of the second halogen region. The fourth contact window is located at the pole and the third thin film electrode; the region is electrically connected to the fourth halogen battery in the present invention. The source of the day, the pole and the fourth thin film transistor. The compensation line = the first compensation, the pixel array further includes a first complement line - the compensation line is located at the second 1380111 AU0812043 30769twf.doc/n scan line extension of the first pixel area. The second compensation line is located in the first sub-halogen region of the second-prime & and extends toward the third scan line. In the extreme example, the above pixel array further includes a plurality of closed gate y lines located between two adjacent data lines. In one embodiment of the present invention, the first and fourth switching elements are first, second, third, and second upper and first thin film transistor secrets and a second thin r S body, respectively: ;:= earn, the third thin ===, the source of the electric Japanese body and the fourth halogen electrode respectively, the electric contact window in the invention - in the actual 'the above includes the first - first contact window, The third contact window, the fourth contact window, and the fifth and sixth sash windows.帛—The thin window is located in the _ 丝丝素区, which is electrically connected to the first book ^ ”, 苐 子 第二 接触 接触 = = 」 」 」 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技 技The bucker of the crystal in the first sub-pixel region, =, and the fourth thin film transistor: and: the inner photon element in the diterpenoid region, which is electrically connected to the fourth pixel electrode Pot electric, car 1::: The second son of the second district. In the embodiment of the invention, the pixel array further includes a first pseudo contact window and a second pseudo-invention. 7 1380111 AU0812043 30769 twf.doc/n. Contact window. The first pseudo-contact window is located in the second sub-tend region of the first pixel region, and is electrically connected to the second halogen electrode. The second pseudo-contact is located in the first sub-tenon region of the second pixel region, and is electrically connected to the third pixel electrode. The present invention further provides a display panel comprising the above-described pixel array, color filter array and display medium. The color filter array is located in the opposite direction of the pixel array. The display medium is located between the pixel array and the color filter array. In the embodiment of the present invention, the color light-emitting array includes a plurality of first, second, and third color filter patterns, and each of the plurality of first, second, and second shirt color patterns is in-line Arrangement. Based on the above, since the pixel array proposed by the present invention is arranged neatly and the opening region is not easily misaligned, the aperture ratio can be increased and the occurrence of the skew can be avoided. Further, since the display panel proposed by the present invention has the above-described pixel array, it can have both a power saving effect and a high luminance. VIII. In order to make the above-mentioned features and advantages of the present invention more obvious, the following is a detailed description of the present invention. [Embodiment] FIG. 1A is an equivalent circuit diagram of a pixel array 200 according to a first embodiment of the present invention. Figure 1B is a top plan view of a halogen array. Fig. 1 is a cross-sectional view of a 昼 Array of 昼 阵列 , , , a a 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 30769 twf.doc/n In the embodiment, the halogen array 200 is composed of a plurality of halogens located on the substrate 202.
單元204所構成，但為便於說明本實施例，圖1A及圖1B 僅繪示單個晝素單元204作為代表。 在一實施例中，晝素單元204包括第一掃描線211、 第二掃描線212、第一資料線221、第一開關元件231、第 二開關元件232、第一晝素電極241以及第二晝素電極 242。在另一较佳實施例中，畫素單元204還包括第三掃描 線213、第二資料線222、第三開關元件233、第四開關元 件234、第三晝素電極243以及第四晝素電極244。 第一掃描線211、第二掃描線212、第一資料線221 以及苐一資料線222設置於基板202上，以於基板202上 疋義出第一晝素區206，且第一畫素區206具有第一子晝 素區206a與第二子晝素區206b。第二掃瞄線212、第三掃 描線213、第一資料線221以及第二資料線222設置於基 板202上，以於基板202上定義出第二晝素區2〇8，且第 一晝素區208具有第一子晝素區208a及第二子晝素區 208b。 一、 第一開關元件231與第二掃描線212以及第一資料線 221電性連接，並位於第一晝素區2〇6的第一子晝素區加如 内。較佳的是，第一開關元件231位於第二掃描線212 正上方。 第二開關元件232與第一掃描線211以及第一開關元 件231電性連接，並位於第一晝素區2〇6的第一子書素區 206a内。較佳的是，第二開關元件232位於第一掃描^ 1380111 AU0812043 30769twf.doc/n 的正上方。 第三開關元件233與第三掃描線213以及第二資 222电性連接，並且位於第二晝素區的第二子蚩二、 =方内。。較佳的是，第三„元件233位於第 第四開關元件234與第二掃描線扣 件B電性連接，並且位於第二晝素區2〇8“二= 區麟内。較佳的是’第四開關元件234位 = 212的正上方。 坪掏綠 第一晝素電極241位於第—畫素區2〇6的第一子金 與第一f元件231及第二開關元件^ 工接苐一晝素電極242位於第一畫素區施的第二 一里素區206b内，並且與第二開關元件232電性連接 =m243位於第二晝素區施的第一子畫素區雇 m第四開關元件234電性連接。第四晝素電極244 位於u區208的第二子晝素區腦内，並且三 開關几件233及第四開關元件234電性連接。” 而言，請同時參照圖1B及圖1C，在本實施例 構200中，第一開關元件231、第二開關元件加、 ，一開，兀件233及第四開關元件234分別為第一、第二、 弟三、弟四薄膜電晶體。第第二、第三、第四薄膜電 晶體分別具有閘極、源極以及汲極。. 、 _ ί細ί言’以第—薄膜電晶體231為例，如圖1C所 示’薄獏電曰曰體231具有間極231g、源極231s及汲 1380111 AU0812043 30769twf.doc/n 極231 d。在本實施例中，第一薄膜電晶體231的閘極23工g 即為第二掃描線212的一部份，源極231s與第一資料線 221電性連接，而汲極231d往第一晝素區2〇6的第二子苎 素區206a内部延伸。另外，第一薄膜電晶體231的閘極 231g上方設置有閘絕緣層G，而在第—薄膜電晶體231的 源極231s與及極231d上方還覆蓋有保護層。 類似地，第二薄膜電晶體232具有閘極232g、源極232s 及汲極232d，其中第二薄膜電晶體232的閘極232g舉例 係為第一掃描線211的一部份。第二薄膜電晶體232的源 極232s與第一薄膜電晶體231的汲極23丨d電性連接。第 一薄膜電晶體232的沒極232d則延伸至第一書素區206 的第二子晝素區206b中。 第二薄膜電晶體233具有閘極233g、源極233s及及 極233d，其令第三薄膜電晶體233的閘極233g即為第三 掃描線213的一部份。源極233s與第二資料線222電性連 接，而汲極233d往第二畫素區208的第二子畫素區208b 内部延伸。 第四》專膜電晶體234具有閘極234g、源極234s及>及 極234d ’其中’第四薄膜電晶體234的閘極234g即為第 二掃描線212的一部份。第四薄膜電晶體234的源極234s 與第三薄膜電晶體233的汲極233d電性連接。第四薄膜電 晶體234的及極234d則延伸至第二晝素區208的第一子晝 素區208a中。 此外，第一薄膜電晶體231、第二薄膜電晶體232、第 11 1380111 AU0812043 30769twf.doc/n 三薄膜電晶體233及第四薄膜電晶體234還包括半導體通 道層及歐j接觸層（未標示），然，本領域具有通常知識者 & 了了解/專膜電aa體之結構與工作方式，故在此不再贅述。 特別要>主意的是，在本實施例中，由於第一薄膜電晶 體231的汲極231d與第二薄膜電晶體232的源極232§連 接’因此第一薄膜電晶體231與第二薄膜電晶體232可以 串聯的方式彼此電性連接；而同樣地，由於第三薄膜電晶 體233的汲極233d與第四薄膜電晶體234的源極234§連 接，因此第三薄膜電晶體233與第四薄膜電晶體234可以 串聯的方式彼此電性連接。 更詳細地說’請參照圖1A與圖1B，上述晝素陣列2〇〇 更包括第-接觸窗25卜第二接觸窗252、第三接觸窗W 以及第四接觸窗254。 第一接觸窗251位於第一晝素區2〇6的第一子晝素區 施内，且第一接觸窗251電性連接第-晝素電極^41、 第一薄膜電晶體23⑽及極231d以及第二薄膜電晶體况 極=°詳細而言’第—接觸窗251是形成在保護層 ΓΛ —晝素電極241暇透過第—接觸窗251而與 :潯膜電晶體231的汲極231d以及第二薄膜電晶體232 的源極232s電性連接。 窗252位於第一畫素區2〇6的第二子晝素區 ^内弟二接觸窗252電性連接第二晝素電極242以 體232的没極232d。詳細而言，第二接觸 齒252疋形成在保護層pv中，而第二晝素電極災則是 1380111 AU0812043 30769twf.doc/n 透過第二接觸窗252而與第 電性連接。 溥膜电晶體232的沒極232d 遍接觸* 253位於第二晝素區施的第〜子者素區 2·内’且第三接觸窗253電性連接第 及弟四薄膜電晶體234的汲極234d。 ^^ λ 窗253是形成在保護層ρν + 全^苐二接觸The unit 204 is constructed, but for convenience of description of the present embodiment, FIG. 1A and FIG. 1B only show a single pixel unit 204 as a representative. In an embodiment, the pixel unit 204 includes a first scan line 211, a second scan line 212, a first data line 221, a first switching element 231, a second switching element 232, a first halogen electrode 241, and a second Alizarin electrode 242. In another preferred embodiment, the pixel unit 204 further includes a third scan line 213, a second data line 222, a third switching element 233, a fourth switching element 234, a third pixel electrode 243, and a fourth pixel. Electrode 244. The first scan line 211, the second scan line 212, the first data line 221, and the first data line 222 are disposed on the substrate 202 to decipher the first pixel region 206 on the substrate 202, and the first pixel region 206 has a first sub-halogen region 206a and a second sub-norr region 206b. The second scan line 212, the third scan line 213, the first data line 221, and the second data line 222 are disposed on the substrate 202 to define a second halogen region 2〇8 on the substrate 202, and the first The prime region 208 has a first sub-tenk region 208a and a second sub-tenox region 208b. 1. The first switching element 231 is electrically connected to the second scan line 212 and the first data line 221, and is located in the first sub-cell region of the first pixel region 2〇6. Preferably, the first switching element 231 is located directly above the second scan line 212. The second switching element 232 is electrically connected to the first scan line 211 and the first switching element 231, and is located in the first sub-segment area 206a of the first pixel area 2〇6. Preferably, the second switching element 232 is located directly above the first scan ^ 1380111 AU0812043 30769twf.doc/n. The third switching element 233 is electrically connected to the third scan line 213 and the second element 222, and is located in the second sub-second of the second pixel region. . Preferably, the third „element 233 is located in the fourth switching element 234 and is electrically connected to the second scan line fastener B, and is located in the second argon region 2〇8 “two= zone lin. Preferably, the fourth switching element 234 is directly above the bit 212. The first sub-gold electrode of the Pingsui green first halogen electrode 241 is located at the second pixel of the first pixel region, and the first f element 231 and the second switching element are disposed in the first pixel region. The second sub-pixel region 206b is electrically connected to the second switching element 232, and the second sub-pixel element 234 is electrically connected to the second sub-pixel region. The fourth halogen electrode 244 is located in the brain of the second sub-tenox region of the u-region 208, and the three-switch 233 and the fourth switching element 234 are electrically connected. Referring to FIG. 1B and FIG. 1C simultaneously, in the embodiment 200, the first switching element 231, the second switching element are added, and the first switching element 233 and the fourth switching element 234 are respectively the first. The second, third, and fourth thin film transistors respectively have a gate, a source, and a drain. . . . For example, as shown in FIG. 1C, the thin-film electric body 231 has an interpole 231g, a source 231s, and a 汲1380111 AU0812043 30769 twf.doc/n pole 231 d. In the present embodiment, the first thin film transistor 231 The gate 23g is a part of the second scan line 212, the source 231s is electrically connected to the first data line 221, and the drain 231d is connected to the second sub-element of the first pixel region 2〇6. The region 206a extends inside. In addition, the gate insulating layer G is disposed above the gate 231g of the first thin film transistor 231, and the protective layer is further covered over the source 231s and the gate 231d of the first thin film transistor 231. The second thin film transistor 232 has a gate 232g, a source 232s and a drain 232d, wherein the gate 2 of the second thin film transistor 232 The 32g is exemplified by a portion of the first scan line 211. The source 232s of the second thin film transistor 232 is electrically connected to the drain 23丨d of the first thin film transistor 231. The immersion of the first thin film transistor 232 232d extends into the second sub-cell region 206b of the first pixel region 206. The second thin film transistor 233 has a gate 233g, a source 233s, and a pole 233d, which causes the gate of the third thin film transistor 233 233g is a part of the third scan line 213. The source 233s is electrically connected to the second data line 222, and the drain 233d extends to the inside of the second sub-pixel area 208b of the second pixel area 208. The film transistor 234 has a gate 234g, a source 234s, and a 234d', and a gate 234g of the fourth thin film transistor 234 is a part of the second scan line 212. The fourth thin film transistor The source 234s of 234 is electrically connected to the drain 233d of the third thin film transistor 233. The parallel electrode 234d of the fourth thin film transistor 234 extends into the first sub-tenon region 208a of the second halogen region 208. , first thin film transistor 231, second thin film transistor 232, 11 1138011 AU0812043 30769twf.doc/n three thin film transistor 233 and the fourth thin film transistor 234 further include a semiconductor channel layer and an ohmic contact layer (not labeled). However, those skilled in the art have learned and constructed the structure and operation of the aa abalone. In particular, in the present embodiment, since the drain 231d of the first thin film transistor 231 is connected to the source 232 of the second thin film transistor 232, the first thin film transistor 231 The second thin film transistor 232 can be electrically connected to each other in series; and likewise, since the drain 233d of the third thin film transistor 233 is connected to the source 234 of the fourth thin film transistor 234, the third thin film is electrically connected. The crystal 233 and the fourth thin film transistor 234 may be electrically connected to each other in series. More specifically, referring to Figs. 1A and 1B, the above-described pixel array 2A further includes a first contact window 25, a second contact window 252, a third contact window W, and a fourth contact window 254. The first contact window 251 is located in the first sub-tend region of the first halogen region 2〇6, and the first contact window 251 is electrically connected to the first-halogen electrode ^41, the first thin film transistor 23 (10) and the pole 231d. And the second thin film transistor state pole = ° in detail, the first contact window 251 is formed on the protective layer ΓΛ - 昼 电极 electrode 241 暇 through the first contact window 251 and: the drain 231d of the 浔 film transistor 231 and The source 232s of the second thin film transistor 232 is electrically connected. The window 252 is located in the second sub-cell region of the first pixel region 2〇6, and the second contact window 252 is electrically connected to the second pixel electrode 242 to the pole 232d of the body 232. In detail, the second contact tooth 252 is formed in the protective layer pv, and the second halogen electrode is 1380111 AU0812043 30769 twf.doc/n is electrically connected to the first through the second contact window 252. The dipole 232d pass of the bismuth film transistor 232 is in contact with * 253 in the second sub-segment region 2' of the second halogen region and the third contact window 253 is electrically connected to the second and fourth thin film transistors 234 Extreme 234d. ^^ λ window 253 is formed in the protective layer ρν + full ^ 苐 two contacts
透過第三接觸窗253而與第薄 =243則是 電性連接。 、㈣，專膜電晶體234的沒極234d 第四接觸窗254位於第二晝魏208的第二子圭何 2齡二且曰第四接觸窗254電性連接第四晝心^ 體233的汲極233d以及第四薄臈電晶體234 ϋ極2=。_細而言，第四接_ 254是形成在保護層 产一中而苐四晝素電極244則是透過第四接觸窗2科而與 第三薄膜電晶體233的沒極233d以及第四薄膜電晶體234 的源極234s電性連接。Through the third contact window 253, it is electrically connected to the thinner = 243. (4), the pole 234d of the special film transistor 234, the fourth contact window 254 is located at the second sub-second 2 of the second Wei 208, and the fourth contact window 254 is electrically connected to the fourth 昼 ^ 233 The drain 233d and the fourth thin germanium transistor 234 have a drain 2=. In a detailed manner, the fourth connection _254 is formed in the protective layer and the quaternary electrode 244 is transmitted through the fourth contact window 2 and the second electrode 233d of the third thin film transistor 233 and the fourth film. The source 234s of the transistor 234 is electrically connected.
、^外，本實施例的晝素陣列200還包括第一補償線261 以及第二補償線262’如圖1B所示。第一補償線261位於 第-晝素區206的第二子晝素區:2_内，並由第二接觸窗 處252往第二掃描線212延伸。第二補償線262位於第二 晝素區208的第—子晝素區2·内，並由第三接觸窗處 253往第二掃描線213延伸。在本實施例中，設置第一補 償線261的目的’主要是為了使第一晝素區2〇6中的第一 子晝素區206a與第二子晝素區2〇6b具有相同的開口率， 以避免第一畫素區206内的第一子晝素區2〇6a與第二子晝 13 1380111 AU0812043 30769twf.doc/n 素區206b的透光率產生差異。而基於相同的理由，第 償線262的設置可避免第二畫素區2〇8内的第一子書=補 208a與第二子晝素區208b的透光率產生差異。思紊® 一由於在畫素結構200中，第一薄膜電晶體231、 薄膜電晶體232、第三薄膜電晶體233及第四薄骐略曰〜 234的配置可使畫素結構2〇〇的開口區域對齊因: = 晝素結構200的顯示面板可避免斜紋瑕疵的產生。米用 第^實施例 圖2A為本發明第二實施例之畫素陣列3〇〇的 路圖。圖2B為晝素單元304的局部上視示意圖。圖^ 對應於圖2B的畫素陣列300巾，e_e，的剖面示意圖。由$ 本發明第二實施例的畫素陣列3〇〇是由多個晝素單元 所構成，目2B僅繪示-個晝素單元3〇4作為代表以 明本實施例。 請參照圖2A及圖2B，各晝素單元3〇4具有與圖ia 與圖1B所示的畫素單元2〇4相同或相似的構件，因此相 同的構件以相_標號表示，且在本實施例中不再贊述。 特別要說明的是，圖2A所示之晝素陣列3〇〇鱼圖 之晝素陣列不同之處在於晝素陣列遍更包括閘極弓丨線 1^’ 212w’213w。換言之’以其中一個晝素單元為例， 旦素早το 304與畫素單元204的不同之處在於，晝素單元 304更包括閘極引線211w，而閘極引線211〜平行第—次 料線221、第二資料線222設置，且閘極引線2Uw位於才貝目 14 1380111 AU0812043 30769twf.doc/n 鄰的第一資料線221與第二資料線222之間。 請參照圖2B及圖2C，各閘極引線會與對應的一條掃 描線電性連接。以閘極引線211w為例，在第一掃描線211 的上方設置閘極接觸窗GW便可使第一掃描線211與閘極 引線21 lw電性連接。閘極接觸窗Gw例如是形成在閘絕 緣層G與保護層PV中。 藉由上述第二實施例中多條閘極引線的設置，即可在 畫素陣列的其中一側設置用以連接掃描線211、212、213 以及資料線221、222、223的驅動晶片。換句話說，可將 閘極驅動晶片與源極驅動晶片整合在晝素陣列的其中一 側，甚至可將閘極驅動晶片與源極驅動晶片整合在相同的 驅動晶片上。因此，使用本實施例晝素陣列3〇〇的產品可 進一步提升其空間利用率。 第三實施例 圖3A為本發明第三實施例之晝素陣列4〇〇的局部上 視示意圖。圖3B為對應於圖3A的晝素陣列4〇〇中，f_f、 h-h’的剖面示意圖。請參照圖3A及圖3B，在此實施例中， 晝素陣列400是由位於基板402上的多個晝素單元4〇4所 構成’但為便於說明本實施例，圖3A僅綠示一個畫素單 元404作為代表。 一、 在一實施例中，晝素單元404包括第_掃描線411、 第二掃描線412、第一資料線421、第一開關元件431、第 二開關元件432、第一晝素電極441以及第二晝素電極 15 1380111 AU0812043 30769twf.doc/n 442。在另一較佳實施例中，晝素陣列400還包括第三掃描 線413、第二資料線422、第三開關元件433、第四開關元 件434、第三晝素電極443以及第四晝素電極444。 第一掃描線411、第二掃描線412、第一資料線421 以及第二資料線422設置於基板402上，以於基板402上 定義出第一晝素區406，且第一晝素區406具有第一子畫 素區406a與第二子晝素區406b。第二掃描線412、第三掃 描線413、第一資料421以及第二資料線422設置於基板 402上，以於基板402上定義出第二晝素區408,且第二晝 素區408具有第—子晝素區408a及第二子晝素區408b。 第一開關元件431與第二掃描線412以及第一資料線 421電性連接，並位於第一畫素區406的第一子晝素區4〇6a 内。較佳的是，第一開關元件431位於第二掃描線412的 正上方。 第二開關元件432與第一掃描線411以及第一開關元 件431電性連接，並位於第一晝素區406的第一子晝素區 4〇6a内。較佳的是，第二開關元件432位於第一掃描線411 的正上方。 第三開關元件433與第三掃描線413以及第二資料線 422電性連接，並且位於第二晝素區408的第二子晝素區 4〇8b内。較佳的是，第三開關元件433位於第三掃描線的 正上方。 第四開關元件434與第二掃描線412以及第三開關元 # 433電性連接，並且位於第二畫素區408的第二子晝素 16 1380111 AU0812043 30769twf.doc/n 區408b内。較佳的是，第四開關元件434位於第二掃描線 412的正上方。 心 第一晝素電極441位於第一晝素區406的第一子書素 區406a内，並且與第一開關元件431及第二開關元件^32 電性連接。第二晝素電極442位於第一晝素區406的第二 子晝素區406b内，並且與第二開關元件432電性連接。第 二晝素電極443位於第二畫素區408的第一子晝素區4〇8a 内，並且與第四開關元件434電性連接。第四晝素電極244 位於第二晝素區408的第二子晝素區4〇8b内，並且與第三 開關元件433及第四開關元件434電性連接。 上述晝素陣列400的第一開關元件431、第二開關元 件432、第三開關元件433、第四開關元件434分別為第一 薄膜電晶體431、第二薄膜電晶體432、第三薄膜電晶體 433與第四薄膜電晶體434。第一、第二、第三、第四薄膜 電晶體431，432, 433, 434分別具有閘極、源極以及汲極。 特別是，第一薄膜電晶體431的汲極431d以及第二薄膜電 晶體432的源極432s分別與第一畫素電極441電性連接， 第二薄膜電晶體433的汲極433d以及第四薄膜電晶體434 的源極434s分別與第四晝素電極444電性連接。 更洋細而言，畫素陣列400更包括第一接觸窗451、 第二接觸窗452、第三接觸窗453、第四接觸窗454、第五 接觸窗455以及第六接觸窗456。 第一接觸窗451位於第一晝素區4〇6的第一子畫素區 406a内，第一晝素電極441以及第二薄膜電晶體犯2的源 17 1380111 AU0812043 30769twf.doc/n 極432s藉由第一接觸窗451電性連接。第二接觸窗税 位於第一晝素區406的第二子晝素區4〇沾内，第二晝素電 ，442以及第二薄膜電晶體432的没極側藉由第二接觸 =52電性連接。第三接觸窗453位於第—晝素區條的 子晝素區406a内，第一晝素電極441以及第一薄膜電 晶體4 31軌極4 31 d藉由第三接觸窗45 3電性連接。第四 =窗伙位於第二畫素區彻的第一子晝素區聲内， f二晝素電極443以及第四薄膜電晶體434的没極43如 藉由第四接觸窗4M電性連接。第五接職455位於第二 旦素區備的第一子晝素區4G8b内，第四畫素電極444 Μ及第四薄膜電晶！| 434的源極43和藉由第五接觸窗价 電性連接。第六接觸窗衫6位於第二晝素區顿的第二子 晝素區4〇8b内，第四晝素電極444與第三薄膜電晶體433 的汲極433d藉由第六接觸窗456電性連接。 一更詳細的來說’第一薄膜電晶體431的汲極431d透過 第三接觸窗453與第-畫素電極441電性連接，且第二薄 膜電晶體432的源極432s又透過第一接觸窗451與第—晝 素電極^41電性連接’因此第一薄膜電晶體431的沒極 43ld與第一薄膜電晶體432的源極43乃兩者便得以電性 連接類似地，第二薄膜電晶體433的汲極433d透過第六 f觸窗456與第四晝素電極444電性連接，且第四薄膜電 晶體434的源極434s又透過第五接觸窗455與第四晝素電 極,444,性連接’因此第三薄膜電晶體433的汲極4別 與第四薄膜電晶體434的源極434s兩者便得以電性連接。 18 AU0812043 30769twf.doc/n 由於本實施例並非直接使第一薄膜電晶體431的汲極 431d與第一薄膜電晶體432的源極432s兩者直接連接， 因此第一薄膜電晶體431的汲極43id與第二薄膜電晶體 432的源極432s不需跨越整個第一畫素區4〇6的第一子畫 素區406a，如此可提高第一子晝素區4〇6a的開口率。類 似地，並非使第三薄膜電晶體433的汲極433d與第四薄膜 電晶體434的源極434s兩者直接連接，因此第三薄膜電晶 體433的汲極433d與第四薄膜電晶體434的源極43如不 需跨越整個第二晝素區408的第二子晝素區408a，如此可 提尚第二子晝素區408a的開口率。 在另一較佳實施例中，上述晝素陣列4〇〇更包括第一 擬接觸窗461以及第二擬接觸窗462。第一擬接觸窗461 位於苐一晝素區406的第二子晝素區4〇6b内，其與第二書 素電極442電性連接，如圖3B所示。而類似地，第二擬 接觸窗462位於第二畫素區408的第一子晝素區4〇8a内， 其與第二畫素電極443電性連接。要注意的是，上述第一 擬接觸窗461與第二擬接觸窗462僅為舉例說明，在其他 的實施例中’第一擬接觸窗461也可不與第二晝素電極442 免性連接’而苐二擬接觸窗462也可不與第三畫素電極443 電性連接。 設置第一擬接觸窗461的目的在使第一畫素區4〇6的 苐一子晝素區406a與第二子晝素區4〇6b具有相同的開口 率。而同樣地，第二擬接觸窗462的設置可使第二晝素區 4〇8的第一子晝素區408a與第二子晝素區408b具有相同 1380111 AU0812043 30769twf.doc/n 的開口率。 此外，類似於圖2B所示的畫素單元3〇4,在本發明之 另一實施例中，晝素單元404更可包括閘極引線4Uw，閘 極引線411w平行第一資料線421、第二資料線422設置， 且閘極引線411w位於相鄰的第一資料線421與第二資料 線422之間。而閘極引線41 lw是透過閘極接觸窗Gw與 第一掃描線411電性連接》 〇 上述各實施例所述之晝素陣列可與另一基板(舉例係 具有彩色濾光陣列的電極基板)組立在一起，以構成一顯示 面板，詳細說明如下。圖4A為本發明較佳實施例的顯示 面板500側視示意圖。圖4B為圖4A的彩色濾光陣列52〇 的局部上視示意圖。 請參照圖4A及圖4B，顯示面板500包括晝素陣列 510、彩色濾光陣列520以及顯示介質530。彩色渡光陣列 520位於晝素陣列510的對向。顯示介質53〇位於畫素陣 列510與彩色濾光陣列520之間，顯示介質530舉例係為 液晶層或是電泳等等。 特別是，晝素陣列510為上述第一實施例所述的晝素 陣列200、第二實施例所述的晝素陣列3〇〇或第三實施例 所述的晝素陣列400其中之一。 彩色濾光陣列520包括多個第一彩色濾光圖案521、 第二彩色濾光圖案522、第三彩色濾光圖案523，且第一彩 色濾光圖案521、第二彩色濾光圖案522及第三彩色濾光 圖案523各自為直列式排列。在本實施例中，第一彩色濾 20 1380111 AU0812043 30769twf.doc/n 光圖案521例如為紅色遽光圖案’第二彩色濾光圖案S22 例如為綠色濾光圖案，而第三彩色遽光圖案切例如 色濾光圖案。 Ί 上述第一至第三實施例所述的晝素陣列2〇〇、3〇〇 400其中之-中的第—畫素電極、第二晝素電極第三^ 素電極及/絲四4素電轉儀包括電極、反射^ 或是穿透電極與反射電極之組合，藉以實現料型顯=面 板、反射型顯示面板或是半穿反型顯示面板。 ^於顯示面板5〇〇具有上述第一至第三實施例所述 旦素陣列200、丨樣其中之一，因 可具有良好的顯示品質。 伋 、’’丁、上所述，由於本發明所提出的畫素陣列赢、 =區Tt產生錯位，因此可維持高開口率並避免二文 夸陵π "，由於本發贿糾的齡面板具有上述書 素陣列’批_品質請、㈣湘 ^ 電效果。 jI八令 定太本發明已轉施方式贿如上，財並非用以限 ’任何所屬技術領域中具有通常知識者，在不脫 精神和範圍内，當可作麟之更動與潤飾，故 準：之保濩範圍當視後附之申請專利範圍所界定者為 【圖式簡單說明】 的等效電 圖1Α為本發明第一實施例之畫素陣列 21 1380111 AU0812043 30769twf.doc/n 路圖。 圖1B為晝素陣列2〇〇的上視示意圖。 圖1C為對應於圖2B的晝素陣列中，a_a，、b_b，、 c-c’及d-d’的剖面示意圖。 圖2A為本發明第二實施例之晝素陣列的等效電 路圖。 圖2B為晝素單元304的局部上視示意圖。 圖2C為對應於圖2B的晝素陣列3〇〇巾，e_e，的剖面 示意圖。 _圖3A為本發明第二實施例之晝素降列働的局部上 視不意圖。 圖3B為對應於圖3A的畫素陣列4〇〇十，、h h， 的剖面示意圖。 圖4A為本發明較佳實施例的顯示面板5〇〇側視示意 圖。 〜 圖4B為圖4A的彩色濾光陣列520的局部上視示音 圖。 【主要元件符號說明】 200、410、510 :晝素陣列 202、402 :基板 204、304、404 :晝素單元 206、406 :第一晝素區 206a、208a、406a、408a ··第一子畫素區 22 1380111 AU0812043 30769twf.doc/n 206b、208b、406b、408b :第二子晝素區 • 208、408 :第二晝素區 211、 411 :第一掃描線 212、 412 :第二掃描線 213、 413 :第三掃描線 221、 421 :第一資料線 222、 422 :第二資料線 231、431 :第一開關元件、第一薄膜電晶體 ® 232、432 :第二開關元件、第二薄膜電晶體 233、 433 :第三開關元件、第三薄膜電晶體 234、 434 :第四開關元件、第四薄膜電晶體 231g、232g :閘極 231s、232s、233s、234s、431s、432s、433s、434s : 源極 231d、232d、233d、234d、431d、432d、433d、434d : 汲極 參 241、441.:第一晝素電極 242、 442 :第二晝素電極 243、 443 :第三晝素電極 244、 444 :第四晝素電極 251、 451 :第一接觸窗 252、 452 :第二接觸窗 253、 453 :第三接觸窗 254、 454 :第四接觸窗 23 1380111 AU0812043 30769twf.doc/n 261 :第一補償線 262 :第二補償線 455 :第五接觸窗 456 :第六接觸窗 461 :第一擬接觸窗 462 :第二擬接觸窗 G:閘絕緣層 GW :閘極接觸窗 PV :保護層 500 :顯示面板 520 :彩色濾光陣列 521 :第一彩色濾光圖案 522 :第二彩色濾光圖案 523 :第三彩色濾光圖案 530 :顯示介質 24In addition, the pixel array 200 of the present embodiment further includes a first compensation line 261 and a second compensation line 262' as shown in FIG. 1B. The first compensation line 261 is located in the second sub-tenon region of the first-norten region 206: 2_ and extends from the second contact window 252 to the second scan line 212. The second compensation line 262 is located in the first sub-halogen region 2· of the second halogen region 208 and extends from the third contact window 253 to the second scanning line 213. In the present embodiment, the purpose of setting the first compensation line 261 is mainly to make the first sub-cell area 206a of the first pixel region 2〇6 and the second sub-tend region 2〇6b have the same opening. The rate is such as to avoid a difference in light transmittance between the first sub-alloy region 2〇6a and the second sub- 13 1338011 AU0812043 30769 twf.doc/n region 206b in the first pixel region 206. For the same reason, the setting of the first pay line 262 can avoid a difference in transmittance between the first sub-book = complement 208a and the second sub-tenon region 208b in the second pixel area 2〇8. In the pixel structure 200, the configuration of the first thin film transistor 231, the thin film transistor 232, the third thin film transistor 233, and the fourth thin 骐 曰 234 can make the pixel structure 2 〇〇 The opening area is aligned with: = The display panel of the halogen structure 200 avoids the occurrence of twill weave. BACKGROUND OF THE INVENTION Fig. 2A is a road view of a pixel array 3〇〇 according to a second embodiment of the present invention. 2B is a partial top plan view of the halogen unit 304. Figure 2 is a schematic cross-sectional view of the pixel array 300, e_e, corresponding to Figure 2B. The pixel array 3 of the second embodiment of the present invention is composed of a plurality of pixel units, and the object 2B shows only a single pixel unit 3〇4 as a representative embodiment. Referring to FIG. 2A and FIG. 2B, each of the pixel units 3〇4 has the same or similar components as the pixel units 2〇4 shown in FIG. 1A and FIG. 1B, and therefore the same members are denoted by phase_labels, and It is not mentioned in the examples. It is to be noted that the pixel array of the squid array 3 shown in Fig. 2A differs in that the pixel array includes the gate bow line 1^' 212w' 213w. In other words, in the case of one of the pixel units, the difference between the pixel unit 304 and the pixel unit 204 is that the pixel unit 304 further includes the gate lead 211w, and the gate lead 211 is parallel to the second-order line 221. The second data line 222 is disposed, and the gate lead 2Uw is located between the first data line 221 and the second data line 222 adjacent to the head 14 1438011 AU0812043 30769 twf.doc/n. Referring to FIG. 2B and FIG. 2C, each gate lead is electrically connected to a corresponding one of the scan lines. Taking the gate lead 211w as an example, the gate contact window GW is disposed above the first scan line 211 to electrically connect the first scan line 211 and the gate lead 21 lw. The gate contact window Gw is formed, for example, in the gate insulating layer G and the protective layer PV. With the arrangement of the plurality of gate leads in the second embodiment described above, a driving wafer for connecting the scanning lines 211, 212, 213 and the data lines 221, 222, 223 can be disposed on one side of the pixel array. In other words, the gate driver wafer and the source driver wafer can be integrated on one side of the pixel array, and even the gate driver wafer and the source driver wafer can be integrated on the same driver wafer. Therefore, the use of the product of the pixel array 3 of the present embodiment can further improve the space utilization rate. THIRD EMBODIMENT Fig. 3A is a partial top plan view showing a pixel array 4A according to a third embodiment of the present invention. Fig. 3B is a schematic cross-sectional view of f_f, h-h' corresponding to the pixel array 4A of Fig. 3A. Referring to FIG. 3A and FIG. 3B, in this embodiment, the pixel array 400 is composed of a plurality of halogen elements 4〇4 located on the substrate 402. However, for convenience of description of the embodiment, FIG. 3A only shows one green. The pixel unit 404 is representative. In one embodiment, the pixel unit 404 includes a first scan line 411, a second scan line 412, a first data line 421, a first switching element 431, a second switching element 432, a first halogen electrode 441, and The second halogen electrode 15 1380111 AU0812043 30769twf.doc/n 442. In another preferred embodiment, the pixel array 400 further includes a third scan line 413, a second data line 422, a third switching element 433, a fourth switching element 434, a third halogen electrode 443, and a fourth pixel. Electrode 444. The first scan line 411, the second scan line 412, the first data line 421, and the second data line 422 are disposed on the substrate 402 to define a first pixel region 406 on the substrate 402, and the first pixel region 406 There is a first sub-pixel area 406a and a second sub-tenk area 406b. The second scan line 412, the third scan line 413, the first data 421, and the second data line 422 are disposed on the substrate 402 to define a second halogen region 408 on the substrate 402, and the second pixel region 408 has The first sub-small element area 408a and the second sub-tenon area 408b. The first switching element 431 is electrically connected to the second scan line 412 and the first data line 421, and is located in the first sub-cell region 4〇6a of the first pixel area 406. Preferably, the first switching element 431 is located directly above the second scan line 412. The second switching element 432 is electrically connected to the first scan line 411 and the first switching element 431, and is located in the first sub-cell region 4〇6a of the first pixel region 406. Preferably, the second switching element 432 is located directly above the first scan line 411. The third switching element 433 is electrically connected to the third scan line 413 and the second data line 422, and is located in the second sub-cell area 4〇8b of the second pixel region 408. Preferably, the third switching element 433 is located directly above the third scanning line. The fourth switching element 434 is electrically coupled to the second scan line 412 and the third switching element # 433 and is located in the second sub-cell 16 1380111 AU0812043 30769 twf.doc/n region 408b of the second pixel region 408. Preferably, the fourth switching element 434 is located directly above the second scan line 412. The first first pixel electrode 441 is located in the first sub-pixel region 406a of the first halogen region 406, and is electrically connected to the first switching element 431 and the second switching element 32. The second halogen electrode 442 is located in the second sub-cell region 406b of the first halogen region 406 and is electrically connected to the second switching element 432. The second halogen electrode 443 is located in the first sub-tenon region 4A8a of the second pixel region 408, and is electrically connected to the fourth switching element 434. The fourth halogen electrode 244 is located in the second sub-tenon region 4〇8b of the second halogen region 408, and is electrically connected to the third switching element 433 and the fourth switching element 434. The first switching element 431, the second switching element 432, the third switching element 433, and the fourth switching element 434 of the above-described pixel array 400 are a first thin film transistor 431, a second thin film transistor 432, and a third thin film transistor, respectively. 433 and fourth thin film transistor 434. The first, second, third, and fourth thin film transistors 431, 432, 433, and 434 have a gate, a source, and a drain, respectively. In particular, the drain 431d of the first thin film transistor 431 and the source 432s of the second thin film transistor 432 are electrically connected to the first pixel electrode 441, the drain 433d of the second thin film transistor 433, and the fourth thin film, respectively. The source 434s of the transistor 434 is electrically connected to the fourth halogen electrode 444, respectively. More specifically, the pixel array 400 further includes a first contact window 451, a second contact window 452, a third contact window 453, a fourth contact window 454, a fifth contact window 455, and a sixth contact window 456. The first contact window 451 is located in the first sub-pixel region 406a of the first halogen region 4〇6, the first halogen electrode 441 and the second thin film transistor 2 source 17 1380111 AU0812043 30769twf.doc/n pole 432s The first contact window 451 is electrically connected. The second contact window tax is located in the second sub-dielectric region 4 of the first halogen region 406, and the second halogen electrode, 442 and the second thin film transistor 432 have the second contact = 52 Sexual connection. The third contact window 453 is located in the sub-tenon region 406a of the first halogen region strip, and the first halogen electrode 441 and the first thin film transistor 4 31 rail 4 31 d are electrically connected by the third contact window 45 3 . . The fourth = window scorpion is located in the sound of the first sub-segment region of the second pixel region, and the f-diode electrode 443 and the electrode 43 of the fourth thin film transistor 434 are electrically connected by the fourth contact window 4M. . The fifth receiver 455 is located in the first sub-divinity zone 4G8b of the second-parent zone, the fourth pixel electrode 444 第四 and the fourth film electro-crystal! The source 43 of 434 is electrically connected to the fifth contact window. The sixth contact window 6 is located in the second sub-dielectric region 4〇8b of the second halogen region, and the fourth halogen electrode 444 and the drain 433d of the third thin film transistor 433 are electrically connected by the sixth contact window 456. Sexual connection. In more detail, the drain 431d of the first thin film transistor 431 is electrically connected to the first pixel electrode 441 through the third contact window 453, and the source 432s of the second thin film transistor 432 is further transmitted through the first contact. The window 451 is electrically connected to the first halogen electrode ^41. Therefore, the electrode 43 of the first thin film transistor 431 and the source 43 of the first thin film transistor 432 are electrically connected. Similarly, the second film The drain 433d of the transistor 433 is electrically connected to the fourth pixel electrode 444 through the sixth f-touch window 456, and the source 434s of the fourth thin film transistor 434 is further transmitted through the fifth contact window 455 and the fourth halogen electrode. 444, the sexual connection 'Therefore, both the drain 4 of the third thin film transistor 433 and the source 434s of the fourth thin film transistor 434 are electrically connected. 18 AU0812043 30769twf.doc/n Since the present embodiment does not directly directly connect the drain 431d of the first thin film transistor 431 and the source 432s of the first thin film transistor 432, the drain of the first thin film transistor 431 The source 432s of the 43id and the second thin film transistor 432 does not need to span the first sub-pixel area 406a of the entire first pixel region 4〇6, so that the aperture ratio of the first sub-tenon region 4〇6a can be improved. Similarly, the drain 433d of the third thin film transistor 433 and the source 434s of the fourth thin film transistor 434 are not directly connected, so the drain 433d of the third thin film transistor 433 and the fourth thin film transistor 434 The source 43 does not need to span the second sub-tenon region 408a of the entire second halogen region 408, so that the aperture ratio of the second sub-tenon region 408a can be raised. In another preferred embodiment, the pixel array 4 further includes a first dummy contact window 461 and a second pseudo contact window 462. The first pseudo-contact window 461 is located in the second sub-tenon region 4〇6b of the monolayer region 406, and is electrically connected to the second pixel electrode 442, as shown in FIG. 3B. Similarly, the second quasi-contact window 462 is located in the first sub-tend region 4A8a of the second pixel region 408, which is electrically connected to the second pixel electrode 443. It should be noted that the first pseudo-contact window 461 and the second pseudo-contact window 462 are merely illustrative. In other embodiments, the first pseudo-contact window 461 may not be connected to the second halogen electrode 442. The second contact window 462 may not be electrically connected to the third pixel electrode 443. The purpose of providing the first pseudo-contact window 461 is such that the first sub-segment region 406a of the first pixel region 4〇6 and the second sub-halogen region 4〇6b have the same aperture ratio. Similarly, the second pseudo-contact window 462 is arranged such that the first sub-tenox region 408a of the second halogen region 4〇8 and the second sub-quartel region 408b have the same aperture ratio of 1380111 AU0812043 30769twf.doc/n. . In addition, similar to the pixel unit 3〇4 shown in FIG. 2B, in another embodiment of the present invention, the pixel unit 404 may further include a gate lead 4Uw, and the gate lead 411w is parallel to the first data line 421, The second data line 422 is disposed, and the gate lead 411w is located between the adjacent first data line 421 and the second data line 422. The gate lead 41 lw is electrically connected to the first scan line 411 through the gate contact window Gw. The pixel array described in the above embodiments may be combined with another substrate (for example, an electrode substrate having a color filter array). ) grouped together to form a display panel, as detailed below. 4A is a side elevational view of a display panel 500 in accordance with a preferred embodiment of the present invention. 4B is a partial top plan view of the color filter array 52A of FIG. 4A. Referring to FIGS. 4A and 4B, the display panel 500 includes a pixel array 510, a color filter array 520, and a display medium 530. The color light-emitting array 520 is located opposite the pixel array 510. The display medium 53 is located between the pixel array 510 and the color filter array 520. The display medium 530 is exemplified by a liquid crystal layer or electrophoresis or the like. In particular, the halogen array 510 is one of the halogen array 200 described in the first embodiment, the halogen array 3 described in the second embodiment, or the halogen array 400 described in the third embodiment. The color filter array 520 includes a plurality of first color filter patterns 521, a second color filter pattern 522, and a third color filter pattern 523, and the first color filter pattern 521, the second color filter pattern 522, and the first The three color filter patterns 523 are each in an in-line arrangement. In this embodiment, the first color filter 20 1380111 AU0812043 30769 twf.doc / n light pattern 521 is, for example, a red calender pattern, the second color filter pattern S22 is, for example, a green filter pattern, and the third color calender pattern is cut. For example, a color filter pattern.昼 The first pixel element of the above-described first to third embodiments, the first pixel electrode, the second halogen electrode, the third electrode, and/or the wire 4 The electrorotator includes an electrode, a reflection ^ or a combination of a penetrating electrode and a reflective electrode, thereby realizing a material type display panel, a reflective display panel or a transflective display panel. The display panel 5 has one of the denier arrays 200 described in the first to third embodiments described above, because it has good display quality.汲, '', as described above, since the pixel array of the present invention wins and the region Tt is misaligned, it is possible to maintain a high aperture ratio and avoid the two-language π " The panel has the above-mentioned pixel array 'batch _ quality please, (four) Xiang ^ electricity effect. jI 八令定太 The invention has been transferred to the bribe as above, the wealth is not limited to 'anyone with the usual knowledge in the technical field, in the spirit and scope, when it can be changed and retouched, so: The scope of the protection is defined as the equivalent electrogram of the schematic description of the appended claims, which is the pixel array 21 1380111 AU0812043 30769twf.doc/n road diagram of the first embodiment of the present invention. Figure 1B is a top plan view of a halogen array 2〇〇. Fig. 1C is a schematic cross-sectional view showing a_a, b_b, c-c' and d-d' in the pixel array corresponding to Fig. 2B. Fig. 2A is an equivalent circuit diagram of a pixel array according to a second embodiment of the present invention. 2B is a partial top plan view of the halogen unit 304. Figure 2C is a schematic cross-sectional view of the alizarin array 3 wipe, e_e, corresponding to Figure 2B. Fig. 3A is a partial top view of a halogen drop in the second embodiment of the present invention. 3B is a schematic cross-sectional view of the pixel array 4〇〇10, h h corresponding to FIG. 3A. 4A is a side elevational view of the display panel 5 in accordance with a preferred embodiment of the present invention. ~ Figure 4B is a partial top view of the color filter array 520 of Figure 4A. [Description of main component symbols] 200, 410, 510: halogen arrays 202, 402: substrates 204, 304, 404: halogen units 206, 406: first halogen regions 206a, 208a, 406a, 408a · · first sub Pixel area 22 1380111 AU0812043 30769twf.doc/n 206b, 208b, 406b, 408b: second sub-divinity area • 208, 408: second pixel area 211, 411: first scan line 212, 412: second scan Lines 213, 413: third scan lines 221, 421: first data lines 222, 422: second data lines 231, 431: first switching element, first thin film transistor ® 232, 432: second switching element, Two thin film transistors 233, 433: third switching element, third thin film transistor 234, 434: fourth switching element, fourth thin film transistor 231g, 232g: gates 231s, 232s, 233s, 234s, 431s, 432s, 433s, 434s: source 231d, 232d, 233d, 234d, 431d, 432d, 433d, 434d: bismuth 241, 441.: first halogen electrode 242, 442: second halogen electrode 243, 443: third Alizarin electrodes 244, 444: fourth halogen electrodes 251, 451: first contact windows 252, 452: second contact windows 253, 453: Third contact window 254, 454: fourth contact window 23 1380111 AU0812043 30769twf.doc / n 261: first compensation line 262: second compensation line 455: fifth contact window 456: sixth contact window 461: first intended contact Window 462: second pseudo-contact window G: gate insulating layer GW: gate contact window PV: protective layer 500: display panel 520: color filter array 521: first color filter pattern 522: second color filter pattern 523 : third color filter pattern 530 : display medium 24