1377530 05759ITW 18169twf.doc/e 九、發明說明： * 【發明所屬之技術領域】 ' 本發明是關於一種平面顯示器驅動裝置，且特別是關 於一種利用同時導通多條閘極線並***黑資料之方式來達 到改善顯示品質的液晶顯示器驅動裝置及其方法。 . 【先前技術】 : 在消費性電子產品中，液晶顯示器提供娛樂及即時影 像等多種功能，所以經常需要顯示動態影像，尤其是液晶 • 電視。然而，由於液晶顯示器是屬於保持型式(h〇、id-typr) 的發光模式，且液晶的反應速度較慢，因此當使用者在觀 看液晶顯示器所播放的動態影像時，往往會因人眼的積分 效應影響，而使得觀看到的影像產生邊緣殘像(edge blur) 等問題^ 在先前技術中，動態影像之顯示品質的改善方式主要 有液晶加速驅動(0Verdrive)與畫面插黑(black丨郎时丨⑽)兩 種方式。凊參照圖卜其繪示一種先前的晝面插黑方式之 • 驅動波形圖，係揭露於美國專利申請案第2002/0084959 號。此方式利用閘極致能信號G〇m將閘極線GL1上之掃 描脈衝信號分為第一期間2〇5與第二期間2〇8，其中閘極 線GL1中的掃描脈衝SP位於第-期間205 ;…；而閘極 線GL32則纪由另一個閘極致能信號分為第一期間2〇5與 第二期間208，其閘極線GU2中的掃描脈衝sp則位於第 一期間208。如此一來，在同一個掃描脈衝信號的週期中， 譬如可以分別在第一期間2〇5寫入正常資料D到問極線 1377530 05759ITW 18169twf.d〇c/e Z 第二期間細寫入黑資料B至閘極線GL32中。 達到降低邊緣殘影，但必須增加源極驅動 太二ί率，因此增加源極驅動器的電路複雜性，而此 :==短液晶畫素的充電時間，因此影響顯示品質。 本發明的目的是在提供一種液晶顯示器驅動裝置，利 2有相同掃描脈衝期間的多個掃描脈衝信號，並配合多1377530 05759ITW 18169twf.doc/e IX. Description of the invention: * [Technical field of the invention] The present invention relates to a flat panel display driving device, and more particularly to a method for simultaneously turning on a plurality of gate lines and inserting black data. A liquid crystal display driving device and method for improving display quality are achieved. [Prior Art]: In consumer electronics, LCD monitors provide a variety of functions such as entertainment and instant video, so it is often necessary to display motion pictures, especially LCD TVs. However, since the liquid crystal display is a light-emitting mode of a hold type (h〇, id-typr), and the reaction speed of the liquid crystal is slow, when the user views the motion image played by the liquid crystal display, it is often caused by the human eye. The effect of the integral effect causes the observed image to produce edge blur and other problems. ^ In the prior art, the display quality of the moving image is improved mainly by the liquid crystal acceleration drive (0Verdrive) and the screen insertion black (black 丨郎) Time 丨 (10)) two ways. A driving waveform diagram of a prior art black-faced insertion method is disclosed in U.S. Patent Application Serial No. 2002/0084959. In this manner, the scan pulse signal on the gate line GL1 is divided into the first period 2〇5 and the second period 2〇8 by the gate enable signal G〇m, wherein the scan pulse SP in the gate line GL1 is located in the first period 205;...; and the gate line GL32 is divided into a first period 2〇5 and a second period 208 by another gate enable signal, and the scan pulse sp in the gate line GU2 is located in the first period 208. In this way, during the period of the same scan pulse signal, for example, the normal data D can be written to the interrogation line 1377530 05759ITW 18169twf.d〇c/e Z in the first period 2〇5, respectively. Data B is in the gate line GL32. To achieve the reduction of edge afterimage, but the source drive must be increased too much, thus increasing the circuit complexity of the source driver, and this: == short liquid crystal pixel charging time, thus affecting the display quality. SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display driving device which has a plurality of scanning pulse signals during the same scanning pulse and cooperates with
能信號’以達難面歸的目的，進轉低影像 邊緣殘像，提升顯示品質。 本發明的另一目的是在提供一種液晶顯示器驅動方 ’’利用輸出致能信號控制掃描脈衝信號巾資料寫入時序 ，灰階寫入時序’使晝素有較長的充電時間並達到晝面插 黑的目的，進而降低邊緣殘像，提升顯示品質。The signal can be used to achieve the goal of returning to the low image edge to improve the display quality. Another object of the present invention is to provide a liquid crystal display driver that uses an output enable signal to control the timing of writing a scan pulse signal, and the gray scale write timing is such that the pixel has a longer charging time and reaches the surface. The purpose of black insertion is to reduce edge residual images and improve display quality.
。為達成上述與其他目的，本發明提出一種液晶顯示器 驅動裝置，用以驅動液晶顯示器之面板，其中面板包括多 個閉極線組’每-該些閘極線組包括多個閉極線。此驅動 裝置包括時序控制器―、源極驅動器以及閘極驅動器。其中， 時序控制H接收景彡像信號並輸出祕信號、_信號以及 致能控制信號。源極驅動器電性連接至時序控制器，並根 據源極信號輸出資料信號與灰階信號。資料信號即上述提 及的正常資料，而灰階信號可依設計而為某一灰階資料， 在本發明一實施例中例如為上述提及的黑資料。 閘極驅動n電性連接至時序控㈣，根制極信號提 供具有相同掃描脈衝期間多個掃描脈衝信號，並根據致能 ⑧ 6 1377530 05759ITW 18 丨 69twf. doc/e =:== =號分別使掃描脈衝信號在該 之-。二；枓寫入期間與灰階寫入期間二者其中 間僅導通閘極線其期::導掃描脈衝信號在同-時 晝素接收源極驅動器輸出的該極線所對應的 =線=應，素接收源極驅動器輸出的該 Ϊ二Ϊί:信號的寫入為一次-條閘極線的方式 如此可的寫入則是一次多條間極線同時寫入， 如此了增加畫素寫入時間與降低閘極驅動器的工作頻率。 =另-觀點來看，本發明提出—種液晶顯示器驅動方 ’用^驗晶顯示器之面板，其中面板包括多個問極 t且’母-$些間極線組包括多個閘極線。此驅動方法 括下列步驟：首先，提供致能㈣信號，接下來，提供具 有相同掃概衝_的多鱗描脈衝錢。然後撼^ 能控，信號，產生與掃描脈衝信號相對應的輸出致能信 號，這些輸出致能信號分別使掃描脈衝信號具有資料二 期間與^灰階寫人期間二者其中之—以控制面板中的問極 線。在資料寫入期間中，同一時間僅導通閘極線其中之一， 且被導通的該閘極線所對應的畫素接收資料信號，以及 灰階寫入期間中，導通閘極線組其中之一，且被導通的該 閘極線組所對應的晝素接收灰階信號。 上述之閘極驅動器，在一實施例中更包括移位暫存器 (shift register)與準位移位器〇evei shifter)。移位暫存5| 7 1377530 05759ITW 18169twf.doc/e 時序控制器所提供的閘極信號以及致能控制信號，暫存並 使掃描脈衝信號移位至下一個閘極線組上，作為控制下一 個閘極線組的脈衝信號。而準位移位器用以調整掃描 信號的電壓位準。 一上述驅動器’在—實施例中更包括多個輸出致 致能單元根據致能控制信號產生輸出致 二:二母=能信號在㈣寫人期間具有不同的 ::期:灰階寫入期間中之每一 動方Ϊ照佳實施例所述’上述之液晶顯示器驅 ;對應的多個輸出致能信號分別使掃描脈衝 下列步驟:^ 間步驟中，在一實施例中更包括 ’判斷輸出致能信號是否在資料寫入划Η 或在灰階寫入期間中。若在仕貝料寫入期間 -輸出致能信號產生相位差，並:二二則依序使每 不同的致能期間；以友若在灰階寫2致能信號具有 ==相同的相位’並使每-輪“信Sit: ζ信號配合多間的多個掃描脈 號之資料寫入期間與灰階寫入期，5驅動器輪出的信 的數量’並能以較低的工作率，曰遠大幅減少移位暫存器 降低影像邊緣殘像，並可維持:^晝面插黑的S的， 的晝素充電時間，提升 8 05759ITW 18169twf.doc/e 影像畫面品質。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下。 【實施方式】 為降低液晶顯示器在顯示動態影像時所產生的晝面 殘景^問題’在本發明—實_巾，閘極驅動器輸出具有相 同掃描脈衝期間的多個掃描脈衝信號並配合輸出致能信 以同時導通多條閘極線並輸人譬如黑資料之灰階信 ，維持晝素充電時間長度下，降低液晶顯示器晝面殘 〜問題利用本發明之架構，尚可降低問極電路工作 頻率與電路複雜度。 —請參照圖2 ’其綠示為根據本發明—實施例之液晶顯 不器驅動裝置的方塊圖。本装置包括時序控制器31〇、源 ，驅=器320以及閘極驅動器33〇。時序控制器3川接收 〜像號’並根據此影像信號輸出源極信號、閘極信號以 及致能控偷號。源極驅㈣挪雜連接至時序控制器 3^，並根據時序控制器31〇所輸出的源極信號，輸出資料 1與灰階信號。資料信號即上述提及的正常資料，而灰 階=可依設計而為某—灰階資料，在本發明—實施例中 1 〇、ΐ述提及的黑資料。閘極驅動器330電性連接至時 I制时310,並根據所接收到的閘極信號，同時產生具 目同知描脈衝躺的多個掃描脈衝信號州，分別控制 反340中的多條閘極線348。再者，間極驅動器根 05759ITW 18169twf.doc/e 05759ITW 18169twf.doc/e 號分別使掃描脈衝信 入期間與灰階寫入期 據致能控制信號產生多個輸出致能信 號338在該掃描脈衝期間具有資料寫 間兩種期間其中一種。 " 更進-步解釋前述之多個掃描脈衝信號338，分別於 1 面中的多條問極線348。即是將液晶顯示器面ΐ 0 括的多條閘極線348分組，每數條間極線348形 極線组349’分別由對應到的掃描脈衝信號組339 二ί 中’以3條閘極線348為-閘極線組 * ^ :、6兒明，所以每一掃描脈衝信號組339包括3 =描脈衝信號338，在個別掃描脈衝信號組339中的每 二描脈衝㈣338具有相同掃描脈衝期間，也就是說在 同：組中的掃描脈衝信號339具有相同的掃描脈衝。一般 而β，較適合的分組數量為3〜1〇條閘極線一組。 其中’以閘極線組3奶為例，在資料寫入期間中，掃 二Γ,5號組339在同一時間僅導通相對應的閘極線組 的-條閘極線348’避免同-資料信號寫入多條閘極 ^ 48之晝素中。❿源極驅動㈣320則在其中-條閘極線 ^8。被導通時，輸出資料信號至相對應的閘極線348的晝 二在灰&寫入期間中，掃描脈衝信號組339同時導通閘 °線、、且349令所有的閘極線348，而源極驅動器320則在 導通期間t輸出譬如黑資料之灰階信號至閘極線组3的 所對應的晝素。 、， 处。〇閘極驅動器330更包括移位暫存器332、多個輸出致 能早元334以及準位移位器336。每一掃描脈衝信號338 1377530 05759ITW 18169twf.doc/e 在輸出之前皆會分別經由上述三個單元做位移、波形調整 與電壓位準調整。為使本技術領域者能更清楚本發明種 術特徵，以下說明將配合圖3 一併說明。請參照圖3，立 根據本發明-實施例之掃描信號波形時序圖。閘極 線時序Gi〜G3n分別代表不同閘極線348上之時序圖。在 本貫施例中，先以3條閘極線348為一間極線組339 作^說明。所以閘極線時序G1〜G3為一組，分別對庫到閑 f線組349令的3條閘極線348，如圖3所示， 序G1〜G3具有相同的掃描脈衝信號4〇5〜4〇7 , 衝信號405〜407具有相同的掃描脈衝 ^ 衝期㈣並非所有間極線338皆被導通，而. To achieve the above and other objects, the present invention provides a liquid crystal display driving device for driving a panel of a liquid crystal display, wherein the panel includes a plurality of closed line groups each of the plurality of gate lines including a plurality of closed lines. This driver includes a timing controller, a source driver, and a gate driver. The timing control H receives the scene image signal and outputs the secret signal, the _ signal, and the enable control signal. The source driver is electrically connected to the timing controller, and outputs a data signal and a gray scale signal according to the source signal. The data signal is the normal data mentioned above, and the gray scale signal can be designed as a gray scale data. In an embodiment of the invention, for example, the black data mentioned above. The gate driver n is electrically connected to the timing control (4), and the root electrode signal provides a plurality of scan pulse signals during the same scan pulse, and according to the enable 8 6 1377530 05759ITW 18 丨 69twf. doc/e =:== = respectively Make the scan pulse signal in the -.枓; 枓 write period and gray-scale write period between the two only open the gate line period:: the scan pulse signal at the same time - the pixel receives the source driver output corresponding to the line = = Should be, the source receives the output of the source driver. The signal is written as a one-gate gate. The way to write is that multiple inter-pole lines are simultaneously written, thus increasing the pixel write. Enter the time and reduce the operating frequency of the gate driver. In another aspect, the present invention provides a panel for a liquid crystal display driver, wherein the panel includes a plurality of gates and the plurality of gate lines includes a plurality of gate lines. This driving method includes the following steps: First, the enable (four) signal is provided, and then, the multi-scale pulse money having the same sweep _ is provided. Then, the control signal can generate an output enable signal corresponding to the scan pulse signal, and the output enable signal respectively causes the scan pulse signal to have both the data period and the gray scale write period - to the control panel In the middle of the line. During the data writing period, only one of the gate lines is turned on at the same time, and the pixel corresponding to the turned-on gate line receives the data signal, and during the gray-scale writing period, the gate group is turned on. First, the pixel corresponding to the gate group that is turned on receives the gray scale signal. The gate driver described above further includes a shift register and a quasi-shifter 〇evei shifter in one embodiment. Shift temporary storage 5| 7 1377530 05759ITW 18169twf.doc/e The gate signal and the enable control signal provided by the timing controller temporarily store and shift the scan pulse signal to the next gate line group as control A pulse signal of a gate line group. The quasi-positioner is used to adjust the voltage level of the scan signal. A driver as described above - in the embodiment further comprising a plurality of output enable units generating an output according to the enable control signal: the second mother = energy signal has a different period during the (4) write period:: period: gray scale write period Each of the actuators is described in the preferred embodiment of the above-mentioned liquid crystal display drive; the corresponding plurality of output enable signals respectively cause the scan pulse to be in the following steps: in the step, in an embodiment further includes 'judgement output Whether the signal can be written in the pad or in the grayscale write period. If during the writing process, the output enable signal produces a phase difference, and: two or two sequentially make each different enable period; if the friend writes the 2 enable signal in grayscale with == the same phase' And each round of "letter Sit: ζ signal with multiple scanning pulse number data writing period and grayscale writing period, 5 drives to rotate the number of letters' and can work at a lower rate,曰 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅 大幅The above and other objects, features, and advantages of the invention will be apparent from the description of the preferred embodiments of the invention. In the present invention, the gate driver outputs a plurality of scan pulse signals having the same scan pulse and cooperates with the output enable signal to simultaneously turn on the plurality of gate lines. Gray-order letter that loses human data, such as black data Under the length of the charging time of the pixel, the surface of the liquid crystal display is reduced. Problem With the architecture of the present invention, the operating frequency and circuit complexity of the gate circuit can be reduced. - Please refer to FIG. 2 'The green color is according to the present invention - implementation A block diagram of a liquid crystal display driver device. The device includes a timing controller 31, a source, a driver 320, and a gate driver 33. The timing controller 3 receives the image number ' and outputs according to the image signal The source signal, the gate signal, and the enable control number. The source driver (4) is connected to the timing controller 3^, and outputs the data 1 and the gray level signal according to the source signal output by the timing controller 31〇. The data signal is the normal data mentioned above, and the gray scale= can be a certain gray-scale data according to the design. In the present invention, the black data mentioned in the description is omitted. The gate driver 330 is electrically connected. At the time of the I system 310, and according to the received gate signal, a plurality of scan pulse signal states having the same visible pulse are simultaneously generated, and the plurality of gate lines 348 in the inverse 340 are respectively controlled. Interpolar drive root 0575 9ITW 18169twf.doc/e 05759ITW 18169twf.doc/e causes the scan pulse feed period and the gray scale write period enable control signal to generate a plurality of output enable signals 338, respectively, during the scan pulse. One of the periods. " Further step-by-step interpretation of the plurality of scan pulse signals 338, respectively, in a plurality of interrogation lines 348 in one side, that is, grouping the plurality of gate lines 348 of the liquid crystal display panel Each of the inter-pole line 348-shaped polar group 349' is respectively composed of the corresponding scan pulse signal group 339, and the three gate lines 348 are - the gate line group * ^ :, 6 children, so Each scan pulse signal group 339 includes a 3 = trace pulse signal 338, and each of the two scan pulses (four) 338 in the individual scan pulse signal group 339 has the same scan pulse period, that is, the scan pulse signal 339 in the same group has the same Scan pulse. In general, β, the number of suitable groups is 3 to 1 set of gate lines. In the example of the gate line 3 milk, during the data writing period, the sweeping group 2, the group 5 339 at the same time only turns on the corresponding gate line group - the strip gate line 348' avoids the same - The data signal is written into the plurality of gates of the gates. The ❿ source drive (four) 320 is in it - the gate line ^8. When turned on, the output data signal to the corresponding gate line 348 is in the gray & write period, the scan pulse signal group 339 simultaneously turns on the gate line, and 349 causes all the gate lines 348, and The source driver 320 outputs a gray scale signal such as black data to the corresponding pixel of the gate line group 3 during the on period t. ,, at the place. The gate driver 330 further includes a shift register 332, a plurality of output enable early elements 334, and a quasi-bit shifter 336. Each scan pulse signal 338 1377530 05759ITW 18169twf.doc/e will be shifted, waveform adjusted and voltage level adjusted via the above three units before output. To make the technical features of the present invention clearer to those skilled in the art, the following description will be described in conjunction with FIG. Referring to Fig. 3, a timing chart of a scanning signal waveform according to the present invention is shown. The gate line timings Gi~G3n represent timing diagrams on different gate lines 348, respectively. In the present embodiment, three gate lines 348 are first described as a pole group 339. Therefore, the gate line timings G1 to G3 are a group, and the three gate lines 348 of the library to the idle f line group 349 are respectively arranged, as shown in FIG. 3, the sequences G1 to G3 have the same scan pulse signal 4〇5~ 4〇7, the rush signals 405~407 have the same scan pulse period (four) not all the interpole lines 338 are turned on, and
=控制诚，在其致能時，其對應到的閉極線3 導通。 J 輸出致能單元334根據致能控制信號輸出—組 能信號〇E1M)E13，且這組輸出致能信號OE11〜〇El3 = :對應到閉極線時序G1〜G3 ’並形成掃描脈衝信； :4〇7導通個別閘極線348的脈衝時序。換句話說，: 有當輸出致能信號0E11〜〇E13為致能位 _ 信號奶，才可以導通所對應到的閘極線338== 所不，在資料寫入期間DP +，輸出致能單元334會輪出 一組具有相位差的輸出致能信號OE11〜OE13,分別 同的致能期間E1〜E3。在第1關P1中，當輸出致 ^ OE11為致驗準(本實施射為低位準)時則在此= 能位準期間’掃描脈衝信號4G5在閘極線時序⑺上形 (S) 11 05759ITW 18l69twf.doc/e =寫人脈衝D1 ’亦即導通閘極線時序G1所對 ==348，源極驅動器32〇並在此時將資料信 極線時序G1所對應到的閘極線348的晝素。依此；1 =線時序G2〜G3上的資料寫入脈衝D2〜m則分別 J所不。 依照掃描脈衝信號405〜407被輸出致能俨 OE11〜⑽3致能的結果，在資料寫入期間Dp分別產^ 料寫入脈衝D1〜D3。所以在第}期間ρι之 門 DP中，間極線時序⑴〜⑺在同一時間内僅有一=相= 的閘極線348被導通。雜暫存器332則依序將一 ^ 線時序G1〜G3向下-組對應到的閘極線組349傳遞並移 位，而在此實施例中也就是每次移位3條閘極線的時序。 掃描脈衝信號415〜417則分別具有資料寫人_ ^韻，閘歸時序G4〜G6也在個別的資料寫入 IM〜D6中分別導通所對應到的閘極線348。以此類推 貧料寫入期間DP甲，每-閘極線時序G(3n_2)〜Gn分別典 到對應的輸出致能草元334所產生的輸出致能^ OEml〜〇Em3所致能’並輸出相對應的資料寫入脈衝: =3n-2)〜D3n，n、m為正整數。紐以3個掃描脈衝信號 為-組，依序往下傳遞，所以移位暫存器说的工作時脈 比二般_鶴时移㈣存賴㈣低，㈣其移 存器332所需之電路元件也大幅簡化。 線組349需要一併導通並寫入灰階信號至所控 制的畫素時，在第n_ Pn中同樣在閘極線時序⑺〜⑺ 05759ITW 18169iwf.doc/e 具有3個相同脈衝信號的掃描脈衝信號425〜427， 號425〜427具有相同的掃描脈衝期間 ： 輸出的致刚㈣，嶋細入^ 本實施例中為低位準），在灰階寫人躺Gp外則 白為非致能㈣(本實施财為高鱗），所叫極 Γ同入期間GP中皆具有—灰階寫入脈衝G， 極序G1〜G3所對應到的閘極線州。源 祕動益320則在灰階寫入期間Gp =序⑴〜⑺所導通的問極線的畫素中。 低人眼的積分效果，通常設計為黑資料： 細心暫子益332㈤樣將掃描脈衝信號425〜427在經過 -個知描脈衝信號期間ρρ後，依序移位至下一崎^ 如圖3中之掃描脈衝信號435〜437所:、， 岐能信號在同—相對期間中形成灰階寫 ΡΡ中皆7資料寫入期間DP與灰階寫入期=== :_===信ϊί:掃描脈_ ==衝信號分別在“間== 同-期間中具有二;掃描脈衝信號在 〇Eml〜〇Em3i失 衝信號則因輸出致能信號 b準(本貫施例為高位準）而無法導通 05759ITW 18169twf.doc/e 相對應的閘極線348。 圖4為根據本發明一實施例之液晶顯示 程圖。為使本技術領域者能更清楚了解本發明之 ^ 段，以下配合圖2與圖3 —併說明。步驟由S5〇2開始。 首先’步驟S5〇4提供源極信號、閘極信號以及致能控制 信號。步驟S506提供資料信號與灰階信號，接著，步驟 S508根據閘極信號’產生具有多個相同掃描脈衝期間$多 個掃描脈衝信號405〜407。然後進入步驟S51〇根據致能控 制信號，產生與掃描脈衝信號4〇5〜407相對應的多個輸出 致能信號OE11〜OE13分別使掃描脈衝信號4〇5〜4〇7在該 掃描脈衝期間具有資料寫入期間Dp與灰階寫入期間 兩種期間其中一種以控制多條閘極線348❶ 接下來在步驟S512判斷輸出致能信號位於資料寫入 期間DP或是灰階寫入期間Gp?若輸出致能信號 OE11〜OE13位於資料寫入期間Dp，則進入步驟輸出 ，能信號OE11〜OE13分別在不同致能期間E1〜E3產生致 能？準(本實施例中為低位準），使掃描脈衝信號他〜術 在肓料寫入期間DP中，同一時間僅能導通一條閘極線 348，並輸出資料信號至被導通之閘極線348所對應的書 素。 〜旦 、若輸出致能信號〇E11〜〇E13位於灰階寫入期間Gp， 則進入步驟S516輸出致能信f虎OE1卜OE13，分別在相同 致能期間E4i生致驗準(本實施射為低位準），如第： 期間Pn中所不，掃描脈衝信號42S〜427在灰階寫入期間 1377530 05759ITW 18169twf.doc/e GP中同時產生灰階寫入脈衝G，並同時導通閘極線组汹 中所有的閘極線348，輸出灰階信號至閉極線組349 應的晝素。在資料寫入期間與灰階寫入期間外的期間中， 輸出致能信號OE11〜OE13則使掃描脈衝信號4〇5〜4〇7失 能。若輸出致能信號不位於資料寫入期間或是灰 間’則進入步驟S518輸出失能，即不輸出任何信號。最 後’步驟㈣流程顏束。前述之流賴步驟中盆餘细 L，本技術領域者’應可經由前述之裝置實施例說明 中輕易推知，在此不再贅述。 前述之液晶顯示器驅動方法，其中在步驟5G4之前更 包括接收影像信號。另外，在步驟508中更 遞掃描脈衝信號。並且以每3個掃描信號為一組作移位^ 送。 ㈣步說明輸出致能單元334在資料寫入 =「與灰L寫入期間GP時的判斷機制 符Γ併說明。圖5為根據本發… 出控制流程圖。由步驟議開始。首 先4S_，輪出致能單元334根據時序 判斷將要輸出的輸出致能信號㈣剛3 位於j寫入期間Dp或是灰階寫入期間Gp。 位一入期間GP，則進入步驟S650輸出3個相= Control is honest, when it is enabled, its corresponding closed-circuit line 3 is turned on. The J output enable unit 334 outputs a set-energy signal 〇E1M)E13 according to the enable control signal, and the set of output enable signals OE11~〇El3 = : corresponds to the closed-line timings G1 GG3' and form a scan pulse signal; : 4〇7 turns on the pulse timing of the individual gate line 348. In other words, when the output enable signal 0E11~〇E13 is the enable bit_signal milk, the corresponding gate line 338== is not turned on, and DP + output is enabled during data writing. The unit 334 will rotate a set of output enable signals OE11 to OE13 having phase differences, respectively, the same enable periods E1 to E3. In the first off P1, when the output OE11 is the accredited (this embodiment is shot to the low level), then during this = level period, the scan pulse signal 4G5 is shaped on the gate line timing (7) (S) 11 05759ITW 18l69twf.doc/e=Write human pulse D1', that is, the turn-on gate line timing G1 is ==348, the source driver 32〇 and the gate line 348 corresponding to the data source line timing G1 at this time Russell. According to this; 1 = line timing G2 ~ G3 data write pulse D2 ~ m respectively J does not. As a result of the enable of the output enable signals OE11 to (10)3 by the scan pulse signals 405 to 407, the write pulses D1 to D3 are respectively generated during the data write period Dp. Therefore, in the gate period DP of the period ρι, the inter-polar line timings (1) to (7) are turned on only one = phase = gate line 348 at the same time. The interleaver 332 sequentially transfers and shifts the gate line group 349 corresponding to the down-group of the line timings G1 to G3, and in this embodiment, shifts 3 gate lines each time. Timing. The scan pulse signals 415 to 417 respectively have data writers, and the gate timings G4 to G6 also turn on the corresponding gate lines 348 in the respective data writes IM to D6. In the case of such a push-pumping material, during the DP-A, the per-gate line timing G(3n_2)~Gn respectively dictates the output enable of the corresponding output-enable grass 334, OEml~〇Em3, and Output the corresponding data write pulse: =3n-2)~D3n, n, m are positive integers. New Zealand takes 3 scan pulse signals as a group, which is transmitted downwards in order, so the working clock of the shift register is lower than the second _ crane time shift (four), (4) low, (4) required for its shifter 332 Circuit components are also greatly simplified. When the line group 349 needs to be turned on and writes the gray scale signal to the controlled pixel, the scan pulse having the same pulse signal in the n_Pn is also in the gate line timing (7) to (7) 05759ITW 18169iwf.doc/e. Signals 425~427, No. 425~427 have the same scanning pulse period: the output is just (four), the fine is in the low level in this embodiment, and the white is non-enabled in the gray level. This implementation is a high scale), and the GP has a gray-scale write pulse G, and a gate line state corresponding to the polar sequence G1 to G3. The source is 320 in the pixel of the line of the line that is turned on during the gray-scale writing period Gp = sequence (1) to (7). The integration effect of the low human eye is usually designed as black data: The careful temporary neutron benefit 332 (five) sample scan pulse signals 425~427 are sequentially shifted to the next sag after passing through a known pp pulse signal. In the scan pulse signals 435 to 437:,, the 岐 energy signal forms a gray scale write 在 in the same-relative period. 7 Data write period DP and gray scale write period === :_===信ϊί : Scan pulse _ == rush signal has two in "between == same-period; scan pulse signal in 〇Eml~〇Em3i miss signal, because output enable signal b is accurate (this example is high level) However, the gate line 348 corresponding to 05759ITW 18169twf.doc/e cannot be turned on. Fig. 4 is a liquid crystal display diagram according to an embodiment of the present invention, in order to enable the person skilled in the art to more clearly understand the section of the present invention, the following cooperation 2 and FIG. 3 - and the description begins with S5 〇 2. First, 'Step S5 〇 4 provides a source signal, a gate signal, and an enable control signal. Step S506 provides a data signal and a gray scale signal, and then, step S508 According to the gate signal 'produces multiple scans with multiple scan pulses during the same period The pulse signals 405 to 407. Then, the process proceeds to step S51, and according to the enable control signal, a plurality of output enable signals OE11 to OE13 corresponding to the scan pulse signals 4〇5 to 407 are generated to respectively make the scan pulse signals 4〇5 to 4〇. 7 having one of two periods of data writing period Dp and gray scale writing period during the scan pulse to control the plurality of gate lines 348 ❶ Next, at step S512, it is judged that the output enable signal is located during the data writing period DP or gray If the output enable signals OE11 to OE13 are located in the data writing period Dp, the step output is output, and the enable signals OE11 to OE13 are respectively enabled in the different enable periods E1 to E3 (in this embodiment). For the low level, the scan pulse signal is made in the DP during the data writing process, and only one gate line 348 can be turned on at the same time, and the data signal is output to the pixel corresponding to the turned-on gate line 348. If the output enable signal 〇E11 〇E13 is located in the gray-scale writing period Gp, the process proceeds to step S516 to output the enable signal f OE1 OE13, respectively, and the detection is generated during the same enabling period E4i (this implementation) Low level For example, during the period Pn, the scan pulse signals 42S to 427 simultaneously generate the gray scale write pulse G in the gray scale write period 1377530 05759ITW 18169twf.doc/e GP, and simultaneously turn on all the gate group 汹The gate line 348 outputs a gray scale signal to the pixel of the closed line group 349. During the data writing period and the period outside the gray scale writing period, the output enable signals OE11 to OE13 cause the scan pulse signal 4 〇5~4〇7 is disabled. If the output enable signal is not located during data writing or ash, then the process proceeds to step S518 to output the disable, that is, no signal is output. Finally, the step (four) process is bundled. In the foregoing flow-through step, the fineness of the basin L can be easily inferred from the description of the device embodiment described above, and will not be further described herein. The liquid crystal display driving method described above, further comprising receiving the image signal before the step 5G4. Additionally, the scan pulse signal is incremented in step 508. And it is shifted by a group of every three scanning signals. (4) The description of the output enable unit 334 in the data write = "with the gray L write period GP symbol and explain. Figure 5 is a control flow chart according to the present invention. Start by the step. First 4S_, The round-out enabling unit 334 determines that the output enable signal (4) to be output is just located in the j writing period Dp or the gray-scale writing period Gp according to the timing. When the bit is in the period GP, the processing proceeds to step S650 to output three phases.
Pn所干一^ ^能信號〇E11〜0E13 ’如同圖3中第η期間 期間Ε4。^^出致能錢〇E11〜0El3具有相同的致能 ^ 力剧出致能信號是在資料寫入期間DP，則進入 ⑧ 15 1377530 05759ITW I8169twf.doc/e 2 S620送出輸出致能信號〇En，並進入步驟s ，出致能單it⑽】經由相移器(ρ_也㈣移動一相位 後’由步驟S63〇送出輸出致能信號㈣2，接著進 如5將輸出致能信號〇E12移動該相位後，由步驟咖 送出輸出致能信號OE13,其結果如圖3第丨細ρι所干， 輸出致能信號_〜咖分別具有不同的致能期間 E1〜E3 。Pn is a ^^ energy signal 〇E11~0E13' as in the η period period Ε4 in Fig. 3. ^^出能能〇E11~0El3 has the same enablement force force output enable signal is DP during data writing, then enter 8 15 1377530 05759ITW I8169twf.doc/e 2 S620 send output enable signal 〇En And proceeding to step s, the enablement unit it(10) is sent via the phase shifter (ρ_also (four) after moving a phase', and the output enable signal (4) 2 is sent by step S63, and then the output enable signal 〇E12 is moved by 5 After the phase, the output enable signal OE13 is sent by the step coffee, and the result is as shown in FIG. 3, and the output enable signal_0 has different enable periods E1 to E3, respectively.
根據上述實施例所述，本發明利用輸出致能信號 斷=制’同時驅動多條間極線，使畫面可以同時***譬如 黑資料的灰階訊號’不只改善動態畫面殘影的問題也降 低移位暫存器駐作頻率，同時麟畫素充電時間的長度。 雖然本發明已以較佳實施例揭露如上，然其並非用^ 限定本發明，任何熟習此技藝者，在不_本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】According to the above embodiment, the present invention utilizes the output enable signal to break the system to simultaneously drive a plurality of inter-pole lines, so that the picture can simultaneously insert gray-scale signals such as black data, which not only improves the residual image of the dynamic picture but also reduces the shift. The bit register is stationed as the frequency, and the length of the charging time of the pixel. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. [Simple description of the map]
圖1為一種先前-的畫面插黑方式之驅動波形圖。 圖2為根據本發明一實施例之液晶顯示器裝置的方 圖。 ^ 圖3為根據本發明一實施例之掃描信號波形時序圖。Fig. 1 is a driving waveform diagram of a previous-picture insertion mode. 2 is a view of a liquid crystal display device in accordance with an embodiment of the present invention. Figure 3 is a timing diagram of a scan signal waveform in accordance with an embodiment of the present invention.
圖4為根據本發明一實施例之液晶顯示器驅動方法漭 程圖。 /;,L 圖5為根據本發明一實施例之輸出致能單元輸出控 流程圖。 1377530 05759ITW 18169twf.doc/e 【主要元件符號說明】 110、120 :掃描脈衝信號 115、125、205 :第一期間 118、128、208 :第二期間 310 :時序控制圖 320 :源極驅動器 330 :閘極驅動器 332 :移位暫存器 334 :輸出致能單元 336 :準位移位器 338 :掃描脈衝信號 340 ·液晶顯不益面板 348 :閘極線 349 :閘極線組 405〜437 :掃描脈衝信號 B :黑資料 D:正常資料 — 0(311-2)~0311:第11個資料寫入脈衝(11為卜2、3、···) DP :資料寫入期間 E1〜E4 :致能期間 G:灰階寫入脈衝 G1〜G3n :閘極線時序 GL1-GL33 :閘極線 GOE1〜GOE3 :閘極致能信號 17 ⑧ 1377530 05759ITW 18169twf.doc/e GP :灰階寫入期間 OE11〜OEm3 :輸出致能信號 P1〜Pn :第η期間 ΡΡ :掃描脈衝期間 S502〜S520 :流程圖步驟 S601〜S690 :流程圖步驟 SP :掃描脈衝4 is a process diagram of a liquid crystal display driving method according to an embodiment of the invention. /; L Figure 5 is a flow chart of the output enable unit output control in accordance with an embodiment of the present invention. 1377530 05759ITW 18169twf.doc/e [Description of main component symbols] 110, 120: scan pulse signals 115, 125, 205: first period 118, 128, 208: second period 310: timing control diagram 320: source driver 330: Gate driver 332: shift register 334: output enable unit 336: quasi-bit shifter 338: scan pulse signal 340 · liquid crystal display panel 348: gate line 349: gate line group 405~437: Scan pulse signal B: black data D: normal data - 0 (311-2) ~ 0311: 11th data write pulse (11 is 2, 3, ...) DP: data writing period E1 ~ E4: During the enable period G: Gray scale write pulse G1~G3n: Gate line timing GL1-GL33: Gate line GOE1~GOE3: Gate enable signal 17 8 1377530 05759ITW 18169twf.doc/e GP: Gray scale write period OE11 ~OEm3: Output enable signals P1 to Pn: nth period ΡΡ: scan pulse period S502 to S520: flowchart steps S601 to S690: flowchart step SP: scan pulse