1375298 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置的製造技術，特別係有關 於一種矽穿礼製程與結構。 【先前技術】1375298 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a manufacturing technique for a semiconductor device, and more particularly to a process and structure for a ruthenium. [Prior Art]
為符合攜帶性電子產品日益講求輕薄短小且高性能 的趨勢，對於能高密度堆疊晶片之半導體裝置需求亦日 趨越高。業界已發展出另一種多晶片堆疊封裝的技術， 期能朝向高功率、高密度與微小化等高精密度製程潑 展，此即為砂穿孔（TSV，Through silic〇n Via)技術。如姜 國專利第7，151，GG9號，其石夕穿孔技術是在晶片内形a 貫穿通孔，並在貫穿通孔内填入導電材料，讓晶片上飞 電性連結。然而，為了讓晶片可以堆疊並對外電性接合 必須在晶片上另設置凸塊，以作為晶片對外電性接合口之 電極。故’必須在矽穿孔製程之外另進行凸塊製程1其 相關的重配置線路製程，使得製程繁鎖與成本提高。 另—種習知的晶片堆疊技術，如美國專利筹 ^=425號，則是捨棄了凸塊，並使石夕穿孔為中空韵 〇t曰曰片之對應矽穿孔必須對準，矽穿孔内更可填入得 接材料或者另以插針或導線穿接，以使堆疊 到電性互連。銶而 @ 然而，一旦孔對孔對不準會有在焊接時这 :焊接材料流動溢出，又無凸塊之晶片堆疊間隙變小， 本應電性分離之矽穿孔因焊接材料之溢流而極 谷 電性短路。|使用插針或導線穿接未對準之 3 1375298In order to meet the trend of increasingly thin, high-performance portable electronic products, the demand for semiconductor devices capable of stacking chips at high density is increasing. Another multi-wafer stacking technology has been developed in the industry to enable high-precision processes such as high power, high density, and miniaturization. This is the TSV (Through Silic〇n Via) technology. For example, in Jiang Guo Patent No. 7,151, GG9, the Shi Xi piercing technique is to form a through hole in the inside of the wafer, and fill the through hole with a conductive material to electrically connect the wafer. However, in order to allow the wafer to be stacked and electrically externally bonded, bumps must be additionally provided on the wafer to serve as electrodes for the external electrical interface of the wafer. Therefore, it is necessary to perform the bump rework process 1 in addition to the boring process, which makes the process complicated and costly. Another conventional wafer stacking technique, such as U.S. Patent No. 425, is to discard the bumps and make the corresponding 矽 perforations of the 夕 穿孔 为 中空 矽 矽 矽 矽 矽 矽 矽 矽The material can be filled in or otherwise connected by pins or wires to make the stack electrically connected. However, once the hole is not aligned with the hole, there will be soldering. The flow of the solder material overflows and the stacking gap of the wafer without the bump becomes smaller. The hole for the electrical separation is due to the overflow of the solder material. The pole is electrically shorted. |Using pins or wires to thread misaligned 3 1375298
貝丨會有無法貫穿引起的電性斷路 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 秒穿孔製程與結構，能在包含晶背研磨步驟之石夕穿 =程中製作具有卡榫_之凸塊，以省略傳統的凸塊 製程，進而達到製程整合與成本降低之功效。 播本發月之- 人一目的係在於提供一種矽穿孔製程與結In order to solve the above problems, the main object of the present invention is to provide a second perforation process and structure, which can be fabricated in the process of including the crystal back grinding step. The bumps of the cassette _ are omitted to omit the conventional bump process, thereby achieving the effects of process integration and cost reduction. The broadcast of the moon - the purpose of the person is to provide a process and knot
sa #堆疊時達到卡合定位並在後續烊接過程 止痒接材料（如銲塊）溢出到石夕穿孔結構之間之功效。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明j居 级 咖 人日 不赞明揭不一種矽穿孔製程，主要步驟包 提供晶片’該晶片係具有一主動面與一背面。接 2 ’形成複數個非貫通孔在該晶片之該主動面。接著， ^置複數個導體柱於該些非貫通孔内，每—導體柱具有 卡榫’係突出於該主動面。之後，研磨該晶片之該背 面’以薄化該晶片直到該些非貫通孔形成為複數個通 孔，並同時使得每—導體柱具有—顯露之底面，係與該 已研磨後之背面為共平面。本發明另揭示―種依照上述 製程所製成之矽穿孔結構。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的石夕穿孔製程中，在上述研磨該晶片之該背面 之步驟之後，可另包含：形成複數個中央***之銲塊於 該些導體柱之該些底面。 在前述的矽穿孔製程中，該卡榫突 位係可為-周邊凸環。 出於該主動面之部 在前述的矽穿孔製轾中，該卡榫 竹总卞犬®於該主動面之部 位係可為兩平行之側邊凸條。 在前述的矽穿孔製程中，該些 栌虹u 丨*硬凸條係可與該肽導 體柱之排列方向為垂直。 —等 在前述的矽穿孔製程中，該卡榫之 於該主動面。 ㈣了相對凹入 在前述㈣穿孔製程中，該些導體柱係可 截面。 〜 由以上技術方案可以看出 構’具有以下優點與功效： 本發明之矽穿孔製程與結 可藉由形成非貫穿通孔、設置導體柱與研磨晶片背 面等步驟順序作為其中一技術手段，在晶背研磨步 驟之刖設置導體柱，其卡榫突出於晶片之主動面， 作為特定功能之凸塊，故能在矽穿孔製程中製作具 有卡榫作用之凸塊，並省略傳統的凸塊製程，進 達到製程整合與成本降低之功效。 可藉由多個矽穿孔結構内導體柱的特定結合關係作 為其中一技術手段，使導體柱具有突出於晶片主動 面之卡榫以及與晶片背面為共平面之底面，故具有 在晶片堆疊時達到卡合定位並在後續焊接過程防止 焊接材料（如銲塊）溢出到矽穿孔結構之間之功效。 【實施方式】 1375298 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的《，該些圖示均為簡化之示意圖僅以示意方法 來說明本發明之基本架構或實施方法故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 Φ 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種矽穿孔製程例舉說 明於第1A至1F圖之製程中元件截面示意圖。 首先，请參閱第ία圖所示，提供一晶片11〇，該晶 片11〇係具有一主動面U1與一背面112。該晶片ιι〇 係可為一半導體晶圓中其中一個晶片，也就是說，複數 個晶片110係可一體形成於半導體晶圓，並且為未分 離。該晶片110係可為積體電路晶片、發光二極體晶片 • 或太陽能電池晶片，其基礎層結構係為矽、砷化鎵等半 導體材料並佈設有適當之線路。該主動面lu係指晶片 用以形成線珞、積體電路或作動元件的表面，在製成線 路或兀件之後，通常會覆蓋一保護層（Passivation Layer) 於該主動面11 1 ,以作表面絕緣之保護。 接著，請參閱第1Β圖所示，形成複數個非貫通孔12〇 在該晶片1ί〇之該主動面lu。也就是說，該些非貫通 孔120係不穿透整個晶片11〇，而形成為盲孔。該些非 貫通孔120係可以㈣、機械鑽孔或是反應性離子餘刻 6 ^375298 等等方法形成。在本實施例中，該些非貫穿通孔丨2〇之 深度係超過該晶片在後續晶.背研磨步驟後之厚度。具體 而言’該些非貫穿通孔12〇之深度係可介於該晶片n0 之厚度的30%至80%。該些非貫穿通孔120係可等距排 列在該晶片110之侧邊。Sa #Fixed positioning is achieved during stacking and the effect of the itching material (such as solder bumps) overflowing to the stone-night perforated structure during the subsequent splicing process. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention does not admit that a boring process is not disclosed. The main step is to provide a wafer. The wafer has an active surface and a back surface. A plurality of non-through holes are formed in the active surface of the wafer. Next, a plurality of conductor posts are disposed in the non-through holes, and each of the conductor posts has a clicker protruding from the active surface. Thereafter, the back surface of the wafer is polished to thin the wafer until the non-through holes are formed into a plurality of through holes, and at the same time, each of the conductor posts has a revealed bottom surface which is common to the ground back surface flat. The present invention further discloses a crucible perforation structure made in accordance with the above process. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing lithography process, after the step of grinding the back surface of the wafer, the method further comprises: forming a plurality of central ridges of the solder bumps on the bottom surfaces of the conductor pillars. In the aforementioned boring and perforating process, the knuckle protrusion system may be a peripheral convex ring. For the part of the active surface, in the aforementioned boring and perforating system, the 卞 卞 卞 于 于 can be two parallel side ribs in the part of the active surface. In the foregoing ruthenium perforation process, the 栌Hong u丨* hard ribs may be perpendicular to the alignment direction of the peptide conductor columns. - Etc. In the aforementioned boring process, the click is on the active surface. (4) Relative recession In the above (4) perforation process, the conductor pillars may have a cross section. ~ It can be seen from the above technical solutions that the structure has the following advantages and effects: The boring process and the junction of the present invention can be used as one of the technical means by forming a step of forming a non-through hole, a conductor post and a back surface of the wafer. After the crystal back grinding step, the conductor post is arranged, and the latch protrudes from the active surface of the wafer as a bump of a specific function, so that the bump having the click effect can be formed in the crucible punching process, and the conventional bump process is omitted. Into the process integration and cost reduction. The specific bonding relationship of the inner conductor pillars of the plurality of 矽-perforated structures can be used as one of the technical means, so that the conductor pillars have the latches protruding from the active surface of the wafer and the bottom surface coplanar with the back surface of the wafer, so that the wafer stacking is achieved The snap fit locates and prevents subsequent effects of solder material (such as solder bumps) from spilling over the perforated structure during subsequent soldering processes. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which: FIG. Only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related dimensions or have been exaggerated or simplified. Provide a clearer description. The actual number, shape and size ratio of the implementation is a Φ option design, and the detailed component layout may be more complicated. In accordance with an embodiment of the present invention, a crucible perforation process is illustrated in a cross-sectional view of an element in the process of Figures 1A through 1F. First, as shown in Fig. 3, a wafer 11 is provided, which has an active surface U1 and a back surface 112. The wafer may be one of the wafers in a semiconductor wafer, that is, the plurality of wafers 110 may be integrally formed on the semiconductor wafer and are not separated. The wafer 110 may be an integrated circuit wafer, a light emitting diode wafer, or a solar cell wafer, and the base layer structure thereof is a semiconductor material such as germanium or gallium arsenide, and an appropriate wiring is disposed. The active surface is used to form a surface of a wire, an integrated circuit or an actuating element. After the circuit or the device is formed, a protective layer is usually covered on the active surface 11 1 . Protection of surface insulation. Next, referring to FIG. 1 , a plurality of non-through holes 12 形成 are formed on the active surface lu of the wafer 1 . That is, the non-through holes 120 do not penetrate the entire wafer 11 but are formed as blind holes. The non-through holes 120 may be formed by (4), mechanical drilling or reactive ion remneration 6 ^ 375 298 or the like. In this embodiment, the depth of the non-through vias exceeds the thickness of the wafer after the subsequent crystal back grinding step. Specifically, the depth of the non-through holes 12A may be between 30% and 80% of the thickness of the wafer n0. The non-through vias 120 are equidistantly arranged on the side of the wafer 110.
接著，請參閱第1C圖所示，設置複數個導體柱130 於該些非貫通孔120内，每一導體柱130具有一卡榫 131，其係突出於該主動面111。該些導體柱n〇係可用 以電性連接該晶片110内部的線路，而該些卡榫m係 作為具有特定卡接功能之凸塊，以使該晶片丨丨〇可對外 電性連接。在本實施例中’該些導體柱13〇係可具有U 形截面，以使該些導體柱130之中央係為凹陷狀。該些 導體柱130之形成方式係可選自於鑲嵌、電鍍 (Electroplate)以及蒸鐘（Evaporation)之其中之一種方 式。在本實施例中，除了焊料之外，該些導體柱13〇係 可以包含任何適當導電材料，例如銅（Cu)、金（Au)、或 其合金。 請再參閱第ic圖所示，在本實施例中，該卡榫ι: 突出於該主動面111之部位係可為一周邊凸環（如第] 圖所示）。該些導體柱130係可為圓柱體，而對應之卡 131係環狀形成在其邊緣。較佳地，該卡榫131之中 係可相對凹入於該主動面1U，以形成一中央凹陷US 並與該主動面111形成一高度差。該些卡榫131 一體 形於該些導體柱i30,並且該些卡榫131之材質係可 1375298 該些導體& 130之材質相!η。因此，在形成該些導體枉 130之步驟中，該些卡榫131係可同時被形成。較佳地， 該些卡榫Hi係可採用電錢方式形成，以精確控制該些 卡榫131突出於該主動面U1夕古痒.„ ^ 叫111之问度。在另一實施例中， 如第3B圖所示，複數個導體桎13〇，之卡榫i3i，突出於 該主動面⑴之部位係可為兩平行之側邊凸條並使該 些卡榫！31’形成有中央凹陷132，，其兩開口側可供排氣 與。具體而言’該些導體柱130,你ότ a 士 at* 往係可具有矩形表面。更 具體而言’該些側邊凸條係可與該些導體柱13〇,之排列 方向為垂直。也就是說’該些侧邊凸條係位於同排之該 些導體柱130,之間相鄰近的側邊 < j叫瓊，以有效阻止焊接材料 的不當溢流。 之後，請參閱第1D圖所示，利用一研磨工具ι〇以 旋動方式研磨該晶片‘ 110之該背面112,以薄化該晶片 no直到該些非貫通孔120形成為複數個通孔i2i(如第 ιέ圖所示）。具體而言’通常會使用含有财磨顆粒之研 磨液’以利於研磨之進行。請參閱第ie圖所示，在此晶 背研磨步驟之後’同時使得每一導體柱13〇具有一顯露 之底面U3,係與該已研磨後之背面ιΐ3為共平面以 使該晶片110可為具有雙面電性導通結構之晶片。 在上述研磨該晶片110之該背面112之步驟之後請 參閱第1F圖所示，在太奢力相丨击 , 在本實施例中，該發穿孔製程可另包 3形成辉塊之步驟，形出滿盤他|也 心成複數個中央***之銲塊140於 該些導體纟13Ό之該些底® 133,以作為對外電性接合 8 Γ375298 之媒介。該些銲塊14G可先利用韻或印刷方式形成於 130之該些底自133’再以回焊方式使其具 有中央***之形狀。 因此，可藉由上述之步驟順序，能在研磨該晶片11〇 之該者面112之步驟之前完成該些導體柱13〇的設置， 並使該些卡榫m突出於該晶μ 11〇之該主動面⑴， 以作為具有特定功能之凸塊，故能在該矽穿孔製程中製 作具有卡榫㈣之凸塊，並可省略傳統的凸塊製程，進 而達到製程整合與成本降低之功效。並且，在設置該些 導體柱130之步驟中，係同時形成該些卡榫i3i，故不 會另增加其他的步驟，而造成製程繁瑣的問題。 本發明還揭示一種依照前述矽穿孔製程所製成之矽 穿孔結構，可例舉說明於第2圖之截面示意圖。請參閱 第2圖所示，該矽穿孔結構主要包含該晶片ιι〇以及該 些導體柱130〇該晶片ι10係具有貫穿該主動面1U與 該背面113之該些通孔121。該些導體柱13〇係設置於 該通孔121内，並具有突出於該主動面lu之卡榫131 以及與該背面11 3為共平面之底面丨3 3。在本實施例中， 該矽穿孔結構係可包含有該些銲塊14〇。該些銲塊14〇 係形成於該些導體柱130之該些底面133，以使多個矽 穿孔結構可互相電性連接或接合至一基板2〇(如第5圖 所不）。請參閲第3 A圖所示，在本實施例中，該卡榫1 3 j 突出於該主動面111之部位係為一周邊凸環，並且在該 卡榫131之中央形成中央凹陷132。該些中央凹陷132 9 1.375298 係可用以收容該些銲塊刚，以避免在後續焊接過程中 產生焊接材料（如銲塊14G)溢出的問題。在—實施例變化 例中’清參閱第3B圖所示，複數個導體柱咖，之卡摔 131’突出於該主動φ lu之部位係為兩平行之側邊凸 條’並在該些侧邊凸條之間形成中央凹陷132，。由此可 知’在後續烊接過程中’該些銲塊14〇 t受到該些卡榫 13 1’之阻擋而往旁邊流動，故不會流向同排之該些導體 柱1 3 0 ，則可避免連接短路之問題。 請參閱第4圖所示’在晶片堆疊過程中，多個矽穿孔 結構係可堆疊設置在—基板。該基板2〇係具有複 數個接墊21以及複數個銲球3〇，其中該些接墊21係用 以接合該矽穿孔結構，該些銲球3 〇係用以對外電性連 接。凊再參閲第4圖所示，位於上方之石夕穿孔結構之該 些銲塊140係卡接於位於其下方之矽穿孔結構之該些卡 榫1 3 1，故可利用該些卡榫J 3丨具有突出於該晶片i 之該主動面111之設計，使在堆疊時，矽穿孔結構能具 有卡合定位以及可限制該些銲塊u〇位置之功效’並可 提高該些銲塊140在接合使用上之可靠度。 請參閱第5圖所示，在回焊過程中，可藉由該些導體 柱130之該些卡榫131具有該些中央凹陷132之設計， 能使位於上方之矽穿孔結構之該些銲塊14〇在回焊時填 入位於下方之石夕穿孔結構之該些中央凹陷Η:。更可藉 由該些卡榫131阻擋該些銲塊14〇由該些導體柱13〇的 頂端溢流，故可防止該些銲塊14〇溢出到矽穿孔結構之 10 1375298 間而導致相鄰之銲塊140連接短路之問題，以提升產〇 的良率…焊之後，該些石夕穿孔結構係可藉由該些： 塊140電性接合至相鄰之石夕穿孔結構或該基板2〇。因 此，在本實施例中，位於最下方之矽穿孔結構係以該些 導體柱130之該些底面133朝向該基板2〇之方式表面接 合於該基板20上’利用該些銲塊14〇連接該些導體柱 130與該些接墊21。並且該些矽穿孔結構係可為同向堆 疊，藉由該些銲塊140焊接至對應之卡榫131以達到矽 穿孔結構之間的電性互連。 因此，综上所述，可藉由多個矽穿孔結構内之該些導 體柱130之間的結合方式以及該些導體柱13〇之形狀設 計’使該些導體柱130具有突出於該晶片11〇之該主動 面111之該些卡榫131以及與該晶片11〇之該背面113 為共平面之該底面133。故具有在晶片堆疊時達到卡合 定位並在後續焊接過程防止該些銲塊丨4 〇溢出到矽穿孔 結構之間造成橋接短路之功效。 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内〇 【圖式簡單說明】 第1A至1F圖：為依據本發明之一具體實施例的矽穿孔 Γ375298Next, as shown in FIG. 1C, a plurality of conductor posts 130 are disposed in the non-through holes 120. Each of the conductor posts 130 has a latch 131 protruding from the active surface 111. The conductive pillars can be electrically connected to the wires inside the wafer 110, and the latches are used as bumps having a specific latching function, so that the wafer cassette can be electrically connected externally. In the present embodiment, the conductor posts 13 may have a U-shaped cross section such that the center of the conductor posts 130 is concave. The conductor posts 130 are formed in a manner selected from the group consisting of inlaying, electroplating, and evaporation. In the present embodiment, in addition to the solder, the conductor posts 13 may comprise any suitable conductive material such as copper (Cu), gold (Au), or alloys thereof. Referring to the ic diagram, in the embodiment, the card 榫: the portion protruding from the active surface 111 can be a peripheral convex ring (as shown in the figure). The conductor posts 130 may be cylindrical, and the corresponding card 131 is formed annularly at its edge. Preferably, the cassette 131 is relatively recessed in the active surface 1U to form a central recess US and form a height difference with the active surface 111. The latches 131 are integrally formed on the conductor posts i30, and the materials of the latches 131 are 1375298. The conductors & Therefore, in the step of forming the conductor turns 130, the plurality of cassettes 131 can be simultaneously formed. Preferably, the cassettes are formed by means of electric money, so as to precisely control the clicks of the cassettes 131 to protrude from the active surface U1. In another embodiment, As shown in FIG. 3B, a plurality of conductors 〇13〇, the card 榫i3i, protruding from the active surface (1) may be two parallel side ridges and the central ridges 31' are formed with a central depression. 132, the two open sides of the exhaust can be used. Specifically, the conductor posts 130, you can have a rectangular surface. More specifically, the side ribs can be The conductor posts 13〇 are arranged in a vertical direction. That is to say, the side ribs are located in the same row of the conductor posts 130, and the adjacent sides are adjacent to each other. Improper overflow of the solder material. Thereafter, as shown in FIG. 1D, the back surface 112 of the wafer '110 is polished by a grinding tool ι to thin the wafer no until the non-through holes 120 Formed into a plurality of through holes i2i (as shown in Figure ι). Specifically, 'usually using the grinding particles Liquid 'to facilitate the grinding process. Please refer to the figure below, after the crystal back grinding step 'at the same time, each conductor post 13〇 has a exposed bottom surface U3, which is in common with the polished back surface ΐ3 The plane is such that the wafer 110 can be a wafer having a double-sided electrically conductive structure. After the step of polishing the back surface 112 of the wafer 110, please refer to FIG. 1F, in the case of too extravagant phase slamming, in this embodiment In the example, the puncturing process may further comprise the step of forming a glow block, forming a full disk, and forming a plurality of centrally raised solder bumps 140 on the bottoms of the conductors 133 to serve as external Electrically bonding the medium of 8 Γ 375298. The solder bumps 14G may be formed by the rhyme or printing method at the bottoms of the 130 from the 133' and then reflowed to have the shape of a central ridge. Therefore, by the above In the sequence of steps, the arrangement of the conductor posts 13A can be completed before the step of grinding the face 112 of the wafer 11 and the chucks m protrude from the active surface (1) of the crystal 11 a bump with a specific function, so it can be worn at the piercing The bumps having the cassettes (4) are fabricated in the process, and the conventional bump process can be omitted, thereby achieving the effects of process integration and cost reduction. Moreover, in the step of setting the conductor posts 130, the cards are simultaneously formed. I3i, so there is no additional step, which causes a cumbersome process. The present invention also discloses a crucible perforation structure made in accordance with the above-described crucible perforation process, which can be exemplified in a cross-sectional view in Fig. 2. As shown in FIG. 2, the cymbal perforated structure mainly comprises the iv 〇 〇 〇 〇 〇 〇 〇 〇 导体 导体 ι ι ι ι ι ι ι ι ι 121 。 。 121 。 。 。 。 121 121 121 121 121 121 121 121 121 121 121 121 121 121 The hole is disposed in the through hole 121, and has a latch 131 protruding from the active surface lu and a bottom surface 丨3 3 coplanar with the back surface 11 3 . In this embodiment, the crucible perforation structure may include the solder bumps 14A. The solder bumps 14 are formed on the bottom surfaces 133 of the conductor posts 130 such that the plurality of via structures are electrically connected or bonded to a substrate 2 (as shown in FIG. 5). Referring to FIG. 3A, in the embodiment, the portion of the latch 1 3 j protruding from the active surface 111 is a peripheral convex ring, and a central recess 132 is formed at the center of the latch 131. The central recesses 132 9 1.375298 can be used to accommodate the solder bumps to avoid the problem of overflow of the solder material (e.g., solder bumps 14G) during subsequent soldering. In the embodiment variant, as shown in FIG. 3B, a plurality of conductor pillars, the card-fall 131' protruding from the active φ lu is a pair of parallel side ridges 'on the sides A central recess 132 is formed between the side ridges. Therefore, it can be seen that in the subsequent splicing process, the solder bumps 14 〇t are blocked by the latches 13 1 ′ and flow to the side, so that they do not flow to the conductor pillars 1 3 0 in the same row. Avoid the problem of shorting the connection. Referring to Fig. 4, during the wafer stacking process, a plurality of ruthenium perforated structures are stackable on the substrate. The substrate 2 has a plurality of pads 21 and a plurality of solder balls 3, wherein the pads 21 are used to bond the via structures, and the solder balls 3 are used for external electrical connection. Referring to FIG. 4 again, the solder bumps 140 of the above-mentioned stone-shaped perforated structure are snapped to the latches 13 of the perforated structure underneath, so that the cassettes can be utilized. J 3丨 has a design protruding from the active surface 111 of the wafer i, so that the stacking structure can have a snap-fit structure and can limit the function of the solder bumps when stacked, and can improve the solder bumps 140 reliability in joint use. Referring to FIG. 5, during the reflow process, the plurality of latches 131 of the conductive posts 130 have the central recesses 132, so that the solder bumps of the upper perforated structures can be located. 14〇 Fill in the central depressions of the Shishi perforation structure located below when reflowing: The plurality of solder bumps 14 can be prevented from overflowing from the top ends of the conductive pillars 13 by the latches 131, so that the solder bumps 14 can be prevented from overflowing to the top of the through-hole structure 10 1375298 to cause adjacent The solder bumps 140 are connected to the short circuit to improve the yield of the calving. After the soldering, the magneto-optical perforated structures can be electrically connected to the adjacent coring structure or the substrate 2 by the block 140. Hey. Therefore, in the embodiment, the bottommost perforated structure is surface-bonded to the substrate 20 by the bottom surfaces 133 of the conductor posts 130 toward the substrate 2'. The conductor posts 130 and the pads 21 are provided. And the 矽-perforated structures can be stacked in the same direction, and the solder bumps 140 are soldered to the corresponding latches 131 to achieve electrical interconnection between the punctured structures. Therefore, in summary, the conductive pillars 130 can protrude from the wafer 11 by the manner of bonding between the conductor pillars 130 in the plurality of turns and the shape of the conductor pillars 13 The cassettes 131 of the active surface 111 and the bottom surface 133 which are coplanar with the back surface 113 of the wafer 11 are formed. Therefore, it has the effect of achieving a snap-fit positioning during wafer stacking and preventing a bridge short circuit between the solder bumps 〇4 〇 and the 矽-perforated structure during subsequent soldering processes. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes, and modifications made by the present invention within the technical scope of the present invention are still within the technical scope of the present invention. [Simplified Drawings] Figures 1A to 1F: Based on this矽 矽 Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ
製程中元件截面的示意圖。 第2圖：為依據本發明之一具體實施例的矽穿孔製程所 製成之一種矽穿孔結構的截面示意圖。 第3A與3B圖.為依據本發明之一具體實施例的發穿孔 製程所製成之該矽穿孔結構以及另一種變化之 矽穿孔結構的俯視圖。Schematic diagram of the cross section of the component in the process. Fig. 2 is a schematic cross-sectional view showing a crucible perforation structure made by a crucible perforation process in accordance with an embodiment of the present invention. 3A and 3B are plan views of the crucible perforation structure and another variation of the perforated structure formed by the perforation process in accordance with an embodiment of the present invention.
第4圖：為依據本發明之一具體實施例的矽穿孔製程所 製成之該矽穿孔結構應用於半導體裝置且在回 焊前之截面圖。 第5圖：為依據本發明之一具體實施例的矽穿孔製程所 製成之該矽穿孔結構應用於半導體裝置且在回 焊後之截面圖。 【主要元件符號說明】 10 研磨工具 20 基板 21 接塾 30 銲球 110 晶片 111 主動面 112 背 面 113 背面 120 非貫通孔 121 通孔 130 導體柱 131 卡榫 132 中 央凹陷 133 底面 130’ 導體柱 131， 卡榫 132, 中 央凹陷 140 銲塊 12Figure 4 is a cross-sectional view of the tantalum perforated structure produced in accordance with an embodiment of the present invention applied to a semiconductor device and before reflow. Figure 5 is a cross-sectional view of the tantalum perforated structure produced in accordance with an embodiment of the present invention applied to a semiconductor device and after reflow. [Main component symbol description] 10 Grinding tool 20 Substrate 21 Connector 30 Solder ball 110 Wafer 111 Active surface 112 Back surface 113 Back surface 120 Non-through hole 121 Through hole 130 Conductor column 131 Card 132 Central recess 133 Bottom surface 130' Conductor column 131, Cartridge 132, central recess 140 solder bumps 12