1375211 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示裝置，尤其係關於一種可透過減 少資料線數目而降低生產成本與功率消耗之液晶顯示裝置。 * 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which can reduce production cost and power consumption by reducing the number of data lines. * [Prior technology]
V 液晶顯示（liquid crystal display; LCD)裝置使用電場控制液 ^ 晶分子之透光比以顯示影像。通常，液晶顯示裝置提供液晶面板， 液晶面板包含兩塊玻璃基板之間的液晶，液晶分子矩陣，以及用 於各自改變液晶分子中訊號之交互裝置；驅動電路，用於驅動液 晶面板，以及背光單元，導引光線至液晶面板上。 最近，減少液晶面板之訊號線數目或者電路元件之數目，以 開發出輕薄且低成本之液晶顯示裝置。例如，韓國專利公報N〇. .10-2003-0039972揭露了一種玻璃上單晶片之液晶顯示裝置，用於 ^ 驅動液晶顯示面板之積體驅動晶片被裝設於顯示區域之周邊上， 以減少面板尺寸及裝置之生產成本。 習知技術之玻璃上單晶狀液晶裝置具有町缺點。單 元晝素巾的彩色晝素晶格包含垂直帶狀結構，這樣彩色晝素晶格 沿液晶顯示面板之水平方向（閘極線方向）排列。每個彩色書素 晶格需要單獨的資料線。因為隨著資料線數目的増加，積體驅動 晶片的尺寸也增加’健小財驗晶顯林置，例如解析 360 X 16〇 ’可使用破璃上單晶片型液晶顯示裝置。為了得到^高 解析度的数’玻璃上單W魏晶鮮裝置需麵外的電路， .例如選擇電路喊少㈣線醜目。當使用選擇電路時，在閉極 ·.·線社動職__，依照時賴分來劃分類比晝素資料，然 2供應至碰條倾線’從而減少晝素資料的充電時間。因此， :=用f擇電鱗’液晶顯示面板的解析度受晝素麟的充電時 、限4。此外，積體驅動晶片之各通道輸出的類比畫素資料交 # 3地破反向以用於各水平線，從而消耗大量功率。 • 【發明内容】 因此，本發明實施例提供一種液晶顯示裝置 知技術之限制及缺點所產生的一或多個問題。、、避以 ^明實施例之目的在於提供—種液晶顯示裝置，可透過減 y貝料線的數目而減少生產成本及功率消耗。 改善ΖΓΓ另一目的在於提供—種液晶顯示裝置，具有 叶· 的特徵和優點將在如下的說日谢部分地加以闡 =可以w本領域的普通技術人員來 明的實踐二出。:日下的說明得以部分地理解或者可以從本發 偏r i發明的目的和其它優點可以透過本發明所記 得以實現=相爾特別指明的結構並結合图式部份， 為了獲得本發明實施例的這些和其他優點，現對本發明作具 处化和概括性的描述，本發明的一種液晶顯示裝置包含：複數條 資，線’包含第-資料線及第二資料線，實質上彼此平行排列； ^數條閘極線’包含第-閘極線、第二閘極線及第三閘極線，實 貝上彼此平行排列，閘極線交叉於資料線；複數個子晝素，由交 又的閘極線與資料線定義’至少三個子晝素，直接地沿鄰接的資 料線其中之—制且對應砰_色以形成晝素；以及驅動積體 電路，依序驅動第一、第二及第三閘極線於水平週期内，其中水 平週期期間’供應至晝素之第—子晝素之第—喊與供應至晝素 之第二子畫素之第二的訊號極性相反，與供應至晝素之第三子晝 素之苐三訊號的極性相同。 另方面種驅動液晶顯示裝置之方法，該液晶顯示裝置 L st數條㈣線、複數條閘極線以及φ資料線及閘極線定義之 複數個晝素，各晝素包含三個子晝素，沿鄰接的資料線其中之一 直接地排列，此液晶顯示驅動裝置之驅動方法包含：於第一框之 每個水平職期間依序地驅動三條閘極線，於第—_間供應第 一極性之視頻訊號至奇數號資料線，以及於第一框中供應第二極 性之視頻訊鼓爐號資料線，其巾水平週期及每個晝素中，供 應至第-子晝素之第—訊號與供應至第二子晝素之第二訊號極性 相反，與供應至第三子晝素之第.三訊號極性相同。 另一方面，本發明之液晶顯示裝置包含m條閘極線，m為大 於-的整數’ η條貧料線，n為大於二的整數；以及複數個第一彩 1375211 色子畫素’排列於第ith條閘極線與第(i+1)th條閘極線之間，複數 個第二彩色子晝素，排列於第(W)th條閘極線與第(i+2)th條閘極 線之間’以及複數個第三彩色子晝素，排列於第㈣&條閑極線 與第(1+3)th條閘極線之間，其中第-彩色子晝素以及第三彩色予 ，.畫素連接於第一至第(n-l)th條資料線其中之―，第二彩色子畫素 連接於第二至nth資料線。 φ 另一方面，本發明之液晶顯示裝置包含m條閘極線，m為大 於六的塾數；n條資料線，η為大於二的整數；以及複數個第一子 旦素依序排列於第則条閘極線與第(i+1)th條閘極線之間，複數 個第一子晝素依序排列於第时沖條閘極線與第㈣地條閉極 線之間’複數個第三彩色子晝素，依序排列於第(i+2)th條閘極線 ”第(i+3)th條閘極線之間，複數個第四子晝素，依序排列於第 (】+3)ώ條閘極線與第(i+4)th條閘極線之間，複數個第五子晝素， ❿依f排列於第㈣th條線與第㈣th條閘極線之間，複數個 第'、子晝素’依序排列於第（i+5)th條間極線與第㈣沖條閑極線 之間’其中第—子晝素、第二子晝素、第五子畫素以及第六子晝 .素連接於第-至第(n-l)th條資料線其中之一，第三子晝素及第四 ^晝素連接於第二至第她條資料線其中之-，其中第-子晝素及 第四Γ晝素包含第—彩色子晝素，第二子晝素及第五子晝:包含 第各色子晝素以及第二子晝素及第六子晝素包含第三彩色子晝 方面’本發HS日顯示裝置包含：.液晶面板，包含複 個2晶格’形成於m+i條資料線與n條閘極線找之區域 ，沿資料線方向重複地排列三種顏色，沿線方向排列相同 的顏色；_内建電路’供應閘極開啟電駐液晶面板中形成的 閘極線；驅動碰電路，形成於液晶面板中，驅動_内建電路 且供應資料線單元及框單元中反向的視頻訊號至資料線，以及撓 性印刷電路，連接液晶面板至外部驅動系統。 可以理解的是’如上所義本發明之概括說明和隨後所述的 本發明之詳細綱均是具有代紐和轉性魄明，並且是為了 進一步揭示本發明之申請專利範圍。 【實施方式】 結合附圖所示之例子詳細說明本發明之較佳實施例。 「第1圖」係為本發明第一實施例之液晶顯示I置之示意圖。 「第1圖」中’液晶顯示裝置包含液晶面板1〇〇，其中包含由複數 條資料線DL以及複數條閘極線（^之交叉部所定義之複數個晝素 晶格110。晝素晶格110 &含沿資料線方向或者垂直方向交替排列 的三種顏色以及沿閘極線方向或水平方向排列的相同顏色。 閘極内建電路120 ’嵌裝於液晶面板1〇〇內，用於驅動閘極線 GL，以及驅動積體電路130’裝設至液晶面板1〇〇,用於驅動閘極 内建電路120且供應視頻訊號至資料線DL。撓性印刷電路2〇〇， 接合於液晶面板1〇〇,用於連接液晶面板1〇〇至外部驅動系統（圖 1375211 中未表示）。 液晶面板100包含下基板1〇2與上基板1〇4，彼此正對接合； 分隔物（圖中未表示）’用於維持下基板102與上基板104之間固 .·定的分子間隙，以及液晶層（圖中未表示填充於分隔物提供的 - 液晶空間中。 ' 下基板102包含與上基板104對應的顯示區域以及除去顯示The V liquid crystal display (LCD) device uses an electric field to control the light transmittance of liquid crystal molecules to display an image. Generally, a liquid crystal display device provides a liquid crystal panel comprising a liquid crystal between two glass substrates, a matrix of liquid crystal molecules, and an interaction device for respectively changing signals in the liquid crystal molecules; a driving circuit for driving the liquid crystal panel, and a backlight unit , guide the light to the LCD panel. Recently, the number of signal lines or the number of circuit elements of the liquid crystal panel has been reduced to develop a thin and low-cost liquid crystal display device. For example, Korean Patent Publication No. 10-2003-0039972 discloses a liquid crystal display device for a single-chip glass, in which an integrated driving wafer for driving a liquid crystal display panel is mounted on a periphery of a display region to reduce Panel size and production cost of the device. The monocrystalline liquid crystal device on glass of the prior art has the disadvantage of being a town. The color enamel lattice of the unitary enamel towel comprises a vertical ribbon structure such that the color enamel lattices are arranged along the horizontal direction (the direction of the gate line) of the liquid crystal display panel. A separate data line is required for each color book lattice. Because the size of the integrated circuit is increased as the number of data lines increases, the size of the integrated circuit is also increased. For example, the analysis of 360 X 16 〇 ' can use a single-wafer type liquid crystal display device. In order to obtain a high resolution number, the glass on the single W Weijing fresh device needs to be out of the circuit, for example, the selection circuit shouts less (four) line ugly. When using the selection circuit, in the closed-end ·.· line agency dynamic __, according to the time to divide the analogy of the data, but 2 supply to the touch line 'to reduce the charging time of the data. Therefore, the resolution of the liquid crystal display panel with :============================================ In addition, the analog pixel data output from each channel of the integrated drive chip is reversed for use in each horizontal line, thereby consuming a large amount of power. SUMMARY OF THE INVENTION Accordingly, embodiments of the present invention provide one or more problems arising from limitations and disadvantages of the known art of a liquid crystal display device. The purpose of the embodiment is to provide a liquid crystal display device which can reduce the production cost and power consumption by reducing the number of y bead lines. The other object of the invention is to provide a liquid crystal display device having the features and advantages of the leaf, which will be explained in part by the following explanations: it can be practiced by one of ordinary skill in the art. The descriptions of the present invention can be partially understood or can be understood from the present invention and other advantages can be realized by the present invention to realize the structure specified by the combination and the combination of the drawings, in order to obtain the embodiment of the present invention. These and other advantages are now described in a general and general description of the present invention. A liquid crystal display device of the present invention comprises: a plurality of elements, the line 'including a first data line and a second data line, substantially parallel to each other ^^Number of gate lines' includes a first gate line, a second gate line and a third gate line, which are arranged parallel to each other on the solid shell, and the gate line intersects the data line; The gate line and the data line define 'at least three sub-tenucine, directly along the adjacent data line, and corresponding to the 砰-color to form a halogen; and driving the integrated circuit to sequentially drive the first and second And the third gate line is in a horizontal period, wherein the first period of the horizontal period is 'the supply of the first element of the prime element—the opposite of the second signal of the second sub-pixel supplied to the element, and Supply to 昼素Di three children of the same polarity day prime ter signals. Another aspect of the method for driving a liquid crystal display device, the liquid crystal display device L st has a plurality of (four) lines, a plurality of gate lines, and a plurality of elements defined by the φ data lines and the gate lines, and each element includes three sub-tendins. Directly arranged along one of the adjacent data lines, the driving method of the liquid crystal display driving device comprises: sequentially driving three gate lines during each horizontal period of the first frame, and supplying the first polarity between the first and the _ The video signal to the odd number data line, and the second polarity of the video signal drum number data line is supplied in the first frame, and the towel horizontal period and each element are supplied to the first signal of the first sub-unit. The polarity of the second signal supplied to the second sub-single is opposite to that of the third signal supplied to the third sub-tend. In another aspect, the liquid crystal display device of the present invention comprises m gate lines, m is an integer 'n lean line greater than -, n is an integer greater than two; and a plurality of first color 1375211 dice pixels are arranged Between the ith gate line and the (i+1)th gate line, a plurality of second color sub-tenks are arranged in the (W)th gate line and the (i+2)th Between the gate lines and a plurality of third color sub-elements, arranged between the (4) & idle line and the (1+3)th gate line, wherein the first-color sub-salm and the first The three color sub-picture elements are connected to the first to the (nl)th data lines, and the second color sub-pixels are connected to the second to nth data lines. Φ In another aspect, the liquid crystal display device of the present invention comprises m gate lines, m is a number of turns greater than six; n data lines, η is an integer greater than two; and a plurality of first sub-deniers are sequentially arranged Between the first gate line and the (i+1)th gate line, a plurality of first sub-elements are sequentially arranged between the gate strip gate line and the (4) ground strip closed line a plurality of third color sub-tendins are sequentially arranged between the (i+2)th gate lines and the (i+3)th gate lines, and the plurality of fourth sub-tenucines are arranged in order Between the ()+3) 闸 gate line and the (i+4)th gate line, a plurality of fifth sub-tendins, the conversion f is arranged in the (fourth)th line and the (fourth)thth gate Between the lines, a plurality of ', sub-salmon' are arranged in order between the (i+5)th inter-pole line and the (iv)-punch idle line. The prime, the fifth sub-pixel, and the sixth sub-segment are connected to one of the first to the (nl)th data lines, and the third sub-alkaline and the fourth sub-alloy are connected to the second to the fourth Among the data lines - where - the first and second elements contain the first color The halogen, the second sub-halogen and the fifth sub-plasma include: the first sub-pixel and the second sub-halogen and the sixth sub-enriche include a third color sub-portion. The present-generation HS-day display device comprises: The panel comprises a plurality of 2 crystal lattices formed in the m+i data line and the n gate lines, and three colors are arranged repeatedly along the data line direction, and the same color is arranged along the line direction; _ built-in circuit 'supply The gate opens the gate line formed in the liquid crystal panel; the driving touch circuit is formed in the liquid crystal panel, drives the built-in circuit and supplies the reversed video signal to the data line in the data line unit and the frame unit, and the flexibility Printed circuit, connecting the liquid crystal panel to the external drive system. It is to be understood that the general description of the invention and the detailed description of the invention as described above are both representative and translating, and are intended to further disclose The preferred embodiments of the present invention are described in detail with reference to the accompanying drawings. FIG. 1 is a schematic diagram of a liquid crystal display I according to a first embodiment of the present invention. . In the "Fig. 1", the liquid crystal display device includes a liquid crystal panel 1A, which includes a plurality of elementary crystal lattices 110 defined by a plurality of data lines DL and a plurality of gate lines (the intersection of ^). The grid 110 & includes three colors alternately arranged along the data line direction or the vertical direction and the same color arranged along the gate line direction or the horizontal direction. The gate built-in circuit 120 ' is embedded in the liquid crystal panel 1 , for Driving the gate line GL, and driving the integrated circuit 130' to the liquid crystal panel 1'', for driving the gate built-in circuit 120 and supplying the video signal to the data line DL. The flexible printed circuit 2 is bonded to The liquid crystal panel 1 is connected to the liquid crystal panel 1 to an external driving system (not shown in FIG. 1375211). The liquid crystal panel 100 includes a lower substrate 1〇2 and an upper substrate 1〇4, which are directly joined to each other; The figure is not shown to 'maintain a molecular gap between the lower substrate 102 and the upper substrate 104, and a liquid crystal layer (not shown in the liquid crystal space provided in the spacer. The lower substrate 102 includes Corresponding to the upper substrate 104 Display area and remove display
#區域之非顯示區域。下基板102之顯示區域中，複數條資料線DL 沿第-方向依照預定間隔彼此平行形成，複數條閘極線GL沿第二 方向依照預定間隔彼此平行形成，以及晝素晶格11〇形成於複數 條資料線與閘極線定義之各區域處^第一方向垂直於第二方向。 供應視頻訊號的資料線DL的數目小於供應閘極開電壓之閘極線 GL的數目。 各晝素晶格110包含溥膜電晶體112，連接於閘極線gl與資 • 料線DL，以及晝素電極114，連接於薄膜電晶體112。各薄膜電 晶體112包含閘電極，連接於閘極線GL;源電極，連接於資料線， 以及>及電極’連接於晝素電極114。薄膜電晶體U2沿資料線DL 交替排列於相對的側面上。就是說，兩個垂直鄰接的晝素晶格u〇 之薄膜電晶體112連接至不同的資料線Dl。因此，.連接於奇數號 閘極線GL2n-l.之薄膜電晶體112供應來自第一至第(m)th資料線 DL1〜DLm之視頻訊號至各自的晝素電極114，連接於偶數號閘 極線GL2n之薄膜電晶體112供應來自第二至第資料線 (S ) 11 1375211 DL2〜DLm+1之視頻訊號至各自的晝素電極u心畫素電極叫 的短邊平行於資料線DL’形成的短邊比平行於開極線GL的長邊 短。因此，晝素電極Π4形成水平帶。 下基板102的非顯示區域中，閘極内建電路12〇連接於各複 數條閘極線GL ’並且裝設有驅動積體電路13〇。上基板ι〇4包含 彩色遽光片、共同電極以及蔽光層。共同電極可卿成於下基板 102之上’取決於液晶層的液晶。形成的彩色濾光片包含紅色遽光 片、綠色渡光片以及藍色遽光片’沿資料線DL方向交替排列，並. 且沿閘極線方向排列相同顏色的彩色遽光片。 共同電極可以貫通上基板1〇4而形成或者形成線狀與晝素電 極114相對以形成通過液晶層的垂直電場。或者，共同電極可以 形成於下基板102之上’平行於晝素電極1M以形成通過液晶層 之水平電場。 ' 敝光層开》成於上基板104之上’以重疊於與晝素電極114重 疊之不包含開口區域之區域。各自位於紅色濾光片、綠色濾光片 以及藍色濾光片上的各紅、綠以及藍色晝素晶格係為一個彩色影 像之單元晝素。 撓性印刷電路200被提供至下基板1〇2之非顯示區域且接合 於下基板102之墊部。撓性印刷電路2〇〇傳送輸入功率Vin、來源 資料訊號Data以及來自驅動系統之同步訊號DE、DCLK、Hsync 及Vsync至驅動積體電路130。此外，撓性印刷電路200包含有裝 12 1375211 設的被動元件，例如電阻21〇、電容器22G以及電感23〇。 驅動積體電路130被裝設至積體電路裝設部，積體電路裝設 部在下基板102之非顯示區域處包含複數個輸人/輸出墊。驅動 積體電路130包含複數個輸人/輸出凸塊，各自電連接於積體電 路裝设部處的輸人/輸出墊。此外，驅動積體電路13()產生間極 驅動訊號以及資料驅動訊號。透過使絲自撓性印刷電路2〇〇之 同步訊號DE、DCLK、Hsync及Vsync至少其中之一，驅動積體 電路130劃分與一個週期的水平同步訊號Hsync對應的一個水平 週期為第一至第三子週期。此外，驅動積體電路13〇排列來源資 料訊號Data，對應於第一至第三子週期的紅色資料R、綠色資料 G以及藍色資料B ’轉換紅色資料R、綠色資料G以及藍色資料B 為類比視頻訊號，以及供應視頻訊號至資料線^^。 「第2圖」係為「第1圖」所示之驅動積體電路之方塊圖。 請參考「第2圖」’驅動積體電路13〇包含訊號延遲單元31〇、第 一電源產生單元320、時脈產生單元322、參考電壓設定單元324 以及第二電源產生單元326。驅動積體電路130還包含共同單元產 生單元328、訊號控制單元330、控制訊號產生單元340 '電壓拉 升單元350、灰階電壓產生單元360以及資料轉換單元380。訊號 延遲卓元310延遲來源資料訊號Data以及來自挽性印刷電路2〇〇 之同步訊號DE、DCLK、Hsync及Vsync (如「第1圖」所示） 進入訊號控制單元330。訊號控制單元330控制訊號延遲單元31〇 C S ) 13 1375211 以及驅動積體電路130中其他電路之驅動β 時脈產生罩元322產生時脈，用於驅動第一及第二電源產生 單元320及326。第一電源產生單元32〇產生第一電源，就是說， 依照來自時脈產生單元322之時脈’使用來自撓性印刷電路2〇〇 (如「第1圖」所示）之輸入功率νώ產生第一及第二參考電壓 VSP及VSN。此外’例如撓性印刷電路2〇〇 (如「第〗圖」所示） ^ .上的電阻210、電容器220以及電感230等被動元件，透過電源訊 號線321a、321b以及321c連接於第一電源產生單元32〇，並且用 於偏壓第一電源產生單元32〇產生的第-及第二參考電壓vsp及 VSN ’或者用於設定驅動積體電路130之選項功能。 透過使用第-電源產生單元32〇產生的第一及第二參考電壓 vsp及VSN，第二電源產生單元326產生驅動液晶面板丨㈨所需 的第二電源，即第—及第二驅動電壓Vdd及Vss、積體電路驅動 φ 電壓Vcc、閘極開啟電壓Von以及閘極關閉電壓v〇ff。 參考電壓奴單元324設定第-及第二參考電壓VSI>及VSN 之位準’從第一電源產生單元320供應至灰階電壓產生單元36〇。 .透過使用來自第-電源產生單元3：26的供應至撓性印刷電路2〇〇 上的被動元件的第-及第二驅動電壓Vdd及Vss，共同電壓產生 單το 328產生共同電壓Vc〇m以供應至液晶面板1〇〇之共同電極。 撓性印刷電路200包含共同電壓變更單元（圖中未表示），透過使 用電阻或電容器（圖_未表示）至少其中之_變更共同賴產生 14 1375211 單元328所產生的共同電壓Vcom。 訊號控制單元330供應來自訊號延遲單元310之同步訊號 DE、DCLK、Hsync以及Vsync至控制訊號產生單元340。透過使 用來自訊號控制單元330之同步訊號DE、DCLK、Hsync以及Vsync 至少其中之一，控制訊號產生單元340產生資料控制訊號DST、 DSC、DOE以及DPS與閘極驅動訊號RVst以及RCLK1至 RCLKi。資料轉換單元380包含位移暫存器381、閂存單元383、 數位/類比轉換單元385、緩衝器單元387以及選擇單元389。 第3圖」係為「第2圖」.所不之訊號控制單元所分類之資 料訊號之示意圖。請參考「第3圖」，訊號控制單元330還排列來 自訊號延遲單元310之來源資料訊號，用於驅動液晶面板1〇〇，並 且供應排列的資料至資料轉換單元380。尤其地，訊號控制單元 330排列來自訊號延遲單元31〇之一個水平週期的來源資料訊號 為紅色資料R、綠色資料G以及藍色資料B，對應於第一至第三 子週期1ST、2ST以及3ST。 水平週期的第一子週期1ST期間，訊號控制單元33〇重新排 列經過排列的紅色資料R為奇數號的紅色資料R01至ROm/2以 存破供應至第一至第(m)th資料線DL1至;〇1^中的奇數號資料線 DLl 'DL3...DLm-l ’以及重新排列為偶數號的紅色資料肪1至 REm/2以待被供應至偶數號資料線DL2、DL4. DLm。然後，水 平週期的第二子週期2ST期間，訊號控制單元33G重新排列經過 15 1375211 排列的綠色資料G為奇數號的綠色資料G01至GOm/2以待被供 應至第二至第資料線DL2至DLm+Ι中的偶數號資料線 DL2、DL4...DLm ’以及重新排列為偶數號的綠色資料Gm至 GEm/2以待被供應至奇數號資料線DL3、DL5 DLm+1。類似地， 水平週期的第三子週期3ST期間，訊號控制單元330重新排列經 過排列的藍色資料B為奇數號的藍色資料B01至BOm/2以待供 應至第一至第(m)th資料線DL1及DLm中的奇數號資料線DL1、 DL3...DLm-l ’以及重新排列為偶數號的藍色資料βει至BEm/2 以待供應至偶數號資料線DL2、DL4...DLm。 訊號控制單元330還供應輸出自訊號延遲單元310之同步訊 號DE、DCLK、Hsync以及Vsync至控制訊號產生單元340。透 過使用訊號控制單元330輸出的同步訊號DE、DCLK、Hsync以 及Vsync至少其中之一，控制訊號產生單元34〇產生資料控制訊 號DST、DSC、DO E以及DPS與閘極驅動訊號RVs以及RCLK1 至RCLKi。資料控制訊號dst、DSC、DOE及DPS包含資料開 始訊號DST、資料位移時脈DSC、資料輸出訊號D〇E以及資料 極性訊號DPS，用於控制資料轉換單元38〇。控制訊號產生單元 340供應不同極性的視頻訊號至鄰接的資料線DL，並且產生資料 極性訊號’在至少一個框單元中用於反向被供應至資料線DL之視 頻訊號極性。控制訊號產生單元34〇產生一行反向類型的資料極 性訊號DPS，反向資料線單元以及至少一個框單元的視頻訊號的 16 1375211 極性。 閘極驅動訊號RVs以及RCLK1至RCLKi包含閘極開始訊號 RVst以及第一至第(i)th時脈訊號RCLK1至RCLKi，用於驅動閘 極内建電路120。第一至第(i)th時脈訊號RCLK1至RCLKi包含依 序延遲的相位，從而第一至第(i)th時脈訊號RCLK1至RCLKi包 含的脈衝寬度能夠各自打開各子週期的薄膜電晶體。第一至第(i)th 時脈訊號RCLKI至RCLKi可以包含二、四、六、八或者十個相 位其中任意之一，取決於閘極内建電路120。 透過使用供應自第二電源產生單元326的閘極開啟電塵Von 以及閘極關閉電壓Voff’電壓拉升電路350拉升供應自控制訊號 產生單元340之閘極驅動訊號RVs以及RCLK1至RCLKi的電壓 位準。閘極開啟電壓Von係為打開各晝素晶格no之薄膜電晶體 112之電壓，閘極關閉電壓Voff係為關閉各晝素晶格11〇之薄膜 電晶體112之電壓。電壓拉升電路350供應經過拉升的閘極驅動 訊號Vst以及CLK1至CLKi通過下基板1 〇2的非顯示區域處的閘 極驅動訊號傳輸線140至閘極内建電路120。 灰階電壓產生旱元360細分來自第一電源產生單元32〇之第 一及第二參考電壓VSP及VSN，以產生複數個灰喈電壓，並且供 應此複數個灰階電壓至資料轉換單元380。如果來源資料訊號Data 包含N個位元，複數個灰階電壓產生2N個正極性灰階電壓以及 2N個負極性灰階電壓。 (S ) •17 ^75211 依照來自控制訊號產生單元340之資料位移時脈DSC，位移 .暫存器381依序移位資料開始訊號DST，以產生位移訊號ss。位 •移暫存盗381可以為具有兩個方向的位移暫存器，依照來自訊號 控制單元之導向訊號被驅動於相反的方向。 閂存單元383回應於來自位移暫存器381之位移訊號SS，依 序問存來自訊號控制單元330之線路總數之資料紅綠藍RGB，並 • 且依照來自控制訊號產生單元340之資料輸出訊號DOE ,供應線 路總數的閂存資料RData至數位/類比轉換單元385。 透過使用來自灰階電壓產生單元36〇的複數個正極性的灰階 電壓以及負極性的灰階電壓，數位〆類比轉換單元385轉換供應 自問存單元383明存資料RData為正極性及負極性的視頻訊號 PVS及NVS。數位/類比轉換單元385從複數個正極性灰階電壓 中選擇與閃存資料RData的灰階值對應的一個灰階電壓作為正極 Φ 性視頻訊號，並且從複數個負極性灰階電壓中選擇與閂存資 料RData的灰階值對應的一個灰階電壓作為負極性的視頻訊號。 使用通過撓性印刷電路200的被動元件的來自第一電源產生 單元320的第一及第二驅動電壓Vdd及Vss，緩衝器單元犯？緩 . 衝正極性以及負極性視頻訊號PVS以及NVS。例如，考慮到資料 • 線DL上的負載，緩衝器單元387放大正極性以及負極性視頻訊號 PVS 以及 NVS。 依照來自控市〗訊號產生單元340的資料極性訊號DPS，選擇 (S ) 18 單元.389選擇供應自緩衝器單元387的正極性或者及負極性視頻 訊號PVS或者NVS，並且透過第一至第(m+1)th|出通道供應選 擇的視頻訊號至資料線£>乙。例如，依照資料極性訊號DpS，輸出 自選擇單元3的的視頻訊號的極性在輸出通道單元以及框單元中 被反向。 请參考「第1圖」，閘及内建電路w形成於下基板1〇2的非 顯不區域，同時形成薄膜電晶體112，閘極内建電路⑽各自連接 於複數條GL。祕崎電路12Q於每個子獅產生閑極開 啟電壓V0n’回應於供應自驅動積體電路13〇的拉升間極驅動訊號 Vsm及CLK1至CLK1，並且依序供制極開啟電壓VGn至問極 線L例如’透過下基板1〇2的非顯示區域處形成的複數個閉極 驅動訊#υ傳輸線14〇，驅動積體電路13()供應拉升關極驅動訊號 Vst以及CLK1至CLKi至閉極内建電路12〇。 第4圖j係為本發明第一實施例之液晶顯示裝置之驅動波 形之不意圖。參号「第4圖」以及「第1圖」描述本發明第-實 %例之具有代表性的液晶顯示裝置之驅動。例如，第—水平週期 被:刀為第-至第三子猶，紅色、綠色以及藍色視頻訊號依序 顯不於子翻處，以混合紅色、綠色以及藍色視頻，從而共同顯 示一個彩色視續。 第尺平週期的第—子週期處，同步供應第一至第㈣出資料 線DU至DLm之閑極開啟電麗—至第一閉極線阳，正極性 19 1375211 的紅色視頻喊R+健應至奇數號㈣線DL—Qdd，並且負極性 的視頻訊號R-被供應至偶數號資料、線DL_even。因此，第一水平 線的晝素晶格11G巾’奇數號之晝素晶格11G顯示對應於正極性 的紅色視頻訊號R+的紅色視頻，偶數號之晝素晶格11〇顯示對應 於負極性紅色視頻訊號R-的紅色視頻。 第-水平週期的第二子週期，同步供應第二至第(㈣沖資料 線DL2至DLm+1之閘極開啟電壓v〇n至第二閘極線Gu，正極 性的綠色觀峨〇+被供紅奇織諸線DL_〇dd，貞極性的 綠色視頻喊G_被供紅偶鮮ufmDL—even。目此，第二水 平線的畫素晶格11G中’奇數號之晝素晶格nG顯示對應於負極 性綠色視頻訊號G_的綠色視頻，偶數號之晝素晶格nG顯示對應 於正極性綠色視頻喊〇+的綠色視頻。因此，沿垂直方向鄰接的 第及第一水平線中的晝素晶格所顯示的視頻訊號彼此包含 不同的極性。 第一水平週期的第三子週期，同步供應第一至第(m)th資料線 DL1至DLm之閘極開啟電壓v〇n至第三閘極線GL3，正極性藍 色視頻訊號B+被供應至奇數號資料線DL一〇dd，負極性藍色視頻 訊號B·被供應至偶數號資料線DL-even。因此，第三水平線的晝 素晶格110中，奇數號之畫素晶格11()顯示與正極性藍色視頻訊 號B+對應的監色視頻，偶數號之晝素晶格11〇顯示與負極性藍色 畫素訊號B-對應的藍色視頻。因此，沿垂直方向鄰接的第二及第 20 1375211 三水平線中的晝素晶格 性0 110所顯示的视頻猶包含彼此不同的極 一結果’第—水平週期_，紅色、綠色錢藍色視頻依序顯 :子紅色、綠色以及藍色視頻’從而共_示一個 彩色視頻。_地’各水平職的晝素晶格依照與上述第一水平 週期相同的方法顯示-個彩色畫素。然後，下，中，視頻訊號 的極性如上所述被反向。 因此’因為各畫素晶格110上的薄膜電晶體112沿資料線dl 交替排列於相對_面之上，從驅動積體電路13Q供應至液晶面 板勘之包含行反向類型極性型樣的視頻罐顯示於點反向類型 的極性型樣中。 「第5圖」係為本發明第二實施例之液晶顯示裝置之示意圖。 如「第5 ®」所示’第二實翻之液晶顯示裝置與第—實施例類 似，但是各晝素晶格.110的排列除外。因此，第二實施例之以下 解釋將關注於各晝素晶格110之排列上。如上所述，第二實施例 之液晶顯示裝置之其他部與第一實施例類似。 如「第5圖」所示，沿鄰接資料線DL排列於相對側面之上的 每兩個畫素晶格110交替連接於鄰接的資料線DL其中之一。例 如，連接於第（4k-3)(k為整數)th條閘極線GL4k_3之各書素晶格 110直接地連接於左侧鄰接的資料線；連接於第(处_2地條間極線 GL4k-2的各晝素晶格110直接地連接於左側鄰接的資料線。另一 21 1375211 方面，連接於第(4k-l)tM条閘極線GL4k-l的各晝素晶格110直接 地連接於右儀接的㈣線；連接於第(4k)th _極線GL4k的各 晝素晶格110直接地連接衿右侧鄰接的資料線。 輸出自積體電路130之視頻訊號被供應至連接於各晝素晶格 之資料線。此時，視頻訊號的極性被反向於資料線單元以及至少 一個框單元中。因此，因為各晝素晶格11〇的每兩個薄膜電晶體 112沿貢料線DL交替地排列於其相對侧面之上，包含行反向類型 極性型樣的視頻訊號從驅動積體電路13〇被供應至液晶面板11〇， 顯示為垂直的兩點反向類型的極性型樣。此時，視頻訊號之極性 透過兩點反向類型極性型樣被反向於每兩個晝素晶格單元以及資 料線單元中。 依照本發明第二實施例，供應自驅動積體電路13〇之視頻訊 號以垂直兩點反向類型顯示於液晶面板1〇〇之上，透過防止出現 閃點（dot-flicker)缺陷以改善影像品質。此外，依照本發明第二 實施例，供應自驅動積體電路130之視頻訊號之極性被反向於至 少一個框單元令，以增加各晝素晶格110之充電時間並且防止視 頻訊號之延遲。 如上所述，本發明實施例之液晶顯示裝置中，組成包含水平 帶狀結構的畫素晶格的單元晝素晶格排列為垂直方向，從而減少 資料線的數目。因此，本發明實施例之液晶顯示裝置可用於大尺 寸的液晶顯示裝置以及小尺寸的液晶顯示裝置。 22 1375211 如上所述’本發明實施例之液晶顯示裝置中，各畫素晶格ιι〇 之上的每一個或兩個薄膜電晶體112沿資料線〇乙交替排列於相對 的側面之上。並非限制於上述解釋。例如，用於各晝素晶格ιι〇 之每三個薄膜電晶體〗12沿祕的㈣線见测於相對的側面之 上’可交替地連接於鄰接的資料線01^其中之一。 因此，本發明實施例之液晶顯示裝置具有以下優點。首先， 一個驅動積體電路嵌裝於液晶面板内，液晶面板之驅動減少單元 ‘成本並且最小化液晶顯示裝置的厚&。第二，資料線單元以及框 單元中的視頻訊號之極性反向允許減少功率消耗。第三，視頻訊 號的極性改變的最小化提供足夠的視頻訊號充電時間週期並且改 善影像品質。第四’晝素晶格沿水平方向排列允許減少第三條資 料線數目，從❿可彻大尺寸騎晶齡面板及小尺寸的液晶顯 示面板。第五，包含行反向類型極性型樣的視頻訊號以垂直兩點 反向類型被顯示’透過防止例如閃點等缺陷而改善影像品質。第 六，供應自驅動積體電路之視頻訊號之極性被反向於至少一個框 單元中’明加各晝素晶格11G之充f時間並且社視頻訊號之 延遲，從而改善影像品質。 此外，本發明實施例之液晶顯示裝置被驅動於列反向方案 中，以點反向其中的晝素電極。例如，根據本發明實施例之晝素 晶格之排列，液晶顯示裝置被驅動於列反向方案，以取得一點反 向驅動方案的效果。或者根據本發明另__實施例之晝素晶格排 (S ) 23 ^75211 列，液晶顯示裝置驅動於列反向方案以得到兩點反向驅動方案之 效果0 此外，僅僅具有一個驅動積體電路之液晶面板之驅動減少了 挽11印刷電路之尺寸，並且減少了撓性印刷電路之單it成本。另 外，驅動嵌裝於液晶面板中之閘極線之閘極驅動器消除了驅動積 體电路、閘極撓性印刷電路以及閘極印刷電路板之使用。並且，#地区的非示区. In the display region of the lower substrate 102, a plurality of data lines DL are formed in parallel with each other along a predetermined interval in the first direction, a plurality of gate lines GL are formed in parallel with each other in a second direction at a predetermined interval, and a pixel lattice 11 is formed in The first direction of each of the plurality of data lines and the gate line definition is perpendicular to the second direction. The number of data lines DL supplying video signals is smaller than the number of gate lines GL supplying the gate opening voltage. Each of the pixel lattices 110 includes a ruthenium film transistor 112 connected to the gate line gl and the material line DL, and a halogen electrode 114 connected to the thin film transistor 112. Each of the thin film transistors 112 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line, and > and an electrode 'connected to the halogen electrode 114. The thin film transistors U2 are alternately arranged on the opposite sides along the data line DL. That is, two vertically adjacent thin film transistors 112 of the pixel cell u〇 are connected to different data lines D1. Therefore, the thin film transistor 112 connected to the odd-numbered gate line GL2n-1 supplies video signals from the first to (m)th data lines DL1 to DLm to the respective pixel electrodes 114, and is connected to the even-numbered gates. The thin film transistor 112 of the polar line GL2n supplies the video signals from the second to the data lines (S) 11 1375211 DL2 DLDL+1 to the respective pixel electrodes, the short sides of the core pixels are parallel to the data line DL' The short side formed is shorter than the long side parallel to the open line GL. Therefore, the halogen electrode Π4 forms a horizontal band. In the non-display area of the lower substrate 102, the gate built-in circuit 12 is connected to each of the plurality of gate lines GL' and is provided with a drive integrated circuit 13A. The upper substrate 〇4 includes a color illuminating sheet, a common electrode, and a light shielding layer. The common electrode can be formed on the lower substrate 102. Depending on the liquid crystal of the liquid crystal layer. The formed color filter comprises a red fluorescent sheet, a green light-emitting sheet, and a blue calender sheet, which are alternately arranged along the direction of the data line DL, and arranged in the direction of the gate line to align the color patches of the same color. The common electrode may be formed through the upper substrate 1〇4 or formed in a line shape to oppose the halogen electrode 114 to form a vertical electric field passing through the liquid crystal layer. Alternatively, a common electrode may be formed on the lower substrate 102 'parallel to the halogen electrode 1M to form a horizontal electric field passing through the liquid crystal layer. The 'Twilight Layer On' is formed on the upper substrate 104 to overlap the region overlapping the halogen electrode 114 and not including the opening region. The red, green, and blue elementary crystal lattices, each of which is located on the red filter, the green filter, and the blue filter, are unitary elements of a color image. The flexible printed circuit 200 is provided to the non-display area of the lower substrate 1〇2 and bonded to the pad portion of the lower substrate 102. The flexible printed circuit 2 transmits the input power Vin, the source data signal Data, and the synchronization signals DE, DCLK, Hsync, and Vsync from the drive system to the drive integrated circuit 130. In addition, the flexible printed circuit 200 includes a passive component such as a resistor 21 〇, a capacitor 22G, and an inductor 23 装 provided with 12 1375211. The drive integrated circuit 130 is mounted to the integrated circuit mounting portion, and the integrated circuit mounting portion includes a plurality of input/output pads at the non-display area of the lower substrate 102. The drive integrated circuit 130 includes a plurality of input/output bumps, each of which is electrically connected to an input/output pad at the integrated circuit mounting portion. In addition, the driving integrated circuit 13() generates a differential driving signal and a data driving signal. The driving integrated circuit 130 divides a horizontal period corresponding to one cycle of the horizontal synchronizing signal Hsync by first at least one of the synchronizing signals DE, DCLK, Hsync, and Vsync of the flexible printed circuit 2 Three sub-cycles. In addition, the driving integrated circuit 13 aligns the source data signal Data, and the red data R, the green data G, and the blue data B ' corresponding to the first to third sub-cycles convert the red data R, the green data G, and the blue data B. For analog video signals, and supply video signals to the data line ^^. "Fig. 2" is a block diagram of the drive integrated circuit shown in "Fig. 1". Referring to "Fig. 2", the drive integrated circuit 13 includes a signal delay unit 31, a first power generating unit 320, a clock generating unit 322, a reference voltage setting unit 324, and a second power generating unit 326. The driving integrated circuit 130 further includes a common unit generating unit 328, a signal control unit 330, a control signal generating unit 340', a voltage boosting unit 350, a grayscale voltage generating unit 360, and a data converting unit 380. The signal delay delay element 310 delay source data signal Data and the synchronization signals DE, DCLK, Hsync and Vsync (shown in FIG. 1) from the printed circuit 2 are entered into the signal control unit 330. The signal control unit 330 controls the signal delay unit 31〇CS ) 13 1375211 and the driving of the other circuits in the driving integrated circuit 130 to generate a clock for generating the first and second power generating units 320 and 326. . The first power generating unit 32 generates a first power source, that is, generates an input power νώ from the flexible printed circuit 2 (shown in FIG. 1) according to the clock from the clock generating unit 322. First and second reference voltages VSP and VSN. In addition, for example, a flexible printed circuit 2 (as shown in the "figure") ^. The passive components such as the resistor 210, the capacitor 220, and the inductor 230 are connected to the first power source through the power signal lines 321a, 321b, and 321c. The generating unit 32 is configured to bias the first and second reference voltages vsp and VSN' generated by the first power generating unit 32 or to set an optional function of the driving integrated circuit 130. The second power generating unit 326 generates the second power source required to drive the liquid crystal panel 九 (9) by using the first and second reference voltages vsp and VSN generated by the first power generating unit 32, that is, the first and second driving voltages Vdd And Vss, the integrated circuit drives φ voltage Vcc, gate turn-on voltage Von, and gate turn-off voltage v〇ff. The reference voltage slave unit 324 sets the first and second reference voltages VSI> and the level of the VSN' to be supplied from the first power generating unit 320 to the gray scale voltage generating unit 36A. By using the first and second driving voltages Vdd and Vss supplied from the first-power generating unit 3: 26 to the passive elements on the flexible printed circuit 2, the common voltage generating unit το 328 generates a common voltage Vc〇m To supply to the common electrode of the liquid crystal panel 1〇〇. The flexible printed circuit 200 includes a common voltage changing unit (not shown), and a common voltage Vcom generated by the unit 13b is generated by using at least one of the resistors or capacitors (not shown). The signal control unit 330 supplies the sync signals DE, DCLK, Hsync, and Vsync from the signal delay unit 310 to the control signal generating unit 340. The control signal generating unit 340 generates the data control signals DST, DSC, DOE, and DPS and the gate driving signals RVst and RCLK1 to RCLKi by using at least one of the synchronizing signals DE, DCLK, Hsync, and Vsync from the signal control unit 330. The data conversion unit 380 includes a shift register 381, a latch unit 383, a digital/analog conversion unit 385, a buffer unit 387, and a selection unit 389. Figure 3 is a schematic diagram of the information signal classified by the signal control unit of "No. 2". Referring to FIG. 3, the signal control unit 330 also arranges the source data signals from the signal delay unit 310 for driving the liquid crystal panel 1 and supplying the arranged data to the data conversion unit 380. In particular, the signal control unit 330 arranges the source data signals from one horizontal period of the signal delay unit 31 to be red data R, green data G, and blue data B, corresponding to the first to third sub-periods 1ST, 2ST, and 3ST. . During the first sub-period 1ST of the horizontal period, the signal control unit 33 rearranges the red data R01 to ROm/2 whose odd-numbered red data R is an odd number to supply the first to the (m)th data lines DL1. To; the odd-numbered data lines DL1 'DL3...DLm-l' in 〇1^ and the red data 1 to REm/2 rearranged to an even number to be supplied to the even-numbered data lines DL2, DL4. DLm . Then, during the second sub-period 2ST of the horizontal period, the signal control unit 33G rearranges the green data G arranged by 15 1375211 as the odd-numbered green data G01 to GOm/2 to be supplied to the second to the data lines DL2 to The even-numbered data lines DL2, DL4, ... DLm' in DLm+Ι and the green data Gm to GEm/2 rearranged to an even number are to be supplied to the odd-numbered data lines DL3, DL5, DLm+1. Similarly, during the third sub-period 3ST of the horizontal period, the signal control unit 330 rearranges the blue data B01 to BOm/2 whose odd-numbered blue data B is an odd number to be supplied to the first to (m)thth. The odd-numbered data lines DL1, DL3, ... DLm-1' in the data lines DL1 and DLm and the blue data βει to BEm/2 rearranged to the even numbers are to be supplied to the even-numbered data lines DL2, DL4... DLm. The signal control unit 330 also supplies the synchronizing signals DE, DCLK, Hsync, and Vsync output from the signal delay unit 310 to the control signal generating unit 340. The control signal generating unit 34 generates the data control signals DST, DSC, DO E and DPS and the gate driving signals RVs and RCLK1 to RCLKi by using at least one of the synchronization signals DE, DCLK, Hsync and Vsync outputted by the signal control unit 330. . The data control signals dst, DSC, DOE and DPS include a data start signal DST, a data shift clock DSC, a data output signal D〇E, and a data polarity signal DPS for controlling the data conversion unit 38〇. The control signal generating unit 340 supplies video signals of different polarities to the adjacent data lines DL, and generates a data polarity signal 'in at least one of the frame units for reversely supplying the video signal polarities to the data lines DL. The control signal generating unit 34 generates a row of inverted type data polarity signals DPS, a reverse data line unit and a polarity of 16 1375211 of at least one frame unit video signal. The gate drive signal RVs and RCLK1 to RCLKi include a gate start signal RVst and first to (i)thth clock signals RCLK1 to RCLKi for driving the gate built-in circuit 120. The first to (i)thth clock signals RCLK1 to RCLKi include sequentially delayed phases, so that the pulse widths of the first to (i)thth clock signals RCLK1 to RCLKi can respectively turn on the thin film transistors of the respective sub-cycles. . The first through (i)thth clock signals RCLKI through RCLKi may comprise any one of two, four, six, eight or ten phases, depending on the gate built-in circuit 120. The voltage of the gate driving signal RVs and the RCLK1 to RCLKi supplied from the control signal generating unit 340 is boosted by using the gate-on dust Von supplied from the second power generating unit 326 and the gate-off voltage Voff' voltage pull-up circuit 350. Level. The gate turn-on voltage Von is a voltage at which the thin film transistor 112 of each of the pixel cells no is turned on, and the gate turn-off voltage Voff is a voltage at which the thin film transistor 112 of each of the individual crystal lattices 11 is turned off. The voltage pull-up circuit 350 supplies the gate drive signal 140 to the gate built-in circuit 120 through the gate drive signal 140 at the non-display area of the lower substrate 1 〇2 through the pulled gate drive signal Vst and CLK1 to CLKi. The gray scale voltage generating ND 360 subdivides the first and second reference voltages VSP and VSN from the first power generating unit 32A to generate a plurality of ash voltages, and supplies the plurality of gradation voltages to the data conversion unit 380. If the source data signal contains N bits, the plurality of gray scale voltages generate 2N positive gray scale voltages and 2N negative gray scale voltages. (S) • 17 ^75211 According to the data from the control signal generating unit 340, the displacement clock DSC, the displacement register 381 sequentially shifts the data start signal DST to generate the displacement signal ss. The bit shift 381 can be a shift register having two directions, which are driven in the opposite direction according to the pilot signal from the signal control unit. The latch unit 383 responds to the displacement signal SS from the shift register 381, sequentially stores the data red, green and blue RGB from the total number of lines of the signal control unit 330, and outputs the signal according to the data from the control signal generating unit 340. The DOE supplies the latch data RData of the total number of lines to the digit/analog conversion unit 385. By using a plurality of positive gray scale voltages from the gray scale voltage generating unit 36A and negative gray scale voltages, the digital chirp analog conversion unit 385 converts the supplied data from the memory unit 383 to the positive and negative polarities. Video signal PVS and NVS. The digit/analog conversion unit 385 selects one gray scale voltage corresponding to the gray scale value of the flash data RData from the plurality of positive gray scale voltages as the positive polarity Φ video signal, and selects and latches from the plurality of negative gray scale voltages. A gray scale voltage corresponding to the gray scale value of the stored data RData is used as a negative polarity video signal. Using the first and second driving voltages Vdd and Vss from the first power generating unit 320 through the passive elements of the flexible printed circuit 200, the buffer unit commits? Slow. Positive and negative video signals PVS and NVS. For example, considering the load on the data line DL, the buffer unit 387 amplifies the positive polarity and negative polarity video signals PVS and NVS. According to the data polarity signal DPS from the control signal generation unit 340, the (S) 18 unit .389 is selected to select the positive polarity or negative polarity video signal PVS or NVS supplied from the buffer unit 387, and through the first to the first ( m+1)th|Output channel supplies selected video signal to data line £> B. For example, according to the data polarity signal DpS, the polarity of the video signal output from the selection unit 3 is inverted in the output channel unit and the frame unit. Referring to Fig. 1, the gate and built-in circuit w are formed in the non-display area of the lower substrate 1〇2, and a thin film transistor 112 is formed at the same time, and the gate built-in circuits (10) are each connected to a plurality of strips GL. The Misaki circuit 12Q generates a idle turn-on voltage V0n' in each of the lions in response to the pull-up inter-pole drive signals Vsm and CLK1 to CLK1 supplied from the driver integrated circuit 13A, and sequentially supplies the pole-on voltage VGn to the question pole. The line L is, for example, a plurality of closed-pole driving signals 14υ formed by the non-display area of the lower substrate 1〇2, and the driving integrated circuit 13() supplies the pull-up gate driving signals Vst and CLK1 to CLKi to the closed state. Extremely built-in circuit 12〇. Fig. 4 is a schematic view showing the driving waveform of the liquid crystal display device of the first embodiment of the invention. The reference numerals "Fig. 4" and "Fig. 1" describe the driving of a representative liquid crystal display device of the first embodiment of the present invention. For example, the first horizontal period is: the knife is the first to the third sub-jud, and the red, green, and blue video signals are sequentially displayed in the sub-over, to mix the red, green, and blue videos to collectively display a color. Continued. At the first-sub-period of the first-level period, the first to fourth (fourth) data lines DU to DLm are synchronously turned on to the first closed-circuit line, and the red video of the positive polarity 19 1375211 is called R+ To the odd number (four) line DL_Qdd, and the negative video signal R- is supplied to the even number data, line DL_even. Therefore, the first horizontal line of the alizarin lattice 11G towel 'odd number of the prime crystal lattice 11G shows a red video corresponding to the positive red video signal R+, and the even number of the prime crystal lattice 11〇 corresponds to the negative polarity red The red video of the video signal R-. The second sub-period of the first-level period synchronously supplies the gate-on voltage v〇n of the second to (fourth) data lines DL2 to DLm+1 to the second gate line Gu, and the positive green view+ The red video weaving lines DL_〇dd, the green video of the 贞 polarity G_ is given to the red ufmDL-even. In this case, the second horizontal line of the pixel lattice 11G 'odd number of the elementary lattice nG displays a green video corresponding to the negative polarity green video signal G_, and the even-numbered elementary lattice nG displays a green video corresponding to the positive green video shouting +. Therefore, the first horizontal line adjacent in the vertical direction The video signals displayed by the pixel cells contain different polarities from each other. The third sub-period of the first horizontal period synchronously supplies the gate turn-on voltages v〇n of the first to (m)th data lines DL1 to DLm to The third gate line GL3, the positive polarity blue video signal B+ is supplied to the odd number data line DL_〇dd, and the negative polarity blue video signal B· is supplied to the even number data line DL-even. Therefore, the third horizontal line In the elementary lattice 110, the odd-numbered pixel lattice 11() is displayed with a positive blue The monitor color video corresponding to the signal B+, the even-numbered prime crystal lattice 11〇 displays the blue video corresponding to the negative blue pixel signal B-. Therefore, the second and the 20th to the 1313011 three horizontal lines adjacent in the vertical direction The video displayed by the elementary crystal lattice 0 110 still contains different results from each other's first-level cycle _, red, green money blue video sequentially: sub-red, green and blue video 'together _ A color video is shown. The radiant crystal lattice of each level is displayed in the same manner as the above first horizontal period. Then, the polarity of the video signal is reversed as described above. Therefore, because the thin film transistors 112 on the respective pixel cells 110 are alternately arranged on the opposite side of the data line dl, the video is supplied from the driving integrated circuit 13Q to the liquid crystal panel to include a video of the reverse type polarity pattern. The tank is shown in the polarity pattern of the dot reverse type. "5th drawing" is a schematic diagram of the liquid crystal display device of the second embodiment of the present invention. The "second 5th liquid crystal display device" as shown in "5th" And the first embodiment Similarly, except for the arrangement of the individual crystal lattices 110. Therefore, the following explanation of the second embodiment will focus on the arrangement of the individual pixel lattices 110. As described above, the other liquid crystal display devices of the second embodiment The portion is similar to the first embodiment. As shown in Fig. 5, each of the two pixel lattices 110 arranged on the opposite side along the adjacent data line DL is alternately connected to one of the adjacent data lines DL. Each of the book crystal lattices 110 connected to the (4k-3) (k is an integer) th gate line GL4k_3 is directly connected to the adjacent data line on the left side; Each of the pixel cells 110 of GL4k-2 is directly connected to the adjacent data line on the left side. In another aspect of 21 1375211, each of the unitary crystal lattices 110 connected to the (4k-1)th gate line GL4k-1 is directly connected to the (four) line connected to the right meter; and connected to the (4k)th _ pole line. Each of the pixel cells 110 of the GL4k is directly connected to the adjacent data line on the right side of the 衿. The video signal output from the integrated circuit 130 is supplied to the data line connected to each of the pixel cells. At this time, the polarity of the video signal is reversed to the data line unit and at least one of the frame units. Therefore, since each of the two thin film transistors 112 of each of the pixel lattices 11A is alternately arranged on the opposite side thereof along the tributary line DL, the video signal including the line reverse type polarity pattern is driven from the integrated circuit 13 The crucible is supplied to the liquid crystal panel 11A, and is displayed as a vertical two-point reverse type polar pattern. At this time, the polarity of the video signal is reversed to each of the two pixel cell units and the data line unit through the two-point reverse type polarity pattern. According to the second embodiment of the present invention, the video signal supplied from the driving integrated circuit 13 is displayed on the liquid crystal panel 1 垂直 in a vertical two-point reverse type to improve the image by preventing dot-flicker defects from occurring. quality. Moreover, in accordance with the second embodiment of the present invention, the polarity of the video signal supplied from the driver integrated circuit 130 is reversed by at least one block unit command to increase the charging time of each of the pixel cells 110 and prevent the delay of the video signal. As described above, in the liquid crystal display device of the embodiment of the invention, the unit cell lattice constituting the pixel lattice including the horizontal strip structure is arranged in the vertical direction, thereby reducing the number of data lines. Therefore, the liquid crystal display device of the embodiment of the present invention can be used for a liquid crystal display device of a large size and a liquid crystal display device of a small size. 22 1375211 As described above, in the liquid crystal display device of the embodiment of the present invention, each of the two or two thin film transistors 112 on each pixel lattice ιι is alternately arranged on the opposite side along the data line. Not limited to the above explanation. For example, each of the three thin film transistors 12 for each of the individual crystal lattices may be alternately connected to one of the adjacent data lines 01^ along the line of the opposite (four) lines. Therefore, the liquid crystal display device of the embodiment of the invention has the following advantages. First, a driver integrated circuit is embedded in the liquid crystal panel, and the driving of the liquid crystal panel reduces the unit cost and minimizes the thickness of the liquid crystal display device. Second, the polarity of the video signal in the data line unit and the frame unit is reversed to allow for reduced power consumption. Third, the minimization of the polarity change of the video signal provides sufficient video signal charging time period and improves image quality. The arrangement of the fourth 'alliant crystal lattices in the horizontal direction allows for a reduction in the number of third data lines, from the large-size riding-size panel and the small-sized liquid crystal display panel. Fifth, a video signal including a line reverse type polarity pattern is displayed in a vertical two-point reverse type to improve image quality by preventing defects such as flash points. Sixth, the polarity of the video signal supplied from the driving integrated circuit is reversed to the charging time of at least one of the frame units and the delay of the video signal, thereby improving the image quality. Further, the liquid crystal display device of the embodiment of the present invention is driven in the column inversion scheme to invert the pixel electrodes therein by dots. For example, according to the arrangement of the pixel lattices of the embodiment of the present invention, the liquid crystal display device is driven in a column inversion scheme to obtain the effect of a reverse driving scheme. Or according to the column of the pixel array (S) 23 ^ 75511 of the other embodiment of the present invention, the liquid crystal display device is driven by the column inversion scheme to obtain the effect of the two-point reverse driving scheme. In addition, there is only one driving product. The driving of the liquid crystal panel of the bulk circuit reduces the size of the pull 11 printed circuit and reduces the single cost of the flexible printed circuit. In addition, the gate driver for driving the gate line embedded in the liquid crystal panel eliminates the use of the driver integrated circuit, the gate flexible printed circuit, and the gate printed circuit board. and,
僅僅具有液晶顯示面板製造製程、驅動積體電路裝設製程以及撓 卜生印刷電路接合製程之液晶顯示裝置之製造使用了簡化的製造製 程，從而最小化缺陷比率。 雖然本發明以前述之實施例揭露如上，然其並_以限定本 發月在不脫離本發明之精神和範圍内，戶斤為之更動與潤飾，均 =本發明之翻保護範圍之内。關於本發明所界定之保護範 >照所附之申請專利範圍。 【圖式簡單說明】 第1圖所示為本發明第—實施例之液晶顯稀置之示意圖； 第2圖所示為苐！圖所示之驅動積體電路之方城圖. 之示^_示為第2圖所示之訊號控制單元所分類之資料訊號 為本發明第一實施例之液晶顯示裝置之驅動波形 圔， 第5圖所示為本發日縣二實施例之液晶顯示裝置之示意 24 (S ) 1375211 【主要元件符號說明】 100 102 104 110 112 114 120 130 140 200 210 220 230 310 320 321a、321b、321c 322 324 326 液晶面板 下基板 上基板 畫素晶格 薄膜電晶體 晝素電極 閘極内建電路. 驅動積體電路 閘極驅動訊號傳輸線 撓性印刷電路 電阻 電容器 電感 訊號延遲單元 第一電源產生單元 電源訊號線 時脈產生單元 參考電壓設定單元 第二電源產生單元 共同電壓產生單元 < S ). 25 328 1375211The manufacture of a liquid crystal display device having only a liquid crystal display panel manufacturing process, a driving integrated circuit mounting process, and a flexographic printed circuit bonding process uses a simplified manufacturing process to minimize the defect ratio. While the invention has been described above in the foregoing embodiments, it is intended that the present invention may be modified and modified within the spirit and scope of the present invention. Regarding the protection scope defined by the present invention > BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the liquid crystal display of the first embodiment of the present invention; The block diagram of the driving integrated circuit shown in the figure is shown as the driving signal of the liquid crystal display device according to the first embodiment of the present invention. 5 is a schematic view of a liquid crystal display device according to a second embodiment of the Japanese-Japanese county. 24 (S) 1375211 [Description of main components] 100 102 104 110 112 114 120 130 140 200 210 220 230 310 320 321a, 321b, 321c 322 324 326 LCD substrate lower substrate substrate pixel lattice film transistor halogen electrode gate built-in circuit. Drive integrated circuit gate drive signal transmission line flexible printed circuit resistance capacitor inductance signal delay unit first power generation unit power signal Line clock generation unit reference voltage setting unit second power generation unit common voltage generation unit < S ). 25 328 1375211
330 訊號控制單元 340 控制訊號產生單元 350 電壓拉升單元 360 灰階電壓產生單元 380 資料轉換單元 381 位移暫存器. 383 閂存單元 385 數位/類比轉換單元 387 緩衝器單元 389 選擇單元 DL 資料線 GL 閘極線 DE、 DCLK、Hsync、Vsync 同步訊號 Vin 輸入功率 Data 來源資料訊號 DST 、DSC、DOE、DPS 資料控制訊號 RVst ' RCLK1.....RCLKi 閘極驅動訊號 Vst、 CLK1.....CLKi 拉升的閘極驅動訊號 Von 閘極開啟電壓 Voff 閘極關閉電壓 RData 問存資料 26 1375211330 signal control unit 340 control signal generating unit 350 voltage pull-up unit 360 gray-scale voltage generating unit 380 data conversion unit 381 shift register. 383 latch unit 385 digital/analog conversion unit 387 buffer unit 389 selection unit DL data line GL gate line DE, DCLK, Hsync, Vsync sync signal Vin input power Data source data signal DST, DSC, DOE, DPS data control signal RVst ' RCLK1.....RCLKi gate drive signal Vst, CLK1.... .CLKi Pulled gate drive signal Von Gate turn-on voltage Voff Gate turn-off voltage RData Question data 26 1375211
PVS、NVS ss 視頻訊號 位移訊號PVS, NVS ss video signal displacement signal
(s ) 27(s) 27