1364553 100年.11月30日按正替換k 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種電潤濕顯示器（E1 ectro-wett ing Display)。 【先前技術】 [0002] 目前，諸多光電技術正在快速的發展且應用於下一代平 板顯示器，如投影顯示器（Projection Display)、可 撓式顯示器（Flexible Display)等。在此環境下，一 種基於電濕潤原理之電潤濕顯示器由於其響應速度快、 視角廣、耗電量小、輕薄便攜等優點受到廣泛的關注。 [0003] 請參閱圖1，係一種先前技術電潤濕顯示器之局部截面示 意圖。該電潤濕顯示器10包括相對設置之一第一基板11 、一第二基板18，設置於該第一基板11與該第二基板18 間之一矩陣電路層12、一疏水性絕緣層13、複數親油性 之隔絕牆14、第一流體15及第二流體16。 [0004] 該矩陣電路層12設置於該第二基板18表面。該疏水性絕 緣層13設置於該矩陣電路層12表面，其材質為疏水性之 透明非晶態含氟聚合物，如AF1 600。該複數隔絕牆14呈 格狀設置於該疏水性絕緣層13上，且藉由相鄰之隔絕牆 14所界定之最小單元定義為一像素區域R，通常該像素區 域R為一矩形區域，其包括相互平行且相對設置之二短邊 及與該二短邊垂直相交之二長邊。該第一流體15對應該 像素區域R填充於該疏水性絕緣層13表面上，其材質通常 為不透明彩油或類似十六烷之烷烴。該第二流體16設置 於該第一流體15與該第一基板11之間，其係與該第一流 096138162 表單编號A0101 第4頁/共33頁 1003444042-0 1364553 100年.11月.30日核正 體15互不相溶之透明導電液體，可為水或者鹽溶液，如 水與乙醇混合物中之氣化鉀（KC1)溶液。 [0005] 請參閱圖2，係該電潤濕顯示器10之矩陣電路層12對應一 像素區域R之俯視示意圖。該矩陣電路層12包括複數平行 . 排列之掃描線121、複數與該掃描線121垂直絕緣相交之 資料線122、複數公共線123。該資料線122與該掃描線 121對應該複數隔絕牆14設置，則由相鄰資料線122與掃 描線121界定之最小區域與該像素區域R相對應。每一最 小區域對應設置有一薄膜電晶體124及一像素電極125， 該薄膜電晶體124設置於該掃描線121與該資料線122相 交處，即設置於一短邊與一長邊相交處，其包括一閘極 140、一源極150及一汲極160，該閘極140與該掃描線 121相連，該源極150與該資料線122相連，該汲極160與 該像素電極125相連。該像素電極125設置於除該薄膜電 晶體124之最小區域内，其近似呈一L形。單一公共線123 沿與該掃描線121平行之方向貫穿該最小區域，且鄰近相 鄰之像素區域R之掃描線121設置，為避免在製程中公共 線123與相鄰像素區域R之掃描線121間發生短路現象，該 公共線1 21距該掃描線1 21之距離通常需保持在1 0〜2 0以m 左右。同時，該公共線123沿該薄膜電晶體124所在一側 延伸出一公共電極墊127,該公共電極墊127、該像素電 極125與夾於其間之絕緣層（圖未示）構成一儲存電容126 〇 [0006] 當加載開啟電壓經由該掃描線1 21使該薄膜電晶體1 24之 閘極140開啟，進而使資料電壓依次經由該資料線122及 096138162 表單編號A0101 第5頁/共33頁 1003444042-0 1364553 100年.11月.30日核正替换π 該源極150、該汲極1 60傳送至該像素電極125，同時， 持續傳送一公共電壓經由該公共線123至該第二流體16。 當該像素電極125與該第二流體16所加載之電壓小於某一 臨界電壓時，該第一流體15平坦覆蓋該像素區域R内之疏 水性絕緣層13，該第二流體16與該第一流體15層疊設置 ，阻隔入射光通過，即使該像素區域R處於暗態。反之， 當該像素電極125與該第二流體16產生電壓差大於該臨界 電壓時，該第一流體15被該第二流體16擠壓往該薄膜電 晶體124對應角落處移動，進而使該第二流體16與該疏水 性絕緣層13增大接觸面積，當電壓差逐漸增大時，該像 素區域R顯示不同之灰階。在理想狀態下，當電壓差加至 一標準最大時，第一流體15應全部匯集至該薄膜電晶體 124對應之角落處，使入射光經由該第二流體16出射，進 而使該像素區域R處於亮態。 [0007] 請一併參閱圖3，係圖2所示矩陣電路層12對應一像素區 域R之分佈示意圖。該像素區域R包括一薄膜電晶體區R1 、一儲存電容區R2及一像素電極區R3。該薄膜電晶體區 R1為該薄膜電晶體124所占區域。該儲存電容區R2為該儲 存電容126及該公共線123所占區域。該像素電極區R3呈 一L形塊狀區域，其用於設置該像素電極125，並具有一 與該薄膜電晶體區R1並行設置之區域X。對於電潤濕顯示 器10而言，當電壓差加至最大時，除了本身不透光之薄 膜電晶體區R1與儲存電容區R2以外，由於一像素區域R内 對應該區域X之第一流體15與親油性的隔絕牆14間吸引力 較其他區域強，其會殘留於區域X對應處，則入射光被區 096138162 表單编號Α0101 第6頁/共33頁 1003444042-0 1364553 100年.11月_ 30日梭正替換頁 « 域X之第一流體15所吸收，使該像素區域R之區域X亦不透 光。再者，受薄膜電晶體區R1周邊區域Y之電場較弱的影 響，亦使得第一流體15無法完全集中在薄膜電晶體R1所 在處，仍有部份第一流體15殘留於薄膜電晶體R1之周邊 區域Y處，亦使得周邊區域Y對應處呈現不透光狀態。因 此，該電潤濕顯示器10在薄膜電晶體區R1與儲存電容區 R2、區域X以及薄膜電晶體區R1之周邊區域Y均不透光， 其像素區域R之開口率（Aperture Ratio)不超過60%。 另外，若要使殘留於區域X以及薄膜電晶體區R1周邊區域 Y之第一流體15全部移動至薄膜電晶體區R1，則需施加更 大的電壓，亦造成額外的功率浪費。 【發明内容】 [0008] [0009] 有鑑於此，提供一種具有較大開口率且不造成功率浪費 之電潤濕顯示器實為必要。 一種電潤濕顯示器，其包括一第一基板、一第二基板、 複數隔絕牆、非導電之第一流體及導電之第二流體。該 第二基板與該第一基板相對設置。該複數隔絕牆呈格狀· 設置於該第二基板上，進而界定複數像素區域。該第一 流體填充於相鄰隔絕牆間之像素區域内。該第二流體填 充於該第一流體與該第一基板之間，其與該第一流體互 不相溶。每一像素區域包括二相對之短邊、與二短邊相 交之二長邊、一儲存電容及至少一薄膜電晶體。該儲存 電容與該至少一薄膜電晶體均鄰近相應像素區域之同一 短邊設置。 一種電潤濕顯示器，其包括一第一基板、一第二基板、 096138162 表單编號A0101 第7頁/共33頁. 1003444042-0 [0010] 1364553 100年.11.月_ 30日核正替換k 複數隔絕牆、非導電之第一流體及導電之第二流體。該 第二基板與該第一基板相對設置。該複數隔絕牆呈格狀 設置於該第二基板上，進而界定複數像素區域，每一像 素區域包括二相對平行設置之第一短邊與第二短邊、與 二短邊相交之二長邊、一公共線、一儲存電容及至少一 薄膜電晶體。該公共線平行二短邊且設置於第一短邊與 第二短邊之間，且其距該第一短邊之距離介於二短邊相 距長度之0. 2倍至0. 5倍之間。該至少一薄膜電晶體與該 儲存電容設置於由該公共線、該第一短邊以及二長邊共 同定義之區域内。 [0011] 相較於先前技術，由於該電潤濕顯示器之至少一薄膜電 晶體與該儲存電容均設置於該像素區域之同一側，使得 在電壓差達到最大標準值時，該第一流體（圖未示）僅集 中於本身不透光之薄膜電晶體與儲存電容所在區域内， 進而使得穿透區面積增太，增加了該電潤濕顯示器之開 口率。 【實施方式】 [0012] 請參閱圖4，係本發明電潤濕顯示器第一實施方式之局部 截面示意圖。該電潤濕顯示器30包括相對設置之一第一 基板31、一第二基板38、設置於該第一基板31與該第二 •基板38間之一矩陣電路層32、一疏水性絕緣層33、複數 隔絕牆34、第一流體35及第二流體36。 [0013] 該矩陣電路層32設置於該第二基板38表面。該疏水性絕 緣層33設置於該矩陣電路層32表面，其材質為疏水性之 透明非晶態含氟聚合物，如AF1 600。該複數隔絕牆34呈 096138162 表單编號 A0101 第 8 頁/共 33 頁 1003444042-0 1364553 I ' 100年.11月30日修正替¥頁 格狀設置於該疏水性絕緣層33上，且藉由相鄰之隔絕牆 34所界定之最小單元定義為一像素區域P。該像素區域P 為一矩形區域，其包括相互平行且相對設置之第一短邊 與第二短邊以及與該二短邊垂直相交之二長邊。該第一 流體35對應該像素區域P填充於該疏水性絕緣層33表面上 .，其材質通常為不透明彩油或類似十六烷之烷烴。該第 二流體36設置於該第一流體35與該第一基板31之間，其 係與該第一流體35互不相溶之透明導電液體，可為水或 者鹽溶液，如水與乙醇混合物中之氯化钟（KC1)溶液。 [0014] 請參閱圖5，係該電潤濕顯示器30之矩陣電路層32對應一 像素區域P之俯視結構示意圖。該矩陣電路層32包括複數 相互平行之掃描線311、複數與該掃描線311垂直絕緣相 交之資料線312以及複數公共線313。該資料線312與該 掃描線311對應該複數隔絕牆34設置，其界定之最小矩形 區域與該像素區域P相對應。每一公共線313與二相鄰掃 描線311相互平行且貫穿該最小矩形區域，其設置於距該 第一短邊之距離為二短邊相距長度之三分之一處，其中 ，該公共線313沿朝向該第一短邊方向垂直延伸出一公共 電極墊314，且該公共電極墊314之延伸長度為該二短邊 相距長度之0.卜0. 25倍。該最小矩形區域包括一第一薄 膜電晶體315、一第二薄膜電晶體316以及一像素電極 317。該像素電極317連續分佈於該最小矩形區域内，並 對應由該公共線313、該第一短邊以及二長邊共同界定之 非穿透區域P1處具有一缺口318。該第一薄膜電晶體315 、該第二薄膜電晶體316以及該公共電極墊314對應該缺 096138162 表單編號A0101 第9頁/共.33頁 1003444042-0 1364553 100年11月.30日梭正替換頁 口 318設置。 [0015] 請一併參閱圖6及圖7，圖6係圖5沿VI-VI方向之剖面放 大示意圖’圖7係圖5沿VII-VII方向之剖面放大示意圖 。該第一薄膜電晶體315包括一第一閘極320、一第一源 極321、一第一汲極323 ' —第一絕緣層324以及一第一 半導體層325。該第二薄膜電晶體316包括一第二閘極 330、一第二源極331、一第二汲極333以及一第二半導 體層335。該第一閘極320、該第二閘極330以及該公共 電極墊314並行設置於該第二基板38上，且該第一閘極 320與該第二閘極330分別與該掃描線311相連。該第一 絕緣層324覆蓋該第一閘極320，並延伸覆蓋具有該第二 閘極330以及該公共電極墊314之第二基板38表面。該第 一半導體層325對應該第一閘極320設置於該第一絕緣層 324上。該第二半導體層335對應該第二閘極330設置於 该第一絕緣層324上。該第一源極321與該第一汲極323 相對設置，且與該第一半導體層325部份交疊，該第一源 極321亦與該貧料線312相連。該第二源極331係由該第 一汲極323延伸形成，其與該第二汲極333亦相對設置， 且與該第二半導體層335部份交疊。該第二沒極挪沿朝 向該公共電極㈣4所在處延伸一沒極塾咖，且該汲極 塾334與該公共電極塾314相重疊，並與該公共線313部 份重疊。該汲極塾334、該公共電極塾314以及夾於二者 間之第—絕緣層324構成1存電容挪。 [0016] 該最小矩㈣域縣之轉料層32進-步包括一第二 絕緣層340及一連接孔350。哕笛 °亥第二絕緣層340覆蓋該第 096138162 表單编號A0101 第10頁/共33頁 1003444042-0 1.364553 [ΪΟΟ年.11月3(3日梭正_頁 一薄膜電晶體315、該第二薄膜電晶體316、該儲存電容 336以及該汲極墊334。該連接孔35〇設置於該像素電極 317與i玄；及極塾334交疊處，進而使該像素電極Μ?經由 該連接孔350與該汲極墊334連接至該第二汲極333。 [0017] 當加載開啟電壓經由該掃描線311使該第一閘極32〇、該 第二閘極330開啟，進而使資料電壓依次經由該資料線 312、該第一源極321、該第一汲極323、該第二源極331 、5玄第一没極333、該汲極堅334及該連接孔350傳送至 該像素電極317，同時，持續傳送一公共電壓至該第二流 體36。當該像素電極317所加載電壓與該第二流體36所加 載電壓之電壓差小於某一臨界電壓時，該第一流體35平 坦覆蓋該像素區域p内之疏水性絕緣層3 3上，該第二流體 36與該第一流體35層疊設置，阻隔入射光通過，即使該 像素區域P處於暗態《反之，當該像素電極317與該第二 流體36產生電壓差大於該臨界電壓時，該第一流體35被 該第二流體36擠壓往二薄膜電晶體315、31 6對應處移動 ，進而使該第二流體36與該疏水性絕緣層33增大接觸面 積，當電壓差逐漸增大時，該像素區域p將顯示不同之灰 階。 [0018] 請一併參閱圖8 ,係該電潤濕顯示器30之一像素區域p之 分佈示意圖。該像素區域P包括一非穿透區域？1及一穿透 區域P2 ’該穿透區域P2與非穿透區域？1平行排列於該像 素區域P内。該非穿透區域P1包括—薄膜電晶體區pll及 一儲存電容區P12 ^該薄膜電晶體區pu為該第一薄膜電 晶體315與第二薄膜電晶體316對應區域。該儲存電容區 096138162 表單編號A0101 第11頁/共33頁 1003444042-0 [0019] P12為該儲存電容336與該公共線3i3對應^，且與^1^3 館存電容336對應設置之儲存電容區Π2部份與該薄膜電 :體區m相互平行排列。該穿㈣域p2對應設置有 素電極317。 心該電潤濕顯示器3G之儲存電容挪與該二薄膜電晶體 15、316設置於像素區财之巧―側，即使該儲存電容 336與該薄膜電晶體324設置於讀非穿透區朗内，從而 使在最大標準電壓下原本因殘流體35心法透光 之區域（如圖3所示X區域以及周邊區明被用於設置本身 不透光之儲存電容336，從而在無需增大驅動電壓的情況 下，使該電潤濕顯示器3 〇獲得了較大的開口率。 另外，由於儲存電容336係⑽極墊334、公共電極塾 =及^於制之第—絕緣層_成，而非由像素電極 _ "共電極塾314及夾於期間之第-絕緣層324與第 、邑緣層340構成，該儲存電容咖之兩電極間之距 小，則在製得相同電容的前提下，可適當減小該公共電. 签314與該沒極整334間之重疊面積，也就是說，可減 儲存電今336之橫戴面積，進一步增大該電潤濕 盗30之開口率。 096138162 [0020] [0021] :併參閱圖9、圖10及圖11，圖9係本發明電潤濕顯示 胃第—實施方式之_像素區域對應之矩陣電路層之俯視 丁思圖’圖1G係、該電潤濕顯示器之另-俯視示意圖，圖 U係圖1G沿.XI-XI之剖視放大示意圖。該㈣濕顯示器 與第—實施方式之電潤竭顯示器3G之結構類似，其區別 在於.每-像素區域“公共線413與相鄰二掃描線4ιι相 表單編號A0101 a _y 共 33 頁 1003444042-0 1364553 • · 100年.11月· 30日按正替換頁 互平行，其設置於距構成該像素區域N之第一短邊之距離 為二短邊相距距離之三分之一處，且該公共線413沿朝向 該第一短邊方向垂直延伸出一公共電極墊414，該公共電 極墊414之延伸寬度為該長邊長度之0.卜0. 25倍。該像 素電極417以等寬度連續分佈於該像素區域N内，且於由 該公共線413、該第一短邊以及該二長邊共同界定之非穿 透區域N1内具有一缺口 418。該第一薄膜電晶體415、第 二薄膜電晶體41 6設置於該缺口41 8内。該第一薄膜電晶 體41 5之第一閘極與該第二薄膜電晶體41 6之第二閘極共 用同一閘極墊420，且該閘極墊420係自該掃描線411向 該像素區域N内部延伸而出之近似矩形結構，其長度L1為 構成該像素區域N之短邊長度之0. 7〜0. 98倍，寬度W1為 構成該像素區域N之長邊長度之0. 12倍。一第一絕緣層 424覆蓋該閘極墊420、該公共電極墊414及該第二基板 48表面。該第一薄膜電晶體415之第一半導體層425該第 二薄膜電晶體416之第二半導體層435間隔設置於該閘極 墊420對應之第一絕緣層424上。該第一薄膜電晶體415 之第一源極421與該第一汲極423藉由該第一半導體層 425相連，且該第一源極421與該資料線412相連。該第 二薄膜電晶體416之第二源極431與該第一汲極423相連 ，該第二汲極433沿朝向該公共電極墊414 一側延伸出一 與該公共電極墊414相重疊之汲極墊434。該汲極墊434 之長度與該閘極墊420之長度L1大致相同，且由於製程控 制較易，該汲極墊434或該公共電極墊414距該閘極墊 4 2 0之間隙D小於當將公共線設置於該二薄膜電晶體相對 一側（如圖2所示）時，公共線與相鄰像素區域之掃描線間 096138162 表單編號A0101 第13頁/共33頁 1003444042-0 1364553 100年.11月.30日修正巷掩★ 的距離，在本實施方式中該間隙D介於3-lOym之間，用 以避免串擾（Cr〇sstalk)現象的發生。同時，該汲極墊 434、該公共電極墊414與夾於其間之第一絕緣層424共 同構成一儲存電容43Θ。該汲極墊434與該像素電極417 重疊處具有一連接孔450，進而使該第二汲極433依次經 由該汲極墊434及該連接孔450連接至該像素電極417。 [0022] 該電潤濕顯示器40之二薄膜電晶體415、41 6與該儲存電 容436均設置於該像素區域N之同一側，使其利用原本不 透光之薄膜電晶體之周邊區域（如圖3所示γ區域）處設置 本身就不透光之儲存電容436，使得在電壓差達到最大標 準值時，不透光之第一流體（圖未示）集中在本身不透光 之薄膜電晶體415、416與存觸電容436處，進而增大穿 透區面積，增加了該電潤濕顯示器4〇之開口率。另外， 由於間隙D小於當將公共線設置於該二薄膜電晶體相對一 側（如圖2所示）時公共線與相鄰像素區域之掃描線間的距 離’使得儲存電容436與二薄膜電晶體415、416所形成 之不透光區域面積小於將公共線設置於二薄膜電晶體兩 側時所形成的不透光區域之面積，進一步增大了開口率 。再者，由於儲存電容436亦由汲極墊434、公共電極塾 414及夾於其間之第一絕緣層424構成，該儲存電容436 之兩電極間之距離較小，可適當減小該儲存電容436之橫 截面積，進一步增大該電潤濕顯示器4〇之開口率。 請參閱圖12 ’係本發明電潤濕顯示器第三實施方式之矩 陣電路層對應· 一像景區域之俯視結構圖。該電〉間、、晏顯示 器與第二實施方式之電潤濕顯示器之結構類似，其區別 096138162 表單编號Α0101 第14頁/共33頁 1003444042-0 [0023] 13645531364553 100. November 30th, according to the positive replacement k. VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to an electrowetting display (E1 ectro-wetting display). [Prior Art] [0002] At present, many optoelectronic technologies are rapidly developing and applied to next-generation flat panel displays such as Projection Display, Flexible Display, and the like. In this environment, an electrowetting display based on the electrowetting principle has received extensive attention due to its fast response, wide viewing angle, low power consumption, light weight and portability. [0003] Referring to Figure 1, a partial cross-sectional view of a prior art electrowetting display is shown. The electrowetting display 10 includes a first substrate 11 and a second substrate 18 disposed opposite to each other, a matrix circuit layer 12 disposed between the first substrate 11 and the second substrate 18, and a hydrophobic insulating layer 13. The plurality of lipophilic barrier walls 14, the first fluid 15 and the second fluid 16. The matrix circuit layer 12 is disposed on the surface of the second substrate 18. The hydrophobic insulating layer 13 is disposed on the surface of the matrix circuit layer 12 and is made of a hydrophobic transparent amorphous fluoropolymer such as AF1 600. The plurality of insulating walls 14 are disposed on the hydrophobic insulating layer 13 in a grid shape, and the smallest unit defined by the adjacent insulating walls 14 is defined as a pixel region R. Generally, the pixel region R is a rectangular region. The utility model comprises two short sides which are parallel and oppositely arranged, and two long sides which intersect perpendicularly with the two short sides. The first fluid 15 is filled on the surface of the hydrophobic insulating layer 13 corresponding to the pixel region R, and is usually made of an opaque color oil or a cetane-like alkane. The second fluid 16 is disposed between the first fluid 15 and the first substrate 11, and is coupled to the first stream 096138162. Form No. A0101 Page 4 / Total 33 Page 1003444042-0 1364553 100. November. The transparent conductive liquid in which the core body 15 is incompatible with each other may be water or a salt solution, such as a potassium carbonate (KC1) solution in a mixture of water and ethanol. Referring to FIG. 2, a schematic top view of a matrix circuit layer 12 of the electrowetting display 10 corresponding to a pixel region R is shown. The matrix circuit layer 12 includes a plurality of parallel scan lines 121, a plurality of data lines 122 perpendicularly insulated from the scan lines 121, and a plurality of common lines 123. The data line 122 and the scan line 121 are disposed corresponding to the plurality of isolation walls 14, and the minimum area defined by the adjacent data lines 122 and the scan lines 121 corresponds to the pixel area R. A thin film transistor 124 and a pixel electrode 125 are disposed in each of the minimum regions. The thin film transistor 124 is disposed at the intersection of the scan line 121 and the data line 122, that is, at a intersection of a short side and a long side. A gate 140, a source 150 and a drain 160 are connected. The gate 140 is connected to the scan line 121. The source 150 is connected to the data line 122. The drain 160 is connected to the pixel electrode 125. The pixel electrode 125 is disposed in a minimum area of the thin film transistor 124, which is approximately in an L shape. A single common line 123 is disposed through the minimum area in a direction parallel to the scan line 121, and is disposed adjacent to the scan line 121 of the adjacent pixel area R. To avoid the scan line 121 of the common line 123 and the adjacent pixel area R in the process. A short circuit occurs, and the distance of the common line 1 21 from the scan line 1 21 is usually kept at about 10 to 2 0 m. At the same time, the common line 123 extends along a side of the thin film transistor 124 to form a common electrode pad 127. The common electrode pad 127, the pixel electrode 125 and an insulating layer (not shown) sandwiched therebetween form a storage capacitor 126. 0006 [0006] When the load-on voltage is turned on, the gate 140 of the thin film transistor 14 is turned on, and the data voltage is sequentially passed through the data line 122 and 096138162. Form No. A0101 Page 5 / Total 33 Page 1003444042 -0 1364553 100. November. 30. The core is replacing π. The source 150, the drain 1 60 is transferred to the pixel electrode 125, while continuously transmitting a common voltage via the common line 123 to the second fluid 16 . When the voltage applied by the pixel electrode 125 and the second fluid 16 is less than a certain threshold voltage, the first fluid 15 flatly covers the hydrophobic insulating layer 13 in the pixel region R, and the second fluid 16 and the first The fluids 15 are stacked to block the passage of incident light even if the pixel region R is in a dark state. On the other hand, when the voltage difference between the pixel electrode 125 and the second fluid 16 is greater than the threshold voltage, the first fluid 15 is pressed by the second fluid 16 to move to a corresponding corner of the thin film transistor 124, thereby making the first The two fluids 16 and the hydrophobic insulating layer 13 increase the contact area, and when the voltage difference is gradually increased, the pixel region R exhibits different gray levels. In an ideal state, when the voltage difference is added to a standard maximum, the first fluid 15 should all be collected to the corresponding corner of the thin film transistor 124, and the incident light is emitted through the second fluid 16, thereby making the pixel region R It is in a bright state. Referring to FIG. 3 together, FIG. 2 is a schematic diagram showing the distribution of a matrix circuit layer 12 corresponding to a pixel region R. The pixel region R includes a thin film transistor region R1, a storage capacitor region R2, and a pixel electrode region R3. The thin film transistor region R1 is the region occupied by the thin film transistor 124. The storage capacitor region R2 is the area occupied by the storage capacitor 126 and the common line 123. The pixel electrode region R3 has an L-shaped block region for arranging the pixel electrode 125 and has a region X disposed in parallel with the thin film transistor region R1. For the electrowetting display 10, when the voltage difference is maximized, except for the thin film transistor region R1 and the storage capacitor region R2 which are not permeable to light, the first fluid 15 corresponding to the region X in the one pixel region R is The attraction between the wall 14 and the lipophilic barrier wall is stronger than other areas, and it will remain in the corresponding area X. Then the incident light is zone 096138162. Form number Α0101 Page 6 of 33 1003444042-0 1364553 100 years. November _ 30-day shuttle replacement page « The first fluid 15 of the field X is absorbed so that the region X of the pixel region R is also opaque. Moreover, due to the weak electric field of the peripheral region Y of the thin film transistor region R1, the first fluid 15 cannot be completely concentrated at the position of the thin film transistor R1, and some of the first fluid 15 remains in the thin film transistor R1. The peripheral area Y also makes the corresponding area of the peripheral area Y opaque. Therefore, the electrowetting display 10 is opaque in the thin film transistor region R1 and the storage capacitor region R2, the region X, and the peripheral region Y of the thin film transistor region R1, and the aperture ratio of the pixel region R does not exceed 60%. Further, if all of the first fluid 15 remaining in the region X and the peripheral region Y of the thin film transistor region R1 is moved to the thin film transistor region R1, a larger voltage is applied, which also causes an extra power waste. SUMMARY OF THE INVENTION [0009] In view of the above, it is necessary to provide an electrowetting display having a large aperture ratio without causing power waste. An electrowetting display includes a first substrate, a second substrate, a plurality of insulating walls, a non-conductive first fluid, and a conductive second fluid. The second substrate is disposed opposite to the first substrate. The plurality of insulating walls are lattice-shaped and disposed on the second substrate to define a plurality of pixel regions. The first fluid is filled in a pixel region between adjacent insulating walls. The second fluid is filled between the first fluid and the first substrate and is incompatible with the first fluid. Each pixel region includes two opposite short sides, two long sides intersecting the two short sides, a storage capacitor, and at least one thin film transistor. The storage capacitor and the at least one thin film transistor are disposed adjacent to the same short side of the corresponding pixel region. An electrowetting display comprising a first substrate, a second substrate, 096138162, form number A0101, page 7 / total 33 pages. 1003444042-0 [0010] 1364553 100 years. 11. month _ 30th nuclear replacement k plural insulating wall, non-conductive first fluid and conductive second fluid. The second substrate is disposed opposite to the first substrate. The plurality of insulating walls are arranged on the second substrate in a grid shape, thereby defining a plurality of pixel regions, each pixel region comprising two first short sides and a second short side disposed opposite to each other, and two long sides intersecting the two short sides a common line, a storage capacitor and at least one thin film transistor.倍倍至0. 5倍之之。 The second time is 0. 2 times to 0. 5 times the distance between the first short side and the second short side. between. The at least one thin film transistor and the storage capacitor are disposed in a region defined by the common line, the first short side, and the two long sides. [0011] Compared with the prior art, since at least one thin film transistor of the electrowetting display and the storage capacitor are disposed on the same side of the pixel region, the first fluid is obtained when the voltage difference reaches a maximum standard value ( The figure is only concentrated in the area where the thin film transistor and the storage capacitor which are opaque, and the area of the penetration area is increased too much, which increases the aperture ratio of the electrowetting display. [Embodiment] [0012] Referring to Figure 4, there is shown a partial cross-sectional view of a first embodiment of an electrowetting display of the present invention. The electrowetting display 30 includes a first substrate 31, a second substrate 38, a matrix circuit layer 32 disposed between the first substrate 31 and the second substrate 38, and a hydrophobic insulating layer 33. The plurality of insulating walls 34, the first fluid 35 and the second fluid 36. [0013] The matrix circuit layer 32 is disposed on the surface of the second substrate 38. The hydrophobic insulating layer 33 is disposed on the surface of the matrix circuit layer 32 and is made of a hydrophobic transparent amorphous fluoropolymer such as AF1 600. The plurality of insulating walls 34 are 096138162 Form No. A0101 Page 8 of 33 1003444042-0 1364553 I '100 years. November 30th correction is placed on the hydrophobic insulating layer 33, and by The smallest unit defined by the adjacent insulating wall 34 is defined as a pixel area P. The pixel region P is a rectangular region including a first short side and a second short side which are parallel to each other and disposed opposite to each other, and two long sides perpendicularly intersecting the two short sides. The first fluid 35 is filled on the surface of the hydrophobic insulating layer 33 corresponding to the pixel region P, and is usually made of an opaque color oil or a cetane-like alkane. The second fluid 36 is disposed between the first fluid 35 and the first substrate 31, and is a transparent conductive liquid that is incompatible with the first fluid 35, and may be water or a salt solution, such as a mixture of water and ethanol. Chlorinated clock (KC1) solution. Referring to FIG. 5, a schematic diagram of a top view of a matrix circuit layer 32 of the electrowetting display 30 corresponding to a pixel region P is shown. The matrix circuit layer 32 includes a plurality of mutually parallel scan lines 311, a plurality of data lines 312 vertically insulated from the scan lines 311, and a plurality of common lines 313. The data line 312 and the scan line 311 are disposed corresponding to the plurality of insulating walls 34, and the defined minimum rectangular area corresponds to the pixel area P. Each of the common lines 313 and the two adjacent scan lines 311 are parallel to each other and extend through the minimum rectangular area, and the distance from the first short side is set to be one third of the length of the two short sides, wherein the common line倍倍。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. The minimum rectangular area includes a first thin film transistor 315, a second thin film transistor 316, and a pixel electrode 317. The pixel electrode 317 is continuously distributed in the minimum rectangular area, and has a notch 318 corresponding to the non-penetrating area P1 defined by the common line 313, the first short side and the two long sides. The first thin film transistor 315, the second thin film transistor 316, and the common electrode pad 314 are correspondingly missing 096138162 Form No. A0101 Page 9/Total.33 Page 1003444042-0 1364553 100 November 30. Page port 318 is set. 6 and FIG. 7, FIG. 6 is a schematic cross-sectional view of FIG. 5 along the line VI-VI. FIG. 7 is an enlarged cross-sectional view taken along line VII-VII of FIG. The first thin film transistor 315 includes a first gate 320, a first source 321, a first drain 323' - a first insulating layer 324 and a first semiconductor layer 325. The second thin film transistor 316 includes a second gate 330, a second source 331, a second drain 333, and a second semiconductor layer 335. The first gate 320, the second gate 330, and the common electrode pad 314 are disposed on the second substrate 38 in parallel, and the first gate 320 and the second gate 330 are respectively connected to the scan line 311. . The first insulating layer 324 covers the first gate 320 and extends over the surface of the second substrate 38 having the second gate 330 and the common electrode pad 314. The first semiconductor layer 325 is disposed on the first insulating layer 324 corresponding to the first gate 320. The second semiconductor layer 335 is disposed on the first insulating layer 324 corresponding to the second gate 330. The first source 321 is disposed opposite to the first drain 323 and partially overlaps the first semiconductor layer 325. The first source 321 is also connected to the lean line 312. The second source 331 is formed by extending the first drain 323, and is disposed opposite to the second drain 333 and partially overlaps the second semiconductor layer 335. The second infinitely extending edge extends toward the common electrode (4) 4, and the drain electrode 334 overlaps with the common electrode 314 and overlaps the common line 313. The drain 334, the common electrode 314, and the first insulating layer 324 sandwiched therebetween constitute a storage capacitor. [0016] The transfer layer 32 of the minimum moment (four) domain includes a second insulating layer 340 and a connection hole 350.哕笛°海Second insulation layer 340 covers the 096138162 Form No. A0101 Page 10/Total 33 Page 1003444042-0 1.364553 [Year of the Year. November 3 (3rd shuttle _ page 1 film transistor 315, the first a thin film transistor 316, the storage capacitor 336 and the drain pad 334. The connection hole 35 is disposed at the intersection of the pixel electrode 317 and the imaginary electrode 334, and the pixel electrode Μ is connected via the connection The hole 350 and the drain pad 334 are connected to the second drain 333. [0017] When the load-on voltage is applied, the first gate 32A and the second gate 330 are turned on via the scan line 311, thereby enabling the data voltage The data line 312, the first source 321 , the first drain 323 , the second source 331 , the fifth first pole 333 , the drain 334 and the connecting hole 350 are sequentially transmitted to the pixel. The electrode 317, at the same time, continuously transmits a common voltage to the second fluid 36. When the voltage difference between the voltage applied by the pixel electrode 317 and the voltage applied to the second fluid 36 is less than a certain threshold voltage, the first fluid 35 is flat. Covering the hydrophobic insulating layer 3 3 in the pixel region p, the second fluid 36 is The first fluids 35 are stacked to block incident light, even if the pixel region P is in a dark state. Conversely, when the voltage difference between the pixel electrode 317 and the second fluid 36 is greater than the threshold voltage, the first fluid 35 is The second fluid 36 is pressed to move correspondingly to the two thin film transistors 315 and 316, thereby increasing the contact area between the second fluid 36 and the hydrophobic insulating layer 33. When the voltage difference is gradually increased, the pixel region p A different gray scale will be displayed. [0018] Please refer to FIG. 8 together, which is a schematic diagram of the distribution of a pixel region p of the electrowetting display 30. The pixel region P includes a non-penetrating region 1 and a penetrating region. P2 'the penetration region P2 is arranged in parallel with the non-penetration region ?1 in the pixel region P. The non-penetration region P1 includes a thin film transistor region p11 and a storage capacitor region P12. The thin film transistor region pu is the A region corresponding to the first thin film transistor 315 and the second thin film transistor 316. The storage capacitor region 096138162 Form No. A0101 Page 11 / Total 33 page 1003444042-0 [0019] P12 corresponds to the storage capacitor 336 corresponding to the common line 3i3 And storage with ^1^3 336 corresponds to the storage capacitor region Π2 portion and the film electricity: body region m is arranged parallel to each other. The through (four) domain p2 corresponds to the set electrode 317. The storage capacitor of the electrowetting display 3G and the two thin film electricity The crystals 15, 316 are disposed on the side of the pixel area, even if the storage capacitor 336 and the thin film transistor 324 are disposed in the read non-penetration area, so that the residual fluid 35 is transparent at the maximum standard voltage. The area of the light (the X area and the peripheral area shown in FIG. 3 are used to set the storage capacitor 336 which is itself opaque, so that the electrowetting display 3 is obtained without increasing the driving voltage. Large aperture ratio. In addition, since the storage capacitor 336 is a (10) pad 334, a common electrode 塾 = and a first insulating layer, instead of the pixel electrode _ " common electrode 314 and the first insulating layer 324 sandwiched therebetween And the first and the rim layer 340, the distance between the two electrodes of the storage capacitor is small, and under the premise that the same capacitance is obtained, the overlap between the public power 314 and the immersed 334 can be appropriately reduced. The area, that is, the cross-sectional area of the current storage 336 can be reduced, further increasing the aperture ratio of the electrowetting thief 30. 096138162 [0020] Referring to FIG. 9, FIG. 10 and FIG. 11, FIG. 9 is a top view of a matrix circuit layer corresponding to the pixel region of the electrowetting display stomach of the present invention. FIG. A further top view of the electrowetting display, and Figure U is an enlarged cross-sectional view of Figure 1G along section XI-XI. The (four) wet display is similar in structure to the electric run-down display 3G of the first embodiment, and the difference is that the per-pixel area "common line 413 and adjacent two scan lines 4" form number A0101 a _y total 33 pages 1003444042-0 1364553 • · 100 years, November, and 30th, the positive replacement pages are parallel to each other, and are disposed at a distance from the first short side constituting the pixel region N by one third of the distance between the two short sides, and the public The line electrode 413 extends in a direction perpendicular to the first short side of the common electrode pad 414. The width of the common electrode pad 414 is 0. 25 times. The pixel electrode 417 is continuously distributed with equal width. The first thin film transistor 415 and the second film are disposed in the pixel region N and in the non-penetrating region N1 defined by the common line 413, the first short side and the two long sides. The first gate of the first thin film transistor 41 5 and the second gate of the second thin film transistor 41 6 share the same gate pad 420, and the gate is provided. Pad 420 extends from the scan line 411 to the inside of the pixel region N 12倍。 First, the length of the length of the short side of the pixel area N is 0. 7~0. 98 times, the width W1 is 0. 12 times the length of the long side of the pixel area N. The insulating layer 424 covers the gate pad 420, the common electrode pad 414, and the surface of the second substrate 48. The first semiconductor layer 425 of the first thin film transistor 415 is spaced apart from the second semiconductor layer 435 of the second thin film transistor 416. The first source 421 of the first thin film transistor 415 is connected to the first drain 423 via the first semiconductor layer 425, and the first The source 421 is connected to the data line 412. The second source 431 of the second thin film transistor 416 is connected to the first drain 423, and the second drain 433 extends along a side facing the common electrode pad 414. a drain pad 434 overlapping the common electrode pad 414. The length of the drain pad 434 is substantially the same as the length L1 of the gate pad 420, and the drain pad 434 or the common electrode pad is easier due to process control. 414 is less than the gap D of the gate pad 4 2 0 when the common line is disposed on the two thin film transistor On the opposite side (as shown in Figure 2), the scan line between the common line and the adjacent pixel area is 096138162. Form No. A0101 Page 13/Total 33 Page 1003444042-0 1364553 100 years. November. 30 Revision Lane★ In the present embodiment, the gap D is between 3 and 10 μm to avoid the occurrence of crosstalk (Cr〇sstalk). At the same time, the drain pad 434, the common electrode pad 414 and the common electrode pad 414 are interposed therebetween. The first insulating layer 424 collectively constitutes a storage capacitor 43A. The drain pad 434 has a connection hole 450 overlapping the pixel electrode 417, and the second drain 433 is sequentially connected to the pixel electrode 417 via the drain pad 434 and the connection hole 450. [0022] The two thin film transistors 415, 41 6 and the storage capacitor 436 of the electrowetting display 40 are disposed on the same side of the pixel region N, so that the peripheral region of the thin film transistor that is originally opaque is utilized (eg, A storage capacitor 436 which is opaque to itself is disposed at the gamma region shown in FIG. 3, so that when the voltage difference reaches a maximum standard value, the first fluid (not shown) that is opaque is concentrated on the thin film that is opaque to itself. The crystals 415, 416 and the contact capacitance 436, thereby increasing the penetration area, increase the aperture ratio of the electrowetting display. In addition, since the gap D is smaller than the distance between the common line and the scan line of the adjacent pixel area when the common line is disposed on the opposite side of the two thin film transistors (as shown in FIG. 2), the storage capacitor 436 and the second thin film are electrically The area of the opaque region formed by the crystals 415, 416 is smaller than the area of the opaque region formed when the common line is disposed on both sides of the two thin film transistors, further increasing the aperture ratio. Moreover, since the storage capacitor 436 is also composed of the drain pad 434, the common electrode 414, and the first insulating layer 424 sandwiched therebetween, the distance between the two electrodes of the storage capacitor 436 is small, and the storage capacitor can be appropriately reduced. The cross-sectional area of 436 further increases the aperture ratio of the electrowetting display. Referring to Fig. 12, there is shown a top plan view of a matrix circuit layer corresponding to the matrix circuit layer of the third embodiment of the electrowetting display of the present invention. The electro->, 晏 display is similar to the electro-wetting display of the second embodiment, and the difference is 096138162 Form No. 1010101 Page 14 of 33 1003444042-0 [0023] 1364553
[ΐ〇〇年.11月.30日核正替换百I 在於· s玄電潤濕顯示器對應一像素區域μ之矩陣電路層52 包括一薄膜電晶體515。该薄膜電晶體515包括一閘極 520、一源極521、一汲極523、一半導體層525及一第一 絕緣層（圖未示）。該閘極520亦係自一掃描線511向該像 素區域Μ内部延伸而出之矩形結構，其長度[2為構成該像 素區域Μ短邊長度之0.7-0. 98倍，寬度W2為構成該像素 區域Μ長邊長度之〇. 12倍。該第—絕緣層覆蓋該閘極52〇 及該第二基板（圖未示）表面。該半導體層525設置於該閘 極520對應之第一絕緣層上。該源極521自該資料線512 向该像素區域μ内側延伸而出’該汲極523藉由該半導體 層525與該源極521實現電連接，且其末端具有一延伸與 公共電極墊514相重疊之汲極墊534，且該汲極墊534距 忒閘極墊520之間隙D -小於當將公共線設置於該二薄膜 電晶體相對-側（如圖2所示）時，公共線與相鄰像素區域 之掃描線間的距離，在本實施方式中該間隙D >介於31〇 V"!之間，用以避免串擾）現象的發生。該汲極墊534、該 公共電極整514及夾於其間之第一絕緣層構成_儲存電容 536，且該汲極墊534與該像素電極517重疊處具有一連 接孔550，該汲極523依吹經由該汲極墊534及該連接孔 550連接至該像素電極517。 [0024] ^電潤濕顯7^ 1150之二薄膜電晶體515、51 6與該儲存電 谷536均设置於該像素區域Μ之同-側，使其利用原本不 透光之薄膜電晶體之周邊區域（如圖3所示Υ區域）處設置 =身就不透光之健存電容536，使得在電壓差達到最大標 寺不透光之第一流體（圖未示）集中在本身不透光 096138162 表^單編號Α0101 第15頁/共叩頁 1003444042-0 1364553 100年.11月.30日修正替换頁 之薄膜電晶體515、516與存觸電容536處，進而增大穿 透區面積，增加了該電潤濕顯示器50之開口率。另外， 由於間隙D >小於當將公共線設置於該二薄膜電晶體相對 一側（如圖2所示）時公共線與相鄰像素區域之掃描線間的 距離，使得儲存電容536與二薄膜電晶體515、516所形 成之不透光區域面積小於將公共線設置於二薄膜電晶體 兩側時所形成的不透光區域之面積，進一步增大了開口 率。再者，由於儲存電容536亦由汲極墊534、公共電極 墊514及夾於其間之第一絕緣層524構成，亦可適當減小 該儲存電容536之橫截面積，進一步增大該電潤濕顯示器 5 0之開口率。 [0025] 前述電潤濕顯示器30、40、50各薄膜電晶體之閘極材質 可為鋁或鋁鈦合金，源極與汲極材質可為鉬或為三層結 構之鋁-镍-鑭材質等。另外，在不增加電壓之情況下， 當該電潤濕顯示器30、40、50之公共線313、413、513 具構成對應像素區域P、N、Μ之第一短邊之間距介於二短 邊間距長度之0. 2〜0. 5倍之間時，均可取得增大開口率之 效果。其中，當公共線313、413、513距第一短邊之間 距為二短邊間距之三分之一時，可獲得66. 6%的開口率。 而對於第一實施方式之電潤濕顯示器30，其進一步利用 了原本殘留有第一流體之區域X，其開口率可達70%以上 〇 [0026] 綜上所述，本發明確已符合發明專利之要件，爰法提出 專利申請。惟，以上所述者僅為本發明之較佳實施方式 ，本發明之範圍並不以上述實施方式為限，舉凡熟悉本 096138162 表單编號Α0101 第16頁/共33頁 1003444042-0 1364553 . · 100年.11.月30日修正替換頁 案技藝之人士援依本發明之精神所作之等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0027] 圖1係一種先前技術電潤濕顯示器之局部截面示意圖。 [0028] 圖2係圖1所示電潤濕顯示器之矩陣電路層對應一像素區 域之俯視示意圖。 [0029] 圖3係圖2所示矩陣電路層對應一像素區域之分佈示意圖 [0030] 圖4係本發明電潤濕顯示器第一實施方式之局部截面示意 圖。 [0031] 圖5係圖4所示電潤濕顯示器之矩陣電路層對應一像素區 域之俯視結構示意圖。 [0032] 圖6係圖5沿VI-VI方向之剖面放大示意圖。 [0033] 圖7係圖5沿V11 -V 11方向之剖面放大示意圖。 [0034] 圖8係圖5所示電潤濕顯示器之一像素區域之分佈示意圖 [0035] 圖9係本發明電潤濕顯示器第二實施方式之一像素區域對 應之矩陣電路層之俯視示意圖。 [0036] 圖1 0係圖9所示電潤濕顯示器之一像素區域對應之矩陣電 路層之另一俯視示意圖。 [0037] 圖11係圖10沿XI-XI方向之剖面放大示意圖。 [0038] 圖12係本發明電潤濕顯示器第三實施方式之矩陣電路層 096138162 表單編號A0101 第17頁/共33頁 1003444042-0 1364553 100年11月3〇日按正替換古 對應一像素區域之俯視結構圖。 【主要元件符號說明】 [0039] 電潤濕顯示器： 30 [0040] 第一基板：31 [0041] 第二基板：38、 48 [0042] 隔絕牆：34 [0043] 疏水性絕緣層： 33 [0044] 第二流體：36 [0045] 第一流體：35 [0046] 第一閘極：3 2 0 [0047] 非穿透區域：P1 ' N1 [0048] 第一薄膜電晶體 :315 、 415 [0049] 像素區域：P、N 、Μ [0050] 第二薄膜電晶體 :316、416 [0051] 矩陣電路層：32 ' 42 ' 52 [0052] 第一汲極：323 、423 [0053] 長度：LI、L2 [0054] 寬度：Wl、W2 [0055] 間隙：D、D 一 [0056] 閘極：520 表單编號A0101 第18頁/共33頁 096138162 1003444042-0 1364553 100年.11月.30日按正替換頁 [0057] 源極：521 [0058] 汲極：523 [0059] 半導體層：525 [0060] 閘極墊：420 [0061] 薄膜電晶體：515 [0062] 穿透區域：P2 [0063] 薄膜電晶體區：P11 [0064] 儲存電容區：P12 [0065] 掃描線：311、411、511 [0066] 第二絕緣層：340 [0067] 資料線：312、412、512 [0068] 第二源極：331 [0069] 公共電極墊：314、414、514 '[0070] 第二閘極：330 [0071] 像素電極：317、417、517 [0072] 閘極塾：4 2 0 [0073] 第一絕緣層：324、424、524 [0074] 第一半導體層：325、425 [0075] 儲存電容：336、436、536 096138162 表單編號A0101 第19頁/共33頁 1003444042-0 1364553 100年11月30曰修正替換食 [0076] 第二半導體層：335、435 [0077] 連接孔：350、450、550 [0078] 第一源極：321、421 [0079] 公共線：313、413、513 [0080] 第二汲極：333、433 [0081] 汲極墊：334、434、534 [0082] 缺口 ： 318 ' 418 096138162 表單編號A0101 第20頁/共33頁 1003444042-0[Years. November. 30. The replacement of the substrate is based on the fact that the matrix circuit layer 52 corresponding to a pixel area μ includes a thin film transistor 515. The thin film transistor 515 includes a gate 520, a source 521, a drain 523, a semiconductor layer 525, and a first insulating layer (not shown). The gate 520 is also a rectangular structure extending from a scanning line 511 to the inside of the pixel region, and the length [2 is 0.7-0. 98 times of the length of the short side of the pixel region, and the width W2 is configured. The length of the long side of the pixel area is 12 times. The first insulating layer covers the gate 52A and the surface of the second substrate (not shown). The semiconductor layer 525 is disposed on the first insulating layer corresponding to the gate 520. The source electrode 521 extends from the data line 512 to the inside of the pixel region μ to form a gate 523 electrically connected to the source electrode 521 via the semiconductor layer 525, and has an extension at the end thereof and the common electrode pad 514. The overlapped pad 534, and the gap D of the pad 534 from the gate pad 520 is smaller than when the common line is disposed on the opposite side of the two thin film transistors (as shown in FIG. 2), the common line and The distance between the scanning lines of the adjacent pixel regions is in the present embodiment, and the gap D > is between 31 〇 V "! to avoid crosstalk. The drain pad 534, the common electrode 514 and the first insulating layer sandwiched therebetween constitute a storage capacitor 536, and the drain pad 534 and the pixel electrode 517 overlap with a connection hole 550. The blow is connected to the pixel electrode 517 via the drain pad 534 and the connection hole 550. [0024] The electrowetting display 7^1150 bis film transistors 515, 516 and the storage valley 536 are both disposed on the same side of the pixel region, so that the thin film transistor which is originally opaque is used. The surrounding area (such as the Υ area shown in FIG. 3) is provided with a storage capacitor 536 that is opaque to the body, so that the first fluid (not shown) that is opaque to the maximum threshold is concentrated in itself. Light 096138162 Table ^ Single Number Α 0101 Page 15 / Total 100 Page 1003444042-0 1364553 100 years. November. 30 days to correct the replacement page of the film transistor 515, 516 and the contact capacitance 536, thereby increasing the penetration area The aperture ratio of the electrowetting display 50 is increased. In addition, since the gap D > is smaller than the distance between the common line and the scan line of the adjacent pixel area when the common line is disposed on the opposite side of the two thin film transistors (as shown in FIG. 2), the storage capacitor 536 and the second The area of the opaque region formed by the thin film transistors 515, 516 is smaller than the area of the opaque region formed when the common line is disposed on both sides of the two thin film transistors, further increasing the aperture ratio. Furthermore, since the storage capacitor 536 is also composed of the drain pad 534, the common electrode pad 514, and the first insulating layer 524 interposed therebetween, the cross-sectional area of the storage capacitor 536 can be appropriately reduced to further increase the electrical continuity. The aperture ratio of the wet display 50. [0025] The gate materials of the thin film transistors of the electrowetting display 30, 40, 50 may be aluminum or aluminum titanium alloy, and the source and the drain material may be molybdenum or aluminum-nickel-bismuth material having a three-layer structure. Wait. In addition, when the voltage is not increased, when the common lines 313, 413, and 513 of the electrowetting display 30, 40, and 50 have the first short side of the corresponding pixel area P, N, and Μ, the distance between them is two short. When the length of the edge is 0. 2~0. 5 times, the effect of increasing the aperture ratio can be obtained. Wherein, when the common line 313, 413, 513 is one third of the distance between the first short sides, the aperture ratio of 66.6% can be obtained. For the electrowetting display 30 of the first embodiment, the region X in which the first fluid originally remains is further utilized, and the aperture ratio thereof is up to 70% or more. [0026] In summary, the present invention has indeed met the invention. Patent requirements, patent application. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, and is familiar with this 096138162 Form No. 1010101, page 16/33, 1003444042-0 1364553. The equivalent modifications or variations made by persons skilled in the art of the replacement of the page on the 30th, 11th, and 11th of the month shall be covered by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0027] FIG. 1 is a partial cross-sectional view of a prior art electrowetting display. 2 is a top plan view of a matrix circuit layer of the electrowetting display of FIG. 1 corresponding to a pixel region. [0028] FIG. 3 is a schematic view showing a distribution of a matrix circuit layer corresponding to a pixel region shown in FIG. 2. FIG. 4 is a partial cross-sectional schematic view showing a first embodiment of the electrowetting display of the present invention. 5 is a top plan view showing a matrix circuit layer of the electrowetting display shown in FIG. 4 corresponding to a pixel region. 6 is an enlarged schematic cross-sectional view taken along line VI-VI of FIG. 5. 7 is a schematic enlarged cross-sectional view taken along line V11-V11 of FIG. 5. 8 is a schematic view showing the distribution of a pixel region of one of the electrowetting displays of the second embodiment of the electrowetting display of the present invention. [0035] FIG. 10 is another top plan view of a matrix circuit layer corresponding to one pixel region of the electrowetting display shown in FIG. 9. 11 is an enlarged schematic cross-sectional view of FIG. 10 taken along the line XI-XI. [0037] FIG. 12 is a matrix circuit layer 096138162 of the third embodiment of the electrowetting display of the present invention. Form No. A0101 Page 17 of 33 1003444042-0 1364553 On November 3, 100, the original pixel area is replaced by the positive one. The top view of the structure. [Main component symbol description] [0039] Electrowetting display: 30 [0040] First substrate: 31 [0041] Second substrate: 38, 48 [0042] Isolated wall: 34 [0043] Hydrophobic insulating layer: 33 [ 0044] Second fluid: 36 [0045] First fluid: 35 [0046] First gate: 3 2 0 [0047] Non-penetrating region: P1 'N1 [0048] First thin film transistor: 315, 415 [ 0049] Pixel area: P, N, Μ [0050] Second thin film transistor: 316, 416 [0051] Matrix circuit layer: 32 '42 ' 52 [0052] First drain: 323, 423 [0053] Length: LI, L2 [0054] Width: Wl, W2 [0055] Gap: D, D a [0056] Gate: 520 Form No. A0101 Page 18 / Total 33 096138162 1003444042-0 1364553 100 years. November. 30 Day Press Positive Replacement Page [0057] Source: 521 [0058] Datum: 523 [0059] Semiconductor Layer: 525 [0060] Gate Pad: 420 [0061] Thin Film Transistor: 515 [0062] Penetration Area: P2 [0063] Thin film transistor region: P11 [0064] Storage capacitor region: P12 [0065] Scanning line: 311, 411, 511 [0066] Second insulating layer: 340 [0067] Data line: 312, 412 512 [0068] Second source: 331 [0069] Common electrode pad: 314, 414, 514 '[0070] Second gate: 330 [0071] Pixel electrode: 317, 417, 517 [0072] Gate 塾: 4 2 0 [0073] First insulating layer: 324, 424, 524 [0074] First semiconductor layer: 325, 425 [0075] Storage capacitor: 336, 436, 536 096138162 Form number A0101 Page 19 of 33 1003444042-0 1364553 November 30, 2014 Correction Replacement Food [0076] Second Semiconductor Layer: 335, 435 [0077] Connection Holes: 350, 450, 550 [0078] First Source: 321, 421 [0079] Public Line: 313, 413, 513 [0080] Second drain: 333, 433 [0081] Bump pad: 334, 434, 534 [0082] Notch: 318 ' 418 096138162 Form number A0101 Page 20 of 33 1003444042 -0