1362735 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，特別係有關於一 種具有矽通孔（Through SUic〇n Via，TSV)之半導體晶片 構造及其堆疊組合。 【先前技術】 在半導體電子產品之領域中，積體電路形成半導體 曲片之主動表面，而傳統晶片之端子，例如銲墊，亦形 成於主動表面。在晶片的高密度電性互連技術中，希望 晶片的主動表面與背面皆設有端子’以供立體堆疊或/ 與尚密度封裝。故有人提出一種晶片堆疊組合構造的技 術能朝向高功率、高密度與微小化等高精密度製程發 展即矽穿孔（Through Silicon Via，TSV)技術。矽穿孔 技術是在晶片内開設貫穿且具有電性導通功能之貫穿 孔，貫穿孔是以垂直導通方式來達成堆疊晶片的電性連 接’不再採用中介基板（Interp〇ser)和銲線，使線路不必 繞道晶片側邊，以縮短電氣訊號傳輸距離。並且，石夕穿 孔技術能夠有效提高系統的整合度與效能並能降低封 裝整體高度與面積，並且大大改善晶片速度和低功耗的 性能。然而，每一晶片在運算時會產生熱能，故產生的 熱應力會使晶片變形或翹曲，進而應力集中到晶片間之 電性接點處導致斷裂。 我國發明專利證書號第123 1 023號「三維堆叠之電 子構裝及其組裝方法」，揭示一種具有石夕通孔之半導 6 1362735 片構造，每〜 遞失敗。 〜晶片具有複數個通透孔，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor wafer structure having a through-via (TSV) and a stacked combination thereof. [Prior Art] In the field of semiconductor electronic products, an integrated circuit forms an active surface of a semiconductor wafer, and a terminal of a conventional wafer, such as a pad, is also formed on an active surface. In the high density electrical interconnect technology of wafers, it is desirable that both the active surface and the back side of the wafer be provided with terminals 'for three-dimensional stacking or/or bulk packaging. Therefore, it has been proposed that a wafer stacking structure technology can develop a high-precision process such as high power, high density, and miniaturization, that is, a through silicon via (TSV) technique. The 矽 矽 技术 是 是 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽The line does not have to bypass the sides of the wafer to shorten the electrical signal transmission distance. Moreover, Shixi through hole technology can effectively improve the integration and performance of the system and reduce the overall height and area of the package, and greatly improve the performance of the chip speed and low power consumption. However, each wafer generates thermal energy during operation, so the resulting thermal stress causes the wafer to deform or warp, and stress concentrates at the electrical contacts between the wafers causing the fracture. China Invention Patent No. 123 1 023 "Electrical Assembly and Assembly Method of Three-Dimensional Stacking" discloses a semi-conductor 6 1362735 piece structure with a stone-shaped through-hole, each failing. ~ The wafer has a plurality of through holes,
孔，其内設有對應 電凸塊，再將晶片作縱向 電性接點在晶片之間。當 ’柱狀導電凸塊位在晶片 而斷裂，造成電氣訊號傳 另美國專利第US 6,908,785號所揭示的技術，如第 1圖所示，一種習知具有矽通孔之半導體晶片構造1〇〇 主要包含一半導體基板11〇以及複數個孔内導電金屬 120。該半導體基板 110係具有一第一表面111、一相對之 第二表面112以及複數個貫穿該第一表面U1與該第二表面 112之通孔113«該些導電金屬12〇係形成於該些通孔U3 内，使该§亥半導體基板11〇之該第一表面lu與該第二表面 112形成電性連接端子。該些通孔丨丨3係為縱向連通，該 導電金屬12 0係形成於其内，作為矽通孔結構。如第2 圖所示’複數個半導體晶片構造i 00在進行晶片堆疊 時’ 一載板10之複數個連接墊11上應先預設有複數個 導電針 l2(conductive bar)，以串接該些半導體晶片構 造100之該些通孔113，達成晶片堆疊之電性互連。然而 所有的導電針12必須無彎斜地穿設於複數個半導體基 板110之對應通孔113,方可使該些半導體晶片構造100 能電性連接至該載板1〇。一旦在堆疊其中一半導體晶 片構造1 〇〇碰歪其中一導電針12，則將使得後續堆疊 之半導體晶片構造之通孔113無法順利被該些導電 136273*5 針12穿接，故有晶片對位困難與的製程良率不佳 題。 【發明内容】 本發明之主要目的係在於提供一種具有矽通孔 導體晶片構造及其堆疊組合，以矽通孔貫通晶片 組，有效降低堆疊高度°並且’能達成一種晶片堆 程，可先晶片堆疊再將填孔物質填入該些通孔’填 質不會溢流而無鄰接通孔電性短路之問題，符合矽 微間距之要求’相對於習知利用基板上的插針串接 孔的方式’本發明更具有高製作良率與製程簡便 效。 本發明之次一目的係在於提供一種具有發通孔 導體晶片構造及其堆疊組合，可以線路重佈局技術 不同晶片尺寸之接合’具有便於控制晶片堆叠對位 效。 本發明之另一目的係在於提供一種具有矽通孔 導體晶片構造及其堆疊組合，取代習知串接晶片矽 之插針，以減少基板製作成本。 本發明之另一目的係在於提供一種具有矽通孔 導體晶片構造及其堆疊組合，利用上下對應之凸緣 晶片堆疊，玎遠成晶片準確對位及避免位移。 本發明的目的及解決其技術問題是採用以下技 案來實現的。依據本發明所揭示之一種具有矽通孔 導體晶片構造，主要包含一半導體基板、複數個第 的問 之半 堆疊 疊製 孔物 通孔 ί夕通 之功 之卒 達成 之功 之半 通孔 之+ 環做 術方 之半 一銲 8 1362735 墊、複數個第二銲墊、複數個第一凸緣環以及複數個第 二凸緣環。該半導體基板係具有一第一表面、一相對之 第二表面以及複數個貫穿該第一表面與該第二表面之 通孔。該些第一銲墊係設置於該第一表面。該些第二銲 墊係設置於該第二表面，其中該些通孔更貫穿垂直對應 之該些第一銲墊與該些第二銲墊。該些第一凸緣環係突 出地設置於該些第一銲墊，並使對應之第一銲墊係具有 一第一接觸表面，其係外露於該第一表面並位於該些第 一凸緣環與該些通孔之間。該些第二凸緣環係突出地設 置於該些第二銲墊，並使對應之第二銲墊係具有一第二 接觸表面’其係外露於該第二表面並圍繞在該些第二凸 緣環之外，其中該第二凸緣環係具有可嵌入於該第一凸 緣環之尺寸。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之半導體晶片構造中，可另包含一孔金屬層， 其係形成於該通孔内，並電性連接該些第一銲墊與對應 之該些第二銲墊。 在前述之半導體晶片構造中，該孔金屬層係可與該些 第一凸緣環及該些第二凸緣環為相同電鍍金屬。 在前述之半導體晶片構造中，該半導體基板之該第二 表面係可形成有積體電路。 在前述之半導體晶片構造中，可另包含一銲罩層，其 係覆蓋於該半導體基板之該第一表面，並且該些第一凸 9 丄观735 緣環係突出地接觸該銲罩層。 /在前述之半導體晶片構造中，可另包含填孔物質，其 係填入於該些通孔。 【實施方式】 依據本發明之第一具體實施例，揭示一種具有矽通 孔之半導體晶片構造及其堆疊組合。請參閱帛3圖所 -種具有矽通孔之半導體晶片構造2〇〇主要包含一 φ半導體基板21〇、複數個第—銲墊22q、複數個第二鲜 墊23 0、複數個第一凸緣環24〇以及複數個第二凸緣環 250。該半導體基板21〇係具有一第一表面2ιι、一相 對之第二表面212以及複數個貫穿該第一表面211與該 第二表面212之通孔213。該半導體基板21〇係為半導 體材質，其材質係可為矽、砷化鎵等等。該半導體基板 210之一表面係可形成有各式積體電路並可電性連接至 該些第一銲墊220與複數個第二銲墊23〇。較佳地，積 • 體電路係形成於該半導體基板210之第二表面212 ’即 該第二表面212係作為晶片主動面，故該半導體基板 210之第一表面211可選用較為低成本之絕緣材料作為 電性隔離層，如銲罩層270或其它，並且不會污染到該 些第一銲墊220。（容後詳述） 該些第一銲墊22 0係設置於該半導體基板21〇之該 第一表面211。該些第二銲墊230係設置於該半導體基 板210之該第二表面212。在具體变態中，該些第一鐸 墊220與該些第二銲墊230係位於該半導體基板21〇之 10 Ϊ362735 兩相對側邊或周邊，以避免與積體電路形成區域產生重 疊。其中該些通孔213除了由該第一表面211貫穿至該 第二表面212，更貫穿了垂直對應之該些第一銲墊220 與該些第二銲墊230，故可減少重配置線路層（RDL)的 製作。具體而言，該些銲墊220與23 0通常為鋁墊，而 該些通孔2 1 3係可以雷射鑽孔、反應性離子蝕刻或是微 影成像技術結合化學或電漿蝕刻據以形成》 如第3及4圖所示’該些第一凸緣環24〇係突出地 設置於該些第一銲墊220，並使對應之第一銲墊220係 具有一第一接觸表面221’其係外露於該第一表面211 並位於該些第一凸緣環240與該些通孔2 1 3之間。如第 3及5圖所示’該些第二凸緣環250係突出地設置於該 些第二銲塾230’並使對應之第二銲墊230係具有一第 一接觸表面231 ’其係外露於該第二表面212並圍繞在 δ亥些第二凸緣環25〇之外，其中該第二凸緣環25〇係具 有可嵌入於該第一凸緣環240之尺寸。該些第一凸緣環 240與該些第二凸緣環25〇之材質係可為金屬或導電 膠。 具體而言，如第3及4圖所示，該半導體晶片構造 2〇〇可另包含一孔.金屬層26〇，其係可形成於該些通孔 213内，以電性連接該些第一銲墊220與對應之該些第 一銲墊230，並可確保該些通孔213内壁平滑，有利於 填孔物質290之流動(如第6圖所示)，以達到矽通孔的 電性貫通。較佳地，該孔金屬層260係可與該些第一凸 Ί362735 緣環240及該些苐二凸緣環250為相同電鑛金屬，以降 低製程步驟。而該孔金屬層260之材料依實際操作之經 驗’由於銅為成熟之電錄材料且成本較低，因此，以電 鍍銅所構成者為較佳，但非以此為限。 在本實施例中，由於該半導體基板21〇之該第二表面 212係形成有積體電路，利用晶圓製程，一例如氮化矽或磷 矽玻璃（PSG)之保護層280(passivati〇n layer)可形成於 癱 該第二表面212，其係具有複數個對準該些第二錄塾 2 3 0之開孔，利用晶圓製程中微影成像技術可準確控制 該些第二銲墊230之第二接觸表面231之形成區域。相 對地’使得在该半導體基板210之該第一表面211可採取 更具有彈性的表面電性絕緣處理。如第3及5圖所示，較 佳地’該半導體晶片構造200可另包含一銲罩層270， 其係覆蓋於該半導體基板210之該第一表面211，以提 供表面絕緣保護，避免外界水氣或塵埃污染。並且該些 φ 第一凸緣環240係突出地接觸該銲罩層270。該銲罩層 270係為一種低成本絕緣性油墨，可調整其稠度以控制 形成厚度。 如第6圖所示，當進行複數個上述半導體晶片構造 200的堆疊組合時，該些半導體基板21〇係以其第二表 面212朝向一載板2〇的方式作堆疊，並使該些半導體 基板210之該些通孔213為縱向對應連通。該載板2〇 係可為一種印刷電路板、陶瓷線路板、電路薄膜或預模導 線架（pre-mo丨d leadframe)，以作為晶片載體並達成晶片之電 12 ^62735 ^傳遞。在本實施例中，該載板2G之上表面係、具有複數個 接墊21，並以複數個電性導通孔22(ρτΗ或稱“幻貫穿該 些連接墊21以及該載板20〇每一電性導通孔22内係可形成 有電鍍金屬層23,以電性貫通該載板2〇之上下表面。The hole is provided with a corresponding electric bump, and the wafer is electrically connected to the wafer between the wafers. The technique disclosed in U.S. Patent No. 6,908,785, the entire disclosure of which is incorporated herein by reference in its entirety, the disclosure of the disclosure of the entire disclosure of It mainly comprises a semiconductor substrate 11A and a plurality of in-hole conductive metals 120. The semiconductor substrate 110 has a first surface 111, an opposite second surface 112, and a plurality of through holes 113 extending through the first surface U1 and the second surface 112. The conductive metal 12 is formed on the conductive substrate 12 In the through hole U3, the first surface lu of the semiconductor substrate 11 is electrically connected to the second surface 112. The through holes 3 are longitudinally connected, and the conductive metal 120 is formed therein as a meandering via structure. As shown in FIG. 2, when a plurality of semiconductor wafer structures i 00 are stacked for a wafer, a plurality of conductive pads 11 of a carrier 10 are preliminarily provided with a plurality of conductive pins 12 to be connected in series. The vias 113 of the semiconductor wafer structures 100 achieve electrical interconnection of the wafer stack. However, all of the conductive pins 12 must be bent through the corresponding through holes 113 of the plurality of semiconductor substrates 110 so that the semiconductor wafer structures 100 can be electrically connected to the carrier. Once one of the semiconductor wafer structures 1 is stacked and touches one of the conductive pins 12, the through-holes 113 of the subsequently stacked semiconductor wafer structure will not be smoothly penetrated by the conductive 136273*5 pins 12, so that there is a wafer pair. The difficulty of the process and the poor yield of the process. SUMMARY OF THE INVENTION The main object of the present invention is to provide a germanium via-hole conductor wafer structure and a stacking combination thereof, such that the through-holes pass through the wafer set, effectively reducing the stack height and 'can achieve a wafer stack, and can be wafer first. Stacking and filling the hole-filling material into the through-holes, the filling does not overflow and there is no problem of electrical short-circuiting of the adjacent-through holes, which meets the requirements of the micro-pitch, which is compared with the conventional pin-seam holes on the substrate. The method of the present invention has a high production yield and a simple process. A second object of the present invention is to provide a wafer structure having a via-hole conductor and a stacked combination thereof, which can be line re-layout technology. The bonding of different wafer sizes has the advantage of facilitating control of the wafer stack pair position. Another object of the present invention is to provide a wafer structure having a meander via conductor and a stacked combination thereof, which replaces the pins of the conventional tandem wafer cassette to reduce the substrate fabrication cost. Another object of the present invention is to provide a wafer structure having a meandering via conductor and a stacked combination thereof, which utilizes the upper and lower corresponding flange wafer stacks to accurately align the wafer and avoid displacement. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. According to the present invention, a germanium via-hole conductor wafer structure mainly comprises a semiconductor substrate, a plurality of semi-stacked stacked vias, and a half-via of the work of the work of the + The ring is a half-welded 8 1362735 mat, a plurality of second pads, a plurality of first flange rings, and a plurality of second flange rings. The semiconductor substrate has a first surface, an opposite second surface, and a plurality of through holes extending through the first surface and the second surface. The first pads are disposed on the first surface. The second pads are disposed on the second surface, wherein the through holes further extend through the first corresponding pads and the second pads. The first flanges are protrudingly disposed on the first pads, and the corresponding first pads have a first contact surface exposed to the first surface and located at the first protrusions The edge ring is between the through holes. The second flange rings are protrudingly disposed on the second pads, and the corresponding second pads have a second contact surface that is exposed on the second surface and surrounds the second pads In addition to the flange ring, the second flange ring has a size that can be embedded in the first flange ring. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor wafer structure, a hole metal layer may be further formed in the through hole and electrically connected to the first pads and the corresponding second pads. In the foregoing semiconductor wafer construction, the hole metal layer may be the same plated metal as the first flange ring and the second flange rings. In the foregoing semiconductor wafer construction, the second surface of the semiconductor substrate may be formed with an integrated circuit. In the foregoing semiconductor wafer structure, a solder mask layer may be further disposed on the first surface of the semiconductor substrate, and the first protrusions 735 edge ring protrudes to contact the solder mask layer. / In the foregoing semiconductor wafer structure, a hole-filling substance may be further included, which is filled in the through holes. [Embodiment] According to a first embodiment of the present invention, a semiconductor wafer structure having a via hole and a stacked combination thereof are disclosed. Referring to FIG. 3, a semiconductor wafer structure having a through-hole is mainly composed of a φ semiconductor substrate 21, a plurality of first pads 22q, a plurality of second fresh pads 23 0, and a plurality of first bumps. The edge ring 24〇 and the plurality of second flange rings 250. The semiconductor substrate 21 has a first surface 2 ι , an opposite second surface 212 , and a plurality of through holes 213 extending through the first surface 211 and the second surface 212 . The semiconductor substrate 21 is made of a semiconductor material, and the material thereof may be tantalum, gallium arsenide or the like. One surface of the semiconductor substrate 210 can be formed with various integrated circuits and can be electrically connected to the first pads 220 and the plurality of second pads 23A. Preferably, the integrated circuit is formed on the second surface 212' of the semiconductor substrate 210, that is, the second surface 212 is used as the active surface of the wafer, so that the first surface 211 of the semiconductor substrate 210 can be insulated with relatively low cost. The material acts as an electrically isolating layer, such as solder mask layer 270 or otherwise, and does not contaminate the first pads 220. (Detailed later) The first pads 22 0 are provided on the first surface 211 of the semiconductor substrate 21 . The second pads 230 are disposed on the second surface 212 of the semiconductor substrate 210. In a specific variant, the first pads 220 and the second pads 230 are located on opposite sides or the periphery of the 10 Ϊ 362735 of the semiconductor substrate 21 to avoid overlapping with the integrated circuit forming regions. The through holes 213 extend through the first surface 211 to the second surface 212, and further extend the vertically corresponding first pads 220 and the second pads 230, thereby reducing the reconfiguration circuit layer. Production of (RDL). Specifically, the pads 220 and 230 are usually aluminum pads, and the through holes 2 1 3 can be combined with chemical drilling or plasma etching by laser drilling, reactive ion etching or lithography. Forming as shown in FIGS. 3 and 4, the first flange rings 24 are protrudingly disposed on the first pads 220, and the corresponding first pads 220 have a first contact surface 221 'It is exposed to the first surface 211 and is located between the first flange ring 240 and the through holes 2 1 3 . As shown in FIGS. 3 and 5, the second flanges 250 are protrudingly disposed on the second pads 230' and the corresponding second pads 230 have a first contact surface 231' Exposed to the second surface 212 and surrounding the second flange ring 25〇, wherein the second flange ring 25 has a size that can be embedded in the first flange ring 240. The materials of the first flange ring 240 and the second flange rings 25A may be metal or conductive glue. Specifically, as shown in FIGS. 3 and 4, the semiconductor wafer structure 2 can further include a hole. The metal layer 26 can be formed in the through holes 213 to electrically connect the first a pad 220 corresponding to the first pads 230, and ensuring that the inner walls of the through holes 213 are smooth, facilitating the flow of the hole-filling substance 290 (as shown in FIG. 6) to achieve the electricity of the through-holes Sexual penetration. Preferably, the hole metal layer 260 is the same as the first protrusion 362735 edge ring 240 and the second flange ring 250 to reduce the process steps. The material of the hole metal layer 260 is based on the actual operation. Since copper is a mature electro-recording material and the cost is low, it is preferable to use copper-plated copper, but not limited thereto. In this embodiment, since the second surface 212 of the semiconductor substrate 21 is formed with an integrated circuit, a protective layer 280 such as tantalum nitride or phosphoric acid glass (PSG) is used by a wafer process (passivati〇n) The layer 2 can be formed on the second surface 212, and has a plurality of openings aligned with the second recording electrodes 230, and the second solder pads can be accurately controlled by using the micro-image imaging technology in the wafer process. The formation area of the second contact surface 231 of 230. Oppositely, the first surface 211 of the semiconductor substrate 210 can be subjected to a more elastic surface electrical insulation treatment. As shown in FIGS. 3 and 5, the semiconductor wafer structure 200 may further include a solder mask layer 270 covering the first surface 211 of the semiconductor substrate 210 to provide surface insulation protection to avoid externalities. Water or dust pollution. And the φ first flange ring 240 is in protruding contact with the solder mask layer 270. The solder mask layer 270 is a low cost insulating ink that can be adjusted in thickness to control the thickness. As shown in FIG. 6, when a plurality of stacked combinations of the above-described semiconductor wafer structures 200 are performed, the semiconductor substrates 21 are stacked with their second surface 212 facing a carrier 2, and the semiconductors are stacked. The through holes 213 of the substrate 210 are vertically correspondingly connected. The carrier 2 can be a printed circuit board, a ceramic circuit board, a circuit film or a pre-mo丨d leadframe to serve as a wafer carrier and to achieve electrical transfer of the wafer. In this embodiment, the upper surface of the carrier 2G has a plurality of pads 21 and a plurality of electrical vias 22 (pτ Η or "phantom through the connection pads 21 and the carrier 20 〇 An electroplated metal layer 23 may be formed in an electrical via 22 to electrically penetrate the upper surface of the carrier 2 .
具體而言，如第7圖所示，在堆疊組合時，位於該 該半導體基板210之該第二表面212之該些第二凸緣環 2 5〇係對位並嵌合於下方另一半導體基板21〇之該第一 表面2U之該些第一凸緣環24〇内，以形成防止溢流的 曲折接觸表面，並能達成該些半導體晶片構造2〇〇準確 對位及避免位移。 再如第6圖所示，利用一填孔物質2 9 0填入於該 通孔213，以使該些半導體晶片構造2〇〇為電性互連。 具體而言’該填孔物質290之材質係可為導電材料，例如 銲料、含銅導電膏、銀膠或導電油墨等等。較佳地，該填 孔物質290可更填入於該載板20之該些電性導通孔 22 ’以使該些半導體晶片構造200電性連接至該載板 2〇。而該載板20之該些電性導通孔22可作為排氣之 用’以促進該填孔物質290之流動。當該填孔物質290 流動到該些半導體晶片構造200之間隙時，該些第一凸 緣環240與該些第二凸緣環250構成之曲折接觸界面能 防止該填孔物質290之溢流，避免相鄰近的通孔2 1 3之 間產生電性短路，故能符合矽通孔微間距之要求，相對 於習知利用基板上的插針串接矽通孔的方式，本發明更 具有高製作良率與製程簡便之功效。 13 136273.5 在本發明之第二具體實施例，揭示另一種具有矽通 孔之半導體晶片構造及其堆疊組合。請參閱第8圖所 示，一種具有矽通孔之半導體晶片構造300主要包含一 半導體基板310、一第一銲墊320、一第二銲墊330、 一第一凸緣環340以及一第二凸緣環350。該半導體基 板310係具有一第一表面311、一相對之第二表面312、 一形成於該第一表面311内之第一半通孔313以及一形成於 ^ 該第二表面312内之第二半通孔314。具體而言，該第一 半通孔313與該第二半通孔314係可以半蝕刻與電鍍方 式形成盲孔型態。 該第一銲墊3 20係設置於該第一表面311，並且該第一 半通孔313更貫穿垂直對應之該第一銲墊320。該第二銲墊 330係設置於該第二表面312，並且該第二半通孔314更貫 穿垂直該第二銲墊330。該第一銲墊320的設置位置可不與 該第二銲墊330垂直對應。 • 如第8及9圖所示’該第一凸緣環340係突出地設置 於該第一銲墊320 ’並使該第一銲墊320係具有一第一接觸 表面32 1 ’其係外露於該第一表面3丨丨並位於該第一凸緣環 340與該第一半通孔313之間。該第二凸緣環35〇係突出地 設置於該第二銲墊330，並使該第二銲墊330係具有一第二 接觸表面331 ,其係外露於該第二表面312並圍繞在該第二 凸緣環350之外，其中該第二凸緣環35〇係具有可嵌入於該 第一凸緣環340之尺寸。 具體而s ’如第8及9圖所示，該半導體晶片構造 14 1362735 300可另包含一孔金屬層360,其係形成於該第—半通孔 313與該第二半通孔314内，以電性連接對應之該第—銲墊 320與該第二銲墊330。其中該孔金屬層36〇係可與該第— 凸緣環340及該第二凸緣環350為相同電鍵金屬 以 製程步驟。 為能提供更佳之電性導通品質，可將一植πια ^ 舉札物質 391Specifically, as shown in FIG. 7 , when stacked and stacked, the second flange rings 25 located on the second surface 212 of the semiconductor substrate 210 are aligned and embedded in another semiconductor underneath. The substrate 21 is disposed in the first flanges 24 of the first surface 2U to form a meandering contact surface for preventing overflow, and the semiconductor wafer structure 2 can be accurately aligned and prevented from being displaced. Further, as shown in Fig. 6, a through-hole material 209 is filled in the via hole 213 to electrically interconnect the semiconductor wafer structures. Specifically, the material of the hole-filling substance 290 may be a conductive material such as solder, a copper-containing conductive paste, silver paste or a conductive ink or the like. Preferably, the hole-filling material 290 can be further filled in the electrical vias 22' of the carrier 20 to electrically connect the semiconductor wafer structures 200 to the carrier. The electrical vias 22 of the carrier 20 can be used as an exhaust gas to promote the flow of the hole-filling material 290. When the hole-filling material 290 flows into the gap between the semiconductor wafer structures 200, the meandering contact interface between the first flange ring 240 and the second flange rings 250 prevents the overflow of the hole-filling material 290. In order to avoid electrical short-circuit between the adjacent through-holes 2 1 3 , the micro-pitch of the through-holes can be met, and the invention has the advantages that the pins on the substrate are connected in series with the through-holes. High production yield and easy process. 13 136273.5 In a second embodiment of the present invention, another semiconductor wafer construction having a via hole and a stacked combination thereof are disclosed. Referring to FIG. 8 , a semiconductor wafer structure 300 having a via hole mainly includes a semiconductor substrate 310 , a first pad 320 , a second pad 330 , a first flange ring 340 , and a second Flange ring 350. The semiconductor substrate 310 has a first surface 311, an opposite second surface 312, a first half via 313 formed in the first surface 311, and a second surface formed in the second surface 312. Half through hole 314. Specifically, the first semi-via 313 and the second semi-via 314 can be formed into a blind via type by half etching and electroplating. The first pad 3 20 is disposed on the first surface 311 , and the first half via 313 further penetrates the first pad 320 corresponding to the vertical. The second pad 330 is disposed on the second surface 312, and the second half via 314 is perpendicular to the second pad 330. The first pad 320 may be disposed at a position that does not vertically correspond to the second pad 330. • As shown in FIGS. 8 and 9 'the first flange ring 340 is protrudingly disposed on the first pad 320 ′ and the first pad 320 has a first contact surface 32 1 'exposed The first surface 3 is located between the first flange ring 340 and the first half through hole 313. The second flange ring 35 is protrudedly disposed on the second pad 330, and the second pad 330 has a second contact surface 331 that is exposed on the second surface 312 and surrounds the second pad 330. Outside of the second flange ring 350, wherein the second flange ring 35 has a size that can be embedded in the first flange ring 340. Specifically, as shown in FIGS. 8 and 9, the semiconductor wafer structure 14 1362735 300 may further include a hole metal layer 360 formed in the first half through hole 313 and the second half through hole 314. The first pad 320 and the second pad 330 are electrically connected. The hole metal layer 36 can be the same as the first flange ring 340 and the second flange ring 350 as a process step. In order to provide better electrical conductivity, a plant can be planted πια ^
填入於該第一半通孔313, 一填孔物質392填入於該第二半 通孔3Μ内’填孔物質39丨與392之材質係可為導電:不 導電之塞孔材料’例如含銅導電膏或油墨樹脂等。較佳地， 該填孔物質392係更填入於該第二凸緣環35〇内以電性接 觸下方堆疊半導體晶片構造300之該第一銲墊32〇之第-接觸表面321 (如第9圖所示）。Filled in the first half through hole 313, a hole filling material 392 is filled in the second half through hole 3, 'the material of the hole filling material 39丨 and 392 can be electrically conductive: non-conductive plug hole material' Copper-containing conductive paste or ink resin. Preferably, the hole-filling material 392 is further filled in the second flange ring 35 to electrically contact the first contact surface 321 of the first pad 32 of the semiconductor wafer structure 300 underlying the stack (eg, Figure 9 shows).
在本實施例中’再如第9圖所示，該第一半通孔313 與該第二半通孔314之間係可具有一水平位移s。該半導體 晶片構造300内可形成一重配置線路層37〇，以連接在該 水平位移s之間的該第一半通孔313與該第二半通孔314= 達到電性連接該第一半通孔與313該第二半通孔314。因 此，利用該重配置線路層370可以克服該水平位移s以電性 連接於該第一銲& 320與該第二銲塾33〇,以改變該半導 體晶片構造300之端子位置（由該第—銲墊32〇改變至 非垂直對應之該第二銲墊33〇)<>該重配置線路層37〇係 可利用濺鍍（ — ng)的方式職，再進行微㈣之製程， 以定義線路層之圖案化的線路。 如第8及9圖所示，該半導體晶片構造3〇〇可另包 15 丄 3保護層380 ’其係覆蓋於該半導體基板310之該第-表 面311或/與該第二表面312。該第一凸緣豸㈣係可突出地 接觸位在該第—表面311之保護層380。 如第10圖所示，當進行不同尺寸之複數個上述半導 體晶片構造300堆疊組合時，以其該第二凸緣環350朝 向同方向的方式作晶片堆疊，例如朝向一載板3〇β 其中’位於較上方之—半導體基& 310 t該第二表面In the present embodiment, as shown in FIG. 9, the first half through hole 313 and the second half through hole 314 may have a horizontal displacement s. A reconfigurable circuit layer 37 is formed in the semiconductor wafer structure 300 to connect the first half via 313 and the second half via 314 between the horizontal displacements s to electrically connect the first half pass The hole and the second half through hole 314 are 313. Therefore, the horizontal displacement s can be overcome by the reconfigured wiring layer 370 to be electrically connected to the first solder & 320 and the second solder tab 33 〇 to change the terminal position of the semiconductor wafer structure 300 (by the first - the pad 32 〇 is changed to the non-vertical corresponding second pad 33 〇) <> The reconfigurable circuit layer 37 can be sputtered (-ng), and then micro (four) process, A line that defines the pattern of the circuit layer. As shown in Figs. 8 and 9, the semiconductor wafer structure 3 can be further provided with a protective layer 380' covering the first surface 311 or/and the second surface 312 of the semiconductor substrate 310. The first flange (4) is capable of projectingly contacting the protective layer 380 of the first surface 311. As shown in FIG. 10, when a plurality of the above-described semiconductor wafer structures 300 of different sizes are stacked and stacked, the wafer is stacked in such a manner that the second flange ring 350 faces in the same direction, for example, toward a carrier 3? 'located on the upper side - semiconductor base & 310 t the second surface
312之該第一凸緣環35〇係對位嵌合於較下方之另一半 導體基板310之該第一表面311之該第一凸緣環34〇 内而位於最下方之該半導體晶片構造300之該第二凸 緣環350係可接合於該載板3〇之連接墊Η，以達成多 晶片之電性連通，並達成該些半導體基板3 10準確對位 及避免位移。因此，本實施例中可以運用到不同晶片尺 寸之晶片堆疊組合。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例’但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾’均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：習知具有矽通孔之半導體晶片構造之截面示意 16 1362735 圖。 第2圖：習知複數個半導體晶片構造之堆疊組合截面示 意圖。 第3圖：依據本發明之第一具體實施例，一種具有矽通 孔之半導體晶片構造之截面示意圖。 第4圖：依據本發明之第一具體實施例，該半導體晶片 構造之第一銲墊與第一凸緣環之截面與立體示意 圖。 第5圖：依據本發明之第一具體實施例，該半導體晶片 構造之第二銲墊與第二凸緣環之戴面與立體示意 圖。 第6圖：依據本發明之第一具體實施例，複數個半導體 晶片構造之堆疊組合之截面示意圖。 第7圖：依據本發明之第一具體實施例，複數個半導體 晶片構造在堆疊時局部放大之截面示意圖。 第8圖：依據本發明之第二具體實施例，另一種具有矽 通孔之半導體晶片構造之截面示意圖。 第9圖：依據本發明之第二具體實施例，複數個半導體 晶片構造在堆疊時局部放大之截面示意圖。 第1 0圖：依據本發明之第二具體實施例，複數個半導 體晶片構造之堆疊組合之局部截面示意圖。 【主要元件符號說明】 S 水平位移 10 載板 11 連接墊 12 導電針 17 136273'5The first flange ring 35 of the 312 is alignably embedded in the first flange ring 34 of the first surface 311 of the lower semiconductor substrate 310 and is located at the lowest position of the semiconductor wafer structure 300. The second flange ring 350 can be bonded to the connection pads of the carrier 3 to achieve electrical communication between the plurality of wafers, and achieve accurate alignment and avoidance of the semiconductor substrates 3 10 . Therefore, a wafer stack combination of different wafer sizes can be applied in this embodiment. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make a few changes or modifications to the equivalent embodiment by using the technical content disclosed above, but the content without departing from the technical solution of the present invention is made according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional semiconductor wafer structure having a through-hole. 16 1362735. Figure 2: A cross-sectional view of a stacked combination of a plurality of semiconductor wafer structures. Figure 3 is a cross-sectional view showing the construction of a semiconductor wafer having a via hole in accordance with a first embodiment of the present invention. Figure 4 is a cross-sectional and perspective view of a first pad and a first flange of the semiconductor wafer construction in accordance with a first embodiment of the present invention. Figure 5 is a perspective view and perspective view of a second pad and a second flange of the semiconductor wafer construction in accordance with a first embodiment of the present invention. Figure 6 is a cross-sectional view showing a stacked combination of a plurality of semiconductor wafer structures in accordance with a first embodiment of the present invention. Figure 7 is a cross-sectional view, partially enlarged, of a plurality of semiconductor wafer structures in a stacked manner in accordance with a first embodiment of the present invention. Figure 8 is a cross-sectional view showing another construction of a semiconductor wafer having a via hole in accordance with a second embodiment of the present invention. Figure 9 is a partially enlarged cross-sectional view showing the construction of a plurality of semiconductor wafers in a stacked manner in accordance with a second embodiment of the present invention. Figure 10 is a partial cross-sectional view showing a stacked combination of a plurality of semiconductor wafer structures in accordance with a second embodiment of the present invention. [Main component symbol description] S Horizontal displacement 10 Carrier board 11 Connection pad 12 Conductive pin 17 136273'5
20 載板 21 連接墊 22 電 性 導 通孔 23 電鍍 金屬層 30 載板 31 連接墊 100 半導 體晶片構造 110 半導 體基板 111 第 一表 面 112 第 二 表 面 113 通孔 120 導電 金屬 200 半導 體晶片構造 210 半導 體基板 211 第 一表 面 212 第 二 表 面 213 通孔 220 第一 銲墊 221 第 一接 觸 表 面 230 第二 銲墊 231 第 二接 觸 表 面 240 第一 凸緣環 250 第 二凸 緣 環 260 孔 金 屬 層 270 銲罩層 280 保 護層 290 填孔物 質 300 半導 體晶片構造 3 10 半導 體基板 311 第 一表 面 312 第 二 表 面 3 13 第一 半通孔 314 第 二半 通孔 320 第一 銲垫 321 第 一接 觸 表 面 330 第二 銲垫 331 第 二接 觸 表 面 340 第一 凸緣環 350 第 二凸 緣 環 360 孔 金 屬 層 370 重配 置線路層 380 保 護層 391、392 填孔物質 1820 carrier 21 connection pad 22 electrical via 23 electroplated metal layer 30 carrier 31 connection pad 100 semiconductor wafer structure 110 semiconductor substrate 111 first surface 112 second surface 113 via 120 conductive metal 200 semiconductor wafer configuration 210 semiconductor substrate 211 First surface 212 second surface 213 through hole 220 first pad 221 first contact surface 230 second pad 231 second contact surface 240 first flange ring 250 second flange ring 260 hole metal layer 270 solder mask layer 280 protective layer 290 hole filling material 300 semiconductor wafer structure 3 10 semiconductor substrate 311 first surface 312 second surface 3 13 first half via 314 second half via 320 first pad 321 first contact surface 330 second solder Pad 331 second contact surface 340 first flange ring 350 second flange ring 360 hole metal layer 370 reconfiguration circuit layer 380 protective layer 391, 392 hole filling Quality 18