1358591 九、發明說明： ‘·'【發明所屬之技術領域】 -' 本發明係關於一種影像顯示系統，特別關於一種與品 字型晶片相連結之薄膜電晶體基板。 . · 【先前技術】 含有薄膜電晶體基板的影像顯示系統，如液晶顯示面 板或是有機發光二極體面板，其係於完成所有的線路配置 • 後，仍須與外部晶片做接合以提供薄膜電晶體基板所需之 運算及驅動來源。在晶片與薄膜電晶體基板接合的過程 中，主要將晶片上之接腳與薄膜電晶體基板上之接點相接 合。 圖1A係為一薄膜電晶體基板1與一晶片2以一字型 接點配置接合後之一側視示意圖。圖1B係為圖1A中走線 與接點形狀之一俯視示意圖。請參照圖1A所示，薄膜電 ^ 晶體基板1具有一基板11、一絕緣層12、一導電層13以 及一平坦層14，絕緣層12係設置在基板11上，導電層 13以及平坦層14係設置在絕緣層12上，平坦層14之一 部份係被挖空使得導電層13得以露出，藉以和晶片2之 接腳21連接。 導電層13上係形成有複數條走線131及複數個接點 132，各接點132係與晶片2之各接腳21連接。如 所示，各接點132係分別與各走線131連接，且各走線131 彼此相鄰設置，各接點132與對應的走線131形狀係似一 5 1358591 字型。 • _·· 薄膜電晶體基板1的線路配置須考慮與晶片2接合產 ·.·生的移位誤差，因此，相鄰之各接點132間必須有足夠的 間隔，以避免如圖1A所示，晶片2的接腳21同時和兩個 _接點132接觸而造成短路的愧況發生。如此一來，單位面 積中所能容納的接點數目有限，使得一字型接點配置需要 較大的佈局面積。 圖2A係為薄膜電晶體基板1'與晶片2'以品字型接點 • 配置接合後之一側視示意圖。圖2B係為圖2A中走線與接 點形狀之一俯視示意圖。請參照圖2A及圖2B所示，其與 圖1A及圖1B不同的是，各接點132'係交錯排列成品字 型，使得單位面積之内設置走線13Γ和接點132'的密度較 高，因而可較節省佈局的面積。然而，在這種架構下，相 鄰之各接點132'間仍必須間隔有足夠的距離D，以避免如 圖2A所示晶片2'的接腳2Γ同時和接點132'與走線131' 接觸而造成短路的情況發生。雖然品字型接點配置較一字 ^ 型接點配置具有較佳的面積使用效率，但仍需要足夠的佈 局面積。 有鑑於此，如何提供一種可防止短路情況發生且節省 佈局面積的配置方式，實為現今的一大課題。 【發明内容】 有鑑於上述課題，本發明之目的為提供一種影像顯示 系統，其係具有可防止短路情況發生節省佈局面積之配置 6 1358591 方式的薄膜電晶體基板。 * *.. . 緣是，為達上述目的，本發明之一種影像顯示系統係 有薄膜電晶體基板，其中薄膜電晶體基板包含一第一 導電層及-第二導電層。第一導電層係形成有一第一走線 -及一第二走線；第二導電層係，設置於該第一導電層上，並 形成有-第-接點，其中第一接點與第一走線電性連接， 且第一接點與第二走線相鄰設置。 承上所述，依據本發明之赛舞顯示系統中薄膜電晶體 籲基=係於第-導電層形成走線，於第二導電層形成接點， 使得走線與接點形成於不同導電層。與習知技術相較，本 發明之薄膜電晶體基板與晶片接合時，因走線與接點形成 於不同導電層，是以，晶片之接腳不會因為同時接觸到接 點及走線而造成短路的情況。且因本發明之接點與走線彼 此相鄰設置而形成品字型接點配置，因而可縮小配線面 積。 【實施方式】 以下將參照相關圖式，說明依據本發明較 影像顯示系統。 μ 圖3A係為薄膜電晶體基板3與晶片4以品 配置接合後之-側視示意圖’圖犯係、為圖3a+ 接 點形狀之-俯視示意圖。請參照圖3A所示，薄膜電二 f3板\包=31、一第一導電層”、-第」絕:層 M、-第二導電層34及一第二絕緣層％，第一導 7 1358591 係設置於該基板31上，第—絕緣層33係覆蓋第一導電層 • 32，第二導電層34係設置於第一絕緣層33上，第二絕緣 •層35係覆蓋第二導電層34,其巾，第二絕緣層％之一部 分挖空以露出第二導電層34。 ° 通常，基板31可為—_基板，其係包含—玻璃基 板以及設置在玻璃基板上的緩衝層（或絕緣層）。第一& 電層32與第二導電層34係可用來形成晝素陣列上的資料 線或掃描線（或稱為行導線或列導線）。帛二絕緣層3 •為一平坦層。 於本實施例中，第一導電層32上形成複數條第一走 線3"21及複數條第二走線322，第二導電層34上形成複數 個第一接點341及複數個第二接點342，其中，各第一 點⑷與第-走線切其中之一電性連接，各第二接點如 與第二走線322其中之一電性連接，且第一接點341盘第 =走線322相鄰設置’第二接點342與第一走線321相鄰 φ 设置。 ^走線321與第一走線322係可與形成於晝素陣列 上的資料線或掃描線電性連接’第—接點341與第二接點 342係連接晶“的接腳41，因而可使晶片4電性連接畫 素陣列上的資料線或掃描線，並使晶片4驅動畫素陣列。 另外’薄膜電晶體基板3更具有複數個第-導電栓（圖 :未不^及複數個第二導電栓（圖中未示），該些導電检係 »又置於第-導電層32與第二導電層％之間，各第一導電 栓電性連接第-接點341及第一走線321其中之一，各第 8 1358591 二導電栓電性連接第二接點342及第二走線322其中之 • 一— 〇 ..· 承上，因第一接點341與第二走線322相鄰設置，第 二接點342與第一走線321相鄰設置，使得該等第一接點 \ · 341與第二接點342呈品字型,接點方式設置，因而可於單 位面積中能容納較多數目之走線及接點，進而縮小線路配 置的面積，且使得影像顯示系統的體積縮小。此外，利用 本發明之薄膜電晶體基板3的配線設置與外部晶片4接合 • 時，因與晶片4相接合之第二導電層34中僅有接點存在， 所以無論受到任何因素的影響而造成晶片4產生位移時， 晶片4中之接腳41僅能與相對應之接點電性連接，使得 接腳41不會因為與走線相接觸而造成短路的情況發生。 於本實施例中，薄膜電晶體基板3可做為一矩陣式顯 示面板的晝素陣·列基板。若矩陣式顯示面板是一有機發光 二極體面板，則在薄膜電晶體基板3上除了形成行、列導 線之外係形成有晝素驅動電路以及有機發光二極體，晝素 ® 驅動電路係電性連接行、列導線以驅動有機發光二極體。 另外，若矩陣式顯示面板是一液晶顯示面板，則矩陣 式顯示面板更包含另一對向基板以及液晶層，液晶層係設 置於薄膜電晶體基板3與對向基板之間。在薄膜電晶體基 板3上除了形成行、列導線之外係形成有晝素驅動電路以 驅動液晶層。 液晶顯示面板可為一扭轉向列型（Twisted Nematic， TN )、多象限垂直配向（Multi-domain Vertical Alignment ’ 9 1358591 MVA )、橫向電場驅動（In-Plane Switching，IPS )、邊緣電 :·場驅動（Fringe-Fiele Switching，FFS)、主動矩陣濾光片、 -穿透式（Transmissive)、反射式（Reflective)或半穿反式 (丁ransflective)等形式。 通常，需要主動光源來顯》示影像的液晶顯示面板會與 一背光模組組合而成一液晶顯示裝置，背光模組係輸出一 光線至液晶顯示面板，以使液晶顯示面板顯示影像。 請參照圖4所示’為本發明另一較佳實施例之一影像 顯示系統5包含一電子裝置51，電子裝置51係具有一矩 陣式顯示面板511及一輸入單元512，其中矩陣式顯示面 板511具有一薄膜電晶體基板5111。薄膜電晶體基板51u 係如前述實施例之薄膜電晶體基板3，相關細節與實施方 式係已於前述實施例中討論過，在此不再贅述。 矩陣式顯示面板511係可以是前述之多象限垂直配 向、橫向電場驅動、邊緣電場驅動、主動矩陣渡光片、穿 透式或半穿反式等形式的液晶顯示面板，輸入單元512與 矩陣式顯示面板511耦合，並對矩陣式顯示面板511提供 輸入，以使矩陣式顯示面板511顯示影像。在本實施例中^ 電子裝置5為移動式電話、數位照相機、個人數位助理、 筆記型電腦、桌上型電腦、電視機、車用顯示器、頭戴式 顯示器、印表機營幕、MP3播放器、掌上型遊戲可^ 式DVD機等。 Λ J瑪 綜上所述，依據本發明之影像顯示系統 基板係於第-導電層形成走線，於第二導電層形成::體 1358591 使得走線與接點形成於不同導電層。與習知技術相較，本 •'發明之薄膜電晶體基板與晶片接合時，因走線與接點形成 • 於不同導電層，是以，晶片之接腳不會因為同時接觸到接 點及走線而造成短路的情況。且因本發明之接點與走線彼 ' 此相鄰設置而形成品字型接,舜配置，因而可縮小配線面 積。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 ,· 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1A為習知薄膜電晶體基板與晶片以一字型接點配 置接合後之一側視示意圖； 圖1B為圖1A中走線與接點形狀之一俯視示意圖； 圖2A為習知薄膜電晶體基板與晶片以品字型接點配 置接合後之側視不意圖， ^ 圖2B為圖2A中走線與接點形狀之一俯視示意圖； 圖3A為依本發明較佳實施例之薄膜電晶體基板與晶 片以品字型接點配置接合後之一側視示意圖； 圖3B為圖3A中走線與接點形狀之一俯視示意圖；以 及 圖4為依本發明另一較佳實施例之影像顯示系統之一 區塊圖。 11 13585911358591 IX. Description of the invention: ‘·' [Technical field to which the invention pertains] - The present invention relates to an image display system, and more particularly to a thin film transistor substrate coupled to a type of wafer. [Prior Art] An image display system including a thin film transistor substrate, such as a liquid crystal display panel or an organic light emitting diode panel, which is required to be bonded to an external wafer to provide a film after all the wiring configurations are completed. The operation and drive source required for the transistor substrate. In the process of bonding the wafer to the thin film transistor substrate, the pins on the wafer are mainly bonded to the contacts on the thin film transistor substrate. Fig. 1A is a side elevational view showing a thin film transistor substrate 1 and a wafer 2 in a one-piece contact arrangement. Figure 1B is a top plan view of the shape of the traces and contacts in Figure 1A. Referring to FIG. 1A, the thin film substrate 1 has a substrate 11, an insulating layer 12, a conductive layer 13, and a flat layer 14. The insulating layer 12 is disposed on the substrate 11, and the conductive layer 13 and the flat layer 14 are provided. The insulating layer 12 is disposed on the insulating layer 12, and a portion of the flat layer 14 is hollowed out so that the conductive layer 13 is exposed to be connected to the pins 21 of the wafer 2. A plurality of traces 131 and a plurality of contacts 132 are formed on the conductive layer 13, and the contacts 132 are connected to the pins 21 of the wafer 2. As shown, each of the contacts 132 is connected to each of the traces 131, and each of the traces 131 is disposed adjacent to each other. Each of the contacts 132 and the corresponding trace 131 are shaped like a 5 1358591 font. • _·· The wiring arrangement of the thin film transistor substrate 1 must take into account the displacement error caused by the bonding with the wafer 2. Therefore, there must be sufficient spacing between adjacent contacts 132 to avoid the arrangement as shown in Figure 1A. It is shown that the pin 21 of the wafer 2 is simultaneously in contact with the two_contacts 132 to cause a short circuit. As a result, the number of contacts that can be accommodated in a unit area is limited, so that a one-line contact configuration requires a large layout area. 2A is a schematic view of a side of a thin film transistor substrate 1' and a wafer 2'. Figure 2B is a top plan view of the shape of the traces and contacts in Figure 2A. Referring to FIG. 2A and FIG. 2B , which is different from FIG. 1A and FIG. 1B , each contact 132 ′ is staggered to arrange the finished font, so that the density of the trace 13 Γ and the contact 132 ′ is set within the unit area. High, thus saving the layout area. However, in this architecture, the adjacent contacts 132' must still be spaced apart by a sufficient distance D to avoid the pins 2' of the wafer 2' and the contacts 132' and traces 131 as shown in FIG. 2A. ' A short circuit has occurred due to contact. Although the pin-shaped contact configuration has better area efficiency than a one-word contact configuration, sufficient layout area is still required. In view of this, how to provide an arrangement that can prevent a short circuit from occurring and save a layout area is a major issue today. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an image display system having a thin film transistor substrate in a configuration that avoids occurrence of a short circuit and saves a layout area. In order to achieve the above object, an image display system of the present invention is a thin film transistor substrate, wherein the thin film transistor substrate comprises a first conductive layer and a second conductive layer. The first conductive layer is formed with a first trace and a second trace; the second conductive layer is disposed on the first conductive layer and is formed with a - contact, wherein the first contact and the first A trace is electrically connected, and the first contact is disposed adjacent to the second trace. According to the above, in the game dance display system of the present invention, the thin film transistor base is formed on the first conductive layer to form a trace, and the second conductive layer is formed in a contact point, so that the trace and the contact are formed on different conductive layers. . Compared with the prior art, when the thin film transistor substrate of the present invention is bonded to the wafer, the traces and the contacts are formed on different conductive layers, so that the pins of the wafer are not contacted by the contacts and the traces at the same time. Causes a short circuit. Further, since the contact and the wiring of the present invention are disposed adjacent to each other to form a pin-shaped contact arrangement, the wiring area can be reduced. [Embodiment] A comparative image display system according to the present invention will be described below with reference to the related drawings. Fig. 3A is a top plan view showing a state in which the thin film transistor substrate 3 and the wafer 4 are arranged in a product arrangement, and is in the shape of a contact of Fig. 3a+. Referring to FIG. 3A, the thin film electric two f3 board \ package = 31, a first conductive layer", - the first: the layer M, the second conductive layer 34 and a second insulating layer%, the first guide 7 1358591 is disposed on the substrate 31, the first insulating layer 33 covers the first conductive layer 32, the second conductive layer 34 is disposed on the first insulating layer 33, and the second insulating layer 35 covers the second conductive layer. 34. The towel, one of the second insulating layers % is hollowed out to expose the second conductive layer 34. ° Generally, the substrate 31 may be a substrate, which includes a glass substrate and a buffer layer (or insulating layer) disposed on the glass substrate. The first & electrical layer 32 and the second conductive layer 34 can be used to form data lines or scan lines (or referred to as row or column conductors) on the pixel array.帛2 insulation layer 3 • is a flat layer. In this embodiment, a plurality of first traces 3 " 21 and a plurality of second traces 322 are formed on the first conductive layer 32, and a plurality of first contacts 341 and a plurality of seconds are formed on the second conductive layer 34. a contact 342, wherein each of the first points (4) is electrically connected to one of the first and second traces, and each of the second contacts is electrically connected to one of the second traces 322, and the first contact 341 is electrically connected. The first = trace 322 is adjacently disposed 'the second contact 342 is adjacent to the first trace 321 φ setting. The trace 321 and the first trace 322 are electrically connected to the data line or the scan line formed on the pixel array. The first contact 341 and the second contact 342 are connected to the pin 41 of the crystal. The wafer 4 can be electrically connected to the data line or the scan line on the pixel array, and the wafer 4 can drive the pixel array. In addition, the thin film transistor substrate 3 has a plurality of first-conducting plugs (Fig. a second conductive plug (not shown), the conductive traces are placed between the first conductive layer 32 and the second conductive layer %, and the first conductive plugs are electrically connected to the first contact 341 and the first One of the traces 321 , each of the 8 1358591 two conductive plugs are electrically connected to the second contact 342 and the second trace 322 of which one - 〇..· bearing, because the first contact 341 and the second The wires 322 are disposed adjacent to each other, and the second contacts 342 are disposed adjacent to the first wires 321 so that the first contacts 341 and the second contacts 342 are in a font shape and are connected in a contact manner. A larger number of traces and contacts can be accommodated in a unit area, thereby reducing the area of the line configuration and reducing the size of the image display system. Further, when the wiring of the thin film transistor substrate 3 of the present invention is bonded to the external wafer 4, only the contact point exists in the second conductive layer 34 bonded to the wafer 4, so that it is affected by any factor. When the wafer 4 is displaced, the pins 41 in the wafer 4 can only be electrically connected to the corresponding contacts, so that the pins 41 do not cause a short circuit due to contact with the traces. In this embodiment, The thin film transistor substrate 3 can be used as a matrix array substrate of a matrix display panel. If the matrix display panel is an organic light emitting diode panel, the row and column wires are formed on the thin film transistor substrate 3. The external system is formed with a halogen driving circuit and an organic light emitting diode, and the halogen® driving circuit electrically connects the row and the column wires to drive the organic light emitting diode. Further, if the matrix display panel is a liquid crystal display panel, The matrix display panel further comprises another opposite substrate and a liquid crystal layer disposed between the thin film transistor substrate 3 and the opposite substrate. The thin film transistor substrate 3 is formed on the line. A halogen drive circuit is formed outside the column conductor to drive the liquid crystal layer. The liquid crystal display panel can be a twisted nematic (TN), multi-domain vertical alignment (Multi-domain Vertical Alignment ' 9 1358591 MVA ), horizontal In-Plane Switching (IPS), Edge Power: Fringe-Fiele Switching (FFS), Active Matrix Filter, Transmissive, Reflective or Semi-Transverse (Ding ransflective) and other forms. Generally, a liquid crystal display panel that requires an active light source to display an image is combined with a backlight module to form a liquid crystal display device, and the backlight module outputs a light to the liquid crystal display panel to cause the liquid crystal display panel to display an image. The image display system 5 of the present invention includes an electronic device 51 having a matrix display panel 511 and an input unit 512, wherein the matrix display panel is shown in FIG. 511 has a thin film transistor substrate 5111. The thin film transistor substrate 51u is a thin film transistor substrate 3 of the foregoing embodiment, and the details and embodiments thereof have been discussed in the foregoing embodiments, and are not described herein again. The matrix display panel 511 may be a liquid crystal display panel of the above-described multi-quadrant vertical alignment, lateral electric field drive, edge electric field drive, active matrix light guide, transmissive or transflective, input unit 512 and matrix The display panel 511 is coupled and provides an input to the matrix display panel 511 to cause the matrix display panel 511 to display an image. In this embodiment, the electronic device 5 is a mobile phone, a digital camera, a personal digital assistant, a notebook computer, a desktop computer, a television, a car display, a head-mounted display, a printer screen, and an MP3 player. , palm-type games, DVD players, etc. In summary, the image display system substrate according to the present invention forms a trace on the first conductive layer, and forms a body on the second conductive layer: body 1358591 such that the traces and contacts are formed on different conductive layers. Compared with the prior art, when the thin film transistor substrate of the invention is bonded to the wafer, the traces and the contacts are formed on different conductive layers, so that the pins of the wafer are not contacted by the contacts at the same time. A short circuit caused by a trace. Further, since the contact of the present invention and the trace are disposed adjacent to each other to form a pin-shaped connection and a 舜 arrangement, the wiring area can be reduced. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a side elevational view of a conventional thin film transistor substrate and a wafer in a one-to-one contact arrangement; FIG. 1B is a top plan view of a trace and a contact shape in FIG. 1A; 2A is a side view of a conventional thin film transistor substrate and a wafer in a pin-shaped contact arrangement, and FIG. 2B is a top plan view of the shape of the trace and the contact in FIG. 2A; FIG. 3A is a schematic view of the present invention. Figure 3B is a top plan view of the shape of the traces and contacts in Figure 3A; and Figure 4 is a top view of the shape of the traces and contacts in Figure 3A; A block diagram of an image display system of a preferred embodiment. 11 1358591
元件符號說明： 1 薄膜電晶體基板 11 基板 12 絕緣層 13 導電層 131 走線 132 接點 14 平坦層 薄膜電晶體基板 13， 導電層 13Γ 走線 132' 接點 2 晶片 21 接腳 T 晶片 2Y 接腳 3 薄膜電晶體基板 31 基板 32 第一導電層 321 第一走線 322 第二走線 33 第一絕緣層 34 第二導電層 341 第一接點 342 第二接點 35 第二絕緣層 4 晶片 41 接腳 5 影像顯示系統 51 電子裝置 511 矩陣式顯示面板 5111 薄膜電晶體基板 512 輸入單元 D 距離 12Description of component symbols: 1 Thin film transistor substrate 11 Substrate 12 Insulation layer 13 Conductive layer 131 Trace 132 Contact 14 Flat layer Thin film transistor substrate 13, Conductive layer 13 Γ Trace 132' Contact 2 Chip 21 Pin T Chip 2Y Foot 3 thin film transistor substrate 31 substrate 32 first conductive layer 321 first trace 322 second trace 33 first insulating layer 34 second conductive layer 341 first contact 342 second contact 35 second insulating layer 4 wafer 41 Pin 5 Image Display System 51 Electronics 511 Matrix Display Panel 5111 Thin Film Transistor Substrate 512 Input Unit D Distance 12