TWI358112B - Packaging substrate and manufacturing method there - Google Patents

Packaging substrate and manufacturing method there Download PDF

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Publication number
TWI358112B
TWI358112B TW096131693A TW96131693A TWI358112B TW I358112 B TWI358112 B TW I358112B TW 096131693 A TW096131693 A TW 096131693A TW 96131693 A TW96131693 A TW 96131693A TW I358112 B TWI358112 B TW I358112B
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TW
Taiwan
Prior art keywords
sub
openings
insulating layer
opening
pads
Prior art date
Application number
TW096131693A
Other languages
Chinese (zh)
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TW200910559A (en
Inventor
Hsiao Chuan Chang
Yi Shao Lai
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Priority to TW096131693A priority Critical patent/TWI358112B/en
Publication of TW200910559A publication Critical patent/TW200910559A/en
Application granted granted Critical
Publication of TWI358112B publication Critical patent/TWI358112B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

1358112 ， ASEK1918 23537twf.doc/n 九、發明說明： . 【發明所屬之技術領域】 θ本發明是有關於一種線路板及其製造方法，且特別 是有關於一種封裝基板及其製造方法。 【先前技術】 近年來’隨著半導體製程技術的不斷成熟與發展， 各種高效能的電子產品不斷推陳出新，而電子產品的功 能朝向人性化與多功能等方面發展，且電子產品内部均 有各種功能不一的積體電路（IC，Integmted Circuit)元 ^。在電子元件的製作過程巾，積體電騎裝扮演著相 當重要的角色’習知的積體電路封裝製程是先將晶片與 ^基板f性連接’而且封裝基板的另—側表面可形成 料塊，以使晶片透過封裝基板電性連接至銲料塊， ，藉由沿焊的方式使銲料塊連接至外部電路板，如印刷 然而，當封裝基板與外部電路板之間 =不2或是外部形狀有差異時，銲料塊會受到應力^ 二’料與線路基板以及與外料路板接合的部 i成銲料塊受到應力時此部份較易斷裂而 成鈈枓塊脫洛以致於積體電路封裝内電性連接失1 也因此降爾裝基板與外料路板·連接的可靠度。’ 【發明内容】 本發明提供-種封裝基板及其製作方法 料塊與基層接合後的結構強度。 了增加銲 5 1358112 ASEK1918 23537twf.d〇c/n 題。本發明提供—種封裝結構，可避免銲料塊脫落的問 供—種電性連接結構，可提升封裝基板與 外邛電路板電性連接的可靠度。 、 為具體說明本發明之内容，在此提出一種封 S料ί主ΐίί;基:面多個接塾、-絕緣層以及。 杆概暴盾具有-表面，而接塾配置於表面上 :覆，面並具有多個開口，且開口可用以暴露出接 料塊輝料塊~別位於開口内，而且絕緣層係部份覆蓋銲 在本發明之—實施例巾，魏層可具有第 絕：:Γ子絕緣層覆蓋表面並具有多個 第子1而苐一子絕緣層覆蓋第一子絕緣 =應於這些第-子開σ的多個第二子開口。第二子開口 子開σ相連以構成開σ，而:每 二:之4=第;子、：所覆蓋。 開口的孔徑。 帛—子開口的孔徑小於第-子 在本發明之一實施例中，笛- (flaShgate) 接其所對應的第二子開口。 的上方’並連 在本發明之一實施例中，相 溢料口可分別位於不同的方位上 一 4 口所連接的 在本發明之一實施例中，基展可具有多個介電層以 1358112 ASEK1918 23537twf.doc/n 及位於兩相鄰介電層之間的至少一線路層。 為具體說明本發明之内容，在此提出一種封裝基板 的製作方法，而此封裝基板的製作方法首先提供一基 層’而基層具有—表面，且表面上配置有多個接墊。^ 著，形成第一絕緣層於表面上。之後，形成多個第一開 口於第-絕緣層中，以暴露出接墊。然後，形成一觀^ 於第一開口中。接著，形成一第二絕緣層於第―: h射第二絕緣層具有對應於上述之第―開口的^ 弟一開口，且第二絕緣層覆蓋每一第一開口中至少部份 的襯層。之後，移除襯層。錢，形成多 一開口及其所對應的第二開口中。 现、弟 侧在本發明之-實施射，移_層的方法包括濕式 f本發明之—實施例中，移除襯層的方法包括水洗。 f本發明之-實施例中，移除襯層的方法包括加熱。 在本發明之一實施例中’封裝基板 括形成多個溢料π於上心帛心,十作万在更包 中’且溢㈣絕緣層 料口分別位於不同^ m’相鄰第二開口所連接的溢 為具體說明本發明之内容 塾封 第二接塾。基層具有第 一接塾配置於第-表面上。絕緣層覆蓋 1358112 ASEK1918 23537twf.doc/n 具有多_口可用以暴露出第—錄。銲料塊分別位於 開=内，而且絕緣層係部份覆蓋銲料塊。第二接墊配置 於第二表面上，並且經由基層電性連接至第一接墊。曰 墊而且這些第三接墊分別電性連: 在本發明之-實關巾，絕緣層包括第—子絕緣層 以及第二子絕緣層。第—子絕緣層覆蓋第—表面並且 iH:子開口。第二子絕緣層覆蓋第-子絕緣 ;，並有對應於封裝結構之第—子開口的多個第二子 ::開分別與其所對應的第-子開口相連以 緣層所覆蓋。母一第一子開口的局部區域被第二子絕 口可月ί—實施例中’第一子開口以及第二子開 開孔’並且第二子開口的孔經小於第-子 實施例中，第二子絕緣層更具有多個 並二對第-子開口的上方， 第—溢料口分別位方::弟二子開口所連接的 結構了 a包發明之内容，在此提出-種電性連接 封裝基板基r 一第二封裝基板。第- 第一基層、多個第一接塾、一第一絕緣 1358112 ASEK1918 23537twf.doc/n 層以及多個第一銲料塊。第一 -接塾則配置於第二二基/具有第-表面’而第 品.0 ^ 弟表面上。第一絕緣層覆蓋第一表 二並弟-絕緣層具有多個第一開口可用以暴露出電 性連接結構之第—接塾。第—銲料塊分難於第一開口 内’而且第—絕緣層係部份覆蓋第-銲料塊。第二封裝 基板包括夕個第二接墊，而且第二接墊分別經由第一 料塊電性連接至第一接墊。1358112, ASEK1918 23537twf.doc/n IX. Description of the Invention: [Technical Field of the Invention] θ The present invention relates to a wiring board and a method of manufacturing the same, and, in particular, to a package substrate and a method of manufacturing the same. [Prior Art] In recent years, with the continuous maturity and development of semiconductor process technology, various high-performance electronic products continue to evolve, and the functions of electronic products are oriented toward humanization and multi-functionality, and various functions are available inside electronic products. Integral circuit (IC, Integmted Circuit) element ^. In the manufacturing process of electronic components, integrated electric riding plays a very important role. [The conventional integrated circuit packaging process is to first connect the wafer to the substrate and the other side of the package substrate can be formed. a block for electrically connecting the wafer to the solder bump through the package substrate, by soldering the solder bump to the external circuit board, such as printing, however, when the package substrate and the external circuit board are not 2 or external When there is a difference in shape, the solder bump is subjected to stress and the soldering block of the circuit substrate and the external material path board is subjected to stress, and the portion is more easily broken to form a block. The electrical connection in the circuit package is lost, so the reliability of the connection between the substrate and the external material board is reduced. SUMMARY OF THE INVENTION The present invention provides a package substrate and a method of fabricating the same. Increased welding 5 1358112 ASEK1918 23537twf.d〇c/n. The invention provides a package structure, which can avoid the problem that the solder bumps fall off, and the electrical connection structure can improve the reliability of the electrical connection between the package substrate and the external circuit board. In order to specifically describe the content of the present invention, a sealing material is proposed herein. The substrate is a plurality of interfaces, an insulating layer, and a plurality of layers. The rod shield has a surface, and the joint is disposed on the surface: the cover has a plurality of openings, and the opening can be used to expose the block of the block block, which is located in the opening, and the insulating layer is partially covered. Soldering in the embodiment of the present invention, the weir layer may have a first:: the braid insulating layer covers the surface and has a plurality of first members 1 and the first insulating layer covers the first sub-insulation = should be opened in these first a plurality of second sub-openings of σ. The second sub-openings are opened σ to form an open σ, and: every two: 4 = the first; the sub, the: covered. The aperture of the opening. The aperture of the pupil opening is smaller than the first sub-port. In one embodiment of the invention, the fla-shear is connected to its corresponding second sub-opening. In the above embodiment, in one embodiment of the present invention, the overflow ports may be respectively connected in different orientations. In one embodiment of the present invention, the base may have a plurality of dielectric layers. 1358112 ASEK1918 23537twf.doc/n and at least one wiring layer between two adjacent dielectric layers. In order to specifically describe the contents of the present invention, a method of fabricating a package substrate is provided. The method of fabricating the package substrate first provides a base layer and the base layer has a surface, and a plurality of pads are disposed on the surface. ^, forming a first insulating layer on the surface. Thereafter, a plurality of first openings are formed in the first insulating layer to expose the pads. Then, a view is formed in the first opening. Next, forming a second insulating layer on the first:-h, the second insulating layer has an opening corresponding to the first opening, and the second insulating layer covers at least a portion of each of the first openings . After that, the liner is removed. The money forms an opening and a corresponding second opening. Now, in the present invention, the method of performing the shot-and-spray layer includes wet-type f. In the embodiment, the method of removing the liner includes water washing. In the embodiment of the invention, the method of removing the liner comprises heating. In one embodiment of the present invention, the 'package substrate includes a plurality of flashes π in the center of the center, and the top of the overflow layer is located in the second opening of the different insulation layers. The connected overflow is a specific description of the present invention and the second interface is sealed. The base layer has a first interface disposed on the first surface. Insulation Coverage 1358112 ASEK1918 23537twf.doc/n has multiple ports available to expose the first record. The solder bumps are respectively located within the open = and the insulating layer partially covers the solder bumps. The second pad is disposed on the second surface and electrically connected to the first pad via the base layer. The pad and the third pads are electrically connected. In the present invention, the insulating layer comprises a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer covers the first surface and the iH: sub-opening. The second sub-insulating layer covers the first sub-insulating; and a plurality of second sub-! openings corresponding to the first sub-openings of the encapsulating structure are respectively connected to the corresponding first sub-openings to be covered by the edge layer. a partial region of the first child opening is blocked by the second sub-portion - the first sub-opening and the second sub-opening in the embodiment, and the hole of the second sub-opening is smaller than in the first sub-embodiment, The second sub-insulating layer further has a plurality of and two pairs of the first sub-openings, and the first overflowing port is respectively located at a position: the structure of the second sub-opening is connected with the contents of the invention, and the electric property is proposed here. Connecting the package substrate base r to a second package substrate. a first first substrate, a plurality of first interfaces, a first insulating 1358112 ASEK1918 23537twf.doc/n layer and a plurality of first solder bumps. The first - interface is disposed on the second base/having a first surface and on the surface of the first product. The first insulating layer covers the first surface and the second insulating layer has a plurality of first openings for exposing the first connection of the electrical connection structure. The first solder bump is difficult to be in the first opening and the first insulating layer partially covers the first solder bump. The second package substrate includes a second pad, and the second pads are electrically connected to the first pads via the first block respectively.

在本發明之一實施例中，第一絕緣層包括第一子絕 緣層以及第二子絕緣層。第一子絕緣層覆蓋第一表面， 並且具有多個第一子開口。第二子絕緣層覆蓋第—子絕 緣層，並具有對應於電性連接結構之第一子開口的多^ 第二子開口。第二子開口分別與其所對應的第一子開口 相連以構成第一開口，而且每一第一子開口的局部區域 被第二子絕緣層所覆蓋。In an embodiment of the invention, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer covers the first surface and has a plurality of first sub-openings. The second sub-insulating layer covers the first sub-insulating layer and has a plurality of second sub-openings corresponding to the first sub-openings of the electrical connection structure. The second sub-openings are respectively connected to their corresponding first sub-openings to form a first opening, and a partial area of each of the first sub-openings is covered by the second sub-insulating layer.

在本發明之一實施例中，第一子開口以及第二子開 口可分別為一圓孔，並且第二子開口的孔徑小於第—子 開口的孔徑。 在本發明之一實施例中’第二子絕緣層可具有多個 第一溢料口’第一溢料口分別位於第一子開口的上方並 連接第一子開口所對應的第二子開口。 在本發明之一實施例中，相鄰第二子開口所連接的 第一溢料口分別位於不同的方位上。 在本發明之一實施例中，第一基層包括多個介電層 以及位於兩相鄰介電層之間的至少一線路層。 在本發明之一實施例中，第二封裝基板更包括一第 ASEK1918 23537twf.d〇c/n 緣Γ及多個第二銲料塊。第二基層 % -^ 且第一接墊配置於第二表面上。 弟二 =覆盍弟二表面並具有 一開口可用以最霡屮筮_祕血 叩1弟 二開口内。第1^；·墊°第二銲料塊分別位於第 二丄層係部份覆蓋第二銲料塊，而且第 封裝基板上的第-銲料塊對應接合。 在本發明之一實施例中，第二锅续爲七贫一 緣層:及ΐ:子絕緣層。第三子:緣層；;第二= :有：個第三子開口。第四子絕緣層覆蓋第三子、絕緣 層=具有對應於電性連接結構之第三子開口的多個第 第四子開口分別與其所對應的第三子開口 才目連=構成弟二開π ’且每—第三子開口的局部區域被 第四子絕緣層所覆蓋。 林發明之-實施例中，第三子開口以及第四子開 二可为別為-®孔，*且第时開口的孔鮮於第三子 開口的孔控。 在本發明之一實施例中’第四子絕緣層更具有多個 第-溢料口，而且第二溢料口分別位於第三子開口的上 方並連接第三子開口所對應的第四子開口。 〜在本發明之-實施例中，相鄰第四子開口所連接的 第一溢料口分別位於不同的方位上。 在本發明之一實施例中，第二基層包括多個介電層 以及位於兩相鄰介電層之間的至少一線路層。 絲上所述，本發明之絕緣層可增加銲料塊與基層接 合後的結構強度，使銲料塊受到應力時不易脫落'。而且， 1358112 ASEK1918 23537twf.doc/n : 本發明之溢料口有助於銲料塊填滿絕緣層的開口。 . ㈣ί讓本發明之上述和其他目的、特徵和優點能更明 』易《 ’下域舉實關，並配合_圖式，作 明如下。 ' 【實施方式】 ^1為本發明一實施例之封裝基板的剖面圖。 Φ 請參照圖1，本實施例之封裝基板100包括—基層 no、—絕緣層12〇、多個接墊130a以及多個銲二^ 130b，其中，接墊13〇a及銲料塊13〇b可做為封裝基板 1〇〇與外部電路板（未繪示）電性連接的接點130。為簡 化起見，圖1只繪示一個接點130，然本發明並不限定二 此。基層110具有一表面112。基層110可以是—般的線 路基層，例如是單層的線路基層或者是多層的線路基 層，若基層110為多層的線路基層則可包括多個介電層 (未繪示）以及位於兩相鄰介電層之間的至少一線路戶 參 （未繪示）。接墊130a配置於表面112上。絕緣層ι2θ〇 覆盍表面112’並具有多個開口 120a可用以暴露接墊 13〇a。絕緣層120的材質可以是感光材料。銲料塊13% 分別位於開口 12〇a内，而且絕緣層120部分覆蓋銲料境 130b。 承上所述’由於絕緣層120部分覆蓋銲料塊13〇b， 因此可藉由絕緣層120的支撐，即絕緣層120與録料塊 130b的卡鎖結構，來增加銲料塊130b與基層no接合後 的結構強度，使銲料塊130b受到應力時不易脫落。將此 11 1358112 ASEK1918 23537tw£doc/n 封裝基板1GG應祕積體電闕裝時，也有助於改善整 體積體電路魏中元件接合的可靠度，而以下將詳細介 紹形成絕緣層120的其中一種方法。 2A〜圖2F為本發明—實施例之絕緣層的製作流 • 程剖面圖。 •、形成絕緣層120的方法例如如圖2A至圖2F所示。 首先’請參照圖2A’提供—基層u〇以及多個接塾， % 但為簡化起見’圖2A只纟會示-個接塾13Ga，然本發明並 不限定於此。基層110具有—表面112，而且接塾i3〇a 配置於表面112上。接著，請參關2B，形成__絕緣層 122於表面112上。請參照圖2C，形成多個開口 122a於 絕緣層122中以暴露出接塾13〇a。當絕緣層122的材質 為感光材料時’可祕光顯影的方式形成開口 122a。形 成開口 122a的方法還包括微影姓刻。然後，請參照圖 2D，形成一襯層14〇於開口咖中。襯層14〇的材質例 如是有機材料。 .之後’請參照® 2E，形成絕緣層124於絕緣層122 上，並且形成多個開口 124a於絕緣層124中，而且開口 124a對應於開π 122a。絕緣層124覆蓋每—開口咖 中至少部分的襯層14〇。開口 122a以及開口 ma分別例 如為一圓孔’而且開口 124a的孔徑小於開口 l22a的孔 徑。絕緣層120包括絕緣層122以及絕緣層124，而開口 120a包括開口 122a以及開口 124a。當絕緣層124的材質 . 為感光材料時，可用曝光顯影的方式形成開口 124a。形 成開口 12如的方法還包括微影蝕刻。然後，請參考圖2F， 12 1358112 • ASEK1918 23537twf.doc/n ： 移除襯層140。移除襯層140的方法包括加熱、濕式蝕刻 • 以及水洗’而且當襯層的材質為有機材料可二 由有機材料具有受熱揮發的特性來移除襯層14〇。 Θ 圖3A為本發明一實施例之封裝基板上的接點陣列 示意圖，而圖3B為圖3A中Μ線段的剖面圖。 上述封裝基板100可具有多種不同的結構，在本實 施例中例舉其中一種結構做說明，如圖3Α與圖3β所示= 本實施例之封裝基板300的絕緣層124還可具有多個溢 • 料口 124b，而溢料口 124b分別位於開口 122a的上方， 且溢料口 124b連接其所對應的開口 124a。相鄰的開口 124a所連接的溢料口 124b分別位於不同的方位上。開口 • 12〇a更包括溢料口 124b。 承上所述’本發明的溢料口 124b可於銲料塊i30b 填入開口 120a時，將開口 120a内的空氣排出，故溢料口 124b有助於銲料塊130b填滿開口 12〇a。而且，相鄰的 開口 124a所連接的溢料口 124b分別位於不同的方位 # 上’因此可避免相鄰的開口 124a所連接的溢料口 124b 太過接近而使得溢料口 124b内的多餘的熔融銲料溢流而 與鄰近的溢料口 124b内的多餘的熔融銲料相接而造成積 體電路封裝短路的情形發生，而且可以使銲塾間之設計 距離更為縮小。 圖4為本發明一實施例之封裝結構的剖面圖。 上述封裝基板300可與晶片接合做為晶片承載器， 封裝結構如圖4所示，本實施例之封裝結構4〇〇包括一 封裝基板410、一晶片420以及一封裝膠體430。封裝基 13 1358112 ASEK1918 23537twf.doc/n 板410與封裝基板300類似，差別之處在於封裝基板 的基層lio具有與表面112相對應的表面114，而且多個 接摯132a配置在表面114上並經由基層11〇電性連接至 接墊130a。晶片420包括多個接墊422&以及多個銲料塊 422b。接墊422a與銲料塊422b可做為晶片42〇與封裝 基板410電性連接的接點422。銲料塊42沘分別配置於 接墊422a上，且接墊422a分別藉由其上的銲料塊幻沘In an embodiment of the invention, the first sub-opening and the second sub-opening may each be a circular hole, and the aperture of the second sub-opening is smaller than the aperture of the first sub-opening. In an embodiment of the present invention, the second sub-insulating layer may have a plurality of first overflow openings. The first overflow openings are respectively located above the first sub-openings and connect the second sub-openings corresponding to the first sub-openings. . In an embodiment of the invention, the first overflow ports to which the adjacent second sub-openings are connected are respectively located in different orientations. In an embodiment of the invention, the first base layer includes a plurality of dielectric layers and at least one wiring layer between the two adjacent dielectric layers. In an embodiment of the invention, the second package substrate further includes a first ASEK1918 23537twf.d〇c/n edge and a plurality of second solder bumps. The second base layer % -^ and the first pad is disposed on the second surface. Brother II = Covering the two faces of the younger brother and having an opening available for the most embarrassing _ secret blood 叩 1 brother two openings. The second solder bumps are respectively located on the second germanium layer portion to cover the second solder bumps, and the first solder bumps on the first package substrate are bonded to each other. In one embodiment of the invention, the second pot continues to be a seven-poor edge layer: and a tantalum: sub-insulator layer. The third child: the edge layer; the second =: there is: a third child opening. The fourth sub-insulating layer covers the third sub-insulation layer; the plurality of fourth sub-openings having the third sub-opening corresponding to the electrical connection structure respectively are connected to the corresponding third sub-openings A partial region of π 'and every - third sub-opening is covered by a fourth sub-insulating layer. In the embodiment of the invention, the third sub-opening and the fourth sub-opening may be other holes, and the first opening is fresher than the third sub-opening. In an embodiment of the present invention, the fourth sub-insulating layer further has a plurality of first overflow ports, and the second overflow openings are respectively located above the third sub-openings and connected to the fourth sub-port corresponding to the third sub-openings. Opening. In the embodiment of the invention, the first overflow ports to which the adjacent fourth sub-openings are connected are respectively located in different orientations. In an embodiment of the invention, the second substrate comprises a plurality of dielectric layers and at least one wiring layer between the two adjacent dielectric layers. As described above, the insulating layer of the present invention can increase the structural strength of the solder bump after bonding with the base layer, so that the solder bump does not easily fall off when subjected to stress. Moreover, 1358112 ASEK1918 23537twf.doc/n: The overflow opening of the present invention helps the solder block fill the opening of the insulating layer. (d) The above and other objects, features and advantages of the present invention will be made clearer by the following paragraphs, and in conjunction with the _ schema, as follows. [Embodiment] ^1 is a cross-sectional view of a package substrate according to an embodiment of the present invention. Φ Referring to FIG. 1, the package substrate 100 of the present embodiment includes a base layer no, an insulating layer 12A, a plurality of pads 130a, and a plurality of solder pads 130b, wherein the pads 13a and the solder bumps 13b It can be used as a contact 130 for electrically connecting the package substrate 1 to an external circuit board (not shown). For the sake of simplicity, Figure 1 shows only one contact 130, although the invention is not limited thereto. The base layer 110 has a surface 112. The base layer 110 may be a general circuit base layer, for example, a single-layer circuit base layer or a multi-layer circuit base layer. If the base layer 110 is a multi-layered circuit base layer, the plurality of dielectric layers (not shown) may be included and located adjacent to each other. At least one line customer (not shown) between the dielectric layers. The pad 130a is disposed on the surface 112. The insulating layer ι2θ〇 covers the surface 112' and has a plurality of openings 120a for exposing the pads 13〇a. The material of the insulating layer 120 may be a photosensitive material. The solder bumps 13% are respectively located in the openings 12a, and the insulating layer 120 partially covers the solder land 130b. According to the above description, since the insulating layer 120 partially covers the solder bumps 13B, the solder bumps 130b and the base layer no can be joined by the support of the insulating layer 120, that is, the latch structure of the insulating layer 120 and the recording block 130b. The subsequent structural strength makes it difficult for the solder bump 130b to fall off when subjected to stress. When the 11 1358112 ASEK1918 23537 tw doc/n package substrate 1GG is assembled, it also helps to improve the reliability of component bonding in the whole bulk circuit, and one of the formation of the insulating layer 120 will be described in detail below. method. 2A to 2F are cross-sectional views showing the flow of the insulating layer of the present invention. • A method of forming the insulating layer 120 is, for example, as shown in FIGS. 2A to 2F. First, please refer to Fig. 2A', a base layer u〇 and a plurality of interfaces, %. However, for the sake of simplicity, Fig. 2A shows only one interface 13Ga, but the present invention is not limited thereto. The base layer 110 has a surface 112, and the interface i3〇a is disposed on the surface 112. Next, please refer to 2B to form __ insulating layer 122 on surface 112. Referring to FIG. 2C, a plurality of openings 122a are formed in the insulating layer 122 to expose the contacts 13A. When the material of the insulating layer 122 is a photosensitive material, the opening 122a is formed in a manner of secret light development. The method of forming the opening 122a also includes lithography. Then, referring to Fig. 2D, a lining layer 14 is formed in the opening coffee. The material of the lining 14 例 is, for example, an organic material. Thereafter, please refer to ® 2E to form an insulating layer 124 on the insulating layer 122, and a plurality of openings 124a are formed in the insulating layer 124, and the opening 124a corresponds to the opening π 122a. An insulating layer 124 covers at least a portion of the liner 14 of each of the openings. The opening 122a and the opening ma are, for example, a circular hole ', and the opening 124a has a smaller hole diameter than the opening l22a. The insulating layer 120 includes an insulating layer 122 and an insulating layer 124, and the opening 120a includes an opening 122a and an opening 124a. When the material of the insulating layer 124 is a photosensitive material, the opening 124a may be formed by exposure development. The method of forming the opening 12 as well includes lithography etching. Then, please refer to FIG. 2F, 12 1358112 • ASEK1918 23537twf.doc/n: The liner 140 is removed. The method of removing the liner 140 includes heating, wet etching, and water washing' and when the material of the liner is an organic material, the organic material has a property of being thermally volatilized to remove the liner 14〇. 3A is a schematic view of an array of contacts on a package substrate according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view of a line segment of FIG. 3A. The package substrate 100 may have a plurality of different structures. One of the structures is illustrated in the embodiment, as shown in FIG. 3A and FIG. 3β. The insulating layer 124 of the package substrate 300 of the present embodiment may also have multiple overflows. • Feed port 124b, and overflow port 124b is located above opening 122a, respectively, and overflow port 124b is connected to its corresponding opening 124a. The overflow ports 124b to which the adjacent openings 124a are connected are respectively located in different orientations. Opening • 12〇a also includes overflow port 124b. The overflow port 124b of the present invention can discharge the air in the opening 120a when the solder block i30b is filled in the opening 120a, so that the overflow port 124b helps the solder bump 130b fill the opening 12〇a. Moreover, the overflow openings 124b to which the adjacent openings 124a are connected are respectively located at different orientations #, so that the overflow ports 124b to which the adjacent openings 124a are connected are prevented from being too close to make the excess in the overflow port 124b The molten solder overflows and is connected to the excess molten solder in the adjacent overflow port 124b to cause a short circuit of the integrated circuit package, and the design distance between the solder fillets can be further reduced. 4 is a cross-sectional view showing a package structure in accordance with an embodiment of the present invention. The package substrate 300 can be bonded to a wafer as a wafer carrier. The package structure is as shown in FIG. 4. The package structure 4 of the present embodiment includes a package substrate 410, a wafer 420, and an encapsulant 430. The package base 13 1358112 ASEK1918 23537twf.doc/n The board 410 is similar to the package substrate 300 except that the base layer lio of the package substrate has a surface 114 corresponding to the surface 112, and the plurality of interfaces 132a are disposed on the surface 114 and via The base layer 11 is electrically connected to the pad 130a. The wafer 420 includes a plurality of pads 422 & and a plurality of solder bumps 422b. The pad 422a and the solder bump 422b can serve as a contact 422 for electrically connecting the wafer 42A and the package substrate 410. The solder bumps 42 are respectively disposed on the pads 422a, and the pads 422a are respectively smashed by the solder bumps thereon.

電性連接至接墊132a。封農膠體43〇則配置於晶片42〇 與封裝基板410之間並包覆銲料塊42沘。封裝結構4〇〇 可透過封裝基板410與外部電路板（未繪示）電性連接， 而以下將介紹封裝基板與外部電路板電性連接 電性連接結構。 Χθ 圖5為本發明—實施歉·連接結構的剖面圖。 請參照圖5’本實施例之電性連接結構5〇〇包括封 基板300以及封裝基板51〇。封裝基板51〇具有—基芦 512、一絕緣層514以及多個接墊516a。基層512具有二Electrically connected to the pad 132a. The sealant colloid 43 is disposed between the wafer 42A and the package substrate 410 and covers the solder bump 42. The package structure 4 can be electrically connected to an external circuit board (not shown) through the package substrate 410, and the electrical connection structure of the package substrate and the external circuit board will be described below. Χθ Fig. 5 is a cross-sectional view showing the apology and connection structure of the present invention. Referring to FIG. 5', the electrical connection structure 5 of the present embodiment includes a sealing substrate 300 and a package substrate 51A. The package substrate 51 has a base 512, an insulating layer 514, and a plurality of pads 516a. Base layer 512 has two

表面512a，而接墊516a則配置於表面512a上。絕緣芦 514則覆蓋表面512a，並具有多個開口 51如可暴露出ς 墊516a。接墊516a分別經由銲料塊130b電性連接至接 墊130a。封裝基板51〇例如是封裝基板3〇〇。 赉 綜上所述，由於本發明之絕緣層係部分覆蓋銲 塊’因此可藉由絕緣層的支撐來增加銲料塊與基層 後的結構強度，使銲料塊受到應力時不易脫落。 裝基板應用於積體電路封裝時，也有助於改善整 触 電路封裝中元件接合的可靠度。料，本發明的溢= ii2 ' ASEK1918 23537twf.doc/n 可於鲜料塊填入開口時，將開口内的空氣排出以利銲料 • 塊填滿開口。而且’相鄰的開口所連接的溢料口分別位 於不同的方位上’因此可避免相鄰的開口所連接的溢料 口太過接近而使得溢料口内的多餘的熔融銲料溢流而與 . 鄰近的溢料口内的多餘的熔融銲料相接而造成積體電路 封裝短路的情形發生。 雖…、:本發明已以實施例揭露如上，然其並非用以限 疋^發明，任何熟習此技藝者，在不脫離本發明之精神 和耗圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為本發明一實施例之封裝基板的剖面圖。 Η 2A圖2F為本發明一實施例之絕緣層的製作流 程剖面圖。 圖3Α為本發明一實施例之封裝基板上的接點陣列 φ 示意圖。 圖3Β為圖3Α中I-Ι線段的剖面圖。 圖4為本發明一實施例之封裝結構的剖面圖。 圖5為本發明一實施例之電性連接結構的剖面圖。 【主要元件符號說明】 100、300、410、510 :封裝基板 . 110、512 :基層 112、114、512a :表面 15 1358112 ASEK1918 23537twf.doc/n 130、422 :接點 130a、132a、422a、516a :接墊 120、122、124、514 :絕緣層 120a、122a、124a、514a :開口 124b :溢料口 130b、422b :銲料塊Surface 512a, and pad 516a is disposed on surface 512a. The insulating reed 514 covers the surface 512a and has a plurality of openings 51 such as to expose the pad 516a. The pads 516a are electrically connected to the pads 130a via solder bumps 130b, respectively. The package substrate 51 is, for example, a package substrate 3A. In summary, since the insulating layer of the present invention partially covers the solder bumps, the structural strength after the solder bumps and the base layer can be increased by the support of the insulating layer, so that the solder bumps are less likely to fall off when subjected to stress. When the substrate is mounted on an integrated circuit package, it also contributes to improving the reliability of component bonding in the integrated circuit package. The overflow of the present invention = ii2 ' ASEK1918 23537twf.doc/n can be used to drain the air in the opening when the fresh block is filled in the opening to fill the opening. Moreover, the 'overflow openings connected to the adjacent openings are located in different orientations', so that the overflow ports connected by the adjacent openings are prevented from being too close to overflow the excess molten solder in the overflow port. The excess molten solder in the adjacent overflow port is connected to cause a short circuit of the integrated circuit package. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention. Any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a package substrate according to an embodiment of the present invention. 2A and 2F are cross-sectional views showing a process of manufacturing an insulating layer according to an embodiment of the present invention. 3 is a schematic view of a contact array φ on a package substrate according to an embodiment of the invention. Figure 3 is a cross-sectional view of the I-Ι line segment of Figure 3A. 4 is a cross-sectional view showing a package structure in accordance with an embodiment of the present invention. Figure 5 is a cross-sectional view showing an electrical connection structure in accordance with an embodiment of the present invention. [Main component symbol description] 100, 300, 410, 510: package substrate. 110, 512: base layer 112, 114, 512a: surface 15 1358112 ASEK1918 23537twf.doc/n 130, 422: contacts 130a, 132a, 422a, 516a : pads 120, 122, 124, 514: insulating layers 120a, 122a, 124a, 514a: openings 124b: overflow ports 130b, 422b: solder bumps

140 :襯層 400 :封裝結構 420 :晶片 430 :封裝膠體 500 :電性連接結構140 : lining 400 : package structure 420 : wafer 430 : encapsulant 500 : electrical connection structure

1616

Claims (1)

1358112 ^年η月β日修(更)正本 100-1Μ7 十、申請專利範圍： 1. 一種封裝基板，包括： 一基層，具有一表面； 多個接墊，配置於該表面上； 一絕緣層，覆蓋該表面，並具有多個開口，用以暴 露出該些接墊；以及 多個銲料塊，分別位於該些開口内，其中該絕緣層 係部份覆蓋該些銲料塊。 2. 如申請專利範圍第1項所述之封裝基板，其中該 絕緣層包括： 一第一子絕緣層，覆蓋該表面，並具有多個第一子 開口；以及 一第二子絕緣層，覆蓋該第一子絕緣層，並具有對 應於該些第一子開口的多個第二子開口，其中該些第二 子開口分別與其所對應的該些第一子開口相連以構成該 些開口，且每一第一子開口的局部區域被該第二子絕緣 層所覆蓋。 3. 如申請專利範圍第2項所述之封裝基板，其中該 些第一子開口以及該些第二子開口分別為一圓孔，且該 些第二子開口的孔徑小於該些第一子開口的孔徑。 4. 如申請專利範圍第2項所述之封裝基板，其中該 第二子絕緣層更具有多個溢料口，分別位於該些第一子 開口的上方，並連接其所對應的該些第二子開口。 5. 如申請專利範圍第4項所述之封裝基板，其中相 鄰該些第二子開口所連接的該些溢料口分別位於不同的 17 1358112 100-11-17 方位上。 美/勺^申請專利龍第1項所述之封裝基板，其中該 土ί^ΐ 電層以及位於兩相鄰介電層之間的至少 一線路層。 7. —種封裝基板的製作方法，包括： 提供—基層，該基層具有一表面， 有多個接塾； 且該表面上配置 形成一第一絕緣層於該表面上； 些接=成多個第—開σ於該第―絕緣層中，以暴露出該 形成一襯層於該些第一開口中； 形成一第二絕緣層於該第一絕緣層上，豆 絕緣層具有對應於該些第—開σ的多;β /二 第二一第一開口中至少部份的:層;… 移除該襯層；以及 形成多個銲料塊於該些第一開口 第二開π中。 *㈣及其所對應的該些 8·如申請專利範圍第7項所述 法，其中歸魏層的方法包_核|。基板的衣作方 9. 如申請專利範圍第7項所述之Χ 法’其中移除該襯層的方法包括水洗。f反的製作方 10. 如申請專利範圍第7項所述之 法’其中移除該襯層的方法包括加熱。、板的4作方 11. 如申請專利範圍第7項所述之 法，更包括形成多個溢料口於該些第〜v土板的衣作方 一〜開口的上方的該 18 100-11-17 100-11-17 第一絕緣層中 第二開口。 且該些溢料口分別連接其所對應的該些 ' 如申請專利範圍第7項所述之封裝基板的製作方 法，，、中相鄰該些第二開口所連接的該些溢料口分別位 於不同的方位上。 13.—種封裝結構，包括： 封裝基板，包括： 一基層，具有一第一表面及相對之一第二表面； 多個第一接墊’配置於該第一表面上； —絕緣層，覆蓋該第一表面，並具有多個開口， 用以暴露出該些第一接墊； 多個銲料塊，分別位於該些開口内，其中該絕 緣層係部份覆蓋該些銲料塊；以及 多個第二接墊，配置於該第二表面上，並經由 該基層電性連接至該些第一接墊；以及 一晶片，包括多個第三接墊，且該些第三接墊分別 電性連接至該些第二接墊。 14.如申請專利範圍第13項所述之封裝結構，其中 該絕緣層包括： 一第一子絕緣層，覆蓋該第一表面，並具有多個第 —子開口；以及 一第二子絕緣層，覆蓋該第一子絕緣層，並具有對 應於該些第—子開口的多個第二子開口，其中該些第二 2開口为別與其所對應的該些第〆子開口相連以構成該 二開口，且每—第一子開口的局部區域被該第二子絕緣 1358112 100-11-17 層所覆蓋。 利顧第Μ销叙料結構，並中 t:r:rr該些第二子開口分別為-圓孔，、且 徑小於該些第—子如的孔徑。 ，.如中請專利範圍第14項所述之封裝結構，盆中 :弟；層更具有多個第一溢料口，分別位於該此 第一子開口的上方，並連接其所對應的該此 一 17. 如申請專利範圍第16項所述之魄^構；^中° 二子開口所連接的該些第—溢料口分職於 不同的方位上。 18. 如申請專利範圍第13項所述之封裝結構，其中 該基層包括多個介電層以及位於兩相鄰介電層之間的至 少一線路層。 19. 一種電性連接結構，包括： 一第一封裝基板，包括： 一第一基層，具有一第一表面； 多個第一接墊，配置於該第一表面上； 々一第一絕緣層，覆蓋該第一表面，並具有多個 第一開口，用以暴露出該些第一接墊； 多個第一銲料塊，分別位於該些第一開口内， 其中該第―絕緣層係部份覆蓋該些第-鮮料塊；以 及 一第二封裝基板，包括多個第二接墊，且該些第二 接墊分別經由該些第—銲料塊電性連接至該些第一接 墊0 20 1358112 100-11-17 20. 如申請專利範圍第19項所述之電性連接結構， 其中該第一絕緣層包括： 一第一子絕緣層，覆蓋該第一表面，並具有多個第 一子開口；以及 一第二子絕緣層，覆蓋該第一子絕緣層，並具有對 應於該些第一子開口的多個第二子開口，其中該些第二 子開口分別與其所對應的該些第一子開口相連以構成該 些第一開口，且每一第一子開口的局部區域被該第二子 絕緣層所覆蓋。 21. 如申請專利範圍第20項所述之電性連接結構， 其中該些第一子開口以及該些第二子開口分別為一圓 孔，且該些第二子開口的孔徑小於該些第一子開口的孔 徑。 22. 如申請專利範圍第20項所述之電性連接結構， 其中該第二子絕緣層更具有多個第一溢料口，分別位於 該些第一子開口的上方，並連接其所對應的該些第二子 開口。 23. 如申請專利範圍第22項所述之電性連接結構， 其中相鄰該些第二子開口所連接的該些第一溢料口分別 位於不同的方位上。 24. 如申請專利範圍第19項所述之電性連接結構， 其中該第一基層包括多個介電層以及位於兩相鄰介電層 之間的至少一線路層。 25. 如申請專利範圍第19項所述之電性連接結構， 其中該第二封裝基板更包括： 21 1358112 100-11-17 一第二基層，具有一第二表面，且該些第二接塾配 置於該第二表面上； ' 一第二絕緣層，覆蓋該第二表面，並具有多個第二 開口，用以暴露出該些第二接墊；以及 多個第二銲料塊，分別位於該些第二開口内，其中 該第二絕緣層係部份覆蓋該些第二銲料塊，且該些第二 銲料塊與該第一封裝基板上的該些第一銲料塊對應接 合。 • 26.如申請專利範圍第25項所述之電性連接結構， 其中該第二絕緣層包括： 一第三子絕緣層，覆蓋該第二表面，並具有多個第 三子開口；以及 一第四子絕緣層，覆蓋該第三子絕緣層，並具有對 應於該些第三子開口的多個第四子開口，其中該些第四 子開口分別與其所對應的該些第三子開口相連以構成該 些第二開口，且每一第三子開口的局部區域被該第四子 | 絕緣層所覆蓋。 27. 如申請專利範圍第26項所述之電性連接結構， 其中該些第三子開口以及該些第四子開口分別為一圓 孔，且該些第四子開口的孔徑小於該些第三子開口的孔 徑。 28. 如申請專利範圍第26項所述之電性連接結構， 其中該第四子絕緣層更具有多個第二溢料口，分別位於 該些第三子開口的上方，並連接其所對應的該些第四子 . 開口。 . 29.如申請專利範圍第28項所述之電性連接結構， 22 13581121358112^年η月月日修(more)本本100-1Μ7 X. Patent application scope: 1. A package substrate comprising: a base layer having a surface; a plurality of pads disposed on the surface; an insulating layer Covering the surface and having a plurality of openings for exposing the pads; and a plurality of solder bumps respectively located in the openings, wherein the insulating layer partially covers the solder bumps. 2. The package substrate of claim 1, wherein the insulating layer comprises: a first sub-insulating layer covering the surface and having a plurality of first sub-openings; and a second sub-insulating layer covering The first sub-insulating layer has a plurality of second sub-openings corresponding to the first sub-openings, wherein the second sub-openings are respectively connected to the corresponding first sub-openings to form the openings. And a partial area of each of the first sub-openings is covered by the second sub-insulating layer. 3. The package substrate of claim 2, wherein the first sub-openings and the second sub-openings are respectively a circular hole, and the second sub-openings have a smaller aperture than the first sub-openings The aperture. 4. The package substrate of claim 2, wherein the second sub-insulating layer further has a plurality of overflow openings respectively located above the first sub-openings and connected to the corresponding ones The second child opens. 5. The package substrate of claim 4, wherein the overflow ports adjacent to the second sub-openings are respectively located at different orientations of 17 1358112 100-11-17. The package substrate according to the first aspect of the invention, wherein the earth layer and the at least one circuit layer between the two adjacent dielectric layers. 7. A method of fabricating a package substrate, comprising: providing a base layer having a surface having a plurality of interfaces; and wherein the surface is configured to form a first insulating layer on the surface; a first opening σ in the first insulating layer to expose the liner to form the first openings; forming a second insulating layer on the first insulating layer, the bean insulating layer having corresponding to the a plurality of first-opening σ; a second layer of the second/first second opening: a layer; a layer; a plurality of solder bumps are formed in the second opening π of the first openings. *(d) and the corresponding ones. 8. The method described in item 7 of the patent application, in which the method of the Wei layer is _core|. The substrate of the substrate is as described in claim 7 wherein the method of removing the liner comprises water washing. The maker of the f-reverse 10. The method of claim 7 wherein the method of removing the liner comprises heating. The method of claim 4, wherein the method of claim 7 further comprises forming a plurality of overflow ports on the clothes of the first to v soil plates, the 18 100- 11-17 100-11-17 The second opening in the first insulation layer. And the overflow ports are respectively connected to the manufacturing method of the package substrate as described in claim 7, wherein the overflow ports respectively connected to the second openings are respectively Located in different orientations. 13. A package structure, comprising: a package substrate, comprising: a base layer having a first surface and a second surface; a plurality of first pads ′ disposed on the first surface; — an insulating layer covering The first surface has a plurality of openings for exposing the first pads; a plurality of solder bumps are respectively located in the openings, wherein the insulating layer partially covers the solder bumps; and a second pad disposed on the second surface and electrically connected to the first pads via the base layer; and a wafer including a plurality of third pads, wherein the third pads are respectively electrically Connect to the second pads. 14. The package structure of claim 13, wherein the insulating layer comprises: a first sub-insulating layer covering the first surface and having a plurality of first sub-openings; and a second sub-insulating layer Covering the first sub-insulating layer and having a plurality of second sub-openings corresponding to the first sub-openings, wherein the second second openings are connected to the corresponding first dice openings to form the A second opening, and a partial area of each of the first sub-openings is covered by the second sub-insulation 1358112 100-11-17 layer. The second pin opening is respectively a round hole, and the diameter is smaller than the apertures of the first sub-like. The package structure described in claim 14 of the patent scope, wherein the layer further has a plurality of first overflow openings respectively located above the first sub-opening and connected to the corresponding one of the first sub-openings In the case of claim 16, the plurality of overflow ports connected to the two sub-openings are assigned to different orientations. 18. The package structure of claim 13, wherein the base layer comprises a plurality of dielectric layers and at least one circuit layer between the two adjacent dielectric layers. An electrical connection structure, comprising: a first package substrate, comprising: a first base layer having a first surface; a plurality of first pads disposed on the first surface; a first insulating layer Covering the first surface and having a plurality of first openings for exposing the first pads; a plurality of first solder bumps respectively located in the first openings, wherein the first insulating layer portion And the second package substrate includes a plurality of second pads, and the second pads are electrically connected to the first pads via the first solder pads 20. The electrical connection structure of claim 19, wherein the first insulating layer comprises: a first sub-insulating layer covering the first surface and having a plurality of a first sub-opening; and a second sub-insulating layer covering the first sub-insulating layer and having a plurality of second sub-openings corresponding to the first sub-openings, wherein the second sub-openings respectively correspond to The first sub-openings are connected to form the first An opening, and a partial area of each of the first sub-openings is covered by the second sub-insulating layer. The electrical connection structure of claim 20, wherein the first sub-openings and the second sub-openings are respectively a circular hole, and the second sub-openings have a smaller aperture than the first ones The aperture of the sub-opening. The electrical connection structure of claim 20, wherein the second sub-insulating layer further has a plurality of first overflow openings respectively located above the first sub-openings and connected thereto The second sub-openings. 23. The electrical connection structure of claim 22, wherein the first overflow ports connected to the second sub-openings are respectively located in different orientations. 24. The electrical connection structure of claim 19, wherein the first base layer comprises a plurality of dielectric layers and at least one circuit layer between the two adjacent dielectric layers. 25. The electrical connection structure of claim 19, wherein the second package substrate further comprises: 21 1358112 100-11-17 a second base layer having a second surface, and the second connections塾 disposed on the second surface; a second insulating layer covering the second surface and having a plurality of second openings for exposing the second pads; and a plurality of second solder bumps, respectively Located in the second openings, the second insulating layer partially covers the second solder bumps, and the second solder bumps are correspondingly engaged with the first solder bumps on the first package substrate. The electrical connection structure of claim 25, wherein the second insulating layer comprises: a third sub-insulating layer covering the second surface and having a plurality of third sub-openings; a fourth sub-insulating layer covering the third sub-insulating layer and having a plurality of fourth sub-openings corresponding to the third sub-openings, wherein the fourth sub-openings respectively correspond to the third sub-openings corresponding thereto Connected to form the second openings, and a partial area of each of the third sub-openings is covered by the fourth sub-insulating layer. 27. The electrical connection structure of claim 26, wherein the third sub-openings and the fourth sub-openings are respectively a circular hole, and the fourth sub-openings have a smaller aperture than the third The aperture of the sub-opening. 28. The electrical connection structure of claim 26, wherein the fourth sub-insulating layer further has a plurality of second overflow openings respectively located above the third sub-openings and connected to the corresponding The fourth son of the opening. 29. Electrical connection structure as described in claim 28, 22 1358112 100-11-17 其中相鄰該些第四子開口所連接的該些第二溢料口分別 位於不同的方位上。 30.如申請專利範圍第25項所述之電性連接結構， 其中該第二基層包括多個介電層以及位於兩相鄰介電層 之間的至少一線路層。 23100-11-17 wherein the second overflow ports connected to the adjacent fourth sub-openings are respectively located in different orientations. 30. The electrical connection structure of claim 25, wherein the second substrate comprises a plurality of dielectric layers and at least one wiring layer between the two adjacent dielectric layers. twenty three
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