TWI357150B

TWI357150B - Nand flash memory cell array and method of fabrica

Info

Publication number: TWI357150B
Application number: TW96120287A
Authority: TW
Inventors: Chung We Pan; Shou Yu Chang; Tzeng Wen Tzeng; Ching Hung Fu; Chihping Chung
Original assignee: Promos Technologies Inc
Priority date: 2007-06-06
Filing date: 2007-06-06
Publication date: 2012-01-21
Also published as: TW200849563A

Description

1357150 九、發明說明：【發明所屬之技術領域】本發明係有關於一種反及閘型快閃記憶體（NAND flash memory)的製造方法’特別係有關於一種具有自對準製程（self-aligned process)的反及閘型快閃記憶體的製造方法。【先前技術】快閃記憶體(flash memory)具有面積小、省電、高速、耐受性佳和低操作電壓等優點。因此，快閃記憶體係成為例如數位相機、行動電話、印表機、個人數位助理（PDA) 等產品的重要元件。反及閘型快閃記憶體（NAND flash memory)是快閃記憶體的一種類型。反及閘型快閃記憶體的晶胞係彼此連接且排成一陣列，其中僅上述陣列之其中一列的第一個晶胞和最後一個晶胞係分別連接一字元線 (word line)和一位元線(bit-line)。由於上述的結構，反及閘型快閃記憶體可以存取較反或閘型快閃記憶體(NOR flash memory)多的資料(data)。表示反及閘型快閃記憶體具有較大的記憶容篁和較快的再寫入速度(rewriting speed)。反及閘型快閃記憶體係廣泛地用於儲存大量資料，且可做為數位相機或音樂數位檔案播放器（MP3 player)的記憶卡。美國專利號碼US 6,936,885係揭露了一種反及閘型快閃記憶體元件及其製造方法。第la圖為一上視圖，其顯示部分反及閘型快閃記憶體元件的晶胞陣列區。第lb圖係沿1357150 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a NAND flash memory, which is particularly related to a self-aligned process (self-aligned) Process) A method of manufacturing a gate-type flash memory. [Prior Art] Flash memory has the advantages of small area, power saving, high speed, good tolerance, and low operating voltage. Therefore, the flash memory system has become an important component of products such as digital cameras, mobile phones, printers, and personal digital assistants (PDAs). NAND flash memory is a type of flash memory. The cell lines of the gate-type flash memory are connected to each other and arranged in an array, wherein only the first cell and the last cell of one of the arrays are connected to a word line and One bit-line. Due to the above structure, the inverse type flash memory can access more data than the reverse or NOR flash memory. It means that the anti-gate type flash memory has a large memory capacity and a faster rewriting speed. The anti-gate flash memory system is widely used for storing large amounts of data and can be used as a memory card for a digital camera or a music digital file player (MP3 player). U.S. Patent No. 6,936,885 discloses an anti-gate type flash memory device and a method of fabricating the same. Figure la is a top view showing a cell array region partially transmissive to the gate type flash memory device. Lb diagram

Client’s Docket No.: 95146TW TT*s Docket No:0593-A41201-TW/Final/ianchen/070605 5 1357150 第la圖的I-Ι切線的剖面圖，其顯示一快閃記憶體元件。請參考第la和lb圖，字串選擇線(string selection line)圖案Is和接地選擇線(ground selection line)圖案lg本質上係定義字串選擇電晶體(string selection transistor)13和接地選擇電晶體(ground selection transistor)19。複數個晶胞電晶體15和17，形成於主動區2和字元線WP1〜WPn的交又處上。字串選擇電晶體（string selection transistor) 13和接鲁地選擇電晶體（ground selection transistor)19係用來驅動上述列的晶胞15和17。由於這種特殊結構及兩個選擇電晶體13和19，而增加了製程複雜度。此外，習知反及閘型快閃記憶體元件的選擇電晶體13和19係有高精確度需求的問題。1|_種必要的兩精確度必然會增加製程成本。美國專利號碼US 6,885,586係揭露了一種自對準 (self-aligned)的分離閘（split_gate)反及閘型快閃記憶體及其製造方法。首先，沉積一層包括摻雜多晶石夕或多晶石夕化鲁物的導電層。然後，非等向性钱刻上述導電層，以形成用 " 來驅動一列反及閘型快閃記憶體晶胞的選擇閘極。上述習 __ 知反及閘型快閃記憶體的結構係有晶胞之間的間隙寬度太大的問題，會使反及閘型快閃記憶體的尺寸難以降低。因此’需要一種反及閘型快閃記憶體晶胞陣列及其製造方法，以解決習知技術之咼製程成本或製程複雜等缺點。【發明内容】有鑑於此’本發明的目的係減少定義反及閘型快閃記憶體晶胞陣列中選擇電晶體的光罩數目和降低其機台等Client's Docket No.: 95146TW TT*s Docket No:0593-A41201-TW/Final/ianchen/070605 5 1357150 A cross-sectional view of the I-inch line of the first drawing showing a flash memory component. Referring to the first and lb diagrams, the string selection line pattern Is and the ground selection line pattern lg essentially define a string selection transistor 13 and a ground selection transistor. (ground selection transistor) 19. A plurality of unit cell transistors 15 and 17 are formed at the intersection of the active area 2 and the word lines WP1 to WPn. A string selection transistor 13 and a ground selection transistor 19 are used to drive the cells 15 and 17 of the above columns. Due to this special structure and the selection of the two crystals 13 and 19, the process complexity is increased. In addition, the selection of transistors 13 and 19, which are conventionally opposed to gate type flash memory elements, has a problem of high precision requirements. 1|_The necessary two precisions will inevitably increase the cost of the process. U.S. Patent No. 6,885,586 discloses a self-aligned split-gate and gate-type flash memory and a method of fabricating the same. First, a layer of conductive layer comprising doped polycrystalline or polycrystalline slabs is deposited. Then, the anisotropic material engraves the conductive layer to form a selection gate for driving a column of anti-gate type flash memory cells with ". The above structure __ knows that the structure of the gate type flash memory has a problem that the gap width between the unit cells is too large, and the size of the anti-gate type flash memory is hard to be reduced. Therefore, there is a need for an anti-gate type flash memory cell array and a manufacturing method thereof to solve the disadvantages of the conventional process cost or complicated process. SUMMARY OF THE INVENTION In view of the above, the object of the present invention is to reduce the number of masks for selecting a transistor in a reverse-gate type flash memory cell array and to reduce the number of the masks, etc.

Client’s Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianchen/070605 6 1357150 級，以控制製程成本。本發明之另一目的係減少反及閘型快閃記憶體晶胞之間的間隙寬度，其可有效縮小晶片尺寸，且可增加晶片的元件密度。本發明提供一種反及閘型快閃記憶體晶胞陣列，包括：一基板，其包括一主動區；複數個排成一列的晶胞，位於上述主動區上；一第一阻障層，覆蓋上述複數個晶胞和圍繞上述列之各末端的上述主動區；一第一氧化物，沉積於上述複數個晶胞之間的一間隙中，且填充上述間隙；一氧化物間隙壁，形成於沿著上述列之各末端之上述晶胞的侧壁上；一多晶矽間隙壁，形成於上述氧化物間隙壁上，上述多晶矽間隙壁係做為驅動上述列晶胞的一選擇閘極。上述間隙的深寬比（aspect ratio)較佳介於1.8至3.2之間。上述第一氧化物係具有優異的階梯覆蓋能力，可在填充上述晶胞之間的上述間隙時不會有孔洞的形成。在另一實施例中，只密封上述晶胞之間的上述間隙，也可使用較低階梯覆蓋能力的材料。本發明較佳實施例的反及閘型快閃記憶體晶胞陣列，更包括一植入區，其係利用植入預定離子方式形成於圍繞上述列之各末端的上述主動區中；一氧化層，沉積於上述多晶矽間隙壁、上述氧化物間隙壁、部分上述第一阻障層和上述第一氧化物上；一第二阻障層，沉積於上述氧化層上；一層間介電層，沉積於上述第二阻障層上及圍繞上述Client’s Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianchen/070605 6 1357150 level to control process cost. Another object of the present invention is to reduce the gap width between the anti-gate type flash memory cells, which can effectively reduce the size of the wafer and increase the cell density of the wafer. The invention provides an anti-gate type flash memory cell array, comprising: a substrate comprising an active region; a plurality of unit cells arranged in a row, located on the active region; a first barrier layer covering The plurality of unit cells and the active region surrounding each end of the column; a first oxide deposited in a gap between the plurality of unit cells and filling the gap; an oxide spacer formed on A polycrystalline germanium spacer is formed on the sidewall of the unit cell along each end of the column; the polysilicon spacer is formed on the oxide spacer, and the polysilicon spacer is used as a selective gate for driving the column cell. The aspect ratio of the above gap is preferably between 1.8 and 3.2. The first oxide layer has excellent step coverage ability, and the pores can be formed without filling the gap between the unit cells. In another embodiment, only the gap between the unit cells described above may be sealed, and a material having a lower step coverage capability may also be used. The anti-gate type flash memory cell array of the preferred embodiment of the present invention further includes an implanted region formed by implanting a predetermined ion in the active region surrounding each end of the column; a layer deposited on the polysilicon spacer, the oxide spacer, a portion of the first barrier layer and the first oxide; a second barrier layer deposited on the oxide layer; an interlayer dielectric layer, Deposited on the second barrier layer and surrounding the above

Client’s Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianchen/070605 1357150 列之各末端的上述主動區上；一接觸孔插塞，其利用沉積一插塞材料於位於上述列各末端的一開口中，再利用一化學機械研磨製程平坦化上述插塞材料的方式形成；一金屬線，形成於上述接觸孔插塞上；一金屬層間介電層’形成於不同之上述金屬線之間。此外，上述第一阻障層和上述第二阻障層係為氮化層或薄氮氧化物層製成。上述金屬線較佳為鋁-銅合金或其他類似的材料製成。Client's Docket No.: 95146TW TT^ Docket No:0593-A41201-TW/Final/ianchen/070605 1357150 on each of the active regions at each end of the column; a contact plug that uses a plug material to deposit in the above column An opening of each end is formed by planarizing the plug material by a chemical mechanical polishing process; a metal line is formed on the contact plug; and a metal interlayer dielectric layer is formed on the metal Between the lines. Further, the first barrier layer and the second barrier layer are made of a nitride layer or a thin oxynitride layer. The above metal wires are preferably made of an aluminum-copper alloy or the like.

在另一實施例中，於形成上述金屬線之後，沉積一金屬層間介電層以防止晶胞陣列中的導電物彼此電性連接。此外，本發明提供一種反及閘型快閃記憶體晶胞陣列的製造方法’包括：形成複數個排成一列的晶胞於一基板的一主動區上；沉積一第一阻障層，其覆蓋上述複數個晶胞和圍繞上述列之各末端的上述主動區；沉積一第一氧化物於上述複數個晶胞之間的一間隙中，以填充上述間隙；形成一氧化物間隙壁於沿著上述列之各末端之上述晶胞的側壁上；形成一多晶矽間隙壁於上述氧化物間隙壁上。在本發明另一實施例中，沿著位於上述列之各末端之上述晶胞的側壁上形成上述氧化物間隙壁之後，氣化層（tunnel 行一預清潔(pre-clean)製程，然後進行一穿隨更匕括進 oxide)氧化製程。在本發明另一實施例中方|示。p分上述第一阻障層，以及植入預定離子於圍繞上述列之各束端〜牙動區中；沉積一氧化層於上述基板上方；形4、的上述主 u战〜第-阻陸層於上述氧化層上；接著於上述基板上方形士 &一味降〜層間介電In another embodiment, after forming the metal lines, a metal interlayer dielectric layer is deposited to prevent the conductive elements in the cell array from being electrically connected to each other. In addition, the present invention provides a method for fabricating an inverted gate type flash memory cell array comprising: forming a plurality of cells arranged in a row on an active region of a substrate; depositing a first barrier layer, Covering the plurality of unit cells and the active regions surrounding each end of the column; depositing a first oxide in a gap between the plurality of unit cells to fill the gap; forming an oxide spacer along the edge On the sidewalls of the unit cell at each end of the column; a polysilicon spacer is formed on the oxide spacer. In another embodiment of the present invention, after forming the oxide spacer along the sidewalls of the unit cell at each end of the column, the gasification layer (tunnel is pre-cleaned and then performed) One wears an oxide oxidation process. In another embodiment of the invention, it is shown. P is divided into the first barrier layer, and implanting predetermined ions in each of the bundle ends to the tooth-moving regions surrounding the column; depositing an oxide layer above the substrate; forming the main U-to-first-resistance Laying on the above oxide layer; then on the substrate, the square &

Client’s Docket No.: 95146TW TT’s Docket No:0593-A41201-TW/Final/ianchen/070605 δ 1357150 層；形成一接觸孔插塞於上述列的各末端；於上述列的各末端形成上述接觸孔插塞；形成一金屬線於上述接觸孔插塞上。在本發明另一實施例中，上述金屬線係各別連接至一導電接墊(conductive pad)。然而，上述反及閘型快閃記憶體晶胞陣列的上述金屬線可連接至一導電溝槽。本發明較佳實施例之反及閘型快閃記憶體晶胞陣列，其具有較間单的結構及較南的深寬比，並結合自對準樂j 程’使其具有許多優於習知反及閘型快閃記憶體晶胞陣列的優點。【實施方式】以下利用製程剖面圖’以更詳細地說明本發明較佳實施例之反及閘型快閃記憶體晶胞陣列及其形成方法，在本發明各實施例中，相同的符號表示相同或類似的元件。請參考第2a至2b圖，其顯示本發明較佳實施例之利用自對準淺溝槽隔離製程（Self-Aligned-Shallow Trench Isolation Technology，SA-STI Technology)开j 成的佈局 (layout)。在各佈局中，標號”Wl〜Wn”係用以定義基板上的字元線。佈局的標號”AA”係用以定義基板上的主動區 (active region)，而佈局的標號”FP”係用以定義複數個漂浮多晶矽層（floating poly layer)。另外，佈局的標號”CB，，係用以定義位元線(bit-line)的接觸孔，而佈局的符號”CS”係用以定義基板上的源極線接觸孔（source line contact)。複數個反及閘型快閃記憶體晶胞係形成於佈局”AA”和任一佈局”Client's Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 δ 1357150 layer; forming a contact hole plug at each end of the above column; forming the above contact hole plug at each end of the above column Forming a metal line on the contact hole plug. In another embodiment of the invention, the metal wires are each connected to a conductive pad. However, the above metal lines of the above-described anti-gate type flash memory cell array can be connected to a conductive trench. The anti-gate type flash memory cell array of the preferred embodiment of the present invention has a relatively simple structure and a souther aspect ratio, and combines self-alignment to make it have many advantages. The advantages of know-how and gate-type flash memory cell arrays. [Embodiment] Hereinafter, a reverse-gate type flash memory cell array and a method for forming the same according to a preferred embodiment of the present invention will be described in more detail by using a process cross-sectional view. In the embodiments of the present invention, the same reference numerals are used. The same or similar components. Referring to Figures 2a through 2b, there is shown a layout of a preferred embodiment of the present invention using a Self-Aligned-Shallow Trench Isolation Technology (SA-STI Technology). In each layout, the designations "Wl~Wn" are used to define the word lines on the substrate. The layout label "AA" is used to define the active region on the substrate, and the layout label "FP" is used to define a plurality of floating poly layers. In addition, the layout label "CB" is used to define a bit-line contact hole, and the layout symbol "CS" is used to define a source line contact on the substrate. A plurality of anti-gate type flash memory cell systems are formed in the layout "AA" and any layout"

Client’s Docket No.: 95146TW TT's Docket N〇：0593-A41201-TW/Finaiyianchen/070605 1357150Client’s Docket No.: 95146TW TT's Docket N〇:0593-A41201-TW/Finaiyianchen/070605 1357150

WrWn”的交叉處上；且上述晶胞係以陣列（array)形式排列。反及閘型快閃記憶體晶胞的操作係被位元線接觸孔、共用（common)的源極線接觸孔、陣列閘極層和選擇閘極 (selection gate)(圖未顯示）的外加電壓所控制。必須注意的是，每個源極線接觸孔係連接一金屬線。如第2b圖顯示的本發明另一實施例中，源極線接觸孔係連接一導電溝槽（conductive trench)。上述結構可導致較低的電阻並可使製程簡化。請參考第3a至3b圖，其顯示兩種類型的反及閘型快閃記憶體晶胞的佈局，上述兩種類型的反及閘型快閃記憶體日日胞係利用自對準多晶破製程（Self-Aligned Poly Technology, SAP Technology)形成。第3a圖中的每個源極線接觸孔為一金屬線’而第3b圖中的每個源極線接觸孔為一溝槽。將第3a圖與第2a圖相比，不同處為第3a圖缺少佈局’’FP”。在利用SA-STI製程的苐2a圖中，佈局，’FP”定義的漂浮多晶矽層係做為反及閘型快閃記憶體晶胞列之間的隔絕物。當反及閘型快閃記憶體晶胞採用0.1 μιη(或小於 O.ljtmi)的製程製造時，佈局”FP”係從設計規則（design rule) 中移除以簡化製程，並且避免微影製程期間的對準誤差 (misalignment)。在利用SAP製程的第3a圖中，首先沉積漂浮多晶矽層，再利用化學機械研磨製程移除上述漂浮多晶矽層。因此可以減少定義反及閘梨快閃記憶體晶胞所需的光罩數目。另外，上述的反及閘型快閃記憶體結構係位於單一區At the intersection of WrWn"; and the above cell lines are arranged in an array form. The operation of the gate type flash memory cell is replaced by a bit line contact hole, a common source line contact hole. Controlled by the applied voltage of the array gate layer and the selection gate (not shown). It must be noted that each source line contact hole is connected to a metal line. The invention as shown in Figure 2b In another embodiment, the source line contact holes are connected to a conductive trench. The above structure can result in lower resistance and can simplify the process. Please refer to Figures 3a to 3b, which show two types of In contrast to the layout of the gate type flash memory cells, the above two types of inverse gate type flash memory cells are formed by Self-Aligned Poly Technology (SAP Technology). Each source line contact hole in Fig. 3a is a metal line' and each source line contact hole in Fig. 3b is a groove. Comparing Fig. 3a with Fig. 2a, the difference is 3a is missing the layout ''FP'. In the 苐2a diagram using the SA-STI process, the layout, the floating polysilicon layer defined by 'FP' is used as an isolation between the gate cell and the gate-type flash memory cell. When the bulk cell is fabricated in a 0.1 μm (or less than 0.1 μm) process, the layout "FP" is removed from the design rule to simplify the process and avoid misalignment during the lithography process. In Figure 3a, which utilizes the SAP process, a floating polycrystalline germanium layer is first deposited, and the floating polycrystalline germanium layer is removed by a chemical mechanical polishing process, thereby reducing the number of masks required to define the reverse flash memory cell. In addition, the above-mentioned anti-gate type flash memory structure is located in a single area.

Client’s Docket No.: 95146TW TT*s Docket No:0593-A41201-TW/Final/ianchen/070605 10 1357150 塊（single block)上。利用上述組成方式重覆形成於曰上’佈局”CB”和佈局”CS”係位於兩區塊之間β 請參考第4a圖，於基板30上形成複數個排成一列的晶胞32。首先，利用SA-STI或SAP製程形成主動區 area)結構。進行漂浮多晶石夕閘極（圖未顯示）的餘列制矛。後，於基板30上形成一閘極疊層。接著，利用微影^二蝕刻製程’於基板30上形成複數個存取多晶矽閘極 polysilicon gate)36。Client’s Docket No.: 95146TW TT*s Docket No:0593-A41201-TW/Final/ianchen/070605 10 1357150 on a single block. The above-described composition is repeatedly formed on the upper side. The layout "CB" and the layout "CS" are located between the two blocks. Referring to Fig. 4a, a plurality of unit cells 32 arranged in a row are formed on the substrate 30. First, an active area area structure is formed using an SA-STI or SAP process. Perform the remaining spears of the floating polycrystalline stone gate (not shown). Thereafter, a gate stack is formed on the substrate 30. Next, a plurality of access polysilicon gates 36 are formed on the substrate 30 by a lithography process.

之後’進行一離子植入製程，以調整晶胞32和選擇電晶體（select transistor)的源/汲極特性。另外，依序於基板 30和存取多晶石夕閘極(access polysilicon gate)36上設置一氧化層42和一第一阻障層43。氧化層42通常為一薄氧化層。第一阻障層43通常為利用遙控電漿化學氣相沉積 (remote plasma chemical vapor deposition, RPCVD)或電漿增強型化學氣相沉積（plasma enhancement chemical vapor deposition, PECVD)方式於氧化層42上形成的薄氮化層或薄氮氧化物層，且其厚度介於5〇A至150A之間。第一阻障層43對氧化層42的蝕刻選擇比須夠高，以使後續的回蝕刻製程可以進行。請參考第4b圖，利用高密度電漿化學氣相沉積(high density plasma chemical vapor deposition，HDP-CVD)或類似的方式，於晶胞32之間的間隙填入第一氧化物47，且設置於圍繞上述列之各末端的主動區上，第一氧化物47 的厚度介於1500人至5000A之間。如第4c圖所示，進行An ion implantation process is then performed to adjust the source/drain characteristics of the cell 32 and the select transistor. In addition, an oxide layer 42 and a first barrier layer 43 are disposed on the substrate 30 and the access polysilicon gate 36. Oxide layer 42 is typically a thin oxide layer. The first barrier layer 43 is usually formed on the oxide layer 42 by remote plasma chemical vapor deposition (RPCVD) or plasma enhanced chemical vapor deposition (PECVD). A thin nitride layer or a thin layer of oxynitride, and having a thickness between 5 Å and 150 Å. The etching selectivity of the first barrier layer 43 to the oxide layer 42 must be high enough for subsequent etchback processes to be performed. Referring to FIG. 4b, a first oxide 47 is filled in the gap between the unit cells 32 by using a high density plasma chemical vapor deposition (HDP-CVD) or the like. The first oxide 47 has a thickness between 1500 and 5000 A on the active region around each end of the above column. As shown in Figure 4c, proceed

Client's Docket No.； 95146TW TT’s Docket No:0593-A41201-TW/Finai/ianchen/070605 11 1357150 一回蝕刻製程，以於上述列之各末端的晶胞側壁上形成氧化物間隙壁49。第一氧化物47仍填充晶胞32之間的間隙。在回蝕刻製程期間，第一阻障層43可視為一蝕刻停止層。本發明較佳實施例的第一氧化物47係具有優異的階梯覆蓋能力，可在填充晶胞32之間的間隙時不會有孔洞的形成。如果只密封晶胞之間的間隙，可使用較低階梯覆蓋能力的材料而不必使用能完全填充間隙的第一氧化物47。在本發明較佳實施例中，晶胞32之間的間隙的深寬比 (aspect ratio)係介於1.8至3.2之間❹控制上述深寬比係特別有助於增加晶片的元件密度。如第4d圖所示，可進行溼蝕刻或乾蝕刻製程以去除露出的第一阻障層43。接著，進行一離子植入製程，以調整後續形成的選擇電晶體（selection transistor)的起始電壓 (threshold voltage)。於上述列之各末端形成一離子植入區 52。 °。接著’進行一預清潔(pre-clean)製程。然後，進行—穿隧氧化層（tunnel oxide)氧化製程之後’形成一多晶石夕間隙壁以做為選擇電晶體的閘極。如第4e圖至4f圖所示，首先’沉積一厚度介於1200A至3200A之間的多晶石夕層54, 然後，進行一回蝕刻製程，非等向性地蝕刻多晶石夕層S 54，’ 於上述列之各末端的晶胞32的侧壁上形成多晶石夕^隙壁 56。. ’、接著’如第4g圖所示’於基板30上方沉積—層氧化層60 ’通常為薄氧化層。然後，於氧化層6〇上沉積—氮Client's Docket No.; 95146TW TT's Docket No:0593-A41201-TW/Finai/ianchen/070605 11 1357150 An etching process to form oxide spacers 49 on the cell sidewalls at each end of the above columns. The first oxide 47 still fills the gap between the unit cells 32. During the etch back process, the first barrier layer 43 can be considered an etch stop layer. The first oxide 47 of the preferred embodiment of the present invention has excellent step coverage and can form no voids when filling the gap between the unit cells 32. If only the gap between the unit cells is sealed, a material having a lower step coverage can be used without using the first oxide 47 which can completely fill the gap. In a preferred embodiment of the invention, the aspect ratio of the gap between the unit cells 32 is between 1.8 and 3.2. Controlling the aspect ratio described above in particular helps to increase the component density of the wafer. As shown in Fig. 4d, a wet etching or dry etching process may be performed to remove the exposed first barrier layer 43. Next, an ion implantation process is performed to adjust the threshold voltage of the subsequently selected selection transistor. An ion implantation region 52 is formed at each end of the above column. °. Then a pre-clean process is performed. Then, after performing a tunnel oxide oxidation process, a polycrystalline whisker wall is formed to serve as a gate for selecting a transistor. As shown in Figures 4e to 4f, first, a polycrystalline layer 54 having a thickness between 1200 A and 3200 A is deposited, and then an etching process is performed to etch the polycrystalline slab layer anisotropically. 54' A polycrystalline stone wall 56 is formed on the sidewall of the unit cell 32 at each end of the above column. And then, as shown in Fig. 4g, a layer of oxide layer 60' deposited over the substrate 30 is typically a thin oxide layer. Then, depositing nitrogen on the oxide layer 6

Client’s Docket No·: 95146TW TT’s Docket No:0593-A41201-TW/Final/ianchen/070605 12 1357150 化層62，氮化層62可視為一阻障層，即為第二阻障層。利用低壓化學氣相沉積（LPCVD)、電漿增強型化學氣相沉積（PECVD)或其他類似的製程，沉積一層間介電層 64 °之後，進行一化學機械研磨（chemicai mechanical polishing，CMP)製程以平坦化層間介電層64。然後，進行微影和非等向性蝕刻製程，以形成位元線(bit-line)接觸孔和源/汲極接觸孔。. 請參考第4h圖’進行一離子植入製程以形成歐姆接觸 (ohmic contact)76。於位元線(bit-line)接觸孔和源/汲極接觸孔填入接觸孔插塞66。首先，利用沉積例如多晶石夕或鎢的插塞材料。然後’利用化學機械研磨（chemical mechanical polishing，CMP)製程平坦化上述插塞材料，以形成接觸孔插塞66。接著’利用物理氣相沉積或其他類似的製程，於接觸孔插塞66和層間介電層64上沉積一導電層，上述導電層係鋁銅合金或其類似的材料。之後，利用微影和蝕刻製程，於接觸孔插塞66上形成一金屬線72。在一實施例中，於形成金屬線72之後，沉積一金屬層間介電層（圖未顯示）以防止晶胞陣列中的導電物彼此電性連接。根據上述製程，金屬線72係位於兩個反及閘型快閃記憶體晶胞陣列區塊之間。如第1 a和1 b圖所示之習知的反及閘型快閃記憶體晶胞陣列，例如兩條選擇線圖案1 s和1 g的佈局，係分別定Client's Docket No:: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 12 1357150 The layer 62, the nitride layer 62 can be regarded as a barrier layer, which is the second barrier layer. A chemical mechanical polishing (CMP) process is performed after depositing an interlayer dielectric layer by 64 ° using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or the like. The interlayer dielectric layer 64 is planarized. Then, a lithography and anisotropic etching process is performed to form a bit-line contact hole and a source/drain contact hole. Please refer to Figure 4h for an ion implantation process to form an ohmic contact 76. The contact hole plug 66 is filled in the bit-line contact hole and the source/drain contact hole. First, a plug material such as polycrystalline or tungsten is deposited. The plug material is then planarized by a chemical mechanical polishing (CMP) process to form contact hole plugs 66. Next, a conductive layer is deposited on the contact plug 66 and the interlayer dielectric layer 64 by physical vapor deposition or the like, and the conductive layer is an aluminum-copper alloy or the like. Thereafter, a metal line 72 is formed on the contact hole plug 66 by means of a lithography and etching process. In one embodiment, after the metal lines 72 are formed, a metal interlayer dielectric layer (not shown) is deposited to prevent electrical connections in the cell array from electrically connecting to each other. According to the above process, the metal line 72 is located between the two inverted gate type flash memory cell array blocks. Conventional anti-gate type flash memory cell arrays as shown in Figures 1a and 1b, such as the layout of two select line patterns 1 s and 1 g, are determined separately

Client's Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Fiiial/ianchen/070605 13 1357150 義為兩個選擇電晶體13和19。由於本發明較佳實施例之自對準製程（self-aligned process)形成的多晶矽間隙壁係用來代替選擇電晶體。表示至少兩條選擇線圖案可於上述製程中移除。此外，由於多晶矽間隙壁係利用自對準製程= 成，可以降低例如步進機台（stepper)等需要精確度的製程機台的等級。因此，本發明實施例的製程的製造成本係大幅低於習知技術的製造成本。 ’' φ 另外，對於具有反及閘型快閃記憶體晶胞陣列的晶片而έ，本發明提供晶胞間之間隙較高的深寬比（&叩£“ ratio) ’其係特別有助於增加晶片的元件密度。由於反及閘型快閃§己憶體晶胞陣列和自對準製程，微衫製程中的關鍵尺寸（critical dimensi〇n，CD)和疊對損失較少，因此增加了製程的穩定性。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精 φ 神和範圍内，當可做些許更動與潤飾，因此本發明之保護 * 範圍當視後附之申請專利範圍所界定者為準。【圖式簡單說明】第la圖為一上視圖，其顯示習知的反及閘型快閃記憶體元件的部分晶胞陣列區。第lb圖係沿第la圖的η切線的剖面圖，其顯示習知的反及閘型快閃記憶體結構。第2a圖顯示本發明一較佳實施例之利用自對準淺溝槽隔離製程形成的佈局。 θClient's Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Fiiial/ianchen/070605 13 1357150 Meaning two crystals 13 and 19. The polycrystalline germanium spacer formed by the self-aligned process of the preferred embodiment of the present invention is used in place of the selective transistor. Indicates that at least two selection line patterns can be removed in the above process. In addition, since the polysilicon barrier system utilizes a self-aligned process = the level of the process machine requiring precision, such as a stepper, can be lowered. Therefore, the manufacturing cost of the process of the embodiment of the present invention is considerably lower than the manufacturing cost of the prior art. '' φ In addition, for a wafer having an inverted gate type flash memory cell array, the present invention provides a higher aspect ratio (& “ "" ratio" between the cells. Helps increase the component density of the wafer. Due to the anti-gate flash § memory cell array and self-aligned process, the critical dimension (CD) and stacking loss in the micro-shirt process are less, Therefore, the stability of the process has been increased. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one skilled in the art should be within the scope of the invention. A few modifications and refinements may be made, so the scope of protection of the present invention is defined by the scope of the appended patent application. [Simplified Schematic] The first drawing is a top view showing a conventional anti-gate Part of the cell array region of the type of flash memory device. Figure lb is a cross-sectional view taken along line η of the first drawing showing a conventional inverse gate type flash memory structure. Fig. 2a shows a first aspect of the present invention Self-aligned shallow trenches using the preferred embodiment Formed from the layout process. Θ

Client's Docket No.: 95146TW TT^s Docket No:0593-A41201-TW/Final/ianchen/070605 14 1357150 第2b圖顯示本發明另一實施例之利用自對準淺溝槽隔離製程形成的佈局。第3a圖顯示本發明較佳實施例之自對準多晶矽製程形成的佈局。第3b圖顯示本發明另一實施例之自對準多晶矽製程形成的佈局。第4a至4h圖分別為沿第2a、2b、3a和3b圖的A-A’ 切線的剖面圖，其顯示本發明實施例之反及閘型快閃記憶體晶胞陣列的製程剖面圖。【主要元件符號說明】 lg〜圖案，Is〜圖案，2〜主動區，13〜字串選擇電晶體， 15、17〜晶胞電晶體；19〜接地選擇電晶體；WP1〜WPn〜字元線；WcWn〜字元線；AA〜主動區；CB〜接觸孔；CS〜源極線接觸孔；FP〜漂浮多晶矽層；30〜基板；32〜晶胞；36〜存取多晶矽閘極；42〜氧化層；43〜第一阻障層；47〜第一氧化物；49〜氧化物間隙壁；52~離子植入區；54〜多晶矽層；56〜多晶石夕間隙壁；60〜氧化層；62〜氮化層；64〜層間介電層；66〜接觸孔插塞；72〜金屬線；76〜歐姆接觸。Client's Docket No.: 95146TW TT^s Docket No:0593-A41201-TW/Final/ianchen/070605 14 1357150 Figure 2b shows a layout formed by a self-aligned shallow trench isolation process in accordance with another embodiment of the present invention. Figure 3a shows the layout of the self-aligned polysilicon process of the preferred embodiment of the present invention. Figure 3b shows a layout of a self-aligned polysilicon process in accordance with another embodiment of the present invention. 4a through 4h are cross-sectional views taken along line A-A' of the 2a, 2b, 3a, and 3b, respectively, showing a process cross-sectional view of the inverted gate type flash memory cell array of the embodiment of the present invention. [Main component symbol description] lg ~ pattern, Is ~ pattern, 2 ~ active area, 13 ~ string selection transistor, 15, 17 ~ cell transistor; 19 ~ ground selection transistor; WP1 ~ WPn ~ word line ; WcWn ~ word line; AA ~ active area; CB ~ contact hole; CS ~ source line contact hole; FP ~ floating polysilicon layer; 30 ~ substrate; 32 ~ unit cell; 36 ~ access polysilicon gate; Oxide layer; 43~ first barrier layer; 47~ first oxide; 49~ oxide spacer; 52~ ion implantation region; 54~ polysilicon layer; 56~ polycrystalline interlayer spacer; 60~ oxide layer ; 62 ~ nitride layer; 64 ~ interlayer dielectric layer; 66 ~ contact hole plug; 72 ~ metal line; 76 ~ ohmic contact.

Client’s Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605Client’s Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605

Claims

1357150 十、申請專利範圍： 1. 一種反及閘型快閃記憶體晶胞陣列，包括：一基板，其包括一主動區；複數個排成一列的晶胞，位於該主動區上；一第一阻障層，覆蓋該複數個晶胞和圍繞該列之各末端的該主動區；一第一氧化物，沉積於該複數個晶胞之間的一間隙中，且填充該間隙；一氧化物間隙壁，形成於沿著該列之各末端之該晶胞的側壁上；以及一多晶矽間隙壁，形成於該氧化物間隙壁上，該多晶矽間隙壁係做為驅動該列晶胞的一選擇閘極。 2. 如申請專利範圍第1項所述之反及閘型快閃記憶體晶胞陣列，更包括一植入區，其係利用植入預定離子方式形成於圍繞該列之各末端的該主動區中。 3. 如申請專利範圍第1項所述之反及閘型快閃記憶體晶胞陣列，更包括一氧化層，其係沉積於該多晶矽間隙壁、該氧化物間隙壁、部分該第一阻障層和該第一氧化物上。 4. 如申請專利範圍第3項所述之反及閘型快閃記憶體晶胞陣列，更包括一第二阻障層，其係沉積於該氧化層上。 5. 如申請專利範圍第4項所述之反及閘型快閃記憶體晶胞陣列，更包括一層間介電層，其係沉積於該第二阻障層上及圍繞該列之各末端的該主動區上。 6. 如申請專利範圍第4項所述之反及閘型快閃記憶體 Client’s Docket No_: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 16 1357150 晶胞陣列，更包括一接觸孔插塞，其係利用沉積一插塞材料於位於該列各末端的一開口中’再利用一化學機械研磨製程平坦化該插塞材料的方式形成。 7. 如申請專利範圍第6項所述之反及閘型快閃記憶體晶胞陣列，更包括一金屬線，其係形成於該接觸孔插塞上。 8. 如申請專利範圍第1項所述之反及閘型快閃記憶體晶胞陣列，其中該複數個晶胞之間的該間隙的深寬比介於 1.8至3.2之間。 9. 如申请專利範圍第1項所述之反及閘型快閃記憶體晶胞陣列，其中該第一阻障層係為氮化層或薄氮氧化物層製成。 10. 如申凊專利範圍第4項所述之反及閘型快閃記憶體晶胞陣列，其中該第一阻障層和該第二阻障層係為氮化層或薄氮氧化物層製成。 11 · 一種反及閘型快閃§己憶體晶胞陣列的製造方法，包括下列步驟：形成複數個排成一列的晶胞於一基板的一主動區上；沉積一第一阻障層，其覆蓋該複數個晶胞和圍繞該列之各末端的該主動區；沉積一第一氧化物於該複數個晶胞之間的一間隙中，以填充該間隙；形成一氧化物間隙壁於沿著位於該列之各末端之該晶胞的側壁上；以及形成一多晶石夕間隙壁於該氧化物間隙壁上。 Clients Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 17 1357150 12. 如申請專利範圍第11項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該形成該氧化物間隙壁於沿著位於該列之各末端之該晶胞的側壁上之步驟後，更包括一去除部分該第一阻障層，以及植入預定離子於圍繞該列之各末端的該主動區中之步驟。 13. 如申請.專利範圍第11項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該形成該多晶矽間隙壁於該氧化物間隙壁上之步驟後，更包括一沉積一氧化層於該基板上方之步驟。 14. 如申請專利範圍第13項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該沉積該氧化層於該基板上方之步驟後，更包括一形成一第二阻障層於該氧化層上之步驟。 15. 如申請專利範圍第14項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該形成該第二阻障層於該氧化層上之步驟後，更包括一形成一層間介電層於該基板上方之步驟。 16. 申請專利範圍第15項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該形成該層間介電層於該基板上方之步驟後，更包括一形成一接觸孔插塞於該列的各末端之步驟。 17. 申請專利範圍第16項所述之反及閘型快閃記憶體晶胞陣列的製造方法，其中該形成該接觸孔插塞於該列的各末端之步驟後，更包括一形成一金屬線於該接觸孔插塞 Clients Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 1357150 上之步驟。1357150 X. Patent application scope: 1. An anti-gate type flash memory cell array, comprising: a substrate comprising an active region; a plurality of unit cells arranged in a row, located on the active region; a barrier layer covering the plurality of unit cells and the active region surrounding each end of the column; a first oxide deposited in a gap between the plurality of unit cells and filling the gap; a spacer formed on a sidewall of the unit cell along each end of the column; and a polysilicon spacer formed on the oxide spacer, the polysilicon spacer being used as a layer for driving the column cell Select the gate. 2. The anti-gate type flash memory cell array according to claim 1, further comprising an implant region formed by implanting a predetermined ion pattern around each end of the column In the district. 3. The anti-gate type flash memory cell array according to claim 1, further comprising an oxide layer deposited on the polysilicon spacer, the oxide spacer, and a portion of the first resistance a barrier layer and the first oxide. 4. The anti-gate type flash memory cell array according to claim 3, further comprising a second barrier layer deposited on the oxide layer. 5. The anti-gate type flash memory cell array according to claim 4, further comprising an interlayer dielectric layer deposited on the second barrier layer and surrounding each end of the column On the active area. 6. For example, the anti-gate type flash memory Client's Docket No_: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 16 1357150 cell array, including one contact A hole plug is formed by depositing a plug material in an opening at each end of the column to re-format the plug material using a chemical mechanical polishing process. 7. The anti-gate type flash memory cell array according to claim 6, further comprising a metal line formed on the contact hole plug. 8. The anti-gate type flash memory cell array according to claim 1, wherein the gap between the plurality of unit cells has an aspect ratio of between 1.8 and 3.2. 9. The anti-gate type flash memory cell array according to claim 1, wherein the first barrier layer is made of a nitride layer or a thin oxynitride layer. 10. The anti-gate type flash memory cell array according to claim 4, wherein the first barrier layer and the second barrier layer are nitride layers or thin oxynitride layers production. 11 . A method for manufacturing a reverse-type flash § cell array, comprising the steps of: forming a plurality of cells arranged in a row on an active region of a substrate; depositing a first barrier layer, And covering the plurality of unit cells and the active region surrounding each end of the column; depositing a first oxide in a gap between the plurality of unit cells to fill the gap; forming an oxide spacer Along the sidewalls of the unit cell at each end of the column; and forming a polycrystalline silicon spacer on the oxide spacer. Clients Docket No.: 95146TW TT's Docket No:0593-A41201-TW/Final/ianchen/070605 17 1357150 12. The method of manufacturing the anti-gate type flash memory cell array according to claim 11 of the patent application, Wherein the step of forming the oxide spacers along the sidewalls of the unit cell at each end of the column further comprises removing a portion of the first barrier layer and implanting predetermined ions around the column The steps in the active zone at each end. 13. The method of manufacturing a reverse-gate type flash memory cell array according to claim 11, wherein the step of forming the polysilicon spacer on the oxide spacer further comprises a deposition. The step of forming an oxide layer over the substrate. 14. The method of fabricating an anti-gate type flash memory cell array according to claim 13, wherein the step of depositing the oxide layer over the substrate further comprises forming a second barrier. The step of layering on the oxide layer. 15. The method of fabricating an anti-gate type flash memory cell array according to claim 14, wherein the step of forming the second barrier layer on the oxide layer further comprises forming a layer. The step of interposing a dielectric layer over the substrate. 16. The method for manufacturing a reverse-gate type flash memory cell array according to claim 15, wherein the step of forming the interlayer dielectric layer over the substrate further comprises forming a contact hole. The step of plugging at each end of the column. 17. The method of manufacturing the anti-gate type flash memory cell array according to claim 16, wherein the step of forming the contact hole at each end of the column further comprises forming a metal. Line the steps on the contact hole plug Clients Docket No.: 95146TW TT5s Docket No:0593-A41201-TW/Final/ianchen/070605 1357150.

Client’s Docket No.: 95146TW TT，s Docket No:0593-A41201 -TW/Final/ianchen/070605Client’s Docket No.: 95146TW TT,s Docket No:0593-A41201 -TW/Final/ianchen/070605